Hybrid waveguide structure and preparation method thereof, and heterogeneous integrated photonic device and preparation method thereof

Abstract

The invention relates to the technical field of photonic devices, and discloses a hybrid waveguide structure and a preparation method thereof, and a heterogeneous integrated photonic device and a preparation method thereof. The preparation method of the hybrid waveguide structure comprises the steps of providing a substrate layer; forming a first modulation structure; forming a first spacing layer; forming a first protective layer; forming a second cladding; forming a second modulation structure; forming a second spacing layer; forming a second protection layer; forming a third cladding; forming a first interconnection structure and a second interconnection structure; a first bonding groove is formed above the first modulation structure, a second bonding groove is formed above the second modulation structure, and the first bonding groove and the second bonding groove are suitable for containing different heterogeneous chips. Combination of various silicon optical heterogeneous materials and the silicon optical waveguide device can be achieved on the same substrate layer, the interlayer distance between each modulation waveguide and the heterogeneous material can be independently controlled, the CMOS process compatibility is high, the bonding area and the non-bonding area have structural compatibility, and the flexibility of the structural design and the process processing of the silicon optical device is guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of photonic devices, and particularly relates to a hybrid waveguide structure and a preparation method thereof, a heterogeneous integrated photonic device and a preparation method thereof. Background Art

[0002] With the rapid development of fields such as data centers, 5G communications, and artificial intelligence, high-speed, low-power, and large-bandwidth photonic devices have gradually become the focus of research. Although lithium niobate (LiNbO, abbreviated as LN) has excellent electro-optic, acousto-optic, and nonlinear optical properties and is the preferred material for preparing key photonic devices such as high-speed optical modulators and filters, traditional lithium niobate devices are large in volume and high in cost, making it difficult to meet the requirements of large-scale integration and low-cost manufacturing. The silicon waveguides and silicon nitride waveguides that interact with it, although having the advantages of being compatible with CMOS processes, low cost, and high integration, have achieved success in the fields of optical communication and optical interconnection, but the materials themselves lack strong electro-optic effects and are limited in applications such as high-speed optical modulation. That is, integrated photonic devices of lithium niobate materials with silicon waveguides or lithium niobate materials with silicon nitride waveguides are difficult to meet the technical requirements.

[0003] Based on this, heterogeneous integration technology has emerged. This technology aims to integrate different heterogeneous materials and waveguide structures together through bonding and other methods to overcome the limitations of single materials, give full play to the advantages of different materials, and achieve the effects of high performance, high integration, and low cost. In addition to lithium niobate (LN) materials, materials such as lead zirconate titanate (PZT) and barium titanate (BTO) can also be integrated with silicon-based photonic devices due to their excellent piezoelectric, ferroelectric, and electro-optic properties, endowing the silicon-based photonic platform with new functions such as high-speed optical modulation, tunable filtering, and acousto-optic interaction. These heterogeneous materials (LN, PZT, BTO, etc.) are usually combined together through heterogeneous integration technologies such as bonding (such as D2W bonding, that is, die-to-wafer bonding) to avoid problems such as lattice mismatch, large differences in thermal expansion coefficients, poor material properties, and incompatibility with CMOS processes.

[0004] However, since different heterogeneous materials usually have waveguide materials that are best matched with them, it is difficult to integrate different heterogeneous materials in the waveguide structures formed on the same wafer substrate. The diversity of silicon photon heterogeneous material integration is limited, and the processability of multifunctional devices on the same waveguide wafer is limited. Moreover, since wafer bonding first requires CMP planarization of the wafer substrate, and CMP planarization acts on the entire surface of the wafer substrate, but an interlayer needs to be set between the waveguide and the heterogeneous material in the bonding area, and a coating layer needs to be set on the waveguide in the non-bonding area. The thickness requirements of the interlayer and the coating layer are different, making the process difficult to be compatible, and ultimately affecting the performance of optoelectronic devices with heterogeneous material integration. Summary of the Invention

[0005] In view of this, the present invention provides a hybrid waveguide structure and a preparation method thereof, a heterogeneous integrated photonic device and a preparation method thereof, so as to solve the problems of poor process structure compatibility, difficulty in ensuring device performance, and limited integration diversity when integrating different heterogeneous materials with the waveguide structure.

[0006] In a first aspect, the present invention provides a method for preparing a hybrid waveguide structure, comprising:

[0007] Providing a substrate layer, wherein a first cladding layer is disposed on one side surface of the substrate layer;

[0008] forming a first modulation structure, the first modulation structure comprising a first modulation waveguide and a first electrode embedded in a side of the first cladding layer away from the substrate layer, the first modulation waveguide and the first electrode being spaced apart;

[0009] Forming a first spacer layer on a surface of the first cladding layer facing away from the substrate layer, wherein the first spacer layer covers the first modulation structure;

[0010] forming a first protective layer on the first spacer layer, wherein the first protective layer at least covers a portion of the first modulation waveguide and a portion of the first electrode;

[0011] A second cladding layer is formed on a surface of the first spacer layer facing away from the substrate layer, the second cladding layer covers the first protective layer, and a continuous plane is formed on a surface of the first protective layer facing away from the substrate layer;

[0012] forming a second modulation structure, wherein the second modulation structure includes a second modulation waveguide and a second electrode embedded in the second cladding layer on a side away from the substrate layer, and the second modulation waveguide and the second electrode are arranged at an interval with respect to the first modulation structure;

[0013] forming a second spacer layer on a surface of the second cladding layer facing away from the substrate layer, wherein the second spacer layer covers the second modulation structure;

[0014] forming a second protective layer on the second spacer layer, wherein the second protective layer at least covers a portion of the second modulation waveguide and a portion of the second electrode;

[0015] A third cladding layer is formed on a surface of the second spacer layer facing away from the substrate layer, the third cladding layer covers the second protective layer, and a continuous plane is formed on a surface of the second protective layer facing away from the substrate layer;

[0016] A first interconnection structure and a second interconnection structure are formed, wherein one end of the first interconnection structure extends into the third cladding, the second spacer, the second cladding and the first spacer to be connected to the first electrode, and the other end is exposed on the third cladding; one end of the second interconnection structure extends into the third cladding and the second spacer to be connected to the second electrode, and the other end is exposed on the third cladding;

[0017] A first bonding groove is formed above the first modulation structure. The first bonding groove is adapted to expose the first spacer layer, and a second bonding groove is formed above the second modulation structure. The second bonding groove is adapted to expose the second spacer layer. The first bonding groove and the second bonding groove are adapted to accommodate different heterogeneous chips.

[0018] Advantages: Through the preparation method of the hybrid optical waveguide of the present invention, firstly, different waveguides such as a first modulation waveguide and a second modulation waveguide with different heights can be obtained on the same substrate layer, which is convenient for realizing the combination of various silicon photonics heterogeneous materials and silicon optical waveguide devices on the same substrate layer, and helps to improve the functional diversity of silicon photonics devices on the same substrate layer. Secondly, the thickness of the first spacer layer on the first modulation waveguide can be controlled independently, and the thickness of the second spacer region on the second modulation waveguide can be controlled independently, that is, the thickness of the spacer layer on each modulation waveguide, that is, the interlayer spacing when integrated with heterogeneous materials, can be controlled independently, improving the flexibility of the processing technology while ensuring the characteristics of CMOS process compatibility; thirdly, by opening a first bonding groove above the first modulation waveguide and a second bonding groove above the second modulation waveguide, a bonding region with a space for bonding and integrating heterogeneous materials is formed, and other non-bonding regions have a cladding layer with the same depth as the groove and much larger than the interlayer spacing of the bonding region, realizing the structural compatibility of the bonding region and the non-bonding region, and making the silicon photonics device more flexible in structural design and process processing.

[0019] In an optional embodiment, the substrate layer, the first sub-cladding layer, and the initial first waveguide layer are sequentially stacked to form a silicon-on-insulator substrate; the steps of forming the first modulation structure include:

[0020] Patterning the initial first waveguide layer to form a first modulation waveguide;

[0021] Forming a second sub-cladding layer on the surface of the first sub-cladding layer facing away from the substrate layer, and the second sub-cladding layer covers the first modulation waveguide; the second sub-cladding layer and the first sub-cladding layer constitute the first cladding layer;

[0022] Etching away a part of the first cladding layer to form a first groove in the region of the first cladding layer spaced from the first modulation waveguide;

[0023] Depositing a first metal material on the surface of the first cladding layer facing away from the substrate layer, and the first metal material fills the first groove;

[0024] Performing a planarization process on the side where the first metal material is located until the first modulation waveguide is exposed, forming a first electrode located in the first groove, and the surface of the first electrode, the surface of the first modulation waveguide, and the surface of the first cladding layer are flush.

[0025] Beneficial effects: By preparing the first cladding in two steps to wrap the first modulation waveguide up and down, it maximally ensures that the first modulation waveguide is not damaged when preparing the first electrode; at the same time, by first depositing the first metal material that completely fills the first groove body and then using the CMP process to polish and remove the excess first metal material and the first cladding on the first modulation structure, it maximally realizes the flatness of the upper surfaces of the first modulation waveguide, the first electrode, and the first cladding, facilitating the precise control of the thickness of the first spacer layer prepared on the first modulation structure subsequently and ensuring the modulation performance of the first modulation structure.

[0026] In an alternative embodiment, the second cladding includes a third sub-cladding and a fourth sub-cladding, and the third sub-cladding is relatively closer to the substrate layer side; the steps of forming the second modulation structure include:

[0027] On the surface of the third sub-cladding facing away from the substrate layer, an initial second waveguide layer is formed over the entire surface by plasma-enhanced chemical vapor deposition;

[0028] The initial second waveguide layer is patterned to form a second modulation waveguide;

[0029] A fourth sub-cladding is formed on the surface of the third sub-cladding facing away from the substrate layer, and the fourth sub-cladding covers the second modulation waveguide. The fourth sub-cladding and the third sub-cladding constitute the second cladding;

[0030] Part of the second cladding is etched away to form a second groove body in the region of the second cladding spaced from the second modulation waveguide;

[0031] A second metal material is deposited on the surface of the second cladding facing away from the substrate layer, and the second metal material covers the surface of the second cladding and fills the second groove body;

[0032] The side where the second metal material is located is planarized until the second modulation waveguide is exposed, forming a second electrode in the second groove body, and the surface of the second electrode, the surface of the second modulation waveguide, and the surface of the second cladding are flush.

[0033] Beneficial effects: By preparing the second cladding in two steps to wrap the second modulation waveguide up and down, it maximally ensures that the second modulation waveguide is not damaged when preparing the second electrode; at the same time, by first depositing the second metal material higher than the second groove body and then using the CMP process to perform full-plane grinding to remove the excess second metal material and the second cladding on the second modulation structure, it maximally realizes the flatness of the upper surfaces of the second modulation waveguide, the second electrode, and the second cladding, facilitating the precise control of the thickness of the second spacer layer prepared on the second modulation structure subsequently and ensuring the modulation performance of the second modulation structure.

[0034] In an alternative embodiment, in the step of forming the first modulation waveguide, it further includes: synchronously forming a first transmission waveguide connected to the first modulation waveguide, and the first transmission waveguide and the first modulation waveguide constitute a first waveguide structure; in the step of forming the second modulation waveguide, it further includes: synchronously forming a second transmission waveguide connected to the second modulation waveguide, and the second transmission waveguide and the second modulation waveguide constitute a second waveguide structure; the projections of the first transmission waveguide and the second transmission waveguide on the substrate layer at least partially overlap to form a composite transmission waveguide, and the composite transmission waveguide is adapted to process the input optical signal and transmit the processed optical signal to the first modulation waveguide and the second modulation waveguide respectively.

[0035] Advantages: The first modulation waveguide and the first transmission waveguide in the first waveguide structure are prepared synchronously, and the second modulation waveguide and the second transmission waveguide in the second waveguide structure are prepared synchronously, improving the preparation efficiency of the waveguide structure. The first transmission waveguide and the second transmission waveguide form a double-layer partially overlapping composite waveguide in the non-bonding region. Firstly, it can expand the working wavelength band. For example, the silicon waveguide has a large absorption loss in the short wavelength band, while the silicon nitride waveguide has a wider optical bandgap. After the two are combined, the silicon nitride waveguide can compensate for the working limitation in the short wavelength band. Secondly, the silicon nitride has a small non-linear loss, and combined with the silicon waveguide, it can increase the power threshold of the non-linear effect and is suitable for non-linear optical processes. Thirdly, the silicon nitride waveguide has good thermal stability, which helps to improve the thermal stability of the device. Fourthly, the silicon nitride waveguide has a low transmission loss in the visible to near-infrared wavelength band. After being combined with the silicon waveguide, it can reduce the energy loss and coupling loss of light during transmission and improve the transmission efficiency of the optical signal. Finally, both silicon nitride and silicon materials are compatible with the CMOS process, and the composite transmission waveguide can be realized by existing semiconductor processes, which is convenient for integration with active devices (such as modulators, detectors) and electronic circuits, promoting the development of the photon-electronic hybrid integration system.

[0036] In an alternative embodiment, the thickness ranges of both the first spacer layer and the second spacer layer are 50 nm to 150 nm, the surface roughnesses of the sides of the first spacer layer and the second spacer layer facing away from the substrate layer are both less than 0.5 nm, and the surface undulations are less than 50 nm.

[0037] Advantages: The first spacer layer and the second spacer layer are set with different thicknesses according to the heterogeneous materials to be bonded as needed to ensure optimal optoelectronic modulation performance. The surfaces of the first spacer layer and the second spacer layer will serve as the bonding interfaces for subsequent heterogeneous silicon-optical materials, and it is required that their surface roughnesses are less than 0.5 nm and the surface undulations (i.e., flatness) are less than 50 nm to ensure the bonding quality.

[0038] In an alternative embodiment, the wet etching selectivity of the first protective layer to the first spacer layer is greater than 100:1; the wet etching selectivity of the second protective layer to the second spacer layer is greater than 100:1.

[0039] Beneficial effects: The materials selected for the first protective layer and the second protective layer have a sufficiently high etching selectivity ratio for the underlying first spacer layer and second spacer layer materials during subsequent wet etching, thereby avoiding risks such as etching damage and increased roughness to the bonding interface.

[0040] In an alternative embodiment, the steps of forming the first interconnect structure and the second interconnect structure include:

[0041] Form a first interlayer via hole above the first electrode not shielded by the first protective layer, and form a second interlayer via hole above the second electrode not shielded by the second protective layer. The first interlayer via hole penetrates through the third cladding layer, the second spacer layer, the second cladding layer, and the first spacer layer to connect the first electrode to the external environment, and the second interlayer via hole penetrates through the third cladding layer and the second spacer layer to connect the second electrode to the external environment;

[0042] Fill the first interlayer via hole and the second interlayer via hole with a third metal material respectively to form a first interlayer interconnect conductive pillar in the first interlayer via hole and a second interlayer interconnect conductive pillar in the second interlayer via hole;

[0043] Form a first pad and a second pad on the surface of the third cladding layer facing away from the substrate layer. The first pad is connected to the first interlayer interconnect conductive pillar to form a first interconnect structure, and the second pad is connected to the second interlayer interconnect conductive pillar to form a second interconnect structure. In an alternative embodiment, the steps of forming a first bonding groove above the first modulation structure and forming a second bonding groove above the second modulation structure include:

[0044] Form a fourth cladding layer on the entire surface of the third cladding layer facing away from the substrate layer. The fourth cladding layer covers the first interconnect structure and the second interconnect structure;

[0045] Etch away the fourth cladding layer, the third cladding layer, the second spacer layer, the second cladding layer, and the first protective layer on the first protective layer to form a first bonding groove above the first modulation structure. The width of the first bonding groove is smaller than the width of the first protective layer; at the same time, remove the fourth cladding layer, the third cladding layer, and the second protective layer on the second protective layer to form a second bonding groove above the second modulation structure. The width of the second bonding groove is smaller than the width of the second protective layer;

[0046] Etch away the fourth cladding layer on the first pad and the second pad to form a first pad window and a second pad window.

[0047] Beneficial effects: In the present invention, when forming the first bonding groove and the second bonding groove, the processing is carried out step by step. First, the silica material of the cladding structure is removed, and then the protective layer material is removed. The step-by-step processing makes the morphology of the groove more accurate, and can avoid damaging the surface morphology of the spacer layer, ensuring the surface performance of the spacer layer, thereby improving the bonding quality with the heterogeneous chip and improving the modulation performance.

[0048] In an alternative embodiment, the distance range between the edge of the first bonding groove and the edge of the first protective layer on the relatively closer side is the thickness range of the first protective layer; the distance range between the edge of the second bonding groove and the edge of the second protective layer on the relatively closer side is the thickness range of the second protective layer.

[0049] Beneficial effects: Specifically, the width of the first bonding groove is slightly smaller than the width of the first protective layer, and the width of the second bonding groove is slightly smaller than the width of the second protective layer. When etching the cladding structure to form the first bonding groove and the second bonding groove, the first protective layer and the second protective layer can fully protect the bonding interfaces of the underlying first spacer layer and the second spacer layer, which helps to improve the bonding performance with heterogeneous materials.

[0050] In a second aspect, the present invention also provides a hybrid waveguide structure, prepared by using the preparation method of the above hybrid waveguide structure, including: a substrate layer, a cladding structure, a first modulation structure, a second modulation structure, a first bonding groove and a second bonding groove, and a first interconnecting structure and a second interconnecting structure. The cladding structure is located on one side surface of the substrate layer, and includes a first cladding, a first spacer layer, a second cladding, a second spacer layer, and a third cladding stacked in sequence from the surface of the substrate layer upward; the first modulation structure is embedded in the first cladding, and the first modulation structure includes a first modulation waveguide and a first electrode, and the first modulation waveguide and the first electrode are arranged at intervals; the second modulation structure is embedded in the second cladding, the second modulation structure includes a second modulation waveguide and a second electrode, and is arranged offset from the first modulation structure, and the second modulation waveguide and the second electrode structure are arranged at intervals; the first bonding groove is located above the first modulation structure and penetrates through the third cladding, the second spacer layer, and the second cladding, and there is a first spacer layer between the first bonding groove and the first modulation structure; the second bonding groove is located above the second modulation structure and penetrates through the third cladding, and there is a second spacer layer between the second bonding groove and the second modulation structure. The first bonding groove and the second bonding groove are adapted to accommodate different heterogeneous chips; one end of the first interconnecting structure penetrates through the third cladding, the second spacer layer, the second cladding, and the first spacer layer to be connected to the first electrode, and the other end is exposed on the third cladding; one end of the second interconnecting structure penetrates through the third cladding and the second spacer layer to be connected to the second electrode, and the other end is exposed on the third cladding.

[0051] Advantageous effects: The hybrid optical waveguide of the present invention first has different waveguides such as a first modulation waveguide and a second modulation waveguide with different heights on the same substrate layer, forming a hybrid waveguide structure, which facilitates the combination of various silicon-based photonic heterogeneous materials and silicon optical waveguide devices on the same substrate layer, and helps to improve the functional diversity of silicon-based photonic devices on the same substrate layer. Secondly, the thickness of the first spacer layer on the first modulation waveguide can be controlled independently, and the thickness of the second spacer region on the second modulation waveguide can be controlled independently, that is, the thickness of the spacer layer on each modulation waveguide, that is, the interlayer spacing when integrated with heterogeneous materials, can be controlled independently, improving the flexibility of the processing technology while ensuring the characteristics of CMOS process compatibility; Thirdly, a first bonding groove is formed above the first modulation waveguide, and a second bonding groove is formed above the second modulation waveguide, forming a bonding region with a space for bonding and integrating heterogeneous materials. The other non-bonding regions have a cladding layer with the same depth as the groove and much larger than the interlayer spacing of the bonding region, realizing the structural compatibility of the bonding region and the non-bonding region, being more flexible in structural design and process processing, and at the same time ensuring the performance of silicon-based photonic devices on the bonding region and the non-bonding region.

[0052] In a third aspect, the present invention also provides a method for manufacturing a heterogeneous integrated photonic device, including:

[0053] Obtaining a hybrid waveguide structure by using the manufacturing method of the above hybrid waveguide structure;

[0054] Bonding a first heterogeneous chip into the first bonding groove and bonding a second heterogeneous chip into the second bonding groove.

[0055] Advantageous effects: Different waveguides are formed at different height positions in the cladding structure, thereby forming a hybrid waveguide structure, and correspondingly forming grooves with different depths. Different heterogeneous chips are bonded and integrated in the grooves by D2W bonding technology, realizing diversified silicon-based photonic heterogeneous integration on the same wafer, having better CMOS process compatibility, and at the same time improving the flexibility of the application method of D2W bonding technology, and can better meet different application requirements; at the same time, the bonding region and the non-bonding region have better process structure compatibility, making the structural design and process processing more flexible.

[0056] In a fourth aspect, the present invention also provides a heterogeneous integrated photonic device manufactured by using the manufacturing method of the above heterogeneous integrated photonic device, including: a hybrid waveguide structure, a first heterogeneous chip and a second heterogeneous chip. The first heterogeneous chip is disposed in the first bonding groove, and the second heterogeneous chip is disposed in the second bonding groove.

[0057] Beneficial effects: Different waveguides are formed at different height positions in the cladding structure, thereby forming a hybrid waveguide structure, and correspondingly forming grooves with different depths. Different heterogeneous chips are bonded and integrated in the grooves through the D2W bonding technology to achieve diversified silicon photonics heterogeneous integration on the same wafer, which has better CMOS process compatibility. At the same time, the flexibility of the application method of the D2W bonding technology is improved, and different application requirements can be better met; at the same time, the bonding area and the non-bonding area have better process structure compatibility, making the structure design and process processing more flexible. Description of the Drawings

[0058] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0059] Figure 1 It is a schematic flowchart of the preparation method of the hybrid waveguide structure according to an embodiment of the present invention;

[0060] Figure 2 It is a schematic structural diagram of the hybrid waveguide structure according to an embodiment of the present invention after forming the first modulation structure;

[0061] Figure 3 It is a schematic structural diagram of the hybrid waveguide structure according to an embodiment of the present invention after forming the first spacer layer on the first modulation structure;

[0062] Figure 4 It is a schematic structural diagram of the hybrid waveguide structure according to an embodiment of the present invention after forming the first protective layer on the first spacer layer;

[0063] Figure 5 It is a top view schematic diagram of the hybrid waveguide structure according to an embodiment of the present invention after forming the first protective layer, subsequently forming the first bonding groove, and setting the first chip at the first modulation structure;

[0064] Figure 6 It is a schematic structural diagram of the hybrid waveguide structure according to an embodiment of the present invention after forming the second modulation structure;

[0065] Figure 7 It is a schematic structural diagram of the hybrid waveguide structure according to an embodiment of the present invention after forming the second spacer layer on the second modulation structure;

[0066] Figure 8 It is a schematic structural diagram of the hybrid waveguide structure according to an embodiment of the present invention after forming the second protective layer on the second spacer layer;

[0067] Figure 9It is a schematic structural diagram of the hybrid waveguide structure in an embodiment of the present invention after forming a third cladding layer on the second protective layer;

[0068] Figure 10 It is a schematic structural diagram of the hybrid waveguide structure in an embodiment of the present invention after forming a first interconnect structure and a second interconnect structure;

[0069] Figure 11 It is a schematic structural diagram of the complete hybrid waveguide structure in an embodiment of the present invention;

[0070] Figure 12 It is a schematic structural diagram of a silicon-on-insulator substrate adopted by the hybrid waveguide structure in an embodiment of the present invention;

[0071] Figure 13 It is a schematic structural diagram of the hybrid waveguide structure in an embodiment of the present invention after etching the silicon device layer of the silicon-on-insulator substrate to form a first waveguide structure;

[0072] Figure 14 It is a schematic structural diagram of the hybrid waveguide structure in an embodiment of the present invention after forming a second sub-cladding layer on the first waveguide structure and forming a first cladding layer with the first sub-cladding layer below;

[0073] Figure 15 It is a schematic structural diagram of the hybrid waveguide structure in an embodiment of the present invention after etching a first groove in the first cladding layer;

[0074] Figure 16 It is a schematic structural diagram of the hybrid waveguide structure in an embodiment of the present invention after depositing a first metal material in the first groove;

[0075] Figure 17 It is a schematic structural diagram of the hybrid waveguide structure in an embodiment of the present invention after forming a third sub-cladding layer on the first protective layer;

[0076] Figure 18 It is a schematic structural diagram of the hybrid waveguide structure in an embodiment of the present invention after setting an initial second waveguide layer on the third sub-cladding layer;

[0077] Figure 19 It is a schematic structural diagram of the hybrid waveguide structure in an embodiment of the present invention after forming a second waveguide structure after patterning the initial second waveguide layer;

[0078] Figure 20 It is a schematic structural diagram of the hybrid waveguide structure in an embodiment of the present invention after forming a fourth sub-cladding layer on the second waveguide structure and forming a second cladding layer with the third sub-cladding layer below;

[0079] Figure 21 It is a schematic structural diagram of the hybrid waveguide structure in an embodiment of the present invention after etching the second cladding layer and the first spacer layer to form a second groove;

[0080] Figure 22 It is a schematic structural diagram of the hybrid waveguide structure according to an embodiment of the present invention after depositing a second metal material in the second groove body;

[0081] Figure 23 It is a schematic structural diagram of the hybrid waveguide structure according to an embodiment of the present invention after forming a first interlayer through-hole and a second interlayer through-hole in the cladding structure;

[0082] Figure 24 It is a schematic structural diagram of the hybrid waveguide structure according to an embodiment of the present invention after filling a third metal material in the first interlayer through-hole and the second interlayer through-hole to form a first interlayer interconnect conductive pillar and a second interlayer interconnect conductive pillar;

[0083] Figure 25 It is a schematic structural diagram of the hybrid waveguide structure according to an embodiment of the present invention after providing a fourth cladding layer covering the first pad and the second pad on the third cladding layer;

[0084] Figure 26 It is a schematic structural diagram of the hybrid waveguide structure according to an embodiment of the present invention after etching the cladding structure above the first modulation structure and the second modulation structure to expose the first protective layer and the second protective layer;

[0085] Figure 27 It is a schematic structural diagram of the hybrid waveguide structure according to an embodiment of the present invention after removing the first protective layer and the second protective layer;

[0086] Figure 28 It is a schematic structural diagram of the heterogeneous integrated photonic device according to an embodiment of the present invention after disposing an initial first heterogeneous chip in the first bonding groove and disposing an initial second heterogeneous chip in the second bonding groove;

[0087] Figure 29 It is a schematic structural diagram of the heterogeneous integrated photonic device according to an embodiment of the present invention.

[0088] Explanation of reference numerals:

[0089] A, the first protective layer; B, the second protective layer; C, the cladding structure;

[0090] D, the first heterogeneous chip; D0, the first substrate; D1, the first buried oxide layer; D2, the first chip body; E, the second heterogeneous chip; E0, the second substrate; E1, the second buried oxide layer; E2, the second chip body;

[0091] 1. Substrate layer; 2. First cladding layer; 201. First sub-cladding layer; 202. Second sub-cladding layer; 203. First groove; 3. First waveguide structure; 301. First modulation waveguide; 302. First transmission waveguide; 300. Initial first waveguide layer; 4. First electrode; 400. First metal material; 5. First spacer layer; 6. Second cladding layer; 601. Third sub-cladding layer; 602. Fourth sub-cladding layer; 603. Second groove; 7. Second waveguide structure; 701. Second modulation waveguide; 702. Second transmission waveguide; 700. Initial second waveguide layer; 8. Second electrode; 800. Second metal material; 9. Second spacer layer; 10. Third cladding layer; 11. First interconnect structure; 1100. First interlayer through hole; 1101. First interlayer interconnect conductive pillar; 1102. First pad; 12. Second interconnect structure; 1200. Second interlayer through hole; 1201. Second interlayer interconnect conductive pillar; 1202. Second pad; 13. First bonding groove; 14. Second bonding groove; 15. Fourth cladding layer; 1501. First pad window; 1502. Second pad window. Detailed implementation manners

[0092] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only parts related to the present invention rather than all structures are shown in the drawings. In the following description, the description of well-known structures and technologies is omitted to avoid unnecessarily confusing the concepts of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the drawings. These figures are not drawn to scale, and for the purpose of clear expression, some details are enlarged, and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0093] Referring to Figures 1 to 27 , this embodiment provides a preparation method for a hybrid waveguide structure. Figure 1 As shown in the flowchart of this preparation method, the preparation method includes the following steps:

[0094] Step S101: Provide a substrate layer 1, and a first cladding layer 2 is disposed on one side surface of the substrate layer 1.

[0095] Exemplarily, the substrate layer 1 of this embodiment may be a silicon wafer, and the first cladding layer 2 is made of silicon dioxide material.

[0096] Step S102: Form a first modulation structure. The first modulation structure includes a first modulation waveguide 301 and a first electrode 4 embedded in the side of the first cladding layer 2 facing away from the substrate layer 1, and the first modulation waveguide 301 and the first electrode 4 are spaced apart.

[0097] Exemplarily, on the side of the first cladding layer 2 facing away from the substrate layer 1, a first modulation waveguide 301 and a first electrode 4 embedded in the first cladding layer 2 are provided. The first electrode 4 is spaced apart on both sides of the first modulation waveguide 301. The first electrode 4 can be used to control the refractive index of a subsequent electro-optic heterogeneous chip (i.e., the first heterogeneous chip D) placed above it through an electric field, so that this heterogeneous chip and the first modulation waveguide 301 are coupled and integrated into a composite structure. The effective refractive index of this composite structure will change with the change of the refractive index of the heterogeneous chip. At the same time, the optical field will also change the phase, intensity, etc. of the light wave with the changing effective refractive index, thereby realizing high-speed electro-optic modulation. The coupling (modulation) efficiency between the modulation waveguide and the heterogeneous chip is related to the electric field distribution (including electrode spacing, electrode material and thickness, etc.), the interlayer spacing distance, the interlayer spacing material and the waveguide structure. Figure 2 Only one first modulation waveguide 301 and two first electrodes 4 respectively disposed on both sides of it are shown. Of course, the first modulation structure includes multiple first modulation waveguides 301 and multiple first electrodes 4, and the first modulation waveguides 301 and the first electrodes 4 are arranged alternately, and the first electrodes 4 are on both sides of each first modulation waveguide 301. The first modulation waveguide 301 of this embodiment is a silicon waveguide, and the first electrode 4 is a metal copper electrode. It should be noted that the thickness and spacing of the electrodes are determined by the structural configuration relationship between the heterogeneous chip - modulation waveguide - electric field to achieve the electric field distribution required to meet the target modulation efficiency. In this embodiment, the thickness of the first electrode 4 is usually greater than 0.5 μm, and the spacing between them is usually less than 10 μm to obtain high modulation efficiency.

[0098] Step S103: Form a first spacer layer 5 on the side surface of the first cladding layer 2 facing away from the substrate layer 1, and the first spacer layer 5 covers the first modulation structure.

[0099] Reference Figure 3 The first spacer layer 5 of this embodiment is the bonding interface for subsequently setting the heterogeneous chip, and is prepared with silicon dioxide material. The specific setting of its thickness matches the characteristics of the heterogeneous material to be bonded to achieve the best modulation performance.

[0100] Step S104: Form a first protective layer A on the first spacer layer 5. The first protective layer A covers at least a part of the first modulation waveguide 301 and a part of the first electrode 4.

[0101] Reference Figure 4 and Figure 5 , the first protective layer A of this embodiment covers at least the first electrode 4 and the first modulation waveguide 301 in the modulation region to ensure that the first modulation structure is not affected in subsequent processes and to ensure the modulation performance. Specifically, in this embodiment, the size of the first protective layer A is set to be greater than 1 mm × 1 mm. Taking the width direction as the left - right direction and the length direction as the up - down direction in Figure 5 as an example for illustration, the first protective layer A only needs to cover a certain length according to specific design requirements, usually several millimeters to several centimeters; Figure 5 only one first modulation waveguide 301 is shown for illustration in , and actually multiple similar first modulation waveguides 301 can be arranged side by side along the width direction. To achieve electro - optical modulation, the upper heterogeneous chip is arranged at a height closer to the lower modulation waveguide for coupling integration. Taking the first modulation structure as an example, in an ideal state, the subsequent heterogeneous chip only needs to cover Figure 5 the left - most waveguide arm (left arm) of the first modulation waveguide 301 shown, and the size is slightly wider than the left arm (that is, the heterogeneous chip only needs to be a few micrometers wide), and then the first electrode 4 is arranged on both sides of the heterogeneous chip. The right arm of the first modulation waveguide 301 can be set in the same way. It should be clear that the first modulation waveguide 301 is integrally connected. However, in actual situations, the D2W bonding technology compatible with CMOS has a size of usually several hundred micrometers or even more than one millimeter during the dicing process of the heterogeneous chip. Therefore, in this embodiment, a large - size heterogeneous chip is selected to cover multiple multi - terminal waveguides to be modulated. However, the configuration of the first electrode 4 can be flexibly selected. For example, Figure 5 although the heterogeneous chip covers both the left arm and the right arm from left to right, the first electrode 4 can only be configured on both sides of the left arm, and no electrode is set on the right side of the right arm. In this way, the electric field only changes the refractive index of the upper part of the heterogeneous chip on the left arm, rather than the entire heterogeneous chip, thereby realizing single - end modulation of only the left arm. The right side of the right arm can also be set as Figure 5 the first electrode 4, but the power supply can be selected to be on or off. When the power supply is on, it is double - end modulation (the strip - shaped electrode in the middle of the modulation waveguide is shared), and when the power supply is off, it is also single - end modulation. Therefore, in actual devices, a large - size heterogeneous chip is usually set to cover multiple uncorrelated and independent waveguide devices ( Figure 5For illustration purposes, only one waveguide device is taken as an example. That is, electrodes can be arranged on both sides of the modulation waveguide to be modulated, which is highly flexible. Based on this, when setting the first protective layer A, the first protective layer A usually extends beyond the edge of the outermost modulation waveguide by a certain distance in the width direction, and of course, it also includes covering the outermost first electrode 4. The specific parameter selection will be described in detail later.

[0102] Step S105: Form a second cladding layer 6 on the surface of the first spacer layer 5 facing away from the substrate layer 1. The second cladding layer 6 covers the first protective layer A and forms a continuous plane on the surface of the first protective layer A facing away from the substrate layer 1.

[0103] Exemplarily, referring to Figure 6 , the second cladding layer 6 of this embodiment is made of silica material. The second cladding layer 6 is disposed entirely on the first spacer layer 5 and covers the first protective layer A, forming a flat plane within a certain thickness range above the first protective layer A.

[0104] Step S106: Form a second modulation structure. The second modulation structure includes a second modulation waveguide 701 and a second electrode 8 embedded in the side of the second cladding layer 6 facing away from the substrate layer 1, and is arranged in a staggered manner with the first modulation structure. The second modulation waveguide 701 and the second electrode 8 are arranged at intervals.

[0105] Continuing to refer to Figure 6 , a second modulation waveguide 701 and a second electrode 8 embedded in the second cladding layer 6 are arranged on the side of the second cladding layer 6 facing away from the substrate layer 1. Similarly, the second electrodes 8 are arranged at intervals on both sides of the second modulation waveguide 701. The second electrodes 8 are used to control the refractive index of another heterogeneous chip (second heterogeneous chip E) with an electro-optic effect placed above them through an electric field, so that this heterogeneous chip is integrated with the second modulation waveguide 701 into another composite structure. The effective refractive index of this composite structure will also change with the change of the refractive index of the heterogeneous chip. At the same time, its optical field will also change the phase, intensity, etc. of the light wave with the changing effective refractive index, thereby realizing high-speed electro-optic modulation. Figure 6Only one second modulation waveguide 701 and two second electrodes 8 respectively arranged on both sides thereof are also shown. Of course, the second modulation structure includes a plurality of second modulation waveguides 701 and a plurality of second electrodes 8, and the second modulation waveguides 701 and the second electrodes 8 are arranged alternately, and both sides of each second modulation waveguide 701 are second electrodes 8. The second modulation waveguide 701 of this embodiment is a silicon nitride waveguide, and the second electrode 8 is a metal copper electrode. According to the characteristics of the silicon nitride waveguide and the heterogeneous chip disposed thereon, the second electrode 8 can extend into the first spacer layer 5, that is, the sum of the thicknesses of the second cladding layer 6 and the first spacer layer 5 is greater than or equal to the thickness of the second electrode 8, but there must be a certain interval between the second modulation waveguide 701 and the first modulation waveguide 301 in the vertical direction to ensure that the two modulation waveguides are isolated from each other.

[0106] Step S107, form a second spacer layer 9 on the surface of the second cladding layer 6 facing away from the substrate layer 1, and the second spacer layer 9 covers the second modulation structure.

[0107] Reference Figure 7 , similarly, the second spacer layer 9 of this embodiment is a bonding interface for subsequently disposing another heterogeneous chip. The second spacer layer 9 is also made of a silica material, and the specific setting of its thickness matches the characteristics of the heterogeneous material to be bonded to achieve the best modulation performance.

[0108] Step S108, form a second protective layer B on the second spacer layer 9, and the second protective layer B covers at least part of the second modulation waveguide 701 and part of the second electrode 8.

[0109] Reference Figure 8 , the second protective layer B of this embodiment covers at least the second electrode 8 and the second modulation waveguide 701 in another modulation region to ensure that the second modulation structure is not affected in subsequent processes and ensure the modulation performance. Similar to the first modulation structure and the first protective layer A, the size of the second protective layer B is also set to 1 mm × 1 mm. The second protective layer B only needs to cover a certain length according to specific design requirements, usually several millimeters to several centimeters, but when covering in the width direction, the second protective layer B usually extends a certain distance beyond the edge of the outermost waveguide to be modulated, and of course, it also includes covering the outermost second electrode 8. The specific parameter selection will be described in detail later.

[0110] Step S109, form a third cladding layer 10 on the surface of the second spacer layer 9 facing away from the substrate layer 1. The third cladding layer 10 covers the second protective layer B and forms a continuous plane on the surface of the second protective layer B facing away from the substrate layer 1.

[0111] See Figure 9, the third cladding layer 10 is also deposited by CVD using a silica material, with a thickness range of 0.5 μm to 1.5 μm; at least part of the regions where the first modulation structure and the second modulation structure are located are bonding regions or modulation regions that need to be bonded to heterogeneous chips, and other regions with waveguide structures or other optical devices are non-bonding regions. The non-bonding regions do not need to be bonded to other structures, and the thickness requirement of the cladding layer thereon is thicker than that of the bonding regions. For example, the layer spacing between the heterogeneous chip and the modulation waveguide in the bonding region needs to satisfy less than 150 nm, while the thickness of the cladding layer in the non-bonding region needs to satisfy greater than 1 μm. Therefore, the third cladding layer 10 here is used to initially meet the thickness requirement of the cladding layer in the non-bonding region and improve the process structure compatibility between the bonding region and the non-bonding region.

[0112] Step S1010, form a first interconnect structure 11 and a second interconnect structure 12. One end of the first interconnect structure 11 extends into the third cladding layer 10, the second spacer layer 9, the second cladding layer 6, and the first spacer layer 5 to connect to the first electrode 4, and the other end is exposed on the third cladding layer 10; one end of the second interconnect structure 12 extends into the third cladding layer 10 and the second spacer layer 9 to connect to the second electrode 8, and the other end is exposed on the third cladding layer 10.

[0113] Reference Figure 10 , both the first interconnect structure 11 and the second interconnect structure 12 are made of metal materials. The first interconnect structure 11 penetrates through each silica layer above the first electrode 4 until it connects to the first electrode 4, and the other end is exposed to the external environment for easy connection to an external power supply to apply a voltage to the first electrode 4. Similarly, the second interconnect structure 12 penetrates through each silica layer above the second electrode 8 until it connects to the second electrode 8, and the other end is exposed to the external environment for easy connection to an external power supply to apply a voltage to the second electrode 8, thereby enabling the first electrode 4 to form an electric field acting on the first modulation waveguide 301 and the second electrode 8 to form an electric field acting on the second modulation waveguide 701.

[0114] Step S1011, form a first bonding groove 13 above the first modulation structure. The first bonding groove 13 is adapted to expose the first spacer layer 5, and form a second bonding groove 14 above the second modulation structure. The second bonding groove 14 is adapted to expose the second spacer layer 9. The first bonding groove 13 and the second bonding groove 14 are adapted to accommodate different heterogeneous chips.

[0115] Reference Figure 11, remove the third cladding layer 10, the second spacer layer 9, the second cladding layer 6 and the first protective layer A itself located on the first protective layer A, form a first bonding groove 13 above the first modulation structure. There is a first spacer layer 5 between the first bonding groove 13 and the first modulation waveguide 301. A heterogeneous chip that can achieve an optimal match with the first modulation waveguide 301 is suitable for bonding to the first spacer layer 5, so as to be coupled and integrated with the first modulation waveguide into a composite structure, and finally achieve efficient electro-optic modulation under the electric field control of the first electrode. Similarly, at the same time, remove the third cladding layer 10 and the second protective layer B itself located on the second protective layer B to form a second bonding groove 14 above the second modulation structure. There is a second spacer layer 9 between the second bonding groove 14 and the second modulation waveguide 701. A heterogeneous chip that can achieve an optimal match with the second modulation waveguide 701 is suitable for bonding to the second spacer layer 9, so as to be coupled and integrated with the second modulation waveguide 701 into another composite structure, and finally achieve efficient electro-optic modulation under the electric field control of the second electrode 8.

[0116] In summary, through the preparation method of the hybrid optical waveguide in this embodiment, first, different waveguides such as the first modulation waveguide 301 and the second modulation waveguide 701 with different heights can be obtained on the same substrate layer 1, which is convenient for realizing the combination of various silicon-based heterogeneous materials and silicon optical waveguide devices on the same substrate layer 1, and helps to improve the functional diversity of silicon optical devices on the same substrate layer 1. Secondly, the thickness of the first spacer layer 5 on the first modulation waveguide 301 can be controlled independently, and the thickness of the second spacer region on the second modulation waveguide 701 can be controlled independently, that is, the thickness of the spacer layer on each modulation waveguide, that is, the interlayer spacing when integrated with heterogeneous materials, can be controlled independently, improving the flexibility of the processing technology while ensuring the characteristics of CMOS process compatibility; thirdly, by opening a first bonding groove 13 above the first modulation waveguide 301 and a second bonding groove 14 above the second modulation waveguide 701, a bonding region with a space for bonding and integrating heterogeneous materials is formed. Other non-bonding regions have a cladding layer with the same thickness as the groove and much larger than the interlayer spacing of the bonding region, realizing the structural compatibility of the bonding region and the non-bonding region, and at the same time ensuring the flexibility of the silicon optical device in structural design and process processing.

[0117] Reference Figure 12, in this embodiment, a commercially mature silicon-on-insulator (SOI) substrate is adopted. The SOI substrate includes a silicon substrate, a buried oxide layer of silicon dioxide, and a silicon device layer arranged in sequence from bottom to top. The silicon substrate layer can be used as the above-mentioned substrate layer 1, the buried oxide layer of silicon dioxide is used as a part of the first cladding layer 2, that is, the first sub-cladding layer 201 in the first cladding layer 2, and the silicon device layer can be used as the initial material layer for preparing the subsequent first modulation waveguide 301, that is, the initial first waveguide layer 300. Specifically, the thickness of the buried oxide layer of silicon dioxide can be selected from 1 μm to 3 μm, and the thickness of the silicon device layer can be selected from 100 nm to 300 nm. Of course, the substrate layer 1 can be the above-mentioned conventional silicon material, and the first cladding layer 2 made of silicon dioxide material is directly arranged on one side surface of the substrate layer 1.

[0118] On the basis of adopting the above SOI substrate, the step S102 of forming the first modulation structure includes the following steps:

[0119] Step S1021, pattern the initial first waveguide layer 300 to form the first modulation waveguide 301.

[0120] Reference Figure 13 , through a photolithography and etching process, pattern the entire initial first waveguide layer 300, and at the same time form a plurality of first modulation waveguides 301.

[0121] Step S1022, form a second sub-cladding layer 202 on the side surface of the first sub-cladding layer 201 facing away from the substrate layer 1. The second sub-cladding layer 202 covers the first modulation waveguide 301, and the second sub-cladding layer 202 and the first sub-cladding layer 201 constitute the first cladding layer 2.

[0122] Reference Figure 14 , exemplarily, in this embodiment, a chemical vapor deposition (CVD) technology is used to deposit a silicon dioxide material with a thickness of 0.2 μm to 1 μm, and then through a chemical mechanical polishing (CMP) process, it is planarized and thinned to a thickness of 50 nm to 150 nm to form the second sub-cladding layer 202. The second sub-cladding layer 202 and the first sub-cladding layer 201 are made of the same material and jointly form the first cladding layer 2.

[0123] Step S1023, etch away part of the first cladding layer 2 to form a first groove 203 in the region of the first cladding layer 2 spaced apart from the first modulation waveguide 301.

[0124] Reference Figure 15 , in this embodiment, a first groove 203 with a depth between 0.5 μm and 1.5 μm and a width greater than 3 μm is formed in the first cladding layer 2 through a photolithography and etching process.

[0125] Step S1024: Deposit a first metal material 400 on the surface of the first cladding layer 2 facing away from the substrate layer 1. The first metal material 400 covers and fills the first groove 203.

[0126] Reference Figure 16 , in this embodiment, a physical vapor deposition (PVD) technique is further used to deposit a thin film of the first metal material 400 with a thickness between 1 μm and 3 μm. For example, the first metal material 400 is selected as a metal copper thin film to completely fill the above-mentioned first groove 203. Of course, other metal electrode materials that can be used in the CMP process are not excluded. As Figure 16 shown, it can be understood that while filling the first groove 203, a certain amount of the first metal material 400 will also be deposited on the surface of the first cladding layer 2.

[0127] Step S1025: Perform a planarization process on the side where the first metal material 400 is located until the first modulation waveguide 301 is exposed, forming a first electrode 4 within the first groove 203, and the surface of the first electrode 4, the surface of the first modulation waveguide 301, and the surface of the first cladding layer 2 are flush with each other.

[0128] Exemplarily, the first metal material 400 is planarized and thinned through a CMP process until the first metal material 400 deposited on the first cladding layer 2 and a part of the second sub-cladding layer 202 are completely removed, until it stops at the surface of the first modulation waveguide 301, so that the first modulation waveguide 301, the first electrode 4 within the first groove 203, and the surface of the first cladding layer 2 are flush with each other. Specifically refer to Figure 2 , thereby realizing precise control of the thickness of the first spacer layer 5 on the first modulation structure. The second sub-cladding layer 202 covering the first modulation waveguide 301 plays a buffering role in this process to avoid direct damage to the first modulation waveguide 301 when the CMP process stops directly on it. In fact, in the actual process, a relative displacement within ±50 nm between the upper surface of the first electrode 4 and the upper surface of the first modulation waveguide 301 is allowed, improving the processing tolerance and efficiency.

[0129] In summary, by preparing the first cladding layer 2 in two steps to cover the first modulation waveguide 301 from above and below, it is ensured to the greatest extent that the first modulation waveguide 301 is not damaged when preparing the first electrode 4; at the same time, after first completely filling the first groove 203 with the first metal material 400, the CMP process is then used to polish and remove the excess first metal material 400 and the first cladding layer 2 located on the first modulation structure, achieving the flush degree of the upper surfaces of the first modulation waveguide 301, the first electrode 4, and the first cladding layer 2 to the greatest extent, facilitating precise control of the thickness of the first spacer layer 5 prepared subsequently on the first modulation structure and ensuring the modulation performance of the first modulation structure.

[0130] In one embodiment, the above-mentioned second cladding layer 6 can be formed in two steps successively. First, a third sub-cladding layer 601 is formed over the entire surface of the first spacer layer 5. The third sub-cladding layer 601 covers the first protective layer A. Since this is an implementation, the second modulation structure can be directly formed by embedding inside the third sub-cladding layer 601, such as by etching, deposition, etc. At this time, the thickness of the third sub-cladding layer 601 should be greater than the thickness of the second electrode 8. As another implementation, first as Figure 17 shown, prepare the third sub-cladding layer 601. At this time, the third sub-cladding layer 601 only needs to be able to cover the first protective layer A. The third sub-cladding layer 601 is a part of the second cladding layer 6, and the overall second cladding layer 6 is prepared during the process of preparing the second modulation structure.

[0131] Based on the latter method of separately preparing the second cladding layer 6, the step S106 of forming the second modulation structure includes the following steps:

[0132] Step S1061, on the surface of the third sub-cladding layer 601 facing away from the substrate layer 1, an initial second waveguide layer 700 is formed over the entire surface by plasma-enhanced chemical vapor deposition.

[0133] Referring to Figure 18 , the initial second waveguide layer 700 is formed by plasma-enhanced chemical vapor deposition (PECVD). The initial second waveguide layer 700 is made of silicon nitride material. The deposition temperature is between 300°C and 600°C. The thickness range of the initial second waveguide layer 700 is 200 nm to 500 nm, and the refractive index range is 1.95 to 2.15. It should be noted that low-pressure chemical vapor deposition (LPCVD) cannot be used when preparing the initial second waveguide layer 700 because the LPCVD process has a relatively high process temperature between 600°C and 800°C, which is prone to problems such as metal ion diffusion and melting, and there are also risks such as stress and film cracking due to different thermal expansion coefficients between the metal-dielectric thin films. Therefore, due to strict pollution control in the traditional CMOS process line, generally, the LPCVD process is not allowed to process wafer samples with a subsequent metal process as a front-end process to avoid contamination of the LPCVD process chamber by metal ions.

[0134] Step S1062, pattern the initial second waveguide layer 700 to form the second modulation waveguide 701.

[0135] Referring to Figure 19 , the entire initial second waveguide layer 700 is patterned by photolithography and etching processes, and at the same time, a plurality of second modulation waveguides 701 are formed.

[0136] Step S1063: On the surface of the third sub-cladding layer 601 facing away from the substrate layer 1, a fourth sub-cladding layer 602 is formed. The fourth sub-cladding layer 602 covers the second modulation waveguide 701. The fourth sub-cladding layer 602 and the third sub-cladding layer 601 constitute the second cladding layer 6.

[0137] Reference Figure 20 , exemplarily, in this embodiment, chemical vapor deposition (CVD) technology is used to deposit a silicon dioxide material with a thickness of 0.2 μm to 1 μm, and then chemical mechanical polishing (CMP) process is used to planarize and thin it to a thickness of 50 nm to 150 nm to form the fourth sub-cladding layer 602. The fourth sub-cladding layer 602 and the third sub-cladding layer 601 are made of the same material and jointly form the first cladding layer 2.

[0138] Step S1064: Part of the second cladding layer 6 is etched away to form a second groove 603 in the region of the second cladding layer 6 spaced apart from the second modulation waveguide 701.

[0139] Exemplarily, a second groove 603 with a depth between 0.5 μm and 1.5 μm and a width greater than 3 μm can be formed in the second cladding layer 6 by photolithography etching process. For specific reference in this embodiment Figure 21 , the second groove 603 penetrates through the second cladding layer 6 and the first spacer layer 5.

[0140] Step S1065: A second metal material 800 is deposited on the surface of the second cladding layer 6 facing away from the substrate layer 1. The second metal material 800 covers the surface of the second cladding layer 6 and fills the second groove 603.

[0141] Reference Figure 22 , in this embodiment, physical vapor deposition (PVD) technology is further used to deposit a second metal material 800 thin film with a thickness between 1 μm and 3 μm. For example, the first metal material 400 is selected as a copper thin film to completely fill the above-mentioned second groove 603. Of course, other metal electrode materials that can be used for the CMP process are not excluded. As Figure 22 shown, it can be understood that while filling the second groove 603, a certain amount of the second metal material 800 will also be deposited on the surface of the second cladding layer 6, and the second cladding layer 6 realizes the protection of the first modulation structure.

[0142] Step S1066: The side where the second metal material 800 is located is planarized until the second modulation waveguide 701 is exposed, forming a second electrode 8 in the second groove 603, and the surface of the second electrode 8 is flush with the surface of the second modulation waveguide 701.

[0143] Exemplarily, the second metal material 800 is planarized and thinned by a CMP process until the second metal material 800 deposited on the second cladding 6 and a part of the fourth sub-cladding 602 are completely removed, until it stops at the surface of the second modulation waveguide 701, so that the second modulation waveguide 701, the second electrode 8 in the second groove body 603 and the surface of the second cladding 6 are flush with each other. For specific reference, see Figure 6 , thereby realizing precise control of the thickness of the second spacer layer 9 on the second modulation structure. The fourth sub-cladding 602 covering the second modulation waveguide 701 plays a buffering role in this process to avoid direct damage to the second modulation waveguide 701 when the CMP process stops directly on it. In fact, in the actual process, it is also allowed that the upper surface of the second electrode 8 has a relative displacement within ±50 nm with respect to the upper surface of the second modulation waveguide 701, improving the processing tolerance and efficiency.

[0144] In summary, by preparing the second cladding 6 in two steps to cover the second modulation waveguide 701 up and down, it is ensured to the greatest extent that the second modulation waveguide 701 is not damaged when the second electrode 8 is prepared; at the same time, after first depositing the second metal material 800 that completely fills the second groove body 603, the CMP process is used to polish and remove the excess second metal material 800 and the second cladding 6 located on the second modulation structure, so as to achieve the flush degree of the upper surfaces of the second modulation waveguide 701, the second electrode 8 and the second cladding 6 to the greatest extent, which is convenient for precisely controlling the thickness of the second spacer layer 9 prepared on the second modulation structure subsequently and ensuring the modulation performance of the second modulation structure.

[0145] As a preferred embodiment, in the step S102 of forming the first modulation waveguide 301, more specifically, in the step S1021 of patterning the initial first waveguide layer 300 to form the first modulation waveguide 301, it further includes: synchronously forming a first transmission waveguide 302 connected to the first modulation waveguide 301, and the first transmission waveguide 302 and the first modulation waveguide 301 constitute the first waveguide structure 3. Similarly, in the step S106 of forming the second modulation waveguide 701, in the step S1062 of patterning the initial second waveguide layer 700 to form the second modulation waveguide 701, it further includes: synchronously forming a second transmission waveguide 702 connected to the second modulation waveguide 701, and the second transmission waveguide 702 and the second modulation waveguide 701 constitute the second waveguide structure 7. The first modulation waveguide 301 and the first transmission waveguide 302 in the first waveguide structure 3 are prepared synchronously, and the second modulation waveguide 701 and the second transmission waveguide 702 in the second waveguide structure 7 are prepared synchronously, improving the preparation efficiency of the waveguide structure.

[0146] The projection of the first transmission waveguide 302 on the second transmission waveguide 702 on the substrate layer 1 at least partially overlaps to form a composite transmission waveguide, which is suitable for processing the input optical signal and transmitting the processed optical signal to the first modulation waveguide 301 and the second modulation waveguide 701 respectively. The first transmission waveguide 302 and the second transmission waveguide 702 form a double-layer partially overlapping composite waveguide in the non-bonding region. First, the working wavelength band can be extended. For example, the silicon waveguide has a large absorption loss in the short wavelength band, while the silicon nitride waveguide has a wider optical bandgap. After the two are combined, the silicon nitride waveguide can make up for the working limitation in the short wavelength band. Second, the silicon nitride has a small non-linear loss, and combining with the silicon waveguide can increase the power threshold of the non-linear effect, which is suitable for non-linear optical processes. Third, the silicon nitride waveguide has good thermal stability, which helps to improve the thermal stability during the period. Fourth, the silicon nitride waveguide has a low transmission loss in the visible light to near-infrared wavelength band. After being combined with the silicon waveguide, it can reduce the energy loss and coupling loss of light during transmission and improve the transmission efficiency of the optical signal. Finally, both silicon nitride and silicon materials are compatible with the CMOS process, and the composite transmission waveguide can be realized by existing semiconductor processes, which is convenient for integration with active devices (such as modulators, detectors) and electronic circuits, and promotes the development of photon-electronic hybrid integrated systems.

[0147] In one embodiment, the thickness ranges of the above-mentioned first spacer layer 5 and second spacer layer 9 are both 50 nm to 150 nm, and the surface roughnesses of the sides of the first spacer layer 5 and the second spacer layer 9 facing away from the substrate layer 1 are both less than 0.5 nm, and the surface undulation is less than 50 nm.

[0148] Specifically, the first spacer layer 5 and the second spacer layer 9 can be set to different thicknesses according to the heterogeneous chips to be bonded to ensure optimal optoelectronic modulation performance. The surfaces of the first spacer layer 5 and the second spacer layer 9 will serve as the bonding interfaces for subsequent heterogeneous silicon photonic chips, and it is required that their surface roughnesses are less than 0.5 nm and the surface undulation (i.e., flatness) is less than 50 nm to ensure the bonding quality. There are usually two preparation schemes: one is to directly deposit silicon dioxide material with a thickness between 50 nm and 150 nm by CVD, and this scheme is easy to accurately control the thickness; the other scheme is to deposit silicon dioxide material with a thickness between 0.2 μm and 1 μm by CVD process, and then perform CMP planarization to thin it to a thickness of 50 nm to 150 nm. This scheme has a large thickness control deviation, but the surface roughness is easier to control.

[0149] In one embodiment, the wet etching selectivity of the first protective layer A to the first spacer layer 5 is greater than 100:1; the wet etching selectivity of the second protective layer B to the second spacer layer 9 is greater than 100:1.

[0150] For the selection of materials for the first protective layer A and the second protective layer B, it is required that they have a sufficiently high etching selectivity for the materials of the underlying first spacer layer 5 and second spacer layer 9 during subsequent wet etching, so as to avoid risks such as etching damage and increased roughness to the bonding interface. Specifically, the materials of the first protective layer A and the second protective layer B can be aluminum thin films deposited by PVD, titanium nitride thin films (TiN) deposited by PVD or CVD, silicon nitride thin films deposited by CVD, etc. The thickness range of the first protective layer A and the second protective layer B is 50nm to 300nm.

[0151] In one embodiment, the above step S1010 of forming the first interconnect structure 11 and the second interconnect structure 12 includes the following steps:

[0152] Step S1010a, forming a first interlayer via 1100 above the first electrode 4 not covered by the first protective layer A, and forming a second interlayer via 1200 above the second electrode 8 not covered by the second protective layer B. The first interlayer via 1100 penetrates through the third cladding layer 10, the second spacer layer 9, the second cladding layer 6 and the first spacer layer 5 to connect the first electrode 4 and the external environment. The second interlayer via 1200 penetrates through the third cladding layer 10 and the second spacer layer 9 to connect the second electrode 8 and the external environment.

[0153] Reference Figure 23 and Figure 11 , respectively form a first interlayer via 1100 corresponding to the first electrode 4 and a second interlayer via 1200 corresponding to the second electrode 8 in the dielectric layer of the cladding structure C formed of silica material through photolithography and etching processes. For ease of explanation, from this step on, the individual silica layers arranged from bottom to top in the above steps are collectively referred to as the cladding structure C. At this time, the first interlayer via 1100 penetrates through the third cladding layer 10, the second spacer layer 9, the second cladding layer 6 and the first spacer layer 5 in the cladding structure C; the second interlayer via 1200 penetrates through the third cladding layer 10 and the second spacer layer 9. In this embodiment, the first interlayer via 1100 and the second interlayer via 1200 are square through-holes, and the side length dimension is between 0.5μm and 1.5μm. Of course, circular through-holes can also be selected, and the specific shape is not limited.

[0154] Step S1010b, filling the first interlayer via 1100 and the second interlayer via 1200 with a third metal material respectively, so as to form a first interlayer interconnect conductive pillar 1101 in the first interlayer via 1100 and a second interlayer interconnect conductive pillar 1201 in the second interlayer via 1200.

[0155] Reference Figure 24, through copper electroplating or tungsten CVD process, the first interlayer vias 1100 and the second interlayer vias 1200 are completely filled, and CMP planarization thinning is performed with the upper surface of the third cladding layer 10 made of silicon oxide material as the stop layer.

[0156] Step S1010c, forming a first pad 1102 and a second pad 1202 on the surface of the third cladding layer 10 facing away from the substrate layer 1. The first pad 1102 is connected to the first interlayer interconnect conductive pillar 1101 to form a first interconnect structure 11, and the second pad 1202 is connected to the second interlayer interconnect conductive pillar 1201 to form a second interconnect structure 12.

[0157] Deposit a metal thin film with a thickness between 0.5 μm and 1 μm, such as an aluminum thin film, by PVD method, and then perform photolithography and etching processes to form the first pad 1102 and the second pad 1202 with a size greater than 50 μm × 50 μm. The first pad 1102 is connected to the first interlayer interconnect conductive pillar 1101, and the second pad 1202 is connected to the second interlayer interconnect conductive pillar 1201, as Figure 10 shown.

[0158] In summary, in this embodiment, by setting the interconnect structure combining conductive pillars and pads, on the one hand, the conductive pillars with a smaller cross-sectional area are extended into the cladding structure C to be connected to the electrodes, and on the other hand, pads with a larger area are set to facilitate external wire bonding, thereby realizing the reliable electrical connection performance of the first interconnect structure 11 and the second interconnect structure 12.

[0159] In one embodiment, the step S1011 of forming the first bonding groove 13 above the first modulation structure and the second bonding groove 14 above the second modulation structure includes the following steps:

[0160] Step S1011a, forming a fourth cladding layer 15 on the entire surface of the side of the third cladding layer 10 facing away from the substrate layer 1. The fourth cladding layer 15 covers the first interconnect structure 11 and the second interconnect structure 12.

[0161] Reference Figure 25 , deposit silicon oxide material with a thickness between 1 μm and 3 μm by CVD method as the fourth cladding layer 15. The fourth cladding layer 15 covers the first interconnect structure 11 and the second interconnect structure 12 to play a protective role for the two in subsequent processes.

[0162] Step S1011b, etch away the fourth cladding layer 15, the third cladding layer 10, the second spacer layer 9, the second cladding layer 6 and the first protective layer A located on the first protective layer A to form a first bonding groove 13 above the first modulation structure. The width of the first bonding groove 13 is smaller than the width of the first protective layer A. At the same time, etch away the fourth cladding layer 15, the third cladding layer 10 and the second protective layer B located on the second protective layer B to form a second bonding groove 14 above the second modulation structure. The width of the second bonding groove 14 is smaller than the width of the second protective layer B.

[0163] Reference Figure 26 , first, through photolithography and etching processes, etch the cladding structure C to the first spacer layer 5 and the second spacer layer 9 corresponding to the first protective layer A and the second protective layer B respectively to form bonding area grooves with different depths, and the width thereof is slightly smaller than the width of the protective layer. After that, if the materials of the first protective layer A and the second protective layer B are titanium nitride, wet etching can be carried out in a hot phosphoric acid (H3PO4) solution at a temperature between 50 °C and 100 °C and a concentration between 70% and 90% to remove the first protective layer A and the second protective layer B, as Figure 27 shown, and the corresponding etching solutions can be selected for the remaining protective layer materials according to their standard wet etching processes.

[0164] Step S1011c, etch away the fourth cladding layer 15 located on the first pad 1102 and the second pad 1202 to form a first pad window 1501 and a second pad window 1502.

[0165] Reference Figure 11 , through photolithography and etching processes, form a first pad window 1501 and a second pad window 1502 in the fourth cladding layer 15 corresponding to the first pad 1102 and the second pad 1202 to facilitate wire bonding of the first pad 1102 and the second pad 1202.

[0166] In summary, in this embodiment, when forming the first bonding groove 13 and the second bonding groove 14, step-by-step processing is adopted. First, the silicon dioxide material of the cladding structure C is removed, and then the protective layer material is removed. The morphology of the step-by-step processed bonding groove is more accurate, and damage to the surface morphology of the spacer layer can be avoided, ensuring the surface performance of the spacer layer, thereby improving the bonding quality with the heterogeneous chip and improving the modulation performance.

[0167] Further, referring to Figure 5 and Figure 11 , the distance range between the edge of the first bonding groove 13 and the edge of the first protective layer A on the relatively close side is the thickness range of the first protective layer A; the distance range between the edge of the second bonding groove 14 and the edge of the second protective layer B on the relatively close side is the thickness range of the second protective layer B.

[0168] Figure 5 Shown is a top view schematic diagram at the first modulation structure. In this embodiment, the first modulation structure is taken as an example for illustration. Figure 5 The horizontal direction shown is the width direction: the size of the first protective layer A > the size of the first bonding groove 13 > the size of the first heterogeneous chip D. The specific description is as follows:

[0169] First of all, if the size of the first bonding groove 13 is smaller than the size of the first protective layer A, then during dry etching of the first bonding groove 13, due to the relatively large depth, when etching downward, the part beyond the first protective layer A is still silicon oxide material, and it is easy to over-etch and contact the underlying modulation waveguide, resulting in damage. Therefore, the size of the first bonding groove 13 needs to be smaller than the size of the first protective layer A, and the etching area is all above the first protective layer A. Moreover, since the etching selectivity of silicon oxide material to the first protective layer A is very high, the situation of over-etching and damaging the modulation waveguide is effectively avoided.

[0170] Secondly, the amount of inward shrinkage of the first bonding groove 13 around it compared to the first protective layer A does not exceed the thickness of the first protective layer A. This is mainly to avoid incomplete removal of the part of the first protective layer A embedded in the silicon oxide material (i.e., the part of the first protective layer A that extends beyond the periphery of the first bonding groove 13) during wet etching. If the inward shrinkage is too much (the first bonding groove 13 is much smaller than the first protective layer A), it is difficult for the etching solvent to enter the embedded gap or the etching rate in the gap is very slow. Either the residual first protective layer A material will affect the device reliability, or more time is required for etching, but this is likely to cause damage to the bonding interface. Even with a large wet etching selectivity, over-long etching time may still affect the device performance.

[0171] Finally, the first bonding groove 13 is larger than the first heterogeneous chip D to facilitate the first heterogeneous chip D to smoothly enter the first bonding groove 13 and contact the bottom bonding interface to achieve bonding. However, at this time, some process dimension deviations need to be considered, such as: the etching process deviation of the first bonding groove 13 (the deviation of lithography etching processing is generally relatively small and can be controlled within ±1μm), the processing dimension deviation of the first heterogeneous chip D (related to the dicing processing method, mechanical dicing is usually greater than several hundred micrometers, and laser stealth dicing can be less than 10μm), and the bonding alignment deviation between the first heterogeneous chip D and the first bonding groove 13 (generally less than 3μm). Therefore, the amount by which the first heterogeneous chip D is smaller than the first bonding groove 13 needs to be set considering the above deviations to avoid the situation where the first heterogeneous chip D cannot be placed into the first bonding groove 13 due to exceeding the deviation.

[0172] The structural settings at the second modulation structure are set with reference to the above principles of the first modulation structure and will not be elaborated here.

[0173] Specifically in this embodiment, refer to Figure 5, the distance range between the edge of the first bonding groove 13 and the edge of the first protective layer A on the relatively closer side, that is Figure 5 The L3 shown is the thickness range of the first protective layer A, specifically 50 nm to 300 nm. Similarly, the distance range between the edge of the second bonding groove 14 and the edge of the second protective layer B on the relatively closer side is the thickness range of the second protective layer B, which is also set to 50 nm to 300 nm in this embodiment. The width of the above-mentioned first bonding groove 13 is slightly smaller than the width of the first protective layer A, and the width of the second bonding groove 14 is slightly smaller than the width of the second protective layer B, so that when etching the cladding structure C to form the first bonding groove 13 and the second bonding groove 14, the first protective layer A and the second protective layer B can fully protect the bonding interface of the underlying first spacer layer 5 and the second spacer layer 9, which helps to improve the bonding performance with the heterogeneous chip.

[0174] Reference Figure 11 , this embodiment also provides a hybrid waveguide structure, which is obtained by using the preparation method of the above-mentioned hybrid waveguide structure, and includes: a substrate layer 1, a cladding structure C, a first modulation structure, a second modulation structure, a first bonding groove 13 and a second bonding groove 14, and a first interconnect structure 11 and a second interconnect structure 12. The cladding structure C is located on one side surface of the substrate layer 1 and includes a first cladding layer 2, a first spacer layer 5, a second cladding layer 6, a second spacer layer 9, and a third cladding layer 10 stacked in sequence from the surface of the substrate layer 1; the first modulation structure is embedded in the first cladding layer 2, and the first modulation structure includes a first modulation waveguide 301 and a first electrode 4, and the first modulation waveguide 301 and the first electrode 4 are arranged at intervals; the second modulation structure is embedded in the second cladding layer 6, the second modulation structure includes a second modulation waveguide 701 and a second electrode 8, and is arranged offset from the first modulation structure, and the second modulation waveguide 701 and the second electrode 8 are arranged at intervals; the first bonding groove 13 is located above the first modulation structure and penetrates through the third cladding layer 10, the second spacer layer 9, and the second cladding layer 6, and there is a first spacer layer 5 between the first bonding groove 13 and the first modulation structure. The second bonding groove 14 is located above the second modulation structure and penetrates through the third cladding layer 10, and there is a second spacer layer 9 between the second bonding groove 14 and the second modulation structure. The first bonding groove 13 and the second bonding groove 14 are adapted to accommodate different heterogeneous chips; one end of the first interconnect structure 11 penetrates through the third cladding layer 10, the second spacer layer 9, the second cladding layer 6, and the first spacer layer 5 to be connected to the first electrode 4, and the other end is exposed on the third cladding layer 10. One end of the second interconnect structure 12 penetrates through the third cladding layer 10 and the second spacer layer 9 to be connected to the second electrode 8, and the other end is exposed on the third cladding layer 10.

[0175] In the hybrid waveguide structure of this embodiment, different waveguides such as the first modulation waveguide 301 and the second modulation waveguide 701 with different heights are first provided on the same substrate layer 1, which facilitates the combination of various silicon photonics heterogeneous materials and silicon optical waveguide devices on the same substrate layer 1, and helps to improve the functional diversity of silicon photonics devices on the same substrate layer 1. Secondly, the thickness of the first spacer layer 5 on the first modulation waveguide 301 can be controlled independently, and the thickness of the second spacer region on the second modulation waveguide 701 can be controlled independently, that is, the thickness of the spacer layer on each modulation waveguide, that is, the interlayer spacing when integrated with the heterogeneous chip can be controlled independently, which improves the flexibility of the processing technology. Moreover, the process parameters of the first electrode 4, the second electrode 8, the first spacer layer 5, the second spacer layer 9, the first protective layer A and the second protective layer B are basically the same, having better CMOS process compatibility; Thirdly, a first bonding groove 13 is formed above the first modulation waveguide 301, and a second bonding groove 14 is formed above the second modulation waveguide 701, forming a bonding region with a space for bonding and integrating heterogeneous chips. The other non-bonding regions have a cladding layer with the same thickness as the groove and much larger than the interlayer spacing of the bonding region, achieving the structural compatibility between the bonding region and the non-bonding region, and making the silicon photonics device more flexible in structural design and process processing.

[0176] In one embodiment, the cladding structure C further includes a fourth cladding layer 15. The fourth cladding layer 15 is disposed on the third cladding layer 10, and the fourth cladding layer 15 covers the first interconnect structure 11 and the second interconnect structure 12, and windows are opened in the corresponding regions of the first pad 1102 and the second pad 1202 to facilitate external wire bonding.

[0177] Reference Figures 1 to 29 , this embodiment further provides a method for manufacturing a heterogeneous integrated photonic device, including: first, obtaining a hybrid waveguide structure by using the manufacturing method of the above hybrid waveguide structure; then bonding the first heterogeneous chip D into the first bonding groove 13, and bonding the second heterogeneous chip E into the second bonding groove 14.

[0178] Exemplarily, in this embodiment, the first heterogeneous chip D is a barium titanate (BTO) chip, and the second heterogeneous chip E is a lithium niobate (LN) chip. The BTO chip is disposed in the first bonding groove 13 and aligned with the first modulation waveguide 301, i.e., a silicon waveguide, by bonding with the first spacer layer 5. The LN chip is disposed in the second bonding groove 14 and aligned with the second modulation waveguide 701, i.e., a silicon nitride waveguide, by bonding with the second spacer layer 9. Waveguides are formed at different height positions in the cladding structure C to form a hybrid waveguide structure, and correspondingly, grooves with different depths are formed. Different heterogeneous chips are integrally bonded in the grooves through the D2W bonding technology to achieve diversified silicon photonics heterogeneous integration on the same wafer, which has better CMOS process compatibility. At the same time, the flexibility of the application mode of the D2W bonding technology is improved, and different application requirements can be better met. At the same time, the bonding area and the non-bonding area have better process structure compatibility, making the structure design and process processing more flexible.

[0179] In one embodiment, before bonding the first heterogeneous chip D into the first bonding groove 13 and bonding the second heterogeneous chip E into the second bonding groove 14, it further includes:

[0180] First, the first heterogeneous chip substrate (BTOI substrate) and the second heterogeneous chip substrate (LNOI substrate) are cut and diced into an initial first heterogeneous chip and an initial second heterogeneous chip with sizes smaller than the bonding grooves. The initial first heterogeneous chip includes a first chip body D2 with a thickness of 80 nm to 300 nm, a first buried oxide layer D1 with a thickness between 0.1 μm and 2 μm, and a first substrate D0. The first chip body D2 is a barium titanate heterogeneous material and is used to bond and fix with the first spacer layer 5. The initial second heterogeneous chip includes a second chip body E2 with a thickness between 100 nm and 500 nm, a second buried oxide layer E1 with a thickness less than 2 μm, and a second substrate E0. The second chip body E2 is a lithium niobate heterogeneous material and is used to bond and fix with the second spacer layer 9, as Figure 28 shown. Generally, the sizes of the cut initial first heterogeneous chip and the initial second heterogeneous chip are each smaller than the corresponding bonding groove by more than 10 μm, mainly considering dicing size deviation, bonding alignment deviation, etc., to ensure that the BTO chip or the LN chip can be embedded in the groove.

[0181] After that, the obtained hybrid waveguide structure as a whole is subjected to surface treatments such as cleaning, drying, and plasma activation.

[0182] In one embodiment, the steps of bonding the first heterogeneous chip D into the first bonding groove 13 and bonding the second heterogeneous chip E into the second bonding groove 14 specifically include:

[0183] First, align and pre-bond the initial first heterogeneous chip with the first bonding groove 13, and align and pre-bond the initial second heterogeneous chip with the second bonding groove 14;

[0184] After that, perform an annealing treatment at a temperature less than 300 °C to enhance the bonding strength between the chip and the spacer layer;

[0185] Finally, remove the first substrate D0 and the second substrate E0 through processes such as CMP process and wet etching (using solutions such as KOH and TMAH), form the first heterogeneous chip D in the first bonding groove 13, and form the second heterogeneous chip E in the second bonding groove 14. Eventually, integrate various silicon photonic heterogeneous materials on the same silicon optical waveguide wafer, such as Figure 29 shown.

[0186] See Figure 5 , taking the setting of the first heterogeneous chip D in the first bonding groove 13 as an example. In the width direction, when the first heterogeneous chip D covers the first modulation waveguide 301, it must exceed the distance of the outermost side L1 of the first modulation waveguide 301. Specifically, the value of L1 in this embodiment is greater than 1 μm. In addition, there should be a gap of L2 between the edge of the first heterogeneous chip D and the edge of the first bonding groove 13 to ensure that the first heterogeneous chip D can be smoothly embedded into the first bonding groove 13 for bonding. In this embodiment, the value of L2 is greater than 5 μm.

[0187] Refer to Figure 29 , this embodiment also provides a heterogeneous integrated photonic device, which is fabricated by using the above-mentioned preparation method of the heterogeneous integrated photonic device, and includes: a hybrid waveguide structure, a first heterogeneous chip D, and a second heterogeneous chip E. The first heterogeneous chip D is disposed in the first bonding groove 13, and the second heterogeneous chip E is disposed in the second bonding groove 14.

[0188] The heterogeneous integrated photonic device of this embodiment forms different waveguides at different height positions in the cladding structure C to form a hybrid waveguide structure, and correspondingly forms grooves with different depths. Different heterogeneous chips are bonded and integrated in the grooves through the D2W bonding technology to achieve diversified silicon photonic heterogeneous integration on the same wafer, having better CMOS process compatibility. At the same time, the flexibility of the application method of the D2W bonding technology is also improved, which can better meet different application requirements; at the same time, the bonding area and the non-bonding area have better process structure compatibility, making the structure design and process processing more flexible.

[0189] The further function descriptions of the above structures are the same as those in the corresponding above embodiments, and will not be elaborated here.

[0190] In the above description, no detailed explanations are given for the technical details such as the composition and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the desired shapes. Additionally, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. Moreover, although the embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0191] Although the embodiments of the present invention are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for preparing a hybrid waveguide structure, characterized in that, include: Providing a substrate layer, wherein a first cladding layer is disposed on one side surface of the substrate layer; forming a first modulation structure, wherein the first modulation structure comprises a first modulation waveguide and a first electrode embedded in a side of the first cladding layer away from the substrate layer, wherein the first modulation waveguide and the first electrode are spaced apart from each other; forming a first spacer layer on a surface of the first cladding layer facing away from the substrate layer, wherein the first spacer layer covers the first modulation structure; forming a first protective layer on the first spacer layer, wherein the first protective layer at least covers a portion of the first modulation waveguide and a portion of the first electrode; A second cladding layer is formed on a surface of the first spacer layer facing away from the substrate layer, the second cladding layer covers the first protective layer, and a continuous plane is formed on a surface of the first protective layer facing away from the substrate layer; forming a second modulation structure, wherein the second modulation structure comprises a second modulation waveguide and a second electrode embedded in the second cladding layer on a side away from the substrate layer, and is staggered with the first modulation structure, and the second modulation waveguide is spaced apart from the second electrode; forming a second spacer layer on a surface of the second cladding layer facing away from the substrate layer, wherein the second spacer layer covers the second modulation structure; forming a second protective layer on the second spacer layer, wherein the second protective layer at least covers a portion of the second modulation waveguide and a portion of the second electrode; A third cladding layer is formed on a surface of the second spacer layer facing away from the substrate layer, the third cladding layer covers the second protective layer, and a continuous plane is formed on a surface of the second protective layer facing away from the substrate layer; forming a first interconnection structure and a second interconnection structure, wherein one end of the first interconnection structure extends into the third cladding, the second spacer layer, the second cladding and the first spacer layer to be connected to the first electrode, and the other end is exposed on the third cladding; one end of the second interconnection structure extends into the third cladding and the second spacer layer to be connected to the second electrode, and the other end is exposed on the third cladding; A first bonding groove is formed above the first modulation structure, the first bonding groove is suitable for exposing the first spacer layer, and a second bonding groove is formed above the second modulation structure, the second bonding groove is suitable for exposing the second spacer layer, and the first bonding groove and the second bonding groove are suitable for accommodating different heterogeneous chips.

2. The manufacturing method of the hybrid waveguide structure according to claim 1, characterized in that, The substrate layer, the first sub-cladding layer and the initial first waveguide layer are stacked in sequence to form a silicon-on-insulator substrate; the step of forming the first modulation structure comprises: Patterning the initial first waveguide layer to form a first modulation waveguide; A second sub-cladding is formed on a surface of the first sub-cladding away from the substrate layer, wherein the second sub-cladding covers the first modulation waveguide; the second sub-cladding and the first sub-cladding constitute a first cladding; Etching and removing a portion of the first cladding layer to form a first groove body in a region of the first cladding layer spaced apart from the first modulation waveguide; Depositing a first metal material on a surface of the first cladding layer facing away from the substrate layer, wherein the first metal material fills the first groove; The side where the first metal material is located is planarized until the first modulation waveguide is exposed, forming a first electrode located in the first groove body, and the surfaces of the first electrode, the first modulation waveguide, and the first cladding are flush with each other.

3. The manufacturing method of the hybrid waveguide structure according to claim 2, characterized in that, The second cladding includes a third sub-cladding and a fourth sub-cladding, and the third sub-cladding is relatively closer to the substrate layer side; The step of forming the second modulation structure includes: On the surface of the third sub-cladding facing away from the substrate layer, an initial second waveguide layer is formed over the entire surface by plasma-enhanced chemical vapor deposition; The initial second waveguide layer is patterned to form a second modulation waveguide; A fourth sub-cladding is formed on the surface of the third sub-cladding facing away from the substrate layer, and the fourth sub-cladding covers the second modulation waveguide, and the fourth sub-cladding and the third sub-cladding constitute the second cladding; Part of the second cladding is etched away to form a second groove body in the region spaced from the second modulation waveguide in the second cladding; A second metal material is deposited on the surface of the second cladding facing away from the substrate layer, and the second metal material covers the surface of the second cladding and fills the second groove body; The side where the second metal material is located is planarized until the second modulation waveguide is exposed, forming a second electrode located in the second groove body, and the surfaces of the second electrode, the second modulation waveguide, and the second cladding are flush with each other.

4. The manufacturing method of the hybrid waveguide structure according to claim 3, characterized in that, In the step of forming the first modulation waveguide, it further includes: synchronously forming a first transmission waveguide connected to the first modulation waveguide, and the first transmission waveguide and the first modulation waveguide constitute a first waveguide structure; in the step of forming the second modulation waveguide, it further includes: synchronously forming a second transmission waveguide connected to the second modulation waveguide, and the second transmission waveguide and the second modulation waveguide constitute a second waveguide structure; the projections of the first transmission waveguide and the second transmission waveguide on the substrate layer at least partially overlap to form a composite transmission waveguide, and the composite transmission waveguide is adapted to process an input optical signal and transmit the processed optical signal to the first modulation waveguide and the second modulation waveguide respectively.

5. The manufacturing method of the hybrid waveguide structure according to claim 1, characterized in that, The thickness ranges of both the first spacer layer and the second spacer layer are 50 nm to 150 nm, the surface roughnesses of the sides of the first spacer layer and the second spacer layer facing away from the substrate layer are both less than 0.5 nm, and the surface undulations are less than 50 nm.

6. The preparation method of the hybrid waveguide structure according to claim 1, wherein, The wet etching selectivity of the first protective layer to the first spacer layer is greater than 100:1; the wet etching selectivity of the second protective layer to the second spacer layer is greater than 100:

1.

7. The manufacturing method of the hybrid waveguide structure according to any one of claims 1-6, characterized in that, The step of forming the first interconnect structure and the second interconnect structure includes: A first interlayer via hole is formed above the first electrode not shielded by the first protective layer, and a second interlayer via hole is formed above the second electrode not shielded by the second protective layer. The first interlayer via hole penetrates through the third cladding layer, the second spacer layer, the second cladding layer, and the first spacer layer to connect the first electrode to the external environment. The second interlayer via hole penetrates through the third cladding layer and the second spacer layer to connect the second electrode to the external environment; The first interlayer via hole and the second interlayer via hole are respectively filled with a third metal material to form a first interlayer interconnect conductive column in the first interlayer via hole and a second interlayer interconnect conductive column in the second interlayer via hole; A first pad and a second pad are formed on a surface of the third cladding layer facing away from the substrate layer. The first pad is connected to the first interlayer interconnect conductive column to form a first interconnect structure, and the second pad is connected to the second interlayer interconnect conductive column to form a second interconnect structure.

8. The manufacturing method of the hybrid waveguide structure according to claim 7, characterized in that, The step of forming a first bonding groove above the first modulation structure and a second bonding groove above the second modulation structure includes: A fourth cladding layer is formed over the entire surface of the third cladding layer on the side facing away from the substrate layer. The fourth cladding layer covers the first interconnect structure and the second interconnect structure; The fourth cladding layer, the third cladding layer, the second spacer layer, the second cladding layer, and the first protective layer located on the first protective layer are etched away to form a first bonding groove above the first modulation structure. The width of the first bonding groove is smaller than the width of the first protective layer. At the same time, the fourth cladding layer, the third cladding layer, and the second protective layer located on the second protective layer are removed to form a second bonding groove above the second modulation structure. The width of the second bonding groove is smaller than the width of the second protective layer; The fourth cladding layer located on the first pad and the second pad is etched away to form a first pad window and a second pad window.

9. The manufacturing method of the hybrid waveguide structure according to claim 8, characterized in that The distance range between the edge of the first bonding groove and the edge of the first protective layer on the relatively closer side is the thickness range of the first protective layer. The distance range between the edge of the second bonding groove and the edge of the second protective layer on the relatively closer side is the thickness range of the second protective layer.

10. A hybrid waveguide structure, prepared by using the preparation method of the hybrid waveguide structure according to any one of claims 1-9, characterized in that, Including: Substrate layer; A cladding structure located on one surface of the substrate layer. The cladding structure includes a first cladding layer, a first spacer layer, a second cladding layer, a second spacer layer, and a third cladding layer stacked in sequence from the surface of the substrate layer; A first modulation structure embedded in the first cladding layer. The first modulation structure includes a first modulation waveguide and a first electrode. The first modulation waveguide is spaced from the first electrode; A second modulation structure embedded in the second cladding layer. The second modulation structure includes a second modulation waveguide and a second electrode, and is offset from the first modulation structure. The second modulation waveguide is spaced from the second electrode structure; A first bonding groove and a second bonding groove, wherein the first bonding groove is located above the first modulation structure and penetrates through the third cladding layer, the second spacer layer and the second cladding layer, and there is a first spacer layer between the first bonding groove and the first modulation structure; the second bonding groove is located above the second modulation structure and penetrates through the third cladding layer, and there is a second spacer layer between the second bonding groove and the second modulation structure; the first bonding groove and the second bonding groove are adapted to accommodate different heterogeneous chips; A first interconnecting structure and a second interconnecting structure, one end of the first interconnecting structure penetrates through the third cladding layer, the second spacer layer, the second cladding layer and the first spacer layer to be connected to the first electrode, and the other end is exposed on the third cladding layer; one end of the second interconnecting structure penetrates through the third cladding layer and the second spacer layer to be connected to the second electrode, and the other end is exposed on the third cladding layer.

11. A method for fabricating a heterogeneous integrated photonic device, characterized in that, Comprising: The hybrid waveguide structure is obtained by using the preparation method of the hybrid waveguide structure according to any one of claims 1-9; Bond the first heterogeneous chip into the first bonding groove and bond the second heterogeneous chip into the second bonding groove.

12. A heterogeneous integrated photonic device, which is obtained by using the preparation method of the heterogeneous integrated photonic device described in claim 11, wherein, Comprising: A hybrid waveguide structure; A first heterogeneous chip and a second heterogeneous chip, the first heterogeneous chip is disposed in the first bonding groove, and the second heterogeneous chip is disposed in the second bonding groove.

Images