Low-power-consumption RFID reader chip architecture applied to rapid tag detection

Abstract

The invention relates to a low power consumption RFID reader chip architecture applied to label rapid detection, which comprises an RISC-V core, an RFID reader, an SRAM, an AHB bus, an APB bus, a power management unit PMU and a peripheral, and is characterized in that the RISC-V core is a CPU of the chip architecture, and the RISC-V performs data interaction with the RFID reader, the SRAM, the power management unit PMU and the peripheral through the AHB bus and the APB bus; in the field domain range of the RFID reader, if the RFID reader detects that the tag enters the field in the polling process, information of the detected tag is encoded and stored in an instruction set in an SRAM (Static Random Access Memory), and the RISC-V directly takes out the instruction from the SRAM and decodes and executes the instruction. According to the low-power-consumption RFID reader chip architecture for rapid tag detection, the tag detection efficiency of the RFID reader can be improved, and efficient interaction with an RISC-V kernel is carried out.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency identification (RFID), and particularly to a low-power RFID reader chip architecture applied to rapid tag detection. Background Art

[0002] RFID technology is an automatic identification technology that realizes long-distance target item identification wirelessly and is also an important part of the Internet of Things technology, with good development prospects and research value. In a system-on-chip (SoC), an RFID reader often communicates with an MCU through the AMBA bus. However, when the response information generated by a tag needs to be interacted, a large amount of power consumption often occurs through the AMBA bus. Due to the inherent limitations of the AMBA bus, the reader mounted on the APB bus cannot directly store data in the RAM mounted on the AHB bus. This results in inefficient data transmission when the reader detects tags.

[0003] Therefore, there is an urgent need for a low-power RFID reader chip architecture for rapid tag detection to improve the efficiency of the RFID reader in detecting tags and to interact efficiently with the RISC-V core. Summary of the Invention

[0004] The purpose of the present invention is to at least solve one of the deficiencies of the prior art and provide a low-power RFID reader chip architecture applied to rapid tag detection.

[0005] To achieve the above purpose, the present invention adopts the following technical solutions: Specifically, a low-power RFID reader chip architecture applied to rapid tag detection is proposed, including a RISC-V core, an RFID reader, an SRAM, an AHB bus, an APB bus, a power management unit PMU, and peripherals. Among them, the RISC-V core is the CPU of the chip architecture, and the RISC-V conducts data interaction with the RFID reader, the SRAM, the power management unit PMU, and the peripherals through the AHB bus and the APB bus; Within the field range of the RFID reader, if the RFID reader detects the entry of a tag during the polling process, it first encodes the information of the detected tag and stores it in the instruction set in the SRAM. The RISC-V directly fetches the instruction from the SRAM and decodes and executes it.

[0006] Furthermore, in the chip architecture, the instruction set is re-partitioned. The 32-bit instruction is divided into 5 fields: (1) Bits 0 to 6 are the Opcode, which is used to distinguish instruction set types; (2) Bits 7 to 11 are the Code, which is used to determine whether it is a card detection code; (3) Bits 12 to 14 are the Funct3, which is used to refine the distinction of instruction sets; (4) Bits 15 to 24 are the Check, which is used to distinguish and determine whether the card detection is successful; (5) Bits 25 to 31 are the Funct7, which is used to refine the distinction of instruction sets.

[0007] Furthermore, specifically, after the 32-bit instruction is divided into 5 fields, the data processing process of the chip architecture is as follows. First, perform initialization configuration to initialize and clear the data; if a tag is detected within the field of the RFID reader, encode the information of the detected tag, otherwise re-perform the initialization configuration; after the encoding is completed, store the encoded instruction in the SRAM for the RISC-V core to extract the instruction; then enter the decoding stage. If Opcode = 0000111, perform the judgment of Funct7, otherwise it is judged as other instructions of RISC-V. If Funct7 = 0000111, perform the judgment of Funct3, otherwise it is judged as other instructions of RISC-V. If Funct3 = 000, perform the judgment of Code, otherwise it is judged as other instructions of RISC-V. If Code = 00111, perform the judgment of Check, otherwise it is judged as other instructions of RISC-V. If Check = 0000011111, it is judged that the tag detection is successful, otherwise it is judged as other instructions of RISC-V.

[0008] Furthermore, the chip architecture is also provided with a SW interface. The chip architecture downloads the running program to the Flash through the SW interface and is bootstrapped through the flash download algorithm, and the flash download algorithm is written in C language.

[0009] Furthermore, specifically, the power management unit PMU is divided into two parts. One part is used for the power-on and power-off management of the RISC-V core, and the other part is used for system clock control. The power-on and power-off management of the RISC-V core directly uses the solution given by the RISC-V core. At the same time, the power management unit PMU provides the system clock for all peripherals.

[0010] Further, specifically, the peripherals mounted on the AHB bus include Sysctrl, ROM, Flash, and GPIO; among them, Sysctrl is the system controller, which is used to configure system control-related registers, including the control of address remapping function, the control of the PMU module, reset information, and the control of Flash and peripheral clocks; ROM is used to store the bootloader, and program the running program into Flash through UART.

[0011] Further, specifically, the 100KHz clock generated by the internal RC oscillator of the chip architecture is used as the system low-frequency clock for the low-power mode; the external crystal oscillator is 27.12MHz, and the system main frequency of 13.56MHz can be obtained through internal frequency division. The 27.12MHz clock is used in the Flash interface and the RFID reader.

[0012] Further, specifically, the peripherals mounted on the APB bus include IWDG, UART, and Timer. Among them, IWDG is used for program monitoring to ensure the normal operation of the program, UART is used for low-speed data communication with other external devices, and Timer is used for timer timing.

[0013] The present invention proposes a low-power RFID reader chip architecture applied to label rapid detection. The beneficial effects compared with the prior art are as follows: 1. Innovatively propose a low-power RFID reader chip architecture applied to label rapid detection. Through this architecture, it is possible to break through the complex method in the traditional method of transmitting card detection data to the APB bus by using FIFO or other interfaces, and then transmitting it to the AHB bus through the AHB / APB bridge and then to the CPU.

[0014] 2. It can significantly save the useless power consumption caused by cumbersome data transmission in the traditional method. If the RFID reader detects the entry of a label during the polling process, the information of the detected label is first encoded and then directly stored in the instruction set of the SRAM, and the RISC-V kernel directly calls it.

[0015] 3. Innovatively propose an instruction set encoding method. The instruction set is re-divided, and the 32-bit instruction is divided into 5 domains, and the card detection instructions are carefully divided. Description of the Drawings

[0016] By elaborating on the embodiments shown in conjunction with the accompanying drawings, the above and other features of the present disclosure will become more apparent. In the accompanying drawings of the present disclosure, the same reference numerals represent the same or similar elements. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. In the drawings: Figure 1 The following shows the structural schematic diagram of a low-power RFID reader chip architecture applied to tag rapid detection according to the present invention; Figure 2 The following shows the information interaction method diagram of a low-power RFID reader chip architecture applied to tag rapid detection according to the present invention; Figure 3 The following shows the schematic diagram of instruction area division in the present invention; Figure 4 The following shows the flowchart of card detection information storage and decoding of the RFID reader chip in the present invention. Specific Embodiments

[0017] The following will clearly and completely describe the concept, specific structure, and technical effects of the present invention in combination with embodiments and drawings to fully understand the purpose, solution, and effects of the present invention. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The same reference numerals used everywhere in the drawings indicate the same or similar parts.

[0018] Referring to Figure 1 , Embodiment 1, the present invention proposes a low-power RFID reader chip architecture applied to tag rapid detection, including, A RISC-V core, an RFID reader, an SRAM, an AHB bus, an APB bus, a power management unit PMU, and peripherals. Among them, the RISC-V core is the CPU of the chip architecture, and the RISC-V performs data interaction with the RFID reader, SRAM, power management unit PMU, and peripherals through the AHB bus and the APB bus; Within the field range of the RFID reader, if the RFID reader detects the entry of a tag during the polling process, it first encodes the information of the detected tag and stores it in the instruction set in the SRAM. The RISC-V directly fetches the instructions from the SRAM and decodes and executes them.

[0019] In this Embodiment 1, as Figure 2As shown, within the field range of the RFID reader, if the RFID reader detects a tag entering the field during polling, it first encodes the information of the detected tag and stores it in the instruction set in the SRAM. RISC-V specifically includes five stages: instruction fetch, decoding, execution, memory access, and write-back. In its instruction fetch stage, instructions are directly fetched from the SRAM and then decoded and executed. By this way of directly extracting instructions from the SRAM to determine whether the RFID reader successfully detects a card, it can eliminate the traditional method where the CPU first sends instructions for the RFID reader to search for a card. If a card enters the field, the RFID reader then stores the information of the detected card in a dedicated card detection register and transfers the data to the APB bus through a FIFO or other interfaces, and then transfers it to the AHB bus through the AHB / APB bridge and then to the CPU. This can significantly save the useless power consumption caused by the cumbersome data transmission in the traditional method.

[0020] Referring to Figure 3 , as a preferred embodiment of the present invention, the chip architecture further includes re-dividing the instruction set. The 32-bit instruction is divided into 5 domains: (1) Bits 0 to 6 are Opcode, which is used to distinguish the instruction set type; (2) Bits 7 to 11 are Code, which is used to determine whether it is a card detection code; (3) Bits 12 to 14 are Funct3, which is used to refine the distinction of the instruction set; (4) Bits 15 to 24 are Check, which is used to distinguish and determine whether the card detection is successful; (5) Bits 25 to 31 are Funct7, which is used to refine the distinction of the instruction set.

[0021] Referring to Figure 4 , as a preferred embodiment of the present invention, specifically, after dividing the 32-bit instruction into 5 domains, the data processing process of the chip architecture is as follows. First, perform initialization configuration to initialize and clear the data. If a tag is detected within the field range of the RFID reader, encode the information of the detected tag; otherwise, re-perform the initialization configuration. After encoding is completed, store the encoded instructions in the SRAM for the RISC-V core to extract the instructions. Then enter the decoding stage. If Opcode = 0000111, judge Funct7; otherwise, judge it as other instructions of RISC-V. If Funct7 = 0000111, judge Funct3; otherwise, judge it as other instructions of RISC-V. If Funct3 = 000, judge Code; otherwise, judge it as other instructions of RISC-V. If Code = 00111, judge Check; otherwise, judge it as other instructions of RISC-V. If Check = 0000011111, judge that the tag detection is successful (i.e., the card detection is successful); otherwise, judge it as other instructions of RISC-V.

[0022] As a preferred embodiment of the present invention, the chip architecture is further provided with a SW interface. The chip architecture downloads the running program to the Flash through the SW interface and is bootstrapped through a flash download algorithm, which is written in C language. By specifying the structure specification size of the flash, the programming, erasing, reading, and writing operations of the flash can be realized. The algorithm also includes a watchdog function. Other instructions refer to instructions other than 0000111, such as 0110111, which are arithmetic logic operation instructions.

[0023] As a preferred embodiment of the present invention, specifically, the power management unit PMU is divided into two parts. One part is used for the power-on and power-off management of the RISC-V core, and the other part is used for system clock control. The power-on and power-off management of the RISC-V core directly uses the solution given by the RISC-V core. At the same time, the power management unit PMU provides the system clock for all peripherals.

[0024] As a preferred embodiment of the present invention, specifically, the peripherals mounted on the AHB bus include Sysctrl, ROM, Flash, and GPIO. Among them, Sysctrl is a system controller used for configuring system control-related registers, including the control of address remapping function, the control of the PMU module, reset information, and the control of Flash and peripheral clocks. ROM is used to store the bootloader, and the running program is programmed into the Flash through the UART.

[0025] As a preferred embodiment of the present invention, specifically, the 100KHz clock generated by the internal RC oscillator of the chip architecture serves as the system low-frequency clock for the low-power mode; the external crystal oscillator is 27.12MHz, and the system main frequency of 13.56MHz can be obtained through internal frequency division. The 27.12MHz clock is used in the Flash interface and the RFID reader.

[0026] As a preferred embodiment of the present invention, specifically, the peripherals mounted on the APB bus include IWDG, UART, and Timer. Among them, IWDG is used for program monitoring to ensure the normal operation of the program, UART is used for low-speed data communication with other external devices, and Timer is used for timer timing. The low-power mode refers to the operation mode of using the system low-frequency clock and using it as the main control clock, which avoids the additional power consumption generated when using the high-frequency clock to achieve the purpose of low power consumption (reducing power consumption).

[0027] Although the description of the present invention has been quite detailed and several specific embodiments have been described, it is not intended to be limited to any of these details or embodiments or any particular embodiment. Instead, it should be regarded as providing a broad possible interpretation of these claims in light of the prior art by referring to the appended claims, thereby effectively covering the intended scope of the present invention. In addition, the present invention is described above with embodiments foreseeable by the inventors for the purpose of providing a useful description, and non-substantive modifications to the present invention that are not currently foreseeable may still represent equivalent modifications of the present invention.

[0028] As mentioned above, it is only a preferred embodiment of the present invention. The present invention is not limited to the above embodiments. As long as it achieves the technical effects of the present invention by the same means, it should fall within the protection scope of the present invention. Within the protection scope of the present invention, various different modifications and changes can be made to its technical solutions and / or embodiments.

Claims

1. A low-power RFID reader chip architecture for rapid label detection, characterized in that, including a RISC-V core, an RFID reader, an SRAM, an AHB bus, an APB bus, a power management unit PMU, and peripherals. Among them, the RISC-V core is the CPU of the chip architecture, and RISC-V exchanges data with the RFID reader, SRAM, power management unit PMU, and peripherals through the AHB bus and the APB bus; Within the field range of the RFID reader, if the RFID reader detects a tag entering the field during polling, it first encodes the detected tag information and stores it in the instruction set in the SRAM. The RISC-V directly fetches the instruction from the SRAM and decodes and executes it.

2. The low-power RFID reader chip architecture for rapid label detection according to claim 1, characterized in that The chip architecture also includes re-partitioning the instruction set dividing the 32-bit instruction into 5 fields: (1) Bits 0 to 6 are the Opcode, used to distinguish the instruction set type; (2) Bits 7 to 11 are the Code, used to determine whether it is a card detection code; (3) Bits 12 to 14 are the Funct3, used to refine the distinction of the instruction set; (4) Bits 15 to 24 are the Check, used to distinguish and judge whether the card detection is successful; (5) Bits 25 to 31 are the Funct7, used to refine the distinction of the instruction set.

3. The low-power RFID reader chip architecture applied to rapid label detection according to claim 2, characterized in that Specifically, after dividing the 32-bit instruction into 5 fields, the data processing process of the chip architecture is as follows First, perform initialization configuration to initialize and clear the data; if a tag is detected within the field range of the RFID reader, encode the detected tag information, otherwise re-perform the initialization configuration; after encoding is completed, store the encoded instruction in the SRAM for the RISC-V core to extract the instruction; then enter the decoding stage. If Opcode = 0000111, judge Funct7, otherwise judge it as other instructions of RISC-V. If Funct7 = 0000111, judge Funct3, otherwise judge it as other instructions of RISC-V [1][jz2][3]. If Funct3 = 000, judge Code, otherwise judge it as other instructions of RISC-V. If Code = 00111, judge Check, otherwise judge it as other instructions of RISC-V. If Check = 0000011111, judge that the tag detection is successful, otherwise judge it as other instructions of RISC-V.

4. A low-power RFID reader chip architecture applied to rapid label detection according to claim 1, characterized in that, The chip architecture is also provided with a SW interface. The chip architecture downloads the running program to the Flash through the SW interface and is bootstrapped through the flash download algorithm, and the flash download algorithm is written in C language.

5. A low-power RFID reader chip architecture for rapid label detection according to claim 1, characterized in that Specifically, the power management unit PMU is divided into two parts. One part is used for the power-on and power-off management of the RISC-V core, and the other part is used for system clock control. The power-on and power-off management of the RISC-V core directly uses the solution given by the RISC-V core. At the same time, the power management unit PMU provides the system clock for all peripherals.

6. A low-power RFID reader chip architecture applied to rapid label detection according to claim 1, characterized in that, Specifically, the peripherals mounted on the AHB bus include Sysctrl, ROM, Flash, and GPIO; Among them, Sysctrl is the system controller, which is used to configure the system control-related registers, including the control of address remapping function, the control of PMU module, reset information, and the control of Flash and peripheral clocks; ROM is used to store the bootloader, and program the running program into Flash through UART.

7. A low-power RFID reader chip architecture applied to rapid label detection according to claim 1, characterized in that, Specifically, the 100KHz clock generated by the internal RC oscillator in the chip architecture is used as the system low-frequency clock for the low-power mode [4][jz5][6]; the external crystal oscillator is 27.12MHz, and the system main frequency of 13.56MHz can be obtained through internal frequency division. The 27.12MHz clock is used in the Flash interface and RFID reader.

8. A low-power RFID reader chip architecture for rapid label detection according to claim 1, characterized in that, Specifically, the peripherals mounted on the APB bus include IWDG, UART, and Timer. Among them, IWDG is used for program monitoring to ensure the normal operation of the program, UART is used for low-speed data communication with other external devices, and Timer is used for timer timing.

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