Memory circuit and operating method thereof

Abstract

A memory circuit includes a memory array including memory cells, where each memory cell is accessible through a plurality of access lines. The memory circuit includes a delay circuit configured to receive a first clock pulse and delay the first clock pulse to a second clock pulse, where the second clock pulse follows the first clock pulse. The memory circuit includes a logic gate configured to receive a first clock pulse and a second clock pulse, and to provide a pre-charge signal for pre-charging the plurality of access lines based on the first and second clock pulses. The delay circuit includes a plurality of inverters and a plurality of transistors such that a time difference between a first transition edge of the first clock pulse and a second transition edge of the second clock pulse is extended with an increased duration of use of the memory circuit. The embodiment of the invention also discloses a method for operating the memory circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory circuit and a method of operating the same. Background Art

[0002] The semiconductor industry has experienced rapid development due to the continuous increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration comes from the continuous reduction of the minimum component size, which allows more components to be integrated into a given area. Summary of the Invention

[0003] According to one aspect of an embodiment of the present application, there is provided a memory circuit, including: a memory array including a plurality of memory cells, wherein each of the plurality of memory cells is accessible via a plurality of access lines; a delay circuit configured to receive a first clock pulse and delay the first clock pulse into a second clock pulse, wherein the second clock pulse follows the first clock pulse; a logic gate configured to receive the first clock pulse and the second clock pulse and provide a precharge signal for precharging the plurality of access lines based on the first clock pulse and the second clock pulse; wherein the delay circuit includes a plurality of inverters and a plurality of transistors such that the time difference between a first transition edge of the first clock pulse and a second transition edge of the second clock pulse extends as the usage duration of the memory circuit increases.

[0004] According to another aspect of an embodiment of the present application, there is provided a memory circuit, including: a delay circuit configured to receive a first clock pulse and delay the first clock pulse into a second clock pulse, wherein the first clock pulse and the second clock pulse are within one clock cycle; wherein the delay circuit includes a plurality of inverters and a plurality of transistors, and the plurality of transistors are configured to delay the rising edge of the second clock pulse following the falling edge of the first clock pulse according to the increasing usage duration of the memory circuit.

[0005] According to yet another aspect of an embodiment of the present application, there is provided a method of operating a memory circuit, including: receiving a first clock pulse configured for a first operation of a first memory cell within a memory array; delaying the first clock pulse into a second clock pulse configured for a second operation of a second memory cell within the memory array, wherein the first clock pulse and the second clock pulse following the falling edge of the first clock pulse are within one clock cycle; precharging a first bit line coupled to the first memory cell and a second bit line coupled to the second memory cell; and delaying the rising edge of the second clock pulse. Brief Description of the Drawings

[0006] As will be best understood in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figure 1 Shows an example block diagram of a memory circuit according to some embodiments.

[0008] Figure 2 Shows according to some embodiments Figure 1 Schematic diagram of the timing controller and precharge circuit of the memory circuit.

[0009] Figure 3 Shows according to some embodiments Figure 2 Example circuit diagram of the timing controller.

[0010] Figure 4 Shows according to some embodiments Figure 2 Another circuit diagram of the timing controller.

[0011] Figure 5 Shows according to some embodiments Figure 2 Another circuit diagram of the timing controller.

[0012] Figure 6 Shows according to some embodiments Figure 2 Another circuit diagram of the timing controller.

[0013] Figure 7 Shows according to some embodiments Figure 2 Another circuit diagram of the timing controller.

[0014] Figure 8 Shows according to some embodiments Figure 2 Another circuit diagram of the timing controller.

[0015] Figure 9 Shows according to some embodiments Figure 2 Another circuit diagram of the timing controller.

[0016] Figure 10 Shows according to some embodiments Figure 2 Another circuit diagram of the timing controller.

[0017] Figure 11 Shows according to some embodiments Figure 2 Another circuit diagram of the timing controller.

[0018] Figure 12 Shows according to some embodiments Figure 2 Another circuit diagram of the timing controller.

[0019] Figure 13 Shows example waveforms of various signals when operating a timing controller for any circuit diagram shown in Figures 3 - 12 the Figure 2 memory circuit.

[0020] Figure 14 Shows an example flowchart of a method for operating a memory circuit according to some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Also, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity, but in itself does not indicate a relationship between the various embodiments and / or configurations discussed.

[0022] In addition, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", "top", "over" etc. may be used herein to describe the spatial relationship of one element or component to another as shown in the figures. Spatial relationship terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be positioned otherwise (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly.

[0023] Integrated circuits typically include static random access memory (SRAM) circuits to provide on-chip data storage. SRAM circuits are typically configured to meet specific design requirements related to the surrounding circuits attached to the SRAM circuit. A common type of SRAM circuit provides one port for read or write access to the data stored in the SRAM circuit. The address input of such a circuit is typically shared for both read and write access. Another common type of SRAM circuit is called a dual-port SRAM circuit, which provides two ports for accessing the data stored in the SRAM circuit. Dual-port SRAM circuits typically restrict all read access to one port and all write access to a second port. Each port of a dual-port SRAM circuit is typically capable of accessing the data stored in the SRAM circuit asynchronously and independently, thus allowing the dual-port SRAM circuit to be incorporated into a range of different applications with different usage models.

[0024] Dual-port SRAM circuits allow designers to achieve system performance levels that are typically higher than those achievable with single-port SRAM circuits alone. However, for a given number of storage bits, the area required by existing dual-port SRAM circuits is approximately twice that of single-port SRAM circuits. Thus, in integrated circuits where SRAM circuit instances represent a large portion of the entire die area, using dual-port SRAM circuits can be an extremely costly design choice.

[0025] One way to reduce the die area cost associated with using dual-port SRAM circuits is to replace each dual-port SRAM cell with a single-port SRAM cell (e.g., a six-transistor SRAM cell) that operates in a sequential read access and write access manner. For example, one read access and one write access can be performed per clock signal cycle, thereby allowing the SRAM circuit to provide two external ports, each capable of executing one transaction per clock cycle. Typically, two clock pulses are generated based on a single clock signal, one configured for read access and the other for write access. Such an SRAM circuit is sometimes referred to as a dual-pump SRAM circuit.

[0026] However, dual-pump SRAM circuits are generally affected by the length of use of the SRAM circuit, sometimes referred to as the bias temperature instability (BTI) effect. As the length of use of the SRAM circuit (or its transistor components) increases, the absolute value of the transistor threshold voltage increases, which makes it more difficult for the transistor to conduct, resulting in a lower conduction current. This thus causes various problems in the dual-pump SRAM circuit, such as during the transition mode of the SRAM circuit. During such a phase, the bit lines (BL) of the SRAM circuit are typically configured to be precharged to VDD or a high logic state. As the BTI effect becomes more pronounced, the window of this precharging phase is typically compressed, e.g., having a delayed rising edge and / or an advanced falling edge. The prior art does not appear to include any circuits or components configured to track such BTI effects. Thus, existing dual-pump SRAM circuits are not entirely satisfactory in some respects.

[0027] The present disclosure provides various embodiments of a memory circuit that includes various components to track in real time the aging effects, if any, present in the memory circuit. Thus, even in the presence of aging effects, the memory circuits disclosed herein can be advantageously immune to the effects of a compressed precharge window. In various embodiments, the memory circuits disclosed herein are dual-pumped static random access memory (SRAM) circuits that can operate first (e.g., read) access and second (e.g., write) access in sequence. The first access and the second access can be activated by a first clock pulse and a second clock pulse, respectively. However, it should be understood that the disclosed memory circuits are not limited to such SRAM circuits. Based on the first clock pulse and the second clock pulse, a precharge signal can be generated for precharging the bit lines of the SRAM circuit. For example, such a precharge signal can have a pulse width defined (e.g., limited) by the falling edge of the first clock pulse and the rising edge of the second clock pulse. The pulse width of the precharge signal is sometimes referred to as the precharge window.

[0028] In one aspect, the disclosed SRAM circuit can include a plurality of always-on p-type transistors and / or a plurality of always-on n-type transistors coupled to a delay chain or a delay circuit of the SRAM circuit. The delay chain can be formed by a plurality of inverter stages. The p-type transistors can be coupled to the even stages, respectively, and the n-type transistors can be coupled to the odd stages, respectively. In another aspect, the delay chain of the disclosed SRAM circuit can include two additional transistors gated by a control signal. The control signal can be configured to change the polarity of the output of each inverter stage. In another aspect, the SRAM circuit includes one or more always-on transmission gates coupled to the delay chain. For any implementation, as long as one or more transistors of the SRAM circuit exhibit the BTI effect, the rising edge of the second clock pulse after the first pulse can be delayed. Thus, when the BTI effect is present, the precharge window can be advantageously increased, which allows the adjusted precharge window to track the BTI effect, or more specifically, to compensate for the BTI effect.

[0029] Figure 1 FIG. shows a schematic diagram of a memory system or circuit 100 according to various embodiments. The memory system 100 is implemented as an integrated circuit. As Figure 1As shown in the illustrated example, memory system 100 includes memory controller 105 and memory array 120. Memory array 120 may include a plurality of storage circuits, memory cells, memory bits, or bit cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 may be accessed via multiple access lines. For example, each memory cell 125 may be connected to at least one corresponding word line WL and a pair of corresponding bit lines BL. Each word line WL and bit line BL may include any conductive (e.g., metal) material. For example, each word line WL and bit line BL may be implemented as one or more metal lines. Memory controller 105 may write data to memory array 120 or read data from memory array according to electrical signals through word line WL and bit line BL. In other embodiments, memory system 100 includes more, fewer, or different components than those shown in Figure 1 but is still within the scope of the present disclosure.

[0030] Memory array 120 is a hardware component for storing data. In various embodiments, memory array 120 is implemented as a semiconductor storage device. Memory array 120 includes a plurality of storage circuits or memory cells 125. In some embodiments, memory array 120 includes word lines WL0, WL1...WLJ, each extending in a first direction, and bit lines BL0, BL1...BLK, each extending in a second direction. Word lines WL and bit lines BL may be conductive metals or conductive rails. Each memory cell 125 is connected to a corresponding word line WL and a corresponding pair of bit lines BL, and may operate according to voltages or currents through the corresponding word line WL and the corresponding pair of bit lines BL. Each memory cell 125 may be a static random access memory (SRAM) cell. For example, memory cell 125 may be implemented as a six-transistor (6T) SRAM cell or a single-port SRAM cell. However, it should be understood that memory cell 125 may be implemented as any of a variety of other memory configurations while still being within the scope of the present disclosure. In some embodiments, memory array 120 includes additional lines (e.g., sense lines, reference lines, reference control lines, power rails, etc.).

[0031] Memory controller 105 is a hardware component that controls the operation of memory array 120. In some embodiments, memory controller 105 includes a bit line controller 112, a word line controller 114, a timing controller 116, and a precharge circuit 118. In one configuration, word line controller 114 is a circuit that provides a voltage or current signal through one or more word lines WL of memory array 120. In one aspect, bit line controller 112 is a circuit that provides a voltage or current signal through one or more bit lines BL of memory array 120 and senses a voltage or current from memory array 120 through one or more bit lines BL. In various embodiments, timing controller 116 is a circuit that provides two clock pulses for a read access and a subsequent write access (or a write access and a subsequent read access) on memory array 120, respectively. Timing controller 116 may include various components to track the BTI effects present in memory array 120, so as to adjust (e.g., delay) the timing of the rising edge of the next clock pulse, which can advantageously widen the pulse window of the precharge signal. Timing controller 116 may provide a precharge signal to precharge circuit 118, and precharge circuit 118 may utilize the precharge signal to precharge bit lines BL to a high logic state (e.g., VDD) during a phase when memory array 120 is not being read or written (e.g., between two clock pulses). Additionally, timing controller 116 may provide control signals or clock signals to word line controller 114 and bit line controller 112 to synchronize the operations of bit line controller 112 and word line controller 114.

[0032] Bit line controller 112 may be connected to bit lines BL of memory array 120, and word line controller 114 may be connected to word lines WL of memory array 120. In one example, to write data to memory cell 125, word line controller 114 is configured to apply a voltage or current signal (sometimes referred to as a WL signal) to memory cell 125 through the corresponding word line WL connected to memory cell 125, and bit line controller 112 is configured to apply a voltage or current signal corresponding to the data to be stored to memory cell 125 through a pair of bit lines BL connected to memory cell 125. To read data from memory cell 125, word line controller 114 is configured to apply the WL signal to memory cell 125 through the corresponding word line WL connected to memory cell 125, and bit line controller 112 is configured to sense a voltage or current corresponding to the data stored in memory cell 125 through the bit lines connected to memory cell 125. In some embodiments, memory controller 105 includes more, fewer, or different components than those Figure 1 shown, while still being within the scope of the present disclosure.

[0033] Figure 2 illustrated in accordance with various embodiments of the present disclosureFigure 1 An example schematic diagram of a portion of the memory controller 105. For example, Figure 2 The schematic diagrams of respectively include circuit implementations of a timing controller 116 and a precharge circuit 118. In various embodiments, the timing controller 116 is configured to generate a second clock pulse based on a first clock pulse and provide a precharge signal based on the first and second clock pulses; and the precharge circuit 118 is configured to receive the precharge signal (or its logically inverted version) to precharge the bit lines of a corresponding memory array (e.g., 120). Details of the timing controller 116 and the precharge circuit 118 will be provided below. It should be understood that Figure 2 The schematic diagrams of are for illustrative purposes only. Thus, each of the timing controller 116 and the precharge circuit 118 can be configured in other ways while still being within the scope of the present disclosure.

[0034] As Figure 2 shown, the timing controller 116 includes a first logic gate 210, a delay chain (or delay circuit) 220, a second logic gate 230, a plurality of first buffers 240, and a plurality of second buffers 250. The first logic gate 210 can be implemented as a dual-input NOR gate, which can receive a write enable inverted (WEB) signal and a first clock pulse (CKP1), and perform a NOR function on its inputs to provide an intermediate (PRE) signal. In some embodiments, when the memory array 120 is configured in the standby mode, the WEB signal can be provided as a logic 1; and when the memory array 120 is configured in the write mode (commonly referred to as the operation mode), the WEB signal can be provided as a logic 0. Then, the PRE signal propagates through the delay chain 220 (which can include an even number of inverter stages) and is output as a second clock pulse (CKP2). In some embodiments, CKP1 can be generated based on a transition edge (e.g., the rising edge) of a corresponding clock signal, and CKP2 can follow CKP1 closely. Thus, in some examples, CKP1 and CKP2 can correspond to (e.g., fall within) half of the period of a corresponding clock signal.

[0035] The second logic gate 230 can be implemented as a dual-input NOR (negative-OR) gate, which can receive CKP1 and CKP2 and perform a NOR function on its inputs to provide a precharge (BLEQ2IO) signal through the first buffer 240. In some embodiments, the number of the first buffers 240 can be even. Due to an intentional delay, CKP2 follows CKP1 with a time difference. A pulse of the BLEQ2IO signal (e.g., logic 1) can be generated from the time difference (e.g., NOR). In other words, between CKP1 and CKP2, where both CKP1 and CKP2 are at logic 0, the NOR gate 230 can generate a pulse of the BLEQ2IO signal through the first buffer 240. Therefore, the pulse width of the BLEQ2IO signal can be determined based on the time difference between the falling edge of CKP1 and the rising edge of CKP2. Then, the BLEQ2IO signal propagates through the second buffer 250 and is output as a logically inverted version of the precharge signal (BLEQB signal). Then, the BLEQB signal is provided to the precharge circuit 118.

[0036] The precharge circuit 118 includes transistors P1, P2, and P3. In some embodiments, each of the transistors P1 to P3 can be implemented as a p-type metal-oxide-semiconductor field-effect transistor. However, each of the transistors P1 to P3 can be implemented as any one of various other transistors while still being within the scope of the present disclosure. In some embodiments, the gate terminals of the transistors P1 to P3 are commonly connected to the output of the last buffer 240, i.e., gated by the BLEQB signal. The respective source terminals of the transistors P1 and P2 are connected to VDD, while their respective drain terminals are connected to the bit lines BL and BLB of the memory array 120. The bit lines BL and BLB are connected to the source / drain terminal of the transistor P3. Generally, when the BLEQB signal is pulled down to logic 0, the transistors P1 to P3 can be turned on, such that the transistors P1 and P2 pull up the voltage levels on the bit lines BL and BLB to VDD, and such that the transistor P3 equalizes the voltage levels on the bit lines BL and BLB.

[0037] Figure 3 A circuit implementation 300 of a timing controller 116 ( Figure 2 ) according to some embodiments of the present disclosure is shown. Hereinafter, Figure 3 the shown circuit implementation is referred to as the timing controller 300. In addition to Figure 2 the shown components, the timing controller 300 further includes one or more tracking metal lines configured to track the propagation delays of the corresponding memory array and NAND logic gates, both of which can be incorporated into or coupled to the delay chain of the timing controller 300, which will be described hereinafter.

[0038] AsFigure 3 As shown, the timing controller 300 includes a first NOR gate 310, a delay chain 320, a second NOR gate 330, and a set of buffers 340, which may be embodiments of the first logic gate 210, the delay chain 220, the second logic gate 230, and the first buffer 240, respectively. In addition, the timing controller 300 includes tracking metal lines 350, a NAND gate 360, and a last inverter stage 370 coupled to the delay chain 320. In some embodiments, the tracking metal lines 350 each physically extend along the column direction of the corresponding memory array, and may be configured to track the propagation delay (e.g., RC delay) present on the bit lines of the memory array. In other words, the length of each tracking metal line 350 may be proportional to the height of the memory array. For example, the first tracking metal line 350 may extend from the edge of the memory array to the midpoint of the memory array, while the second tracking metal line 350 may extend from the midpoint to the edge of the memory array.

[0039] In Figure 3 the illustrative example of, the first NOR gate 310 includes transistors 311, 312, 313, and 314, where transistors 311 and 312 are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 313 and 314 are each implemented as n-type metal oxide semiconductor field effect transistors. The delay chain 320 includes transistors 321, 322, 323, 324, 325, 326, 327, 328, 329A, and 329B, where transistors 321, 323, 325, 327, 329A, and 329B are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 322, 324, 326, and 328 are each implemented as n-type metal oxide semiconductor field effect transistors. The NAND gate 360 includes transistors 361, 362, 363, and 364, where transistors 361 and 364 are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 362 and 363 are each implemented as n-type metal oxide semiconductor field effect transistors. The last inverter stage 370 includes transistors 371 and 372, where transistor 371 is implemented as a p-type metal oxide semiconductor field effect transistor, and transistor 372 is implemented as an n-type metal oxide semiconductor field effect transistor. The second NOR gate 330 includes transistors 331, 332, 333, and 334, where transistors 331 and 332 are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 333 and 334 are each implemented as n-type metal oxide semiconductor field effect transistors. The buffer 340 includes transistors 341, 342, 343, and 344, where transistors 341 and 343 are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 342 and 344 are each implemented as n-type metal oxide semiconductor field effect transistors.

[0040] According to some embodiments, transistors 311, 312, 313, and 314 of the NOR gate 310 are respectively configured to receive CKP1, the WEB signal, CKP1, and the WEB signal, and jointly perform a NOR operation on the CKP1 and the WEB signal to provide the PRE signal. For example, in the standby mode, the WEB signal is logic 1 and CKP1 is logic 0, such that the PRE signal is NORed to logic 0; in the working mode, the WEB signal is logic 0 and CKP1 can transition between logic 0 and logic 1, such that when CKP1 transitions to (or remains) logic 0, the PRE signal is NORed to transition to logic 1, and when CKP1 transitions to (or remains) logic 1, the PRE signal is NORed to transition to logic 0.

[0041] Transistors 321 and 322, transistors 323 and 324, transistors 325 and 326, and transistors 327 and 328 of the delay chain 320 can be respectively used as the first stage, the second stage, the third stage, and the fourth stage in multiple inverter stages. The PRE signal provided by the NOR gate 310 can propagate through the inverter stages. The first inverter stage can receive the PRE signal as its input and output its logically inverted version (PREB) as its output, the second inverter stage can receive the PREB signal as its input and output its logically inverted version (PRE) as its output, and so on. The delay chain 320 (along with the tracking metal line 350) outputs a delayed version (PRE’) of the PRE signal. In some embodiments, the second inverter stage (i.e., 323 and 324) further includes a transistor 329A coupled between the p-type transistor 323 and VDD, and the fourth inverter stage (i.e., 327 and 328) further includes a transistor 329B coupled between the p-type transistor 327 and VDD. Such p-type transistors 329A and 329B can be coupled to the even-numbered stages of the inverters on the delay chain 320. Transistors 361, 362, 363, and 364 of the NAND gate 360 are respectively configured to receive the PRE’ signal, the PRE’s signal, the PRE signal, and the PRE signal, and jointly perform a NAND operation on the PRE’ signal and the PRE signal, thereby providing an input for the last inverter stage 370 capable of generating CKP2. Transistors 331, 332, 333, and 334 of the NOR gate 330 are respectively configured to receive CKP2, CKP1, CKP1, and CKP2, and jointly perform a NOR operation on CKP1 and CKP2, so as to provide an input for the buffer 340 that can generate the BLEQ2IO signal.

[0042] In some embodiments, respective gate terminals of transistors 329A and 329B are connected to VSS, and each transistor is implemented as a p-type transistor. Thus, transistors 329A and 329B can each be configured as always-on transistors to track the BTI effect. In other words, when the BTI effect becomes significant (e.g., the absolute value of the threshold voltage increases), the always-on transistors 329A and 329B can reflect this adjusted threshold voltage, thereby reducing the charging ability of the connected p-type transistors (e.g., 323 and 327). In some embodiments, the size (e.g., width, width / length ratio, etc.) of the always-on transistors 329A and 329B can be smaller than that of the connected p-type transistors 323 and 327. Accordingly, the transition edges from these inverter stages (e.g., the second and fourth inverter stages) can be delayed, thereby intentionally delaying the transition edge of CKP2. Thus, when the BTI effect becomes significant, the transition (e.g., rising) edge of CKP2 can be delayed relative to the transition (e.g., falling) edge of CKP1, allowing a wider time window to pre-charge BL / BLB.

[0043] For example, during a standby mode in which CKP1 has not been provided, the WEB signal and CKP1 are provided as logic 1 and logic 0, respectively, resulting in the PRE signal being provided as logic 0. The first, second, third, and fourth inverter stages of the delay chain 320 can output logic 1, logic 0, logic 1, and logic 0, respectively. Generally, when the memory circuit is in the standby mode for a long time, the BTI effect may occur. After the standby mode, the WEB signal can be provided as logic 0 and CKP1 is provided. Further, when CKP1 transitions from logic 1 to logic 0, the PRE signal transitions to logic 1, which causes the first, second, third, and fourth inverter stages of the delay chain 320 to pull down, pull up, pull down, and pull down their respective inputs. Since the always-on transistors 329A and 329B are connected to the second and fourth inverter stages (or pull-up stages), when there is a BTI effect, the always-on transistors 329A and 329B can intentionally reduce the ability of the pull-up stages. Accordingly, the rising edge of CKP2 can be delayed. Given the delay of the rising edge of CKP2, the falling edge of the BLEQ2IO signal can be delayed, thereby extending the pulse width of the BLEQ2IO signal.

[0044] Figure 4 A circuit diagram showing another circuit implementation of a timing controller 116 ( Figure 2 ) according to some embodiments of the present disclosure. Hereinafter, Figure 4 the circuit implementation shown is referred to as a timing controller 400. In addition to Figure 2In addition to the components shown, the timing controller 400 further includes one or more tracking metal lines configured to track the propagation delays of the corresponding memory array and the NAND logic gates, both of which may be incorporated into or coupled to the delay chain of the timing controller 400, which will be described hereinafter.

[0045] As Figure 4 shown, the timing controller 400 includes a first NOR gate 410, a delay chain 420, a second NOR gate 430, and a set of buffers 440, which may be embodiments of the first logic gate 210, the delay chain 220, the second logic gate 230, and the first buffer 240, respectively. Additionally, the timing controller 400 includes tracking metal lines 450, NAND gates 460, and a last inverter stage 470 coupled to the delay chain 420. In some embodiments, the tracking metal lines 450 each extend along the column direction of the corresponding memory array, which may be configured to track the propagation delays (e.g., RC delays) present on the bit lines of the memory array. In other words, the length of each tracking metal line 450 may be proportional to the height of the memory array. For example, the first tracking metal line 450 may extend from the edge of the memory array to the midpoint of the memory array, while the second tracking metal line 450 may extend from the midpoint to the edge of the memory array.

[0046] In Figure 4In an illustrative example, the first NOR gate 410 includes transistors 411, 412, 413, and 414, where transistors 411 and 412 are each implemented as p-type metal-oxide-semiconductor field-effect transistors, and transistors 413 and 414 are each implemented as n-type metal-oxide-semiconductor field-effect transistors. The delay chain 420 includes transistors 421, 422, 423, 424, 425, 426, 427, 428, 429A, and 429B, where transistors 421, 423, 425, and 427 are each implemented as p-type metal-oxide-semiconductor field-effect transistors, and transistors 422, 424, 426, 428, 429A, and 429B are each implemented as n-type metal-oxide-semiconductor field-effect transistors. The NAND gate 460 includes transistors 461, 462, 463, and 464, where transistors 461 and 464 are each implemented as p-type metal-oxide-semiconductor field-effect transistors, and transistors 462 and 463 are each implemented as n-type metal-oxide-semiconductor field-effect transistors. The final inverter stage 470 includes transistors 471 and 472, where transistor 471 is implemented as a p-type metal-oxide-semiconductor field-effect transistor, and transistor 472 is implemented as an n-type metal-oxide-semiconductor field-effect transistor. The second NOR gate 430 includes transistors 431, 432, 433, 434, where transistors 431 and 432 are each implemented as p-type metal-oxide-semiconductor field-effect transistors, and transistors 433 and 434 are each implemented as n-type metal-oxide-semiconductor field-effect transistors. The buffer 440 includes transistors 441, 442, 443, 444, where transistors 441 and 443 are each implemented as p-type metal-oxide-semiconductor field-effect transistors, and transistors 442 and 444 are each implemented as n-type metal-oxide-semiconductor field-effect transistors.

[0047] According to some embodiments, transistors 411, 412, 413, and 414 of the NOR gate 410 are respectively configured to receive CKP1, WEB signal, CKP1, and WEB signal, and jointly perform a NOR operation on the CKP1 and WEB signals to provide a PRE signal. For example, in the standby mode, the WEB signal is logic 1 and CKP1 is logic 0, such that the PRE signal is NORed to logic 0; in the operating mode, the WEB signal is logic 0, and CKP1 can transition between logic 0 and logic 1, such that when CKP1 transitions to (or remains) logic 0, the PRE signal is NORed to transition to logic 1, and when CKP1 transitions to (or remains) logic 1, the PRE signal is NORed to transition to logic 0.

[0048] The transistors 421 and 422, transistors 423 and 424, transistors 425 and 426, and transistors 427 and 428 of the delay chain 420 can be used as the first stage, second stage, third stage, and fourth stage in a plurality of inverter stages, respectively. The PRE signal provided by the NOR gate 410 can propagate through the inverter stages. The first inverter stage can receive the PRE signal as its input and output its logically inverted version (PREB) as its output, the second inverter stage can receive the PREB signal as its input and output its logically inverted version (PRE) as its output, and so on. The delay chain 420 (along with the tracking metal line 450) outputs a delayed version (PRE’) of the PRE signal. In some embodiments, the first inverter stage (i.e., 421 and 422) further includes a transistor 429A coupled between the n-type transistor 422 and VSS, and the third inverter stage (i.e., 425 and 426) further includes a transistor 429B coupled between the n-type transistor 426 and VSS. Such n-type transistors 429A and 429B can be coupled to the odd stages of the inverters on the delay chain 420. The transistors 461, 462, 463, and 464 of the NAND gate 460 are respectively configured to receive the PRE’ signal, PRE’s signal, PRE signal, and PRE signal, and jointly perform a NAND operation on the PRE’ signal and the PRE signal, so as to provide an input for the last inverter stage 470 capable of generating CKP2. The transistors 431, 432, 433, and 434 of the NOR gate 430 are respectively configured to receive CKP2, CKP1, CKP1, and CKP2, and jointly perform a NOR operation on CKP1 and CKP2, so as to provide an input for the buffer 440 that can generate the BLEQ2IO signal.

[0049] In some embodiments, the respective gate terminals of the transistors 429A and 429B are connected to VDD, and each transistor is implemented as an n-type transistor. Therefore, the transistors 429A and 429B can each be configured as transistors that are always on to track the BTI effect. In other words, when the BTI effect becomes significant (e.g., the absolute value of the threshold voltage increases), the transistors 429A and 429B that are always on can reflect this adjusted threshold voltage, thereby reducing the discharge ability of the connected n-type transistors (e.g., 422 and 426). In some embodiments, the size (e.g., width, width / length ratio, etc.) of the transistors 429A and 429B that are always on can be smaller than that of the connected n-type transistors 422 and 426. Therefore, the transition edges from these inverter stages (e.g., the first and third inverter stages) can be delayed, thereby intentionally delaying the transition edge of CKP2. Therefore, when the BTI effect becomes significant, the transition (e.g., rising) edge of CKP2 can be delayed relative to the transition (e.g., falling) edge of CKP1, thereby allowing a wider time window to precharge BL / BLB.

[0050] Figure 5 A circuit diagram showing another circuit implementation of the timing controller 116 according to some embodiments of the present disclosure. Hereinafter, Figure 5 the circuit implementation shown is referred to as the timing controller 500. In addition to Figure 2 the components shown, the timing controller 500 further includes one or more tracking metal lines configured to track the propagation delays of the corresponding memory array and the NAND logic gates, both of which can be incorporated into or coupled to the delay chain of the timing controller 500, which will be described hereinafter.

[0051] As Figure 5 shown, the timing controller 500 includes a first NOR gate 510, a delay chain 520, a second NOR gate 530, and a set of buffers 540, which can be embodiments of the first logic gate 210, the delay chain 220, the second logic gate 230, and the first buffer 240, respectively. In addition, the timing controller 500 includes tracking metal lines 550, a NAND gate 560, and a last inverter stage 570 coupled to the delay chain 520. In some embodiments, the tracking metal lines 550 each extend along the column direction of the corresponding memory array, which can be configured to track the propagation delay (e.g., RC delay) present on the bit lines of the memory array. In other words, the length of each tracking metal line 550 can be proportional to the height of the memory array. For example, the first tracking metal line 550 can extend from the edge of the memory array to the midpoint of the memory array, while the second tracking metal line 550 can extend from the midpoint to the edge of the memory array.

[0052] In Figure 5In the illustrative example, the first NOR gate 510 includes transistors 511, 512, 513, and 514, where transistors 511 and 512 are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 513 and 514 are each implemented as n-type metal oxide semiconductor field effect transistors. The delay chain 520 includes transistors 521, 522, 523, 524, 525, 526, 527, 528, 529A, 529B, 529C, and 529D, where transistors 521, 523, 525, 527, 529B, and 529D are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 522, 524, 526, 528, 529A, and 529C are each implemented as n-type metal oxide semiconductor field effect transistors. The NAND gate 560 includes transistors 561, 562, 563, and 564, where transistors 561 and 564 are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 562 and 563 are each implemented as n-type metal oxide semiconductor field effect transistors. The final inverter stage 570 includes transistors 571 and 572, where transistor 571 is implemented as a p-type metal oxide semiconductor field effect transistor, and transistor 572 is implemented as an n-type metal oxide semiconductor field effect transistor. The second NOR gate 530 includes transistors 531, 532, 533, 534, where transistors 531 and 532 are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 533 and 534 are each implemented as n-type metal oxide semiconductor field effect transistors. The buffer 540 includes transistors 541, 542, 543, 544, where transistors 541 and 543 are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 542 and 544 are each implemented as n-type metal oxide semiconductor field effect transistors.

[0053] According to some embodiments, the transistors 511, 512, 513, and 514 of the NOR gate 510 are respectively configured to receive CKP1, the WEB signal, CKP1, and the WEB signal, and jointly perform a NOR operation on the CKP1 and the WEB signal to provide the PRE signal. For example, in the standby mode, the WEB signal is logic 1 and CKP1 is logic 0, such that the PRE signal is NORed to logic 0; in the operating mode, the WEB signal is logic 0, and CKP1 can transition between logic 0 and logic 1, such that when CKP1 transitions to (or holds) logic 0, the PRE signal is NORed to transition to logic 1, and when CKP1 transitions to (or holds) logic 1, the PRE signal is NORed to transition to logic 0.

[0054] The transistors 521 and 522, transistors 523 and 524, transistors 525 and 526, and transistors 527 and 528 of the delay chain 520 can be used as the first stage, second stage, third stage, and fourth stage in a plurality of inverter stages, respectively. The PRE signal provided by the NOR gate 510 can propagate through the inverter stages. The first inverter stage can receive the PRE signal as its input and output its logically inverted version (PREB) as its output, the second inverter stage can receive the PREB signal as its input and output its logically inverted version (PRE) as its output, and so on. The delay chain 520 (along with the tracking wire 550) outputs a delayed version (PRE’) of the PRE signal. In some embodiments, the first inverter stage (i.e., 521 and 522) further includes a transistor 529A coupled between the n-type transistor 522 and VSS, the second inverter stage (i.e., 523 and 524) further includes a transistor 529B coupled between the p-type transistor 523 and VDD, the third inverter stage (i.e., 525 and 526) further includes a transistor 529C coupled between the n-type transistor 526 and VSS, and the fourth inverter stage (i.e., 527 and 528) further includes a transistor 529D coupled between the p-type transistor 527 and VDD. The n-type transistors 529A and 529C can be coupled to the odd stages of the inverters on the delay chain 520, while the p-type transistors 529B and 529D can be coupled to the even stages of the inverters on the delay chain 520. The transistors 561, 562, 563, and 564 of the NAND gate 560 are respectively configured to receive the PRE’ signal, PRE’s signal, PRE signal, and PRE signal, and jointly perform a NAND operation on the PRE’ signal and the PRE signal, so as to provide an input for the last inverter stage 570 that can generate CKP2. The transistors 531, 532, 533, and 534 of the NOR gate 530 are respectively configured to receive CKP2, CKP1, CKP1, and CKP2, and jointly perform a NOR operation on CKP1 and CKP2, so as to provide an input for the buffer 540 that can generate the BLEQ2IO signal.

[0055] In some embodiments, respective gate terminals of transistors 529A and 529C (each transistor implemented as an n-type transistor) are connected to VDD, and respective gate terminals of transistors 529B and 529D (each transistor implemented as a p-type transistor) are connected to VSS. Thus, transistors 529A to 529D can each be configured as always-on transistors to track the BTI effect. In other words, when the BTI effect becomes significant (e.g., the absolute value of the threshold voltage increases), the always-on transistors 529A to 529D can reflect this adjusted threshold voltage, thereby reducing the discharge ability of the connected n-type transistors and the charge ability of the connected p-type transistors. In some embodiments, the sizes (e.g., width, width / length ratio, etc.) of the always-on transistors 529A and 529C can be smaller than the connected n-type transistors 522 and 526. Similarly, the sizes (e.g., width, width / length ratio, etc.) of the always-on transistors 529B and 529D can be smaller than the connected p-type transistors 523 and 527. Thus, the transition edges from these inverter stages (e.g., the first and third inverter stages) can be delayed, thereby intentionally delaying the transition edge of CKP2. Therefore, when the BTI effect becomes significant, the transition (e.g., rising) edge of CKP2 can be delayed relative to the transition (e.g., falling) edge of CKP1, thereby allowing a wider time window to pre-charge BL / BLB.

[0056] Figure 6 A circuit diagram showing yet another circuit implementation of the timing controller 116 according to some embodiments of the present disclosure. Hereinafter, Figure 6 the shown circuit implementation is referred to as the timing controller 600. In addition to Figure 2 the components shown, the timing controller 600 further includes one or more tracking metal lines configured to track the propagation delays of the corresponding memory array and NAND logic gates, and they can all be incorporated into or coupled to the delay chain of the timing controller 600, which will be described hereinafter.

[0057] As Figure 6As shown, the timing controller 600 includes a first NOR gate 610, a delay chain 620, a second NOR gate 630, and a set of buffers 640, which may be embodiments of the first logic gate 210, the delay chain 220, the second logic gate 230, and the first buffer 240, respectively. In addition, the timing controller 600 includes tracking metal lines 650, a NAND gate 660, and a last inverter stage 670 coupled to the delay chain 620. In some embodiments, the tracking metal lines 650 each extend along the column direction of a corresponding memory array, and may be configured to track the propagation delay (e.g., RC delay) present on the bit lines of the memory array. In other words, the length of each tracking metal line 650 may be proportional to the height of the memory array. For example, the first tracking metal line 650 may extend from the edge of the memory array to the midpoint of the memory array, while the second tracking metal line 650 may extend from the midpoint to the edge of the memory array.

[0058] In Figure 6 the illustrative example of, the first NOR gate 610 includes transistors 611, 612, 613, and 614, where transistors 611 and 612 are each implemented as p-type metal-oxide-semiconductor field-effect transistors, and transistors 613 and 614 are each implemented as n-type metal-oxide-semiconductor field-effect transistors. The delay chain 620 includes transistors 621, 622, 623, 624, 625, 626, 627, 628, 629A, and 629B, where transistors 621, 623, 625, 627, and 629A are each implemented as p-type metal-oxide-semiconductor field-effect transistors, and transistors 622, 624, 626, 628, and 629B are each implemented as n-type metal-oxide-semiconductor field-effect transistors. The NAND gate 660 includes transistors 661, 662, 663, and 664, where transistors 661 and 664 are each implemented as p-type metal-oxide-semiconductor field-effect transistors, and transistors 662 and 663 are each implemented as n-type metal-oxide-semiconductor field-effect transistors. The last inverter stage 670 includes transistors 671 and 672, where transistor 671 is implemented as a p-type metal-oxide-semiconductor field-effect transistor, and transistor 672 is implemented as an n-type metal-oxide-semiconductor field-effect transistor. The second NOR gate 630 includes transistors 631, 632, 633, 634, where transistors 631, 632 are each implemented as p-type metal-oxide-semiconductor field-effect transistors, and transistors 633, 634 are each implemented as n-type metal-oxide-semiconductor field-effect transistors. The buffer 640 includes transistors 641, 642, 643, 644, where transistors 641, 643 are each implemented as p-type metal-oxide-semiconductor field-effect transistors, and transistors 642, 644 are each implemented as n-type metal-oxide-semiconductor field-effect transistors.

[0059] According to some embodiments, transistors 611, 612, 613, and 614 of NOR gate 610 are respectively configured to receive CKP1, WEB signal, CKP1 and WEB signal, and jointly perform a NOR operation on the CKP1 and WEB signals to provide a PRE signal. For example, in the standby mode, the WEB signal is logic 1 and CKP1 is logic 0, such that the PRE signal is NORed to logic 0; in the operating mode, the WEB signal is logic 0 and CKP1 can transition between logic 0 and logic 1, such that when CKP1 transitions to (or remains) logic 0, the PRE signal is NORed to transition to logic 1, and when CKP1 transitions to (or remains) logic 1, the PRE signal is NORed to transition to logic 0.

[0060] Transistors 621 and 622, transistors 623 and 624, transistors 625 and 626, and transistors 627 and 628 of delay chain 620 can be respectively used as the first stage, the second stage, the third stage, and the fourth stage in a plurality of inverter stages. The PRE signal provided by NOR gate 610 can propagate through the inverter stages. The first inverter stage can receive the PRE signal as its input and output its logically inverted version (PREB) as its output, the second inverter stage can receive the PREB signal as its input and output its logically inverted version (PRE) as its output, and so on. Delay chain 620 (along with tracking metal line 650) outputs a delayed version (PRE’) of the PRE signal. In some embodiments, the first inverter stage (i.e., 621 and 622) further includes transistor 629A coupled between p-type transistor 623 and VDD, and transistor 629B is coupled between the output of the first inverter stage and the input of the second inverter stage (i.e., 623 and 624). The respective gate terminals of transistor 629A and transistor 629B are coupled to a control signal (CKP3B). The CKP3B signal provides logic 1 and logic 0 in the standby mode and the operating mode, respectively. Transistors 661, 662, 663, and 664 of NAND gate 660 are respectively configured to receive the PRE’ signal, PRE’s signal, PRE signal, and PRE signal, and jointly perform a NAND operation on the PRE’ signal and the PRE signal, thereby providing an input for the last inverter stage 670 capable of generating CKP2. Transistors 631, 632, 633, and 634 of NOR gate 630 are respectively configured to receive CKP2, CKP1, CKP1, and CKP2, and jointly perform a NOR operation on CKP1 and CKP2 to provide an input for buffer 640 that can generate the BLEQ2IO signal.

[0061] In some embodiments, the gate terminals of transistors 629A and 629B (implemented as a p-type transistor and an n-type transistor, respectively) are configured to receive the same CKP3B signal. Additionally, when in the standby mode, the CKP3B signal is provided as logic 1; when in the operating mode, the CKP3B signal is provided as logic 0. In this way, transistors 629A and 629B can be turned off and on, respectively, in the standby mode, while transistors 629A and 629B can be turned on and off, respectively, in the operating mode, thereby tracking the BTI effect. In other words, when the BTI effect becomes significant (e.g., the absolute value of the threshold voltage increases), in the standby mode, the turned-off transistor 629A and the turned-on transistor 629B can change the polarity of the output of the first inverter stage and the polarity of each subsequent inverter stage. Therefore, transistors 623, 626, and 627 can reflect the adjusted threshold voltage. When switching to the operation mode (where transistor 629A is turned on and transistor 629B is turned off), transistors 623, 626, and 627 can be configured to track the BTI effect. Therefore, the transition edges of each inverter stage can be delayed, thereby intentionally delaying the transition edge of CKP2. Therefore, when the BTI effect becomes significant, the transition (e.g., rising) edge of CKP2 can be delayed relative to the transition (e.g., falling) edge of CKP1, thereby allowing a wider time window to pre-charge BL / BLB.

[0062] For example, during the standby mode when CKP1 has not been provided, the WEB signal and CKP1 are provided as logic 1 and logic 0, respectively, resulting in the PRE signal being provided as logic 0. By turning off transistor 629A and turning on transistor 629B (through the CKP3B signal), the first inverter stage, the second inverter stage, the third inverter stage, and the fourth inverter stage of the delay chain 620 can output logic 0, logic 1, logic 0, and logic 1, respectively. If there is a BTI effect, the turned-off transistor 629A and the turned-on transistor 629B can track the threshold voltage degradation of transistors 621, 623, 626, and 627 caused by the BTI effect. After the standby mode, the WEB signal can be provided as logic 0 and CKP1 is provided. Additionally, when CKP1 transitions from logic 1 to logic 0, the PRE signal transitions to logic 1, which causes the first inverter stage, the second inverter stage, the third inverter stage, and the fourth inverter stage of the delay chain 620 to pull down, pull up, pull down, and pull down their respective inputs. Since transistors 623, 626, and 627 reflect the adjusted threshold voltage, when there is a BTI effect, the pull-up ability of the second inverter stage, the pull-down ability of the third inverter stage, and the pull-up ability of the fourth inverter stage can be lower. Therefore, the rising edge of CKP2 can be delayed. Given the delay of the rising edge of CKP2, the falling edge of the BLEQ2IO signal can be delayed, thereby extending the pulse width of the BLEQ2IO signal.

[0063] Figure 7 A circuit diagram showing yet another circuit implementation of the timing controller 116 according to some embodiments of the present disclosure. Hereinafter, Figure 7 the circuit implementation shown is referred to as the timing controller 700. In addition to Figure 2 the components shown, the timing controller 700 further includes one or more tracking metal lines configured to track the propagation delays of the corresponding memory array and NAND logic gates, both of which can be incorporated into or coupled to the delay chain of the timing controller 700, which will be described hereinafter.

[0064] As Figure 7 shown, the timing controller 700 includes a first NOR gate 710, a delay chain 720, a second NOR gate 730, and a set of buffers 740, which can be embodiments of the first logic gate 210, the delay chain 220, the second logic gate 230, and the first buffer 240, respectively. In addition, the timing controller 700 includes a tracking metal line 750, a NAND gate 760, a final inverter stage 770, and a transmission gate 780 coupled to the delay chain 720. In some embodiments, the tracking metal lines 750 each extend along the column direction of the corresponding memory array, which can be configured to track the propagation delays (e.g., RC delays) present on the bit lines of the memory array. In other words, the length of each tracking metal line 750 can be proportional to the height of the memory array. For example, the first tracking metal line 750 can extend from the edge of the memory array to the midpoint of the memory array, while the second tracking metal line 750 can extend from the midpoint to the edge of the memory array.

[0065] In Figure 7In the illustrative example, the first NOR gate 710 includes transistors 711, 712, 713, and 714, where transistors 711 and 712 are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 713 and 714 are each implemented as n-type metal oxide semiconductor field effect transistors. The delay chain 720 includes transistors 721, 722, 723, 724, 725, 726, 727, and 728, where transistors 721, 723, 725, and 727 are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 722, 724, 726, and 728 are each implemented as n-type metal oxide semiconductor field effect transistors. The NAND gate 760 includes transistors 761, 762, 763, and 764, where transistors 761 and 764 are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 762 and 763 are each implemented as n-type metal oxide semiconductor field effect transistors. The final inverter stage 770 includes transistors 771 and 772, where transistor 771 is implemented as a p-type metal oxide semiconductor field effect transistor, and transistor 772 is implemented as an n-type metal oxide semiconductor field effect transistor. The second NOR gate 730 includes transistors 731, 732, 733, 734, where transistors 731 and 732 are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 733 and 734 are each implemented as n-type metal oxide semiconductor field effect transistors. The buffer 740 includes transistors 741, 742, 743, 744, where transistors 741 and 743 are each implemented as p-type metal oxide semiconductor field effect transistors, and transistors 742 and 744 are each implemented as n-type metal oxide semiconductor field effect transistors. The transmission gate 780 includes transistors 781 and 782, where transistor 781 is implemented as a p-type metal oxide semiconductor field effect transistor, and transistor 782 is implemented as an n-type metal oxide semiconductor field effect transistor.

[0066] According to some embodiments, transistors 711, 712, 713, and 714 of the NOR gate 710 are respectively configured to receive CKP1, the WEB signal, CKP1, and the WEB signal, and jointly perform a NOR operation on the CKP1 and the WEB signal to provide the PRE signal. For example, in the standby mode, the WEB signal is logic 1 and CKP1 is logic 0, such that the PRE signal is NORed to logic 0; in the operating mode, the WEB signal is logic 0, and CKP1 can transition between logic 0 and logic 1, such that when CKP1 transitions to (or remains) logic 0, the PRE signal is NORed to transition to logic 1, and when CKP1 transitions to (or remains) logic 1, the PRE signal is NORed to transition to logic 0.

[0067] The transistors 721 and 722, transistors 723 and 724, transistors 725 and 726, and transistors 727 and 728 of the delay chain 720 can be used as the first stage, the second stage, the third stage, and the fourth stage in a plurality of inverter stages, respectively. The PRE signal provided by the NOR gate 710 can propagate through the inverter stages. The first inverter stage can receive the PRE signal as its input and output its logically inverted version (PREB) as its output, the second inverter stage can receive the PREB signal as its input and output its logically inverted version (PRE) as its output, and so on. The delay chain 720 (along with the transmission gate 780 and the trace metal line 750) outputs a delayed version (PRE’) of the PRE signal. In some embodiments, the gate terminal of the p-type transistor 781 of the transmission gate 780 is connected to VSS, and the gate terminal of the n-type transistor 782 of the transmission gate 780 is connected to VDD. The transistors 761, 762, 763, and 764 of the NAND gate 760 are respectively configured to receive the PRE’ signal, the PRE’s signal, the PRE signal, and the PRE signal, and jointly perform a NAND operation on the PRE’ signal and the PRE signal, so as to provide an input for the last inverter stage 770 that can generate CKP2. The transistors 731, 732, 733, and 734 of the NOR gate 730 are respectively configured to receive CKP2, CKP1, CKP1, and CKP2, and jointly perform a NOR operation on CKP1 and CKP2, so as to provide an input for the buffer 740 that can generate the BLEQ2IO signal.

[0068] In some embodiments, the respective gate terminals of the transistors 781 and 782 (implemented as a p-type transistor and an n-type transistor) of (the transmission gate 780) are connected to VSS and VDD, respectively. Thus, the transmission gate 780 can be configured as a transmission gate that is always on to track the BTI effect. In other words, when the BTI effect becomes significant (e.g., the absolute value of the threshold voltage increases), the always-on transmission gate 780 can reflect this adjusted threshold voltage, thereby deliberately delaying the transition edge of CKP2. Therefore, when the BTI effect becomes significant, the transition (e.g., rising) edge of CKP2 can be delayed from the transition (e.g., falling) edge of CKP1, thereby allowing a wider time window for precharging BL / BLB.

[0069] For example, during the standby mode in which CKP1 is not yet provided, the WEB signal and CKP1 are provided as logic 1 and logic 0, respectively, resulting in the PRE signal being provided as logic 0. The first inverter stage, the second inverter stage, the third inverter stage, and the fourth inverter stage of the delay chain 720 can output logic 1, logic 0, logic 1, and logic 0, respectively. If there is a BTI effect, the always-on transmission gate 780 can track the threshold voltage degradation caused by the BTI effect. After the standby mode, the WEB signal can be provided as logic 0 and CKP1 is provided. In addition, when CKP1 transitions from logic 1 to logic 0, the PRE signal transitions to logic 1, which causes the first inverter stage, the second inverter stage, the third inverter stage, and the fourth inverter stage of the delay chain 720 to pull down, pull up, pull down, and pull down their respective inputs. Since the transmission gate 780 is always on, the equivalent resistance of the transmission gate 780 can increase as the entire circuit ages to track the BTI effect. Therefore, the rising edge of CKP2 can be delayed. Given the delay of the rising edge of CKP2, the falling edge of the BLEQ2IO signal can be delayed, thereby extending the pulse width of the BLEQ2IO signal.

[0070] Figure 8 and Figure 9 both show a circuit diagram of yet another circuit implementation of the timing controller 116 according to some embodiments of the present disclosure. Hereinafter, Figure 8 and Figure 9 the shown circuit implementations are referred to as the timing controller 800 and the timing controller 900, respectively. The timing controllers 800 and 900 are similar to the timing controller 700 except for the position of the always-on transmission gate or the number of always-on transmission gates being different. Therefore, the following discussion of the timing controllers 800 and 900 will focus on the differences.

[0071] In Figure 8 the illustrative example of, the timing controller 800 includes a first NOR gate 810, a delay chain 820, a tracking metal wire 850, a transmission gate 880, a NAND gate 860, a final inverter stage 870, a second NOR gate 830, and a set of buffers 840. The transmission gate 880 also includes an always-on p-type transistor and an always-on n-type transistor. Different from the timing controller 700, the transmission gate 880 of the timing controller 800 is coupled between the tracking metal wire 850 and the NAND gate 860.

[0072] In Figure 9In the illustrative example of the timing controller 900, the timing controller 900 includes a first NOR gate 910, a delay chain 920, a first transmission gate 980, a tracking metal line 950, a second transmission gate 990, a NAND gate 960, a final inverter stage 970, a second NOR gate 930, and a group of buffers 940. Each of the transmission gates 980 and 990 also includes a p-type transistor that is always turned on and an n-type transistor that is always turned on. Unlike the timing controller 700, the transmission gate 980 and the transmission gate 990 of the timing controller 900 are coupled to both ends of the tracking metal line 950. In other words, the transmission gate 980 is coupled between the output of the fourth inverter stage of the delay chain 920 and the tracking metal line 950; and the transmission gate 990 is coupled between the tracking metal line 950 and the NAND gate 960.

[0073] Figure 10 , Figure 11 and Figure 12 1 and 2 show circuit diagrams of another circuit implementation of the timing controller 116 according to some embodiments of the present disclosure. Figure 10 , Figure 11 and Figure 12 The circuit implementations shown in the figures are respectively referred to as timing controller 1000, timing controller 1100, and timing controller 1200. Timing controllers 1000 to 1200 are similar to timing controller 300 except for the configuration of tracking metal lines or the number of tracking metal lines, and therefore, the following discussion of timing controllers 1000 to 1200 will focus on the differences.

[0074] exist Figure 10 In the illustrative example of , the timing controller 1000 includes a first NOR gate 1010, a delay chain 1020, a tracking metal line 1050, a NAND gate 1060, a final inverter stage 1070, a second NOR gate 1030, and a set of buffers 1040. The tracking metal line 1050 is also coupled between the delay chain 1020 and the NAND gate 1060. Unlike the timing controller 300, the tracking metal lines 1050 of the timing controller 1000 each physically extend along the row direction of the corresponding memory array, which can be configured to track the propagation delay (e.g., RC delay) on the word line of the memory array. In other words, the length of each tracking metal line 1050 can be proportional to the width of the memory array. For example, the first tracking metal line 1050 can extend from the edge of the memory array to the midpoint of the memory array, and the second tracking metal line 1050 can extend from the midpoint to the edge of the memory array.

[0075] exist Figure 11In an illustrative example, the timing controller 1100 includes a first NOR gate 1110, a delay chain 1120, a first tracking metal line 1150, a second tracking metal line 1155, a NAND gate 1160, a final inverter stage 1170, a second NOR gate 1130, and a set of buffers 1140. In some embodiments, the first tracking metal line 1150 is coupled between adjacent inverter stages of the delay chain 1120, and the second tracking metal line 1155 is coupled between the delay chain 1120 and the NAND gate 1160. Further, the first tracking metal lines 1150 each physically extend along the row direction of the corresponding memory array, while the second tracking metal lines 1155 each physically extend along the column direction of the memory array. In other words, the length of each of the first tracking metal lines 1150 can be proportional to the width of the memory array, while the length of each of the second tracking metal lines 1155 can be proportional to the height of the memory array. For example, the first of the first tracking metal lines 1150 can extend from a first edge of the memory array to the midpoint of the memory array, while the second of the first tracking metal lines 1150 can extend from the midpoint to the first edge of the memory array; and the first of the second tracking metal lines 1155 can extend from a second edge of the memory array to the midpoint of the memory array, while the second of the second tracking metal lines 1155 can extend from the midpoint to the second edge of the memory array. In some embodiments, the first edge can be perpendicular to the second edge.

[0076] In Figure 12In an illustrative example, the timing controller 1200 includes a first NOR gate 1210, a delay chain 1220, a first tracking metal line 1250, a second tracking metal line 1255, a NAND gate 1260, a final inverter stage 1270, a second NOR gate 1230, and a set of buffers 1240. In some embodiments, the first tracking metal line 1250 and the second tracking metal line 1255 are coupled between the delay chain 1220 and the NAND gate 1260. Additionally, the first tracking metal line 1250 physically extends along the row direction of the corresponding memory array, while the second tracking metal line 1255 physically extends along the column direction of the memory array. In other words, the length of each of the first tracking metal lines 1250 can be proportional to the width of the memory array, and the length of each of the second tracking metal lines 1255 can be proportional to the height of the memory array. For example, the first of the first tracking metal lines 1250 can extend from a first edge of the memory array to the midpoint of the memory array, while the second of the first tracking metal lines 1250 can extend from the midpoint to the first edge of the memory array; and the first of the second tracking metal lines 1255 can extend from a second edge of the memory array to the midpoint of the memory array, while the second of the second tracking metal lines 1255 can extend from the midpoint to the second edge of the memory array. In some embodiments, the first edge can be perpendicular to the second edge.

[0077] Figure 13 Exemplary waveforms of various signals over time when operating a timing controller 116 operably coupled to a memory array 120 in accordance with various embodiments of the present disclosure are shown. For example, when operating the timing controller 116, CKP1, CKP2, BLEQ2IO signals, and BLEQB signals are shown. It should be understood that Figure 13 the waveforms of the signals shown in

[0078] are for illustrative purposes only. Thus, the configuration (e.g., scale) of these signals can be changed while remaining within the scope of the present disclosure. Figure 13As shown, CKP1 and CKP2 each have their own pulses. CKP1 can be generated (e.g., pulled up) in response to a clock signal, while CKP2 can be generated immediately after CKP1 (e.g., pulled down). In some examples, the pulses of CKP1 and CKP2 can be within a half period of the clock signal. The pulse of CKP2 follows the pulse of CKP1, i.e., CKP1 remains at logic 0 after being pulled low, while CKP2 remains at logic 1 until being pulled high. In one aspect, the pulse of CKP1 can be configured for the read operation of the memory array 120, while the pulse of CKP2 can be configured for the write operation of the memory array 120. In another aspect, the pulse of CKP1 can be configured for the write operation of the memory array 120, while the pulse of CKP2 can be configured for the read operation of the memory array 120.

[0079] Using Figures 3 to 12 In any of the embodiments shown, the rising edge of CKP2 (or its pulse) can be delayed with respect to the falling edge of CKP1 (or its pulse), as indicated by the symbol arrow 1301. This intentional delay can advantageously help widen the pulse window of the BLEQ2IO signal, the logically inverted version of which is the BLEQB signal configured to activate the corresponding precharge circuit (e.g., 118). As described above, the BLEQ2IO signal is generated by performing a NOR operation on CKP1 and CKP2. Thus, the pulse window of the BLEQ2IO signal is determined based on the time difference between the falling edge of CKP1 and the rising edge of CKP2. When the BTI effect is present, the pulse window of the BLEQ2IO signal may be compressed, e.g., using a delayed rising edge. To compensate for this effect, the delayed rising edge of CKP2 can help delay the falling edge of the BLEQ2IO signal, as indicated by the symbol arrow 1303. Thus, even when the BTI effect is present, the compressed pulse window of the BLEQ2IO signal can be restored.

[0080] Figure 14 A flowchart illustrating an example method 1400 for operating a memory circuit in accordance with various embodiments of the present disclosure. The operations of method 1400 can be performed by the above components (e.g., Figures 1 - 13 ), and thus, some of the reference numerals used above can be reused in the following discussion of method 1400. For example, method 1400 can be performed by a timing controller to track the BTI effect and thus optimize the pulse window of the precharge signal. Additionally, it should be understood that method 1400 has been simplified, and thus, additional operations can be provided before, during, and after method 1400 of Figure 14 , and some other operations may only be briefly described herein.

[0081] Method 1400 begins with operation 1410, receiving a first clock pulse that is a first operational configuration for a first memory cell within a memory array. In some embodiments, the memory array may include multiple memory cells, and each memory cell may be configured as a dual-pumped SRAM cell. For example, any memory cell can be sequentially read and then written within one cycle of a clock signal. In some embodiments, the first clock pulse may be generated in response to the rising edge of the clock signal. Using Figure 1 memory circuit 100 of

[0082] as a non-limiting example, the timing controller 116 may receive the clock signal and generate the first clock pulse (e.g., CKP1) in response to the clock signal being pulled up.

[0083] Method 1400 proceeds to operation 1420, delaying the first clock pulse into a second clock pulse that is configured for a second operation of a second memory cell within the memory array. As a non-limiting example, the first memory cell may be selected for reading according to the first clock pulse (CKP1) first, and then the second memory cell may be selected for writing according to the second clock pulse (e.g., CKP2). In some embodiments, the first memory cell and the second memory cell are different memory cells and may be arranged on the same word line WL or on respective word lines WL. In some other embodiments, the first memory cell and the second memory cell may be the same memory cell. The first clock pulse and the second clock pulse following the first clock pulse are within one clock cycle. Continuing with the above example, the timing controller 116 may generate the second clock pulse (CKP2) immediately after the first clock pulse (CKP1). Additionally, according to various embodiments, the timing controller 116 may include a delay chain that is configured to delay the first clock pulse into the second clock pulse.

[0084] Method 1400 proceeds to operation 1440 to generate a precharge signal, the pulse width of which is determined based on the time difference between the first clock pulse and the second clock pulse. Continuing with the above example, the timing controller 116 can generate the precharge signal (e.g., the BLEQ2IO signal or its logically inverted version, the BLEQB signal) by performing a NOR operation on the first clock pulse (CKP1) and the second clock pulse (CKP2). In some embodiments, the pulse width of the BLEQ2IO signal is determined based on the time difference between the falling edge of CKP1 and the rising edge of CKP2. When there is a BTI effect, the timing controller 116 can track this effect to delay the rising edge of CKP2, thereby widening or maintaining the pulse width of BLEQ2IO. Thus, the corresponding precharge circuit (e.g., 118) can have sufficient time to precharge the bit lines to the correct voltage level.

[0085] In one aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes a memory array, the memory array including a plurality of memory cells, wherein each of the plurality of memory cells is accessible via a plurality of access lines. The memory circuit includes a delay circuit configured to receive a first clock pulse and delay the first clock pulse to a second clock pulse, where the second clock pulse follows the first clock pulse. The memory circuit includes a logic gate configured to receive the first clock pulse and the second clock pulse and provide a precharge signal for precharging the plurality of access lines based on the first and second clock pulses. The delay circuit includes a plurality of inverters and a plurality of transistors such that the time difference between a first transition edge of the first clock pulse and a second transition edge of the second clock pulse lengthens as the usage duration of the memory circuit increases.

[0086] In some embodiments, the first clock pulse and the second clock pulse are within one clock cycle.

[0087] In some embodiments, the first transition edge is a falling edge and the second transition edge is a rising edge.

[0088] In some embodiments, at least the first memory cell is configured to be read during the first clock pulse, at least the second memory cell is configured to be programmed, and the access lines of the memory cells are configured to be precharged to the logical state between the first clock pulse and the second clock pulse.

[0089] In some embodiments, the plurality of transistors include p-type transistors connected to even levels of the plurality of inverters, and wherein the respective gate terminals of the p-type transistors are connected to VSS.

[0090] In some embodiments, the plurality of transistors include p-type transistors connected to the even levels of the plurality of inverters and n-type transistors connected to the odd levels of the plurality of inverters, and wherein the respective gate terminals of the p-type transistors are connected to VSS, and the respective gate terminals of the n-type transistors are connected to VDD.

[0091] In some embodiments, the plurality of transistors include p-type transistors connected to the first stage of the plurality of inverters and n-type transistors connected to the inputs of the second stage of the plurality of inverters, and wherein the respective gate terminals of the p-type transistors and the n-type transistors are both connected to a control signal.

[0092] In some embodiments, the control signal is provided in a first logic state during a first clock pulse, a time difference, and a second clock pulse, and is provided in a second logic state outside of the first clock pulse, the time difference, and the second clock pulse.

[0093] In some embodiments, the plurality of transistors include a transmission gate connected to the output of the last stage of the plurality of inverters, and wherein the transmission gate has a p-type transistor with a gate terminal connected to VSS and an n-type transistor with a gate terminal connected to VDD.

[0094] In some embodiments, the precharge signal has a pulse width determined based on the time difference.

[0095] In some embodiments, the delay circuit further includes a plurality of metal lines, and the length of each metal line is proportional to the height of the memory array.

[0096] In some embodiments, the delay circuit further includes a plurality of metal lines, and the length of each metal line is proportional to the width of the memory array.

[0097] In another aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes a delay circuit configured to receive a first clock pulse and delay the first clock pulse into a second clock pulse, wherein the first clock pulse and the second clock pulse are within one clock cycle. The delay circuit includes a plurality of inverters and a plurality of transistors, and the plurality of transistors are configured to delay the rising edge of the second clock pulse following the falling edge of the first clock pulse according to an increased usage duration of the memory circuit.

[0098] In some embodiments, the plurality of transistors include p-type transistors connected to the even levels of the plurality of inverters, and wherein the respective gate terminals of the p-type transistors are connected to VSS.

[0099] In some embodiments, the plurality of transistors includes p-type transistors connected to the even stages of the plurality of inverters and n-type transistors connected to the odd stages of the plurality of inverters, and wherein the respective gate terminals of the p-type transistors are connected to VSS, and the respective gate terminals of the n-type transistors are connected to VDD.

[0100] In some embodiments, the plurality of transistors includes p-type transistors connected to the first stage of the plurality of inverters and n-type transistors connected to the inputs of the second stage of the plurality of inverters, and wherein the respective gate terminals of the p-type transistors and the n-type transistors are both connected to a control signal.

[0101] In some embodiments, the plurality of transistors includes a transmission gate connected to the output of the last stage of the plurality of inverters, and wherein the transmission gate has a p-type transistor with a gate terminal connected to VSS and an n-type transistor with a gate terminal connected to VDD.

[0102] In some embodiments, the memory circuit further includes: a logic gate configured to receive a first clock pulse and a second clock pulse and provide a precharge signal by performing an OR operation on the first clock pulse and the second clock pulse; wherein the precharge signal is configured to precharge a plurality of bit lines, and the pulse width of the precharge signal is determined based on the time difference between the first clock pulse and the second clock pulse.

[0103] In another aspect of the present disclosure, a method for operating a memory circuit is disclosed. The method includes receiving a first clock pulse configured for a first operation of a first memory cell within a memory array. The method includes delaying the first clock pulse to a second clock pulse configured for a second operation of a second memory cell within the memory array, wherein the first clock pulse and the second clock pulse following the falling edge of the first clock pulse are within one clock cycle. The method includes precharging a first bit line coupled to the first memory cell and a second bit line coupled to the second memory cell. The method includes delaying the rising edge of the second clock pulse.

[0104] In some embodiments, the method further includes: providing a precharge signal between the first clock pulse and the second clock pulse, the pulse width of the precharge signal being determined based on the falling edge of the first clock pulse and the rising edge of the second clock pulse; wherein the precharge signal is configured to precharge all bit lines of the memory array.

[0105] As used herein, the words "about" and "approximately" generally denote a value of a given quantity, which may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the word "about" may denote a value of a given quantity that varies within, for example, 10 - 30% of that value (e.g., +10%, ±20%, or ±30% of that value).

[0106] The components of several embodiments have been described above, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that it is easy to use the present invention as a basis to design or modify other processes and structures to achieve the same purpose and / or realize the same advantages as the embodiments introduced in the present invention. Those skilled in the art should also be aware that these equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present invention.

Claims

1. A memory circuit, comprising: A memory array including a plurality of memory cells, wherein each of the plurality of memory cells is accessible via a plurality of access lines; A delay circuit configured to receive a first clock pulse and delay the first clock pulse into a second clock pulse, wherein the second clock pulse follows the first clock pulse; A logic gate configured to receive the first clock pulse and the second clock pulse and provide a precharge signal for precharging the plurality of access lines based on the first clock pulse and the second clock pulse; Wherein the delay circuit includes a plurality of inverters and a plurality of transistors such that a time difference between a first transition edge of the first clock pulse and a second transition edge of the second clock pulse extends as the usage duration of the memory circuit increases.

2. The memory circuit according to claim 1, wherein, The first clock pulse and the second clock pulse are within one clock cycle.

3. The memory circuit according to claim 1, wherein, The first transition edge is a falling edge and the second transition edge is a rising edge.

4. The memory circuit according to claim 1, wherein, At least a first memory cell is configured to be read during the first clock pulse, at least a second memory cell is configured to be programmed, and access lines of the memory cells are configured to be precharged to a logical state between the first clock pulse and the second clock pulse.

5. The memory circuit according to claim 1, wherein, The plurality of transistors include p-type transistors connected to even levels of the plurality of inverters, and wherein respective gate terminals of the p-type transistors are connected to VSS.

6. The memory circuit according to claim 1, wherein, The plurality of transistors include p-type transistors connected to even levels of the plurality of inverters and n-type transistors connected to odd levels of the plurality of inverters, and wherein respective gate terminals of the p-type transistors are connected to VSS and respective gate terminals of the n-type transistors are connected to VDD.

7. The memory circuit according to claim 1, wherein, The plurality of transistors include a p-type transistor connected to a first stage of the plurality of inverters and an n-type transistor connected to an input of a second stage of the plurality of inverters, and wherein respective gate terminals of the p-type transistor and the n-type transistor are both connected to a control signal.

8. The memory circuit according to claim 7, wherein, The control signal is provided in a first logical state during the first clock pulse, the time difference, and the second clock pulse, and is provided in a second logical state outside the first clock pulse, the time difference, and the second clock pulse.

9. A memory circuit, comprising: A delay circuit configured to receive a first clock pulse and delay the first clock pulse into a second clock pulse, wherein the first clock pulse and the second clock pulse are within one clock cycle; Wherein the delay circuit includes a plurality of inverters and a plurality of transistors, and the plurality of transistors are configured to delay a rising edge of a second clock pulse following a falling edge of the first clock pulse according to an increase in the usage duration of the memory circuit.

10. A method of operating a memory circuit, comprising: Receiving a first clock pulse configured for a first operation of a first memory cell within a memory array; Delay the first clock pulse to a second clock pulse, the second clock pulse being configured for a second operation of a second memory cell within the memory array, wherein the first clock pulse and the second clock pulse following the falling edge of the first clock pulse are within one clock cycle; Precharge a first bit line coupled to the first memory cell and a second bit line coupled to the second memory cell; and Delay the rising edge of the second clock pulse.

Images