Integrated circuit system, DRAM circuitry, method for forming integrated circuit system, and method for forming DRAM circuitry

Abstract

The invention relates to an integrated circuit system, a DRAM circuit system, a method for forming the integrated circuit system and a method for forming the DRAM circuit system. A method for forming an integrated circuit system includes forming a plurality of conductive vias including a conductive material. The conductive paths are spaced from each other by an intermediate material. A discontinuous material is formed on top of the conductive material of the vias and on top of the intermediate material between the vias. A metallic material is formed on top of the discontinuous materials, directly against the discontinuous materials and between the discontinuous materials and on top of the conductive material of the via and directly against the conductive material of the via. The metallic material has a composition different from that of the discontinuous material and is over the intermediate material between the passages. Structures independent of the method are disclosed.

Description

[0001] Relevant information on divisional applications

[0002] This application is a divisional application. Its parent application is a patent application for invention with the application date of February 21, 2020, application number 202080019662.7, and invention title "Integrated Circuit System, DRAM Circuit System, Method for Forming an Integrated Circuit System, and Method for Forming a DRAM Circuit System". Technical Field

[0003] The embodiments disclosed herein relate to an integrated circuit system, a DRAM circuit system, a method for forming an integrated circuit system, and a method for forming a DRAM circuit system. Background Art

[0004] A memory is a type of integrated circuit and is used to store data in a computer system. Memories can be fabricated as one or more arrays of individual memory cells. Digital lines (also referred to as bit lines, data lines, or sense lines) and access lines (also referred to as word lines) can be used to write to or read from the memory cells. The digital lines can conductively interconnect the memory cells along the columns of the array, and the access lines can conductively interconnect the memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of digital lines and access lines.

[0005] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for a long time without power. Conventionally, non-volatile memory is designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is thus refreshed / rewritten to maintain data storage. Volatile memory can have a hold time of a few milliseconds or less. In any case, the memory cells are configured to retain or store the memory in at least two different selectable states. In a binary system, the states are considered "0" or "1". In other systems, at least some individual memory cells can be configured to store more than two information levels or states.

[0006] A capacitor is a type of electronic component that can be used in a memory cell. A capacitor has two electrical conductors separated by an electrically insulating material. Energy can be stored electrostatically as an electric field within this material. Depending on the composition of the insulator material, the storage field will be volatile or non-volatile. For example, a capacitor insulator material consisting only of SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor, which has a ferroelectric material as at least part of the insulating material. A ferroelectric material is characterized by having two stable polarization states and can thus comprise a programmable material for a capacitor and / or a memory cell. The polarization state of a ferroelectric material can be changed by applying an appropriate programming voltage and remains (at least for some time) after the programming voltage is removed. Each polarization state has a charge storage capacitance different from the other, and ideally, it can be used to write (i.e., store) and read a memory state without inverting the polarization state until such inversion is desired. Less desirably, in some memories having ferroelectric capacitors, the act of reading the memory state can cause the polarization to invert. Therefore, when determining the polarization state, the memory cell is rewritten immediately after its determination to place the memory cell in the pre-read state. In any case, due to the bistable nature of the ferroelectric material forming part of the ferroelectric capacitor, ideally, the memory cell incorporating the capacitor is non-volatile. Other programmable materials can be used as capacitor insulators to make the capacitor non-volatile.

[0007] A field effect transistor is another type of electronic component that can be used in a memory cell. These transistors include a pair of conductive source / drain regions with a semiconductor channel region therebetween. A conductive gate is adjacent to the channel region and is separated therefrom by a thin gate insulator. Applying an appropriate voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is largely prevented. A field effect transistor can also include additional structures, such as a reversible programmable charge storage region, as part of the gate structure between the gate insulator and the conductive gate. In any case, the gate insulator can be programmable, e.g., ferroelectric.

[0008] Flash memory is a type of memory and has numerous uses in modern computers and devices. For example, a modern personal computer can have a BIOS stored on a flash memory chip. As another example, computers and other devices are increasingly commonly using flash memory in solid state drives to replace conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade the device to enhance features.

[0009] NAND can be the infrastructure for integrated flash memory. The NAND cell unit includes at least one select device, which is serially coupled to a serial combination of memory cells (the serial combination is commonly referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement, which includes vertically stacked memory cells, and the memory cells individually include reversibly programmable vertical transistors. Control circuitry or other circuitry can be formed under the vertically stacked memory cells. Other volatile or non-volatile memory array architectures can also include vertically stacked memory cells that individually include transistors.

[0010] Capacitors and transistors can of course be used in circuitry other than memory circuitry. In any case, conductive interconnects are used to connect the various components of an integrated circuit system. SUMMARY OF THE INVENTION

[0011] One aspect of the present disclosure provides an integrated circuit system, which includes: a plurality of conductive vias, which include conductive material, and the conductive vias are spaced apart from each other by an intermediate material; a conductive wire, which is on top of the intermediate material between the vias and is directly electrically coupled to an individual one of the vias, and the conductive wire includes elemental form Ru that directly abuts the conductive material of the via; and a discontinuous material, which includes a separated portion vertically between the conductive wire and the conductive material of the via and a separated portion vertically between the conductive wire and the intermediate material between the vias, and the discontinuous material has a composition different from that of elemental form Ru.

[0012] Another aspect of the present disclosure provides an integrated circuit system, which includes: a plurality of conductive vias, which include conductive material, and the conductive vias are spaced apart from each other by an intermediate material; a conductive wire, which is on top of the intermediate material between the vias and is directly electrically coupled to an individual one of the vias, and the conductive wire includes elemental form Mo that directly abuts the conductive material of the via; and a discontinuous material, which includes a separated portion vertically between the conductive wire and the conductive material of the via and a separated portion vertically between the conductive wire and the intermediate material between the vias, and the discontinuous material has a composition different from that of the elemental form Mo.

[0013] Another aspect of the present disclosure provides a memory circuit system, comprising: digital lines that conductively interconnect memory cells of the memory circuit system; conductive vias that individually and directly electrically couple individual ones of the memory cells to individual ones of the digital lines, the conductive vias comprising a conductive material and being spaced apart from each other by an intermediate material, the individual digital lines being on top of the intermediate material, the digital lines comprising elemental form Ru directly abutting the conductive material of the conductive vias; and a discontinuous material that comprises separated portions vertically between the individual digital lines and the conductive material of the conductive vias and separated portions vertically between the individual digital lines and the intermediate material, the discontinuous material having a composition different from that of the elemental form Ru.

[0014] Another aspect of the present disclosure provides a memory circuit system, comprising: digital lines that conductively interconnect memory cells of the memory circuit system; conductive vias that individually and directly electrically couple individual ones of the memory cells to individual ones of the digital lines, the conductive vias comprising a conductive material and being spaced apart from each other by an intermediate material, the individual digital lines being on top of the intermediate material, the digital lines comprising elemental form Mo directly abutting the conductive material of the conductive vias; and a discontinuous material that comprises separated portions vertically between the individual digital lines and the conductive material of the conductive vias and separated portions vertically between the individual digital lines and the intermediate material, the discontinuous material having a composition different from that of the elemental form Mo. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic cross-sectional view of a part of a DRAM configuration according to some embodiments of the present invention and is taken along Figures 2 to 8 line 1-1 in

[0016] Figure 2 is a view taken along Figure 1 , 7 and line 2-2 in 8.

[0017] Figure 3 is a view taken along Figure 1 , 7 and line 3-3 in 8.

[0018] Figure 4 is a view taken along Figure 1 , 7 and line 4-4 in 8.

[0019] Figure 5 is a view taken along Figure 1 , 7and a view taken along line 5-5 in FIG. 8.

[0020] Figure 6 is taken along Figure 1 , 7 and a view taken along line 6-6 in FIG. 8.

[0021] Figure 7 is taken along Figures 1 to 6 a view taken along line 7-7 in FIG.

[0022] Figure 8 is taken along Figures 2 to 6 a view taken along line 8-8 in FIG.

[0023] Figures 9 to 29 is a schematic sequential cross-sectional view of a precursor structure of an in-progress Figures 1 to 8 in accordance with some embodiments of the present invention.

[0024] Figures 30 to 32 is a schematic sequential cross-sectional view of an alternative precursor structure of an in-progress Figures 9 to 28 precursor structure shown as DETAILED DESCRIPTION

[0025] Embodiments of the present invention encompass integrated circuit system architectures such as DRAM architectures, and methods for forming integrated circuit system architectures for, e.g., DRAM circuit system architectures. Referring Figures 1 to 8 to a first exemplary embodiment including a DRAM architecture, Figures 1 to 8 an exemplary fragment of a substrate structure 8 including an array or array region 10 fabricated relative to a base substrate 11 is shown. The substrate structure 11 may include any one or more of conductive / conductor / conductive, semiconductive / semiconductor / semiconductive, and insulating / insulator / insulating (i.e., electrically herein) materials. Various materials are on the base substrate 11. The materials may be Figures 1 to 8 beside, vertically internal, or vertically external to the materials depicted. For example, other parts or all of the manufacturing components of the integrated circuit system may be provided somewhere above, around, or within the base substrate 11. Control circuitry and / or other peripheral circuitry for operating the components within the memory array may also be fabricated and may or may not be all or part within the memory array or subarray. Additionally, multiple subarrays may be fabricated and operated independently, in series, or otherwise relative to each other. As used in this document, a "subarray" may also be considered an array.

[0026] The base substrate 11 includes a semiconductor material 12 (such as appropriately and differently doped single-crystalline silicon and / or polycrystalline silicon, Ge, SiGe, GaAs, and / or other existing or future-developed semiconductor materials), a trench isolation region 14 (such as silicon nitride and / or silicon dioxide), and an active area region 16 (which includes appropriately and differently doped semiconductor material 12). In one embodiment, the structure 8 includes memory cells 75 ( Figure 4 , 5 and 8. For clarity in such diagrams, only four outlines 75 are shown in Figure 4 and 5 , and only two outlines 75 are shown in Figure 8 ), for example, individually including field effect transistor devices 25 ( Figure 3 ) and storage elements (such as, capacitor 85; Figure 1 and 8 ) of a DRAM memory cell. However, embodiments of the present invention cover other memory cells and other integrated circuit system structures, regardless of whether they contain memory cells.

[0027] Example transistor devices 25 individually include a pair of source / drain regions, a channel region between the pair of source / drain regions, a conductive gate operably close to the channel region, and a gate insulator between the conductive gate and the channel region. Device 25 is shown as a recessed access device, and example structure 8 shows such recessed access devices grouped in individual pairs of such devices. Individual recessed access devices 25 include a buried access line structure 18, for example, within a trench 19 in the semiconductor material 12. Structure 18 includes a conductive gate material 22 (such as, a conductively doped semiconductor material and / or a metal material, which includes, for example, elements W, Ru, and / or Mo) that serves as the conductive gate of the individual device 25. Gate insulator 20 (such as, silicon dioxide and / or silicon nitride) lines the sidewalls 21 and the base 23 of the individual trench 19 between the conductive gate material 22 and the semiconductor material 12. Insulating material 37 (such as, silicon dioxide and / or silicon nitride) is within the trench 19 above materials 20 and 22. Individual devices 25 include a pair of source / drain regions 24, 26 (such as, regions 24, 26 are laterally external to the access line structure 18 and above the access line structure 18) in the upper portions of the semiconductor material 12 on opposite sides of the individual trench 19. At least a portion of each of the source / drain regions 24, 26 has a conductivity-increasing dopant therein, and the conductivity-increasing dopant has a maximum concentration of this dopant within the corresponding source / drain regions 24, 26, for example, to render this portion conductive (such as, having at least 10 19 atoms / cm 3(maximum dopant concentration). Thus, all or only a portion of each source / drain region 24, 26 may have this maximum concentration of conductivity-increasing dopant. The source / drain regions 24 and / or 26 may include other doped regions (not shown), such as halo regions, LDD regions, and the like.

[0028] One of the source / drain regions (e.g., region 26) of the pair of source / drain regions in each of the plurality of individual recessed access devices 25 is laterally between the conductive gate materials 22 and is shared by the pair of devices 25. The other of the source / drain regions (e.g., region 24) of the pair of source / drain regions is not shared by the pair of devices 25. Thus, in an example embodiment, each active region 16 includes two devices 25 (e.g., a pair of devices 25), each of which shares a central source / drain region 26.

[0029] Example channel regions 27 ( Figure 1 , 3 , 7, and 8) are located in the semiconductor material 12 below a pair of source / drain regions 24, 26 and along the trench sidewalls 21 ( Figure 7 and 8 ) and around the trench base 23. The channel regions 27 may be undoped or may be suitably doped with a conductivity-increasing dopant that may have a conductivity type opposite to that of the dopant in the source / drain regions 24, 26, and for example, the maximum concentration in its channel is not greater than 1×10 17 atoms / cm 3 . When a suitable voltage is applied to the gate material 22 of the access line structure 18, a conductive channel is formed in the channel region 27 near the gate insulator 20 (e.g., along the channel current flow line / path 28 Figure 8 ), enabling current to flow between a pair of source / drain regions 24 and 26 below the access line structure 18 within an individual active region 16. Dashed lines are schematically shown to indicate the major conductivity-modifying dopant concentration (regardless of type), where denser dashed lines indicate a higher dopant concentration and lighter dashed lines indicate a lower dopant concentration. Conductivity-modifying dopants may and likely are in other parts of the material 12, as shown. For convenience, only two different dashed line densities are shown in the material 12, and additional dopant concentrations may be used, and a constant dopant concentration is not required in any region.

[0030] A first conductive / conductor path 36 is individually and directly electrically coupled to one of the source / drain regions (e.g., 24) of the pair of source / drain regions. A storage element (e.g., capacitor 85) is directly electrically coupled to the individual first conductive / conductor path 36.

[0031] The second conductive vias 33 are each directly and individually electrically coupled to the other of the source / drain regions (e.g., 26) in the pair of source / drain regions. The second vias 33 are spaced relative to each other (e.g., longitudinally relative to the digit line 39 thereabove, as described below) by an intermediate material (e.g., one or more of materials 32, 37, 14, 38, 48, and / or 46 when present, where materials 32, 38, 48, and 46 are described below) and include conductive materials (e.g., 34 and 35). In one embodiment, the conductive materials 34 / 35 of the second vias 33 include a lower conductively doped semiconductive material 34 (e.g., conductively doped polysilicon) beneath an upper conductive material 35 (e.g., a metal material) having a composition different from that of the conductive doped semiconductive material 34. Additional example conductive materials for materials 34 and 35 and by way of example only include metal nitrides (e.g., TiN, TaN, WN, MoN), metal carbonitrides (e.g., TiCN, TaCN, WCN, MoCN), and metals in elemental form (e.g., Ti, Ta, W, Mo, Co, Cu, Ru, Be), including combinations, compounds, and alloys thereof.

[0032] The digit line 39 is on top of the intermediate materials 32, 37, 14, 38, 48, 46 between and directly electrically coupled to the respective second vias 33 of the plurality of transistors 25. The digit line 39 includes a metal material 42 (e.g., elemental W, Ru, and / or Mo) directly abutting the conductive materials 34 / 35 of the second vias 33. Example digit lines 39 include portions of the digit line structure 30 that include opposing longitudinally insulating sides 38 (e.g., silicon dioxide and / or silicon nitride) and an insulating cap 50 (e.g., silicon nitride and / or silicon dioxide). Example material 46 is beneath the digit line 39 between longitudinally adjacent second vias 33. A lower insulating material 48 (e.g., one or more of silicon dioxide, silicon nitride, aluminum dioxide, hafnium oxide, etc.; e.g., a thickness of 50 to 200 angstroms) is beneath the material 46 between longitudinally adjacent second vias 33. The material 46 can be insulating, semiconductive (i.e., a material not sufficiently doped to be conductive), or conductive or can be removed, with the metal material 42 extending into the lower insulating material 48 (not shown).

[0033] In one embodiment, the topmost portion of the intermediate material (e.g., the topmost portion of one or both of materials 32 and 46) includes an insulating material, includes a conductive material in one embodiment, and includes a semiconductive material (i.e., not sufficiently doped to be conductive) in one embodiment. In one embodiment, if conductive, the topmost portion of the intermediate material includes a conductively doped semiconductive material. In one embodiment, the topmost portion of the intermediate material includes an insulating material and a conductive material. By way of example only, example insulating materials include silicon dioxide, silicon nitride, aluminum oxide, high-k materials, low-k materials, hafnium oxide, zirconium oxide, and insulating metal oxides including combinations of two or more elemental metals. Example conductive materials include conductively doped polysilicon, which is an example of a conductively doped semiconductive material, and metallic materials. An example semiconductive material is undoped or lightly doped polysilicon.

[0034] The discontinuous material 55 is vertically between the digital line 39 and the conductive materials 34 / 35 of the second via 33, and is vertically between the intermediate materials 32, 46 between the digital line 39 and the second via 33. The discontinuous material 55 has a composition different from that of the metallic material 42 of the digital line 39. In one embodiment and as shown, the discontinuous material 55 includes void spaces therethrough (i.e., void spaces laterally between and among spaced-apart portions of the material 55), where the void spaces have a total horizontal area greater than the total horizontal area of the material of the discontinuous material 55. In one embodiment, the discontinuous material is insulating, is conductive in one embodiment, is semiconductive in one embodiment, and includes silicon in elemental form in one embodiment. In one embodiment, the discontinuous material 55 includes a metal in elemental form (e.g., Ti, Ta, W, Mo, Co, Cu, Ru, Be), and has a composition different from that of the conductive materials 34 / 35 in one embodiment.

[0035] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0036] Embodiments of the present invention cover integrated circuit system configurations (e.g., 8) that are independent of whether DRAM or other memory circuitry is included. This configuration includes a plurality of conductive vias (e.g., 33) that are spaced from each other by an intervening material (when present, one or more of materials 32, 37, 14, 38, 48, and / or 46). Conductive lines (e.g., 39) are on top of the intervening material between the vias and are directly electrically coupled to individual ones of the vias. The conductive lines include a metallic material (e.g., 42) that abuts directly against the conductive material (e.g., 34 / 35) of the vias. A discontinuous material (e.g., 55) is vertically between the conductive material of the conductive lines and the vias and is vertically between the conductive lines and the intervening material located between the vias. The discontinuous material has a composition different from that of the metallic material. In one embodiment, the conductive lines are part of a memory circuit system (e.g., digital lines) that includes a NAND architecture. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0037] Embodiments of the present invention cover a method for forming an integrated circuit system configuration (e.g., including DRAM, other memory, and / or non-memory circuitry). In any case, aspects of the methods of the present invention may use or have any of the properties described herein in the structural and / or device embodiments. Similarly, the structural embodiments described above may incorporate any of the properties described with respect to aspects of the method embodiments.

[0038] Initially referring to Figures 9 to 29 Describe an example method embodiment and an example of this embodiment for generating Figures 1 to 8 the configuration 8. Referring to Figure 9 and 10 this shows Figure 1 and 7 a precursor configuration of the configuration where structure 8 has been fabricated to the point of including materials 46 and 48 within array 10. Figures 11 to 13 An opening 56 is shown as being formed therethrough to the source / drain region 26 and, in one embodiment, to a height below the bottom of material 48 as shown.

[0039] Referring to Figures 14 to 16, the opening 56 has been lined with the insulating material 32 and then anisotropically etched to remove the material 32 centered above the source / drain regions 26. The conductive materials 34 / 35 are then formed and planarized back to at least the vertical outermost surfaces of the materials 46 and 32. This includes only one example of forming the conductive vias 33, which are individually directly electrically coupled to one of the source / drain regions (e.g., 26) in the pair of source / drain regions. The conductive vias 33 are spaced relative to each other by an intermediate material (e.g., one or more of the materials 32, 37, 14, 48, and / or 46 when present) and include the conductive materials 34 / 35. In one such embodiment, the method sequentially includes forming a lower conductive doped semiconductor material (e.g., 34) within the opening 56 in the intermediate material. For example, this can be formed to completely fill the remaining volume of the opening 56 and then at least planarized back to the vertical outermost surfaces of the materials 32 and 46. Then, the conductive doped semiconductor material 34 is vertically recessed (e.g., by etching) within the opening 56. Thereafter, a conductor material 35 is formed on top of the vertically recessed conductive doped semiconductor material 34 within the opening 56, e.g., to overfill the remaining volume of the opening 56 and then at least planarized back to the vertical outermost surfaces of the materials 32 and 46.

[0040] Reference Figures 17 to 19 , a discontinuous material 55 has been formed on top of the conductive materials 34 / 35 of the conductive vias 33 and on top of the intermediate materials 32 and 46 between the conductive vias 33.

[0041] Reference Figures 20 to 22 , a metal material 42 has been formed on top of the discontinuous material 55, directly against the discontinuous material 55 and between the discontinuous materials 55 and on top of the conductive materials 34 / 35 of the conductive vias 33 and directly against the conductive materials 34 / 35 of the conductive vias 33 and over the intermediate materials 32 and 46 between the conductive vias 33. The discontinuous material 55 can be used as a crystal growth seed material to promote the growth of the metal material 42 such that the metal material 42 forms in a desired crystal orientation / phase. An example insulating material 50 has been formed on top of it.

[0042] Reference Figures 23 to 25 , the metal material 42 having the discontinuous material 55 thereunder has been formed (e.g., by subtractive etching) to include digital lines 39 on top of the intermediate materials 32 and 46 between the conductive vias 33 and directly against the individual conductive vias 33 of a plurality of transistors 25. For example, and in one embodiment, the plurality of digital lines 39 have been formed by subtractive patterning and etching, where in one example, the etching removes the discontinuous material 55 laterally between the lines 39.

[0043] Reference Figures 26 to 28, insulating spacers 38 leading to the formation of digit line structures 30 have been formed, and dielectric material 40 deposited therebetween. Figure 29 An opening 41 is shown formed therethrough to the source / drain region 24. Processing will then occur to produce Figures 1 to 8 For example, a conductor via 36 will be formed in the opening 41 to be directly electrically coupled to the other source / drain region 24 in the source / drain region pair. A storage element (e.g., capacitor 85) will be formed to be directly electrically coupled to an individual one of the conductor vias 36.

[0044] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0045] The example processing and depicted constructions described above show the formation of multiple digit lines 39 that are laterally spaced relative to each other, wherein discontinuous material is not laterally between such multiple digit lines 39. For example, Figures 23 to 25 The discontinuous material 55 is shown removed from between the digit lines 39. Alternatively, the discontinuous material may be laterally between multiple digit lines, such as with respect to Figures 30 to 32 8a and an alternative embodiment structural embodiment are shown and described in FIG. 8a. Like numerals from the above-described embodiments are used where appropriate, with some structural differences indicated by the suffix "a".

[0046] refer to Figure 30 and 31 , patterning metal material 42 to form digit lines 39 has left discontinuous material 55 laterally therebetween. Figure 32 Subsequent processing is shown whereby the discontinuous material 55 is thus maintained outside the level of the conductive / conductor vias 36. In one embodiment, the discontinuous material 55 is non-insulating (e.g., elemental silicon), and the method further includes converting the non-insulating discontinuous material 55 to be lateral insulation between the plurality of conductive lines (e.g., by annealing in an oxygen-containing environment). For example, and by way of example only, elemental silicon as material 55 may be annealed in an oxygen-containing environment to form silicon dioxide material 55, or the conductive material 55 may be coated with a non-conductive material. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0047] Embodiments of the present invention encompass a method for forming an integrated circuit system, regardless of whether the circuit system is a DRAM or other memory circuit system. The method includes forming a plurality of conductive vias (e.g., 33) including a conductive material (e.g., 34 / 35). The conductive vias are spaced relative to each other by an intervening material (e.g., one or more of materials 32, 37, 14, 38, 48, and / or 46 when present). A discontinuous material (e.g., 55) is formed on top of the conductive material of the vias and on top of the intervening material between the vias. A metal material (e.g., 42) is formed on top of the discontinuous material, directly against the discontinuous material, and between the discontinuous materials and on top of the conductive material of the vias and directly against the conductive material of the vias. The metal material has a composition different from that of the discontinuous material and is over the intervening material between the vias. The metal material having the discontinuous material thereunder is formed to include conductive lines (e.g., 39) on top of the intervening material between the vias and directly against individual ones of the vias. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0048] The above processing or construction may be considered with respect to an array of components formed as a single stack or single layer of such components or formed within a single stack or single layer of such components over or as part of a portion of a underlying base substrate (although the single stack / layer may have multiple layers). Control circuitry and / or other peripheral circuitry for operating or accessing such components in the array may also be formed anywhere as part of the completed construction and, in some embodiments, may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / layers may be provided or fabricated above and / or below the stack / layer shown in the figures or described above. Further, the arrays of components may be the same or different relative to each other in different stacks / layers. Intermediate structures (e.g., additional circuitry and / or dielectric layers) may be provided between closely vertically adjacent stacks / layers. Additionally, different stacks / layers may be electrically coupled to each other. Multiple stacks / layers may be fabricated individually and sequentially (e.g., one on top of the other) or two or more stacks / layers may be fabricated substantially simultaneously.

[0049] The assemblies and structures discussed above may be used in integrated circuits and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and specialized modules and may include multi-layer, multi-chip modules. The electronic system may be any of a wide range of systems, such as (by way of example) cameras, wireless devices, displays, chip sets, set-top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, airplanes, etc.

[0050] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "on top of", "bottom", "above", "below", "beneath", "under", "upward", and "downward" generally refer to the vertical direction. "Horizontal" refers to a general direction along the main substrate surface (i.e., within 10 degrees), and can be relative to the direction in which the substrate is processed during manufacturing, and vertical is a direction generally orthogonal to the horizontal. By "perfectly horizontal" is meant a direction along the main substrate surface (i.e., at no angle to the main substrate surface), and can be relative to the direction in which the substrate is processed during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally relative to directions perpendicular to each other and independent of the orientation of the substrate in three-dimensional space. Additionally, "vertically extending" and "extending vertically" refer to a direction that is at least 45° angularly separated from perfectly horizontal. Further, with respect to a field effect transistor, "vertically extending", "extending vertically", "horizontally extending", "extending horizontally", and the like are with reference to the orientation of the channel length of the transistor along which current flows during operation between the source / drain regions. For a bipolar junction transistor, "vertically extending", "extending vertically", "horizontally extending", "extending horizontally", and the like are with reference to the orientation of the base length along which current flows between the emitter and the collector during operation. In some embodiments, any component, feature, and / or region that extends vertically extends vertically or within 10° of vertical.

[0051] In addition, "directly above", "directly below", and "directly beneath" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components relative to each other. Further, the use of "above" without the prefix "directly" only requires that a portion of the stated region / material / component that is above another stated region / material / component is vertically outside the other stated region / material / component (i.e., independent of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, the use of "below" and "beneath" without the prefix "directly" only requires that a portion of the stated region / material / component that is below / beneath another stated region / material / component is vertically inside the other stated region / material / component (i.e., independent of whether there is any lateral overlap of the two stated regions / materials / components).

[0052] Any one of the materials, regions, and structures described herein may be homogeneous or heterogeneous and, in any case, may be continuous or discontinuous over any material over which any one of the materials, regions, and structures is overlaid. Where one or more example components are provided for any material, the material may include, consist essentially of, or consist of such one or more components. Additionally, unless otherwise stated, each material may be formed using any suitable existing or future-developed techniques, where atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation are examples.

[0053] Additionally, "thickness" itself (without a prefixed directional adjective) is defined as the average straight-line distance perpendicular to the closest surface of an adjacent material or adjacent region having a different composition through a given material or region. Additionally, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If the thickness is variable, then unless otherwise indicated, the thickness refers to the average thickness, and due to the variable thickness, this material or region will have some minimum thickness and some maximum thickness. As used herein, "different composition" requires only that those portions of two stated materials or regions that can be directly adjacent to each other are chemically and / or physically different, e.g., provided that such materials or regions are not homogeneous. If two stated materials or regions are not directly adjacent to each other, then "different composition" requires only that those portions of the two stated materials or regions that are closest to each other are chemically and / or physically different, provided that such materials or regions are not homogeneous. In this document, stated materials, regions, or structures are "directly adjacent" to each other when there is at least some physical touch contact between the materials, regions, or structures relative to each other. In contrast, "over", "on", "adjacent to", "along", and "against" without the prefix "directly" cover both "directly adjacent" and configurations where intervening materials, regions, or structures result in no physical touch contact between the stated materials, regions, or structures relative to each other.

[0054] In this document, regions-materials-components are "electrically coupled" to each other if, during normal operation, current can flow continuously from one region-material-component to another region-material-component, and such flow is achieved primarily by the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between the region-materials-components and be electrically coupled to the region-materials-components. In contrast, when region-materials-components are said to be "directly electrically coupled", there is no intermediate electronic component (e.g., no diode, transistor, resistor, transducer, switch, fuse, etc.) between the directly electrically coupled region-materials-components.

[0055] The composition of any one of the conductive / conductor / conductive materials in this document can be a metallic material and / or a conductively doped semi-conductive / semiconductor / semi-conductive material. "Metallic material" is any one or combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0056] In this document, "selectivity" with respect to etching (etch / etching), removing (removing / removal), deposition, forming (forming / formation) is an action in which a stated material acts on another stated material at a ratio of at least 2:1 by volume. Additionally, selectively depositing, selectively growing, or selectively forming refers to depositing, growing, or forming a material at a ratio of at least 2:1 by volume with respect to another stated material for at least the first 75 angstroms of deposition, growth, or formation.

[0057] Unless otherwise indicated, the use of "or" in this document encompasses either and both.

[0058] Conclusion

[0059] In some embodiments, a method for forming an integrated circuit system includes forming a plurality of conductive vias including a conductive material. The conductive vias are spaced apart from each other by an intermediate material. A discontinuous material is formed on top of the conductive material of the vias and on top of the intermediate material between the vias. A metallic material is formed on top of the discontinuous material, directly against the discontinuous material, and between the discontinuous materials and on top of the conductive material of the vias and directly against the conductive material of the vias. The metallic material has a composition different from that of the discontinuous material and is over the intermediate material between the vias. The metallic material having the discontinuous material thereunder is formed to include conductive lines on top of the intermediate material between the vias and directly against individual ones of the vias.

[0060] In some embodiments, a method for forming a DRAM circuit system includes forming transistors, each of which individually includes: a pair of source / drain regions; a channel region between the pair of source / drain regions; a conductive gate operably proximate to the channel region; and a gate insulator between the conductive gate and the channel region. Form conductive paths that are individually directly electrically coupled to one of the pair of source / drain regions. The conductive paths are spaced apart from each other by an intermediate material and include a conductive material. Form a discontinuous material on top of the conductive material of the conductive paths and on top of the intermediate material between the conductive paths. Form a metal material on top of the discontinuous material, directly against the discontinuous material, and between the discontinuous materials and on top of the conductive material of the paths and directly against the conductive material of the conductive paths. The metal material has a composition different from that of the discontinuous material and is over the intermediate material between the conductive paths. Form the metal material having the discontinuous material thereunder to include a digital line on top of the intermediate material between the conductive paths and directly against the individual ones of the conductive paths of a plurality of the transistors. Form conductor paths that are individually directly electrically coupled to the other source / drain region of the pair. Form storage elements that are directly electrically coupled to the individual ones of the conductor paths.

[0061] In some embodiments, an integrated circuit system includes a plurality of conductive paths that include a conductive material. The conductive paths are spaced apart from each other by an intermediate material. A conductive line is on top of the intermediate material between the paths and is directly electrically coupled to the individual ones of the paths. The conductive line includes a metal material that is directly against the conductive material of the paths. A discontinuous material is vertically between the conductive line and the conductive material of the paths and is vertically between the conductive line and the intermediate material between the paths. The discontinuous material has a composition different from that of the metal material.

[0062] In some embodiments, a DRAM circuit system includes transistors, each of the transistors individually including: a pair of source / drain regions; a channel region between the pair of source / drain regions; a conductive gate operably proximate to the channel region; and a gate insulator between the conductive gate and the channel region. A first conductive path is individually directly electrically coupled to one of the pair of source / drain regions. A storage element is directly electrically coupled to an individual one of the first conductive paths, and a second conductive path is individually directly electrically coupled to the other of the pair of source / drain regions. The second conductive paths are spaced apart from each other by an intervening material and include conductive material. A digital line is on top of the intervening material between the second paths and directly electrically coupled to an individual one of the second paths of a plurality of the transistors. The digital line includes a metal material directly abutting the conductive material of the second path. A discontinuous material is vertically between the digital line and the conductive material of the second path and vertically between the digital line and the intervening material between the second paths. The discontinuous material has a composition different from that of the metal material.

Claims

1. An integrated circuit system, comprising: A plurality of conductive vias, comprising a conductive material, the conductive vias being spaced apart from each other by an intermediate material; A conductive wire on top of the intermediate material between the vias and directly electrically coupled to an individual one of the vias, the conductive wire comprising elemental form Ru directly abutting the conductive material of the via; and A discontinuous material comprising a separated portion vertically between the conductive wire and the conductive material of the via and a separated portion vertically between the conductive wire and the intermediate material between the vias, the discontinuous material having a composition different from that of elemental form Ru.

2. The integrated circuit system according to claim 1, wherein the conductive material of the via comprises a lower conductive doped semiconductive material under an upper conductor material, the upper conductor material having a composition different from that of the lower conductive doped semiconductive material.

3. The integrated circuit system according to claim 2, wherein the conductive doped semiconductive material comprises conductive doped polysilicon.

4. The integrated circuit system according to claim 1, wherein the conductive material comprises a metal nitride.

5. The integrated circuit system according to claim 1, wherein the conductive material comprises a metal carbonitride.

6. The integrated circuit system according to claim 1, wherein the conductive material comprises elemental form metal.

7. The integrated circuit system according to claim 1, wherein the discontinuous material comprises void spaces therethrough, the void spaces having a total horizontal area greater than the total horizontal area of the separated portions of the discontinuous material.

8. The integrated circuit system according to claim 1, wherein the discontinuous material is insulating.

9. The integrated circuit system according to claim 1, wherein the discontinuous material is conductive.

10. The integrated circuit system according to claim 9, wherein the discontinuous material has the same composition as the conductive material.

11. The integrated circuit system according to claim 9, wherein the discontinuous material comprises elemental form metal.

12. The integrated circuit system according to claim 1, wherein the discontinuous material has a composition different from that of the conductive material.

13. The integrated circuit system according to claim 1, wherein the discontinuous material comprises elemental form silicon.

14. The integrated circuit system according to claim 1, comprising a plurality of the conductive wires laterally spaced apart from each other, the discontinuous material not being laterally between the plurality of conductive wires.

15. The integrated circuit system according to claim 1, comprising a plurality of the conductive wires laterally spaced apart from each other, the discontinuous material being laterally between the plurality of conductive wires.

16. The integrated circuit system according to claim 1, comprising a NAND, the conductive wire being a digital wire.

17. An integrated circuit system, comprising: A plurality of conductive vias, comprising a conductive material, the conductive vias being spaced apart from each other by an intermediate material; A conductive wire on top of the intermediate material that is between the channels and is directly electrically coupled to an individual one of the channels, the conductive wire including elemental form Mo of the conductive material that abuts directly against the channel; and A discontinuous material including a separated portion vertically between the conductive wire and the conductive material of the channel and a separated portion vertically between the conductive wire and the intermediate material between the channels, the discontinuous material having a composition different from that of the elemental form Mo.

18. A memory circuit system comprising: Digital lines that conductively interconnect memory cells of the memory circuit system; Conductive channels that individually and directly electrically couple an individual one of the memory cells to an individual one of the digital lines, the conductive channels including a conductive material and being spaced apart from each other by an intermediate material, the individual digital lines being on top of the intermediate material, the digital lines including elemental form Ru of the conductive material that abuts directly against the conductive material of the conductive channels; And A discontinuous material including a separated portion vertically between the individual digital lines and the conductive material of the conductive channels and a separated portion vertically between the individual digital lines and the intermediate material, the discontinuous material having a composition different from that of the elemental form Ru.

19. The memory circuit system according to claim 18, wherein the conductive material of the channel includes a lower conductive doped semiconductive material under an upper conductor material, the upper conductor material having a composition different from that of the lower conductive doped semiconductive material.

20. The memory circuit system according to claim 19, wherein the conductive doped semiconductive material includes conductively doped polysilicon.

21. The memory circuit system according to claim 18, wherein the discontinuous material includes void spaces therethrough, the void spaces having a total horizontal area greater than the total horizontal area of the separated portions of the discontinuous material.

22. A memory circuit system comprising: Digital lines that conductively interconnect memory cells of the memory circuit system; Conductive channels that individually and directly electrically couple an individual one of the memory cells to an individual one of the digital lines, the conductive channels including a conductive material and being spaced apart from each other by an intermediate material, the individual digital lines being on top of the intermediate material, the digital lines including elemental form Mo of the conductive material that abuts directly against the conductive material of the conductive channels; And A discontinuous material including a separated portion vertically between the individual digital lines and the conductive material of the conductive channels and a separated portion vertically between the individual digital lines and the intermediate material, the discontinuous material having a composition different from that of the elemental form Mo.

23. The memory circuit system according to claim 22, wherein the conductive material of the channel includes a lower conductive doped semiconductive material under an upper conductor material, the upper conductor material having a composition different from that of the lower conductive doped semiconductive material.

24. The memory circuit system according to claim 23, wherein the conductively doped semiconductive material comprises conductively doped polysilicon.

25. The memory circuit system according to claim 22, wherein the discontinuous material comprises interstitial spaces therethrough, the interstitial spaces having a total horizontal area greater than the total horizontal area of the separated portions of the discontinuous material.

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