Split-gate flash memory and forming method thereof

Abstract

The invention discloses a split-gate flash memory and a forming method thereof. The memory comprises a substrate; the first floating gate structure and the second floating gate structure are located in the substrate; the first erasing gate structure and the second erasing gate structure are located on the substrate; the first side wall is located on the side wall of the first erasure gate structure, and the second side wall is located on the side wall of the second erasure gate structure. The coating thicknesses of the first side wall and the second side wall on the first erasure gate structure and the second erasure gate structure are uniform, so that the oxidation open circuit of the erasure gate structures in the heat treatment process can be reduced. The first floating gate structure can block diffusion between the first drain electrode doping layer and the source electrode doping layer, and the second floating gate structure can block diffusion between the second drain electrode doping layer and the source electrode doping layer. Therefore, the short circuit between the first drain electrode doping layer and the source electrode doping layer and the short circuit between the second drain electrode doping layer and the source electrode doping layer due to ion diffusion can be effectively prevented.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a split-gate flash memory and a method for forming the same. Background Art

[0002] A flash memory is a non-volatile memory. Its operating principle is to control the switching of the gate channel by changing the critical voltage of the transistor or the memory cell to achieve the purpose of storing data, so that the data stored in the memory will not be lost due to a power interruption. Nowadays, flash memories have occupied most of the market share of non-volatile semiconductor memories and have become the fastest-growing non-volatile semiconductor memories. Among them, flash memories are mainly divided into split-gate structures and stacked-gate structures. Compared with stacked-gate flash memories, split-gate flash memories have higher programming efficiency, and the structure of the erase gate can avoid "over-erasure". Therefore, split-gate flash memories are currently widely used in mobile and communication devices such as mobile phones, notebooks, PDAs, and USB flash drives.

[0003] However, there are still many problems in the split-gate flash memories in the prior art. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a split-gate flash memory and a method for forming the same to improve the performance and reliability of the memory.

[0005] To solve the above problems, the present invention provides a split-gate flash memory, comprising: a substrate having mutually discrete first floating-gate trenches and second floating-gate trenches therein; a first floating-gate structure located in the first floating-gate trench and a second floating-gate structure located in the second floating-gate trench; a first erase gate structure located on the substrate, the first erase gate structure being located on the first floating-gate structure, and a second erase gate structure located on the substrate, the second erase gate structure being located on the second floating-gate structure; a first sidewall located on the sidewall of the first erase gate structure and a second sidewall located on the sidewall of the second erase gate structure; a source doping layer located in the substrate, the source doping layer being located between the adjacent first floating-gate structure and the second floating-gate structure; a source line layer located on the substrate, the source line layer being located on the source doping layer and between the adjacent first erase gate structure and the second erase gate structure; a first word line structure located on the substrate, the first erase gate structure and the first sidewall being located between the first word line structure and the source line layer, and a second word line structure located on the substrate, the second erase gate structure and the second sidewall being located between the second word line structure and the source line layer; a third sidewall located on the sidewall of the first word line structure and a fourth sidewall located on the sidewall of the second word line structure; a first drain doping layer and a second drain doping layer located in the substrate, the first floating-gate structure being located between the first drain doping layer and the source doping layer, and the second floating-gate structure being located between the second drain doping layer and the source doping layer.

[0006] Optionally, the first floating-gate structure includes: a first middle portion and first edge portions located on both sides of the first middle portion; the projection of the first erase gate structure onto the substrate coincides with the projection of the first middle portion onto the substrate; the second floating-gate structure includes: a second middle portion and second edge portions located on both sides of the second middle portion; the projection of the second erase gate structure onto the substrate coincides with the projection of the second middle portion onto the substrate.

[0007] Optionally, the projection of the first sidewall onto the substrate and the projection of the first edge portion onto the substrate have an overlapping area; the projection of the second sidewall onto the substrate and the projection of the second edge portion onto the substrate have an overlapping area.

[0008] Optionally, the first floating-gate structure includes: a first coupling oxide layer located on the surface of the first floating-gate trench and a first floating-gate layer located on the first coupling oxide layer, the first floating-gate layer filling the first floating-gate trench; the second floating-gate structure includes: a second coupling oxide layer located on the surface of the second floating-gate trench and a second floating-gate layer located on the second coupling oxide layer, the second floating-gate layer filling the second floating-gate trench.

[0009] Optionally, the first erase gate structure includes: a first tunneling oxide layer and a first erase gate layer located on the first tunneling oxide layer; the second erase gate structure includes: a second tunneling oxide layer and a second erase gate layer located on the second tunneling oxide layer.

[0010] Optionally, the first tunneling oxide layer is made of silicon oxide; the first tunneling oxide layer is made of silicon oxide.

[0011] Optionally, the first word line structure includes: a first word line oxide layer located on the sidewall of the first spacer and the surface of the substrate, and a first word line layer located on the first word line oxide layer; the second word line structure includes: a second word line oxide layer located on the sidewall of the second spacer and the surface of the substrate, and a second word line layer located on the second word line oxide layer.

[0012] Optionally, it further includes: a first capping layer located on the first erase gate structure and a second capping layer located on the second erase gate structure.

[0013] Optionally, the material of the first capping layer is silicon nitride; the material of the second capping layer is silicon nitride.

[0014] Correspondingly, the technical solution of the present invention further provides a method for forming a split-gate flash memory, including: providing a substrate; forming mutually discrete first floating gate trenches and second floating gate trenches in the substrate; forming a first floating gate structure in the first floating gate trench and a second floating gate structure in the second floating gate trench; forming a first erase gate structure and a second erase gate structure on the substrate, the first erase gate structure being located on the first floating gate structure, and the second erase gate structure being located on the second floating gate structure; forming a first sidewall on the sidewall of the first erase gate structure and a second sidewall on the sidewall of the second erase gate structure; forming a source doping layer in the substrate, the source doping layer being located between the adjacent first floating gate structure and the second floating gate structure; forming a source line layer on the substrate, the source line layer being located on the source doping layer and between the adjacent first erase gate structure and the second erase gate structure; forming a first word line structure and a second word line structure on the substrate, the first erase gate structure and the first sidewall being located between the first word line structure and the source line layer, and the second erase gate structure and the second sidewall being located between the second word line structure and the source line layer; forming a third sidewall on the sidewall of the first word line structure and a fourth sidewall on the sidewall of the second word line structure; forming a first drain doping layer and a second drain doping layer in the substrate, the first floating gate structure being located between the first drain doping layer and the source doping layer, and the second floating gate structure being located between the second drain doping layer and the source doping layer.

[0015] Optionally, the first floating gate structure includes: a first middle portion and first edge portions located on both sides of the first middle portion; the projection of the first erase gate structure onto the substrate coincides with the projection of the first middle portion onto the substrate; the second floating gate structure includes: a second middle portion and second edge portions located on both sides of the second middle portion; the projection of the second erase gate structure onto the substrate coincides with the projection of the second middle portion onto the substrate.

[0016] Optionally, the projection of the first sidewall onto the substrate has an overlapping area with the projection of the first edge portion onto the substrate; the projection of the second sidewall onto the substrate has an overlapping area with the projection of the second edge portion onto the substrate.

[0017] Optionally, the first floating gate structure includes: a first coupling oxide layer located on the surface of the first floating gate trench and a first floating gate layer located on the first coupling oxide layer, the first floating gate layer filling the first floating gate trench; the second floating gate structure includes: a second coupling oxide layer located on the surface of the second floating gate trench and a second floating gate layer located on the second coupling oxide layer, the second floating gate layer filling the second floating gate trench.

[0018] Optionally, the method for forming the first floating gate structure and the second floating gate structure includes: forming a coupling oxide material layer on the surface of the first floating gate trench, the surface of the second floating gate structure, and the substrate surface; forming a floating gate material layer on the coupling oxide material layer, and the floating gate material layer fills the first floating gate trench and the second floating gate trench; performing a back-etching process on the floating gate material layer until the coupling oxide material layer is exposed, to form the first floating gate structure and the second floating gate structure.

[0019] Optionally, before forming the first sidewall and the second sidewall, it further includes: forming a first covering layer on the first erasing gate structure and a second covering layer on the second erasing gate structure.

[0020] Optionally, the first erasing gate structure includes: a first tunneling oxide layer and a first erasing gate layer located on the first tunneling oxide layer; the second erasing gate structure includes: a second tunneling oxide layer and a second erasing gate layer located on the second tunneling oxide layer.

[0021] Optionally, the method for forming the first erasing gate structure, the second erasing gate structure, the first covering layer and the second covering layer includes: forming a tunneling oxide material layer on the substrate; forming an erasing gate material layer on the tunneling oxide material layer; forming a covering material layer on the erasing gate material layer; performing a patterning etching process on the erasing gate material layer and the covering material layer to form the first erasing gate structure, the second erasing gate structure, the first covering layer and the second covering layer.

[0022] Optionally, the method for forming the first sidewall and the second sidewall includes: forming a first sidewall material layer on the substrate; performing a patterning etching process on the first sidewall material layer to form the first sidewall and the second sidewall.

[0023] Optionally, the method for forming the source doping layer includes: performing a source ion implantation process on the substrate to form the source doping layer.

[0024] Optionally, the method for forming the source line layer includes: forming a source line material layer on the substrate, and the source line material layer covers the first erasing gate structure, the second erasing gate structure, the first covering layer, the second covering layer, the first sidewall and the second sidewall; performing a planarization process on the source line material layer until the surfaces of the first covering layer and the second covering layer are exposed, to form an initial source line layer; performing a patterning etching process on the initial source line layer to form the source line layer.

[0025] Optionally, the first word line structure includes: a first word line oxide layer located on the sidewall of the first sidewall and the substrate surface, and a first word line layer located on the first word line oxide layer; the second word line structure includes: a second word line oxide layer located on the sidewall of the second sidewall and the substrate surface, and a second word line layer located on the second word line oxide layer.

[0026] Optionally, the method for forming the first word line structure and the second word line structure includes: forming a word line oxide material layer on the sidewall of the first sidewall, the sidewall of the second sidewall, and the substrate surface; forming a word line material layer on the word line oxide material layer; performing a patterning etching process on the word line oxide material layer and the word line material layer to form the first word line structure and the second word line structure.

[0027] Optionally, the method for forming the third sidewall and the fourth sidewall includes: forming a second sidewall material layer on the substrate; performing a patterning etching process on the second sidewall material layer to form the third sidewall and the fourth sidewall.

[0028] Optionally, the method for forming the first drain doping layer and the second drain doping layer includes: performing a drain ion implantation process on the substrate to form the first drain doping layer and the second drain doping layer.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] In the split-gate flash memory of the technical solution of the present invention, the thickness of the first sidewalls on both sides of the first erase gate structure is uniform, which can provide a good coating effect for the first erase gate structure, and thus can effectively reduce the oxidation open circuit of the first erase gate structure during the heat treatment process of the subsequent process. Correspondingly, the thickness of the second sidewalls on both sides of the second erase gate structure is uniform, which can provide a good coating effect for the second erase gate structure, and thus can effectively reduce the oxidation open circuit of the second erase gate structure during the heat treatment process of the subsequent process. The first floating gate structure and the second floating gate structure are respectively located in the substrate, and the first floating gate structure is located between the first drain doping layer and the source doping layer, and the second floating gate structure is located between the second drain doping layer and the source doping layer. Therefore, the first floating gate structure can block the diffusion of the first drain doping layer and the source doping layer, and thus effectively prevent the short circuit between the first drain doping layer and the source doping layer. The second floating gate structure can block the diffusion of the second drain doping layer and the source doping layer, and thus effectively prevent the short circuit between the second drain doping layer and the source doping layer. Moreover, the channel areas and volumes of the first floating gate structure and the second floating gate structure are increased, which can improve the control ability of the first floating gate structure and the second floating gate structure over the channel, and can also improve the coupling ratio between the first floating gate structure and the source line layer, and between the second floating gate structure and the source line layer, thereby improving the programming efficiency of the device.

[0031] Further, the projection of the first sidewall onto the substrate overlaps with the projection of the first edge portion onto the substrate; the projection of the second sidewall onto the substrate overlaps with the projection of the second edge portion onto the substrate. The first sidewall is formed on the area already occupied by the first floating gate structure, so that the first sidewall does not additionally occupy more area regions. Correspondingly, the second sidewall is formed on the area already occupied by the second floating gate structure, so that the second sidewall does not additionally occupy more area regions, thereby reducing the overall area region occupied by the device unit and improving the integration degree of the chip.

[0032] Further, it further includes: a first covering layer located on the first erase gate structure and a second covering layer located on the second erase gate structure. The first covering layer can cover and protect the top surface of the first erase gate structure. Correspondingly, the second covering layer can cover and protect the top surface of the second erase gate structure. Moreover, the first covering layer and the second covering layer can also serve as a polishing stop layer for planarization during the formation of the source line layer, preventing the short circuit between the source line layer and the first erase gate structure and the second erase gate structure.

[0033] In the method for forming a split-gate flash memory according to the technical solution of the present invention, the thicknesses of the first sidewalls on both sides of the first erase gate structure are uniform, which can provide a good coating effect for the first erase gate structure, and thus can effectively reduce the oxidation open circuit of the first erase gate structure during the heat treatment process of subsequent processes. Correspondingly, the thicknesses of the second sidewalls on both sides of the second erase gate structure are uniform, which can provide a good coating effect for the second erase gate structure, and thus can effectively reduce the oxidation open circuit of the second erase gate structure during the heat treatment process of subsequent processes. The first floating gate structure and the second floating gate structure are respectively located in the substrate, and the first floating gate structure is located between the first drain doping layer and the source doping layer, and the second floating gate structure is located between the second drain doping layer and the source doping layer. Therefore, the first floating gate structure can block the diffusion of the first drain doping layer and the source doping layer, and thus effectively prevent the short circuit between the first drain doping layer and the source doping layer. The second floating gate structure can block the diffusion of the second drain doping layer and the source doping layer, and thus effectively prevent the short circuit between the second drain doping layer and the source doping layer. Moreover, the channel areas and volumes of the first floating gate structure and the second floating gate structure are increased, which can improve the control ability of the first floating gate structure and the second floating gate structure over the channel, and can also improve the coupling ratio between the first floating gate structure and the source line layer, as well as between the second floating gate structure and the source line layer, thereby improving the programming efficiency of the device.

[0034] Further, the projection of the first sidewall onto the substrate overlaps with the projection of the first edge portion onto the substrate; the projection of the second sidewall onto the substrate overlaps with the projection of the second edge portion onto the substrate. The first sidewall is formed on the area already occupied by the first floating gate structure, so that the first sidewall does not additionally occupy more area regions. Correspondingly, the second sidewall is formed on the area already occupied by the second floating gate structure, so that the second sidewall does not additionally occupy more area regions, thereby reducing the overall area region occupied by the device unit and improving the integration degree of the chip.

[0035] Further, before forming the first sidewall and the second sidewall, it further includes: forming a first covering layer on the first erase gate structure and forming a second covering layer on the second erase gate structure. The first covering layer can cover and protect the top surface of the first erase gate structure, and correspondingly, the second covering layer can cover and protect the top surface of the second erase gate structure. Moreover, the first covering layer and the second covering layer can also serve as a polishing stop layer for planarization during the formation of the source line layer, preventing the short circuit between the source line layer and the first erase gate structure and the second erase gate structure. Description of the Drawings

[0036] Figure 1 is a schematic structural diagram of a split-gate flash memory;

[0037] Figures 2 to 15 is a schematic structural diagram of each step of the method for forming the split-gate flash memory according to the embodiment of the present invention. Detailed Embodiments

[0038] As described in the background art, there are still many problems in the split-gate flash memories in the prior art. The following will be specifically described with reference to the drawings.

[0039] Figure 1 is a schematic structural diagram of a split-gate flash memory.

[0040] Please refer to Figure 1 , a split-gate flash memory, comprising: a substrate 100; a first floating gate structure 101 and a second floating gate structure 102 located on the substrate 100; a first erase gate structure 103 and a second erase gate structure 104 located on the substrate 100, the first erase gate structure 103 being located on the first floating gate structure 101, and the second erase gate structure 104 being located on the second floating gate structure 102; a first sidewall structure 105 located on the substrate 100, the first sidewall structure 105 covering the first floating gate structure 101, the second floating gate structure 102, the first erase gate structure 103, and the second erase gate structure 104; a source doping layer 106 located in the substrate 100, the source doping layer 106 being located between the first floating gate structure 101 and the second floating gate structure 102; a source line layer 107 located on the substrate 100, the source line layer 107 being located on the source doping layer 106; a first word line structure 108 and a second word line structure 109 located on the substrate 100; a second sidewall structure 110 located on the substrate 100, the second sidewall structure 110 being respectively located on the sidewalls of the first word line structure 108 and the second word line structure 109; a first drain doping layer 111 and a second drain doping layer 112 located in the substrate 100, the source doping layer 106 being located between the first drain doping layer 111 and the second drain doping layer 112.

[0041] In this embodiment, the split-gate flash memory uses top erasure of the floating gate. To improve the erasure efficiency and reduce the erasure voltage, it is necessary to minimize the coupling ratio between the first erasure gate structure 103 and the first floating gate structure 101, and between the second erasure gate structure 104 and the second floating gate structure 102. Without disconnecting the first erasure gate structure 103 and the second erasure gate structure 104, the lengths of the first erasure gate structure 103 and the second erasure gate structure 104 should be minimized as much as possible.

[0042] However, since the lengths of the first erasure gate structure 103 and the second erasure gate structure 104 are shortened, and the thickness of the first sidewall structure 105 covering the side of the first erasure gate structure 103 close to the first word line structure 108 and covering the side of the second erasure gate structure 104 close to the second word line structure 109 is relatively thin, the coating effect on the first erasure gate structure 103 and the second erasure gate structure 104 is not good. During subsequent multiple heat treatment processes, oxidation of the first erasure gate structure 103 and the second erasure gate structure 104 is likely to occur, which may further cause open circuits in the first erasure gate structure 103 and the second erasure gate structure 104. In addition, there is a risk of diffusion short-circuit between the source doping layer 106 and the first drain doping layer 111, and between the source doping layer 106 and the second drain doping layer 112 located in the substrate 100.

[0043] On this basis, the present invention provides a split-gate flash memory and a method for forming the same. The thickness of the first sidewalls on both sides of the first erase gate structure is uniform, which can provide a good coating effect for the first erase gate structure, and thus can effectively reduce the oxidation open circuit of the first erase gate structure during the heat treatment process of subsequent processes. Correspondingly, the thickness of the second sidewalls on both sides of the second erase gate structure is uniform, which can provide a good coating effect for the second erase gate structure, and thus can effectively reduce the oxidation open circuit of the second erase gate structure during the heat treatment process of subsequent processes. The first floating gate structure and the second floating gate structure are respectively located in the substrate, and the first floating gate structure is located between the first drain doping layer and the source doping layer, and the second floating gate structure is located between the second drain doping layer and the source doping layer. Therefore, the first floating gate structure can block the diffusion of the first drain doping layer and the source doping layer, and thus effectively prevent the short circuit between the first drain doping layer and the source doping layer. The second floating gate structure can block the diffusion of the second drain doping layer and the source doping layer, and thus effectively prevent the short circuit between the second drain doping layer and the source doping layer. Moreover, the channel areas and volumes of the first floating gate structure and the second floating gate structure increase, which can improve the control ability of the first floating gate structure and the second floating gate structure over the channel, and can also improve the coupling ratio between the first floating gate structure and the source line layer, and between the second floating gate structure and the source line layer, thereby improving the programming efficiency of the device.

[0044] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following describes the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0045] Figures 2 to 15 It is a schematic structural diagram of each step of the method for forming a split-gate flash memory according to an embodiment of the present invention.

[0046] Please refer to Figure 2 , and provide a substrate 200.

[0047] In this embodiment, the material of the substrate 200 is silicon.

[0048] In other embodiments, the material may also include silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI), etc. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0049] Please refer to Figure 3, first floating gate trenches 201 and second floating gate trenches 202 that are separated from each other are formed within the substrate 200.

[0050] In this embodiment, the method for forming the first floating gate trenches 201 and the second floating gate trenches 202 includes: forming a patterned layer (not shown) on the substrate 200, where the patterned layer exposes a part of the top surface of the substrate 200; etching the substrate 200 using the patterned layer as a mask to form the first floating gate trenches 201 and the second floating gate trenches 202 within the substrate 200.

[0051] In this embodiment, after forming the first floating gate trenches 201 and the second floating gate trenches 202, a first floating gate structure is formed within the first floating gate trenches 201, and a second floating gate structure is formed within the second floating gate trenches 202. For the specific formation process, please refer to Figures 4 to 6 .

[0052] Please refer to Figure 4 , a coupled oxidation material layer 203 is formed on the surface of the first floating gate trenches 201, the surface of the second floating gate structure, and the surface of the substrate 200.

[0053] In this embodiment, the coupled oxidation material layer 203 is formed using a chemical vapor deposition process.

[0054] In other embodiments, the coupled oxidation material layer may also be formed using a thermal oxidation process.

[0055] In this embodiment, the material of the coupled oxidation material layer 203 is silicon oxide.

[0056] Please refer to Figure 5 , a floating gate material layer 204 is formed on the coupled oxidation material layer 203, and the floating gate material layer 204 fills the first floating gate trenches 201 and the second floating gate trenches 202.

[0057] In this embodiment, the floating gate material layer 204 is formed using a chemical vapor deposition process.

[0058] In this embodiment, the material of the floating gate material layer 204 is polysilicon.

[0059] Please refer to Figure 6 , the floating gate material layer 204 is subjected to a re-etching process until the coupled oxidation material layer 203 is exposed, to form the first floating gate structure 205 and the second floating gate structure 206.

[0060] In this embodiment, the re-etching process uses a dry etching process.

[0061] In this embodiment, the first floating gate structure 205 includes: a first coupling oxide layer (not labeled) on the surface of the first floating gate trench 201, and a first floating gate layer (not labeled) on the first coupling oxide layer. The first floating gate layer fills the first floating gate trench 201; the second floating gate structure 206 includes: a second coupling oxide layer (not labeled) on the surface of the second floating gate trench 202, and a second floating gate layer (not labeled) on the second coupling oxide layer. The second floating gate layer fills the second floating gate trench 202.

[0062] It should be noted that, in this embodiment, the first coupling oxide layer is the coupling oxide material layer 203 on the surface of the first floating gate trench 201, and the first floating gate layer is the floating gate material layer 204 filled in the first floating gate trench 201 after the re-etching process; the second coupling oxide layer is the coupling oxide material layer 203 on the surface of the second floating gate trench 202, and the second floating gate layer is the floating gate material layer 204 filled in the second floating gate trench 202 after the re-etching process.

[0063] In this embodiment, after forming the first floating gate structure 205 and the second floating gate structure 206, a first erase gate structure and a second erase gate structure are formed on the substrate 200. The first erase gate structure is located on the first floating gate structure 205, and the second erase gate structure is located on the second floating gate structure 206. For the specific formation process, please refer to Figures 7 to 8 .

[0064] Please refer to Figure 7 , a tunneling oxide material layer 207 is formed on the substrate 200; an erase gate material layer 208 is formed on the tunneling oxide material layer 207.

[0065] In this embodiment, it further includes: forming a covering material layer 209 on the erase gate material layer 208.

[0066] In this embodiment, the material of the tunneling oxide material layer 207 is silicon oxide.

[0067] In this embodiment, the material of the erase gate material layer 208 is polysilicon.

[0068] In this embodiment, the material of the covering material layer 209 is silicon nitride.

[0069] Please refer to Figure 8, the erasing gate material layer 208 and the covering material layer 209 are subjected to a patterning etching process to form the first erasing gate structure 210, the second erasing gate structure 211, the first covering layer 213, and the second covering layer 214.

[0070] In this embodiment, the method for patterning and etching the erasing gate material layer 208 and the covering material layer 209 includes: forming a patterning layer (not shown) on the covering material layer 209, and the patterning layer exposes a partial top surface of the covering material layer 209; using the patterning layer as a mask to etch the covering material layer 209 and the erasing gate material layer 208 in sequence until the surface of the tunneling oxide material layer 207 is exposed.

[0071] In this embodiment, the first erasing gate structure 210 includes: a first tunneling oxide layer (not labeled), and a first erasing gate layer (not labeled) located on the first tunneling oxide layer; the second erasing gate structure 211 includes: a second tunneling oxide layer (not labeled), and a second erasing gate layer (not labeled) located on the second tunneling oxide layer.

[0072] It should be noted that, in this embodiment, the first tunneling oxide layer is the tunneling oxide material layer 207 covered by the first erasing gate layer after the patterning etching process, and the second tunneling oxide layer is the tunneling oxide material layer 207 covered by the second erasing gate layer after the patterning etching process; the first erasing gate layer and the second erasing gate layer are the remaining erasing gate material layer 208 after the patterning etching process; the first covering layer 213 is based on the covering material layer 209 located on the first erasing gate layer after the patterning etching process, and the second covering layer 214 is based on the covering material layer 209 located on the second erasing gate layer after the patterning etching process.

[0073] In this embodiment, the formed first covering layer 213 can cover and protect the top surface of the first erasing gate structure 210, and the corresponding second covering layer 214 can cover and protect the top surface of the second erasing gate structure 211. Moreover, the first covering layer 213 and the second covering layer 214 can also serve as a polishing stop layer for planarization processing during the subsequent formation of the source line layer, preventing short circuits between the source line layer and the first erasing gate structure 210 and the second erasing gate structure 211.

[0074] In this embodiment, the first floating gate structure 205 includes a first intermediate portion 205a and first edge portions 205b located on both sides of the first intermediate portion 205a; the projection of the first erase gate structure 210 onto the substrate 200 coincides with the projection of the first intermediate portion 205a onto the substrate 200; the second floating gate structure 206 includes a second intermediate portion 206a and second edge portions 206b located on both sides of the second intermediate portion 206a; the projection of the second erase gate structure 211 onto the substrate 200 coincides with the projection of the second intermediate portion 206a onto the substrate 200.

[0075] Please refer to Figure 9 , a first spacer 215 is formed on the sidewalls of the first erase gate structure 210, and a second spacer 216 is formed on the sidewalls of the second erase gate structure 211.

[0076] In this embodiment, the method for forming the first spacer 215 and the second spacer 216 includes: forming a first spacer material layer (not shown) on the substrate 200; performing a patterning etching process on the first spacer material layer to form the first spacer 215 and the second spacer 216.

[0077] It should be noted that since the first spacer 215 on the two sidewalls of the first erase gate structure 210 and the second spacer 216 on the two sidewalls of the second erase gate structure 211 are synchronously formed after etching the deposited first spacer material layer, the thicknesses of the first spacer 215 on the two sidewalls of the first erase gate structure 210 and the second spacer 216 on the two sidewalls of the second erase gate structure 211 are uniform.

[0078] In this embodiment, after forming the first spacer 215 and the second spacer 216, the tunneling oxide material layer 207 and the coupling oxide material layer 203 located on the substrate 200 are etched using the first spacer 215 and the second spacer 216 as masks until the surface of the substrate 200 is exposed. The tunneling oxide material layer 207 and the coupling oxide material layer 203 remaining on the substrate 200 are used as an etch stop layer during dry etching of the first spacer material layer, and the tunneling oxide material layer 207 and the coupling oxide material layer 203 on the substrate 200 are removed by wet etching after forming the first spacer 215 and the second spacer 216.

[0079] In this embodiment, the material of the first spacer material layer is one or both of silicon oxide and silicon nitride.

[0080] In this embodiment, the projection of the first sidewall 215 onto the substrate 200 and the projection of the first edge portion 205b onto the substrate 200 have an overlapping area; the projection of the second sidewall 216 onto the substrate 200 and the projection of the second edge portion 206b onto the substrate 200 have an overlapping area. The first sidewall 215 is formed on the area already occupied by the first floating gate structure 205, such that the first sidewall 215 does not additionally occupy more area. Correspondingly, the second sidewall 216 is formed on the area already occupied by the second floating gate structure 206, such that the second sidewall 216 does not additionally occupy more area, thereby reducing the area occupied by the overall device unit and improving the integration of the chip.

[0081] Please refer to Figure 10 , a source doping layer 217 is formed in the substrate 200, and the source doping layer 217 is located between the adjacent first floating gate structure 205 and the second floating gate structure 206.

[0082] In this embodiment, the method for forming the source doping layer 217 includes: performing source ion implantation on the substrate 200 to form the source doping layer 217.

[0083] In this embodiment, after forming the source doping layer 217, a source line layer is formed on the substrate 200, and the source line layer is located on the source doping layer 217 and between the adjacent first erasing gate structure 210 and the second erasing gate structure 211. For the specific forming process, please refer to Figures 11 to 12 .

[0084] Please refer to Figure 11 , a source line material layer (not shown) is formed on the substrate 200, and the source line material layer covers the first erasing gate structure 210, the second erasing gate structure 211, the first covering layer 213, the second covering layer 214, the first sidewall 215, and the second sidewall 216; the source line material layer is planarized until the surfaces of the first covering layer 213 and the second covering layer 214 are exposed, thereby forming an initial source line layer 218.

[0085] In this embodiment, the source line material layer is formed by chemical vapor deposition.

[0086] In this embodiment, the material of the source line material layer is polysilicon.

[0087] In this embodiment, the planarization process uses chemical mechanical polishing.

[0088] Please refer to Figure 12, the initial source line layer 218 is subjected to a patterning etching process to form the source line layer 219.

[0089] In this embodiment, the method for patterning and etching the initial source line layer 218 includes: forming a patterning layer (not shown) on the initial source line layer 218, the patterning layer exposing a part of the top surface of the initial source line layer 218; etching the initial source line layer 218 using the patterning layer as a mask to form the source line layer 219.

[0090] Please refer to Figure 13 , after forming the source line layer 219, a first word line structure 220 and a second word line structure 221 are formed on the substrate 200, and the first erase gate structure 210 and the first sidewall 215 are located between the first word line structure 220 and the source line layer 219, and the second erase gate structure 211 and the second sidewall 216 are located between the second word line structure 221 and the source line layer 219.

[0091] In this embodiment, the first word line structure 220 includes: a first word line oxide layer (not labeled) located on the sidewall of the first sidewall 215 and the surface of the substrate 200, and a first word line layer (not labeled) located on the first word line oxide layer; the second word line structure 221 includes: a second word line oxide layer (not labeled) located on the sidewall of the second sidewall 216 and the surface of the substrate 200, and a second word line layer (not labeled) located on the second word line oxide layer.

[0092] In this embodiment, the method for forming the first word line structure 220 and the second word line structure 221 includes: forming a word line oxide material layer (not shown) on the sidewall of the first sidewall 215, the sidewall of the second sidewall 216, and the surface of the substrate 200; forming a word line material layer (not shown) on the word line oxide material layer; and performing a patterning etching process on the word line oxide material layer and the word line material layer to form the first word line structure 220 and the second word line structure 221.

[0093] It should be noted that, in this embodiment, the first word line oxide layer and the second word line oxide layer are the remaining word line oxide material layer after the patterning etching process; the first word line layer is the word line material layer located on the first word line oxide layer after the patterning etching process, and the second word line layer is the word line material layer located on the second word line oxide layer after the patterning etching process.

[0094] In this embodiment, the material of the word line oxide material layer is silicon oxide.

[0095] In this embodiment, the material of the word line material layer is polysilicon.

[0096] Please refer to Figure 14 , after forming the first word line structure 220 and the second word line structure 221, a third sidewall 222 is formed on the sidewall of the first word line structure 220, and a fourth sidewall 223 is formed on the sidewall of the second word line structure 221.

[0097] In this embodiment, the method for forming the third sidewall 222 and the fourth sidewall 223 includes: forming a second sidewall material layer on the substrate 200; performing a patterning etching process on the second sidewall material layer to form the third sidewall 222 and the fourth sidewall 223.

[0098] In this embodiment, the material of the second sidewall material layer is one or both of silicon oxide and silicon nitride.

[0099] In this embodiment, before forming the second sidewall material layer, an etching stop layer (not shown) for stopping dry etching of the second sidewall material layer needs to be formed. After dry etching the second sidewall material layer, the etching stop layer not covered by the third sidewall 222 and the fourth sidewall 223 is removed by wet etching.

[0100] Please refer to Figure 15 , after forming the third sidewall 222 and the fourth sidewall 223, a first drain doping layer 224 and a second drain doping layer 212 are formed in the substrate 200. The first floating gate structure 205 is located between the first drain doping layer 224 and the source doping layer 217, and the second floating gate structure 206 is located between the second drain doping layer 212 and the source doping layer 217.

[0101] The thickness of the first sidewalls 215 on both sides of the first erasing gate structure 210 is uniform, which can provide a good coating effect for the first erasing gate structure 210, and thus can effectively reduce the oxidation open circuit of the first erasing gate structure 210 during the heat treatment process of subsequent processes. Correspondingly, the thickness of the second sidewalls 216 on both sides of the second erasing gate structure 211 is uniform, which can provide a good coating effect for the second erasing gate structure 211, and thus can effectively reduce the oxidation open circuit of the second erasing gate structure 211 during the heat treatment process of subsequent processes. The first floating gate structure 205 and the second floating gate structure 206 are respectively located in the substrate 200, and the first floating gate structure 205 is located between the first drain doping layer 224 and the source doping layer 217, and the second floating gate structure 206 is located between the second drain doping layer 212 and the source doping layer 217. Therefore, the first floating gate structure 205 can block the diffusion of the first drain doping layer 224 and the source doping layer 217, and thus effectively prevent the short circuit between the first drain doping layer 224 and the source doping layer 217. The second floating gate structure 206 can block the diffusion of the second drain doping layer 212 and the source doping layer 217, and thus effectively prevent the short circuit between the second drain doping layer 212 and the source doping layer 217. Moreover, the channel area and volume of the first floating gate structure 205 and the second floating gate structure 206 are increased, which can improve the control ability of the first floating gate structure 205 and the second floating gate structure 206 on the channel, and can also improve the coupling rate between the first floating gate structure 205 and the source line layer 217, and between the second floating gate structure 206 and the source line layer 217, thereby improving the programming efficiency of the device.

[0102] In this embodiment, the forming method of the first drain doping layer 224 and the second drain doping layer 212 includes: performing a drain ion implantation process on the substrate 200 to form the first drain doping layer 224 and the second drain doping layer 212.

[0103] Correspondingly, in an embodiment of the present invention, a split-gate flash memory is further provided. Please continue to refer to Figure 15, comprising: 200, within the substrate 200 there are mutually discrete first floating gate trenches 201 and second floating gate trenches 202; a first floating gate structure 205 located within the first floating gate trench 201, and a second floating gate structure 206 located within the second floating gate trench 202; a first erase gate structure 210 located on the substrate 200, the first erase gate structure 210 being located on the first floating gate structure 205, and a second erase gate structure 211 located on the substrate 200, the second erase gate structure 211 being located on the second floating gate structure 206; a first sidewall 215 located on the sidewall of the first erase gate structure 210, and a second sidewall 216 located on the sidewall of the second erase gate structure 211; a source doping layer 217 located within the substrate 200, the source doping layer 217 being located between the adjacent first floating gate structure 205 and the second floating gate structure 206; a source line layer 219 located on the substrate 200, the source line layer 219 being located on the source doping layer 217 and between the adjacent first erase gate structure 210 and the second erase gate structure 211; a first word line structure 220 located on the substrate 200, the first erase gate structure 210 and the first sidewall 215 being located between the first word line structure 220 and the source line layer 219, and a second word line structure 221 located on the substrate 200, the second erase gate structure 211 and the second sidewall 216 being located between the second word line structure 221 and the source line layer 219; a third sidewall 222 located on the sidewall of the first word line structure 220, and a fourth sidewall 223 located on the sidewall of the second word line structure 221; a first drain doping layer 224 and a second drain doping layer 212 located within the substrate 200, the first floating gate structure 205 being located between the first drain doping layer 224 and the source doping layer 217, and the second floating gate structure 206 being located between the second drain doping layer 212 and the source doping layer 217.

[0104] The thickness of the first sidewalls 215 on both sides of the first erasing gate structure 210 is uniform, which can provide a good coating effect for the first erasing gate structure 210, and thus can effectively reduce the oxidation open circuit of the first erasing gate structure 210 during the heat treatment process of subsequent processes. Correspondingly, the thickness of the second sidewalls 216 on both sides of the second erasing gate structure 211 is uniform, which can provide a good coating effect for the second erasing gate structure 211, and thus can effectively reduce the oxidation open circuit of the second erasing gate structure 211 during the heat treatment process of subsequent processes. The first floating gate structure 205 and the second floating gate structure 206 are respectively located in the substrate 200, and the first floating gate structure 205 is located between the first drain doping layer 224 and the source doping layer 217, and the second floating gate structure 206 is located between the second drain doping layer 212 and the source doping layer 217. Therefore, the first floating gate structure 205 can block the diffusion of the first drain doping layer 224 and the source doping layer 217, and thus effectively prevent the short circuit between the first drain doping layer 224 and the source doping layer 217. The second floating gate structure 206 can block the diffusion of the second drain doping layer 212 and the source doping layer 217, and thus effectively prevent the short circuit between the second drain doping layer 212 and the source doping layer 217. Moreover, the channel areas and volumes of the first floating gate structure 205 and the second floating gate structure 206 increase, which can improve the control ability of the first floating gate structure 205 and the second floating gate structure 206 over the channel, and can also improve the coupling rate between the first floating gate structure 205 and the source line layer 217, as well as between the second floating gate structure 206 and the source line layer 217, thereby improving the programming efficiency of the device.

[0105] In this embodiment, the material of the substrate 200 is silicon.

[0106] In other embodiments, the material may further include silicon carbide, silicon germanium, a multi-semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI), etc. Among them, the multi-semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0107] Please continue to refer to Figure 8 and Figure 9, in this embodiment, the first floating gate structure 205 includes: a first intermediate portion 205a and first edge portions 205b located on both sides of the first intermediate portion 205a; the projection of the first erasing gate structure 210 onto the substrate 200 coincides with the projection of the first intermediate portion 205a onto the substrate 200; the second floating gate structure 206 includes: a second intermediate portion 206a and second edge portions 206b located on both sides of the second intermediate portion 206a; the projection of the second erasing gate structure 211 onto the substrate 200 coincides with the projection of the second intermediate portion 206a onto the substrate 200.

[0108] Please continue to refer to Figure 8 and Figure 9 , in this embodiment, the projection of the first sidewall 215 onto the substrate 200 and the projection of the first edge portion 205b onto the substrate 200 have an overlapping area; the projection of the second sidewall 216 onto the substrate 200 and the projection of the second edge portion 206b onto the substrate 200 have an overlapping area. The first sidewall 215 is formed on the area already occupied by the first floating gate structure 205 such that the first sidewall 215 does not additionally occupy more area regions, and correspondingly, the second sidewall 216 is formed on the area already occupied by the second floating gate structure 206 such that the second sidewall 216 does not additionally occupy more area regions, thereby reducing the overall area region occupied by the device unit and improving the integration degree of the chip.

[0109] In this embodiment, the first floating gate structure 205 includes: a first coupling oxide layer on the surface of the first floating gate trench 201 and a first floating gate layer on the first coupling oxide layer, and the first floating gate layer fills the first floating gate trench 201; the second floating gate structure 206 includes: a second coupling oxide layer on the surface of the second floating gate trench 202 and a second floating gate layer on the second coupling oxide layer, and the second floating gate layer fills the second floating gate trench 202.

[0110] In this embodiment, the materials of both the first coupling oxide layer and the second coupling oxide layer are silicon oxide; the materials of both the first floating gate layer and the second floating gate layer are polysilicon.

[0111] In this embodiment, the first erasing gate structure 210 includes: a first tunneling oxide layer and a first erasing gate layer on the first tunneling oxide layer; the second erasing gate structure 211 includes: a second tunneling oxide layer and a second erasing gate layer on the second tunneling oxide layer.

[0112] In this embodiment, the materials of both the first tunneling oxide layer and the second tunneling oxide layer are silicon oxide.

[0113] In this embodiment, the materials of the first erasing gate layer and the second erasing gate layer are both polysilicon.

[0114] In this embodiment, the materials of the first sidewall 215 and the second sidewall 216 are both one or both of silicon oxide and silicon nitride.

[0115] In this embodiment, it further includes: a first covering layer 213 located on the first erasing gate structure 210 and a second covering layer 214 located on the second erasing gate structure 211. The first covering layer 213 can cover and protect the top surface of the first erasing gate structure 210, and correspondingly, the second covering layer 214 can cover and protect the top surface of the second erasing gate structure 211. Moreover, the first covering layer 213 and the second covering layer 214 can also serve as a polishing stop layer for planarization processing during the subsequent formation of the source line layer, preventing short circuits between the source line layer and the first erasing gate structure 210 and the second erasing gate structure 211.

[0116] In this embodiment, the materials of the first covering layer 213 and the second covering layer 214 are both silicon nitride.

[0117] In this embodiment, the first word line structure 220 includes: a first word line oxide layer located on the sidewall of the first sidewall 215 and the surface of the substrate 200, and a first word line layer located on the first word line oxide layer; the second word line structure 221 includes: a second word line oxide layer located on the sidewall of the second sidewall 216 and the surface of the substrate 200, and a second word line layer located on the second word line oxide layer.

[0118] In this embodiment, the materials of the first word line oxide layer and the second word line oxide layer are both silicon oxide; the materials of the first word line layer and the second word line layer are both polysilicon.

[0119] In this embodiment, the materials of the third sidewall 222 and the fourth sidewall 223 are both one or both of silicon oxide and silicon nitride.

[0120] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A split-gate flash memory, characterized in that, Comprising: A substrate having mutually discrete first floating gate trenches and second floating gate trenches therein; A first floating gate structure located in the first floating gate trench and a second floating gate structure located in the second floating gate trench; A first erase gate structure located on the substrate, the first erase gate structure being located on the first floating gate structure, and a second erase gate structure located on the substrate, the second erase gate structure being located on the second floating gate structure; A first sidewall located on the sidewall of the first erase gate structure and a second sidewall located on the sidewall of the second erase gate structure; A source doping layer located in the substrate, the source doping layer being located between the adjacent first floating gate structure and the second floating gate structure; A source line layer located on the substrate, the source line layer being located on the source doping layer and between the adjacent first erase gate structure and the second erase gate structure; A first word line structure located on the substrate, the first erase gate structure and the first sidewall being located between the first word line structure and the source line layer, and a second word line structure located on the substrate, the second erase gate structure and the second sidewall being located between the second word line structure and the source line layer; A third sidewall located on the sidewall of the first word line structure and a fourth sidewall located on the sidewall of the second word line structure; A first drain doping layer and a second drain doping layer located in the substrate, the first floating gate structure being located between the first drain doping layer and the source doping layer, and the second floating gate structure being located between the second drain doping layer and the source doping layer.

2. The split-gate flash memory according to claim 1, wherein, The first floating gate structure includes: a first middle portion and first edge portions located on both sides of the first middle portion; the projection of the first erase gate structure onto the substrate coincides with the projection of the first middle portion onto the substrate; the second floating gate structure includes: a second middle portion and second edge portions located on both sides of the second middle portion; the projection of the second erase gate structure onto the substrate coincides with the projection of the second middle portion onto the substrate.

3. The split-gate flash memory according to claim 2, wherein The projection of the first sidewall onto the substrate has an overlapping area with the projection of the first edge portion onto the substrate; the projection of the second sidewall onto the substrate has an overlapping area with the projection of the second edge portion onto the substrate.

4. The split-gate flash memory according to claim 1, wherein The first floating gate structure includes: a first coupling oxide layer located on the surface of the first floating gate trench and a first floating gate layer located on the first coupling oxide layer, the first floating gate layer filling the first floating gate trench; the second floating gate structure includes: a second coupling oxide layer located on the surface of the second floating gate trench and a second floating gate layer located on the second coupling oxide layer, the second floating gate layer filling the second floating gate trench.

5. The split-gate flash memory according to claim 1, characterized in that, The first erase gate structure includes: a first tunneling oxide layer and a first erase gate layer located on the first tunneling oxide layer; the second erase gate structure includes: a second tunneling oxide layer and a second erase gate layer located on the second tunneling oxide layer.

6. The split-gate flash memory according to claim 5, wherein The first tunneling oxide layer is made of silicon oxide; the first tunneling oxide layer is made of silicon oxide.

7. The split-gate flash memory according to claim 1, wherein The first word line structure includes: a first word line oxide layer located on the sidewall of the first spacer and the surface of the substrate, and a first word line layer located on the first word line oxide layer; the second word line structure includes: a second word line oxide layer located on the sidewall of the second spacer and the surface of the substrate, and a second word line layer located on the second word line oxide layer.

8. The split-gate flash memory according to claim 1, wherein, It further includes: a first capping layer located on the first erase gate structure and a second capping layer located on the second erase gate structure.

9. The split-gate flash memory according to claim 8, wherein, The material of the first capping layer is silicon nitride; the material of the second capping layer is silicon nitride.

10. A method for forming a split-gate flash memory, characterized in that, It includes: providing a substrate; forming mutually discrete first floating gate trenches and second floating gate trenches in the substrate; forming a first floating gate structure in the first floating gate trench and a second floating gate structure in the second floating gate trench; forming a first erase gate structure and a second erase gate structure on the substrate, the first erase gate structure being located on the first floating gate structure and the second erase gate structure being located on the second floating gate structure; forming a first spacer on the sidewall of the first erase gate structure and a second spacer on the sidewall of the second erase gate structure; forming a source doping layer in the substrate, the source doping layer being located between the adjacent first floating gate structure and the second floating gate structure; forming a source line layer on the substrate, the source line layer being located on the source doping layer and between the adjacent first erase gate structure and the second erase gate structure; forming a first word line structure and a second word line structure on the substrate, the first erase gate structure and the first spacer being located between the first word line structure and the source line layer, and the second erase gate structure and the second spacer being located between the second word line structure and the source line layer; forming a third spacer on the sidewall of the first word line structure and a fourth spacer on the sidewall of the second word line structure; forming a first drain doping layer and a second drain doping layer in the substrate, the first floating gate structure being located between the first drain doping layer and the source doping layer, and the second floating gate structure being located between the second drain doping layer and the source doping layer.

11. The method for forming a split-gate flash memory according to claim 10, wherein, The first floating gate structure includes: a first middle portion and first edge portions located on both sides of the first middle portion; the projection of the first erase gate structure towards the substrate coincides with the projection of the first middle portion towards the substrate; the second floating gate structure includes: a second middle portion and second edge portions located on both sides of the second middle portion; the projection of the second erase gate structure towards the substrate coincides with the projection of the second middle portion towards the substrate.

12. The method for forming a split-gate flash memory according to claim 11, wherein The projection of the first spacer towards the substrate has an overlapping region with the projection of the first edge portion towards the substrate; the projection of the second spacer towards the substrate has an overlapping region with the projection of the second edge portion towards the substrate.

13. The method for forming a split-gate flash memory according to claim 10, wherein The first floating gate structure includes: a first coupling oxide layer located on the surface of the first floating gate trench, and a first floating gate layer located on the first coupling oxide layer, the first floating gate layer filling the first floating gate trench; the second floating gate structure includes: a second coupling oxide layer located on the surface of the second floating gate trench, and a second floating gate layer located on the second coupling oxide layer, the second floating gate layer filling the second floating gate trench.

14. The method for forming a split-gate flash memory according to claim 13, wherein The method for forming the first floating gate structure and the second floating gate structure includes: forming a coupling oxide material layer on the surface of the first floating gate trench, the surface of the second floating gate structure, and the surface of the substrate; forming a floating gate material layer on the coupling oxide material layer, the floating gate material layer filling the first floating gate trench and the second floating gate trench; performing a back-etching process on the floating gate material layer until the coupling oxide material layer is exposed, to form the first floating gate structure and the second floating gate structure.

15. The method for forming a split-gate flash memory according to claim 10, wherein Before forming the first sidewall and the second sidewall, it further includes: forming a first covering layer on the first erasing gate structure and forming a second covering layer on the second erasing gate structure.

16. The method for forming a split-gate flash memory according to claim 15, wherein, The first erasing gate structure includes: a first tunneling oxide layer, and a first erasing gate layer located on the first tunneling oxide layer; the second erasing gate structure includes: a second tunneling oxide layer, and a second erasing gate layer located on the second tunneling oxide layer.

17. The method for forming a split-gate flash memory according to claim 16, wherein The method for forming the first erasing gate structure, the second erasing gate structure, the first covering layer and the second covering layer includes: forming a tunneling oxide material layer on the substrate; forming an erasing gate material layer on the tunneling oxide material layer; forming a covering material layer on the erasing gate material layer; performing a patterning etching process on the erasing gate material layer and the covering material layer to form the first erasing gate structure, the second erasing gate structure, the first covering layer and the second covering layer.

18. The method for forming a split-gate flash memory according to claim 10, wherein, The method for forming the first sidewall and the second sidewall includes: forming a first sidewall material layer on the substrate; performing a patterning etching process on the first sidewall material layer to form the first sidewall and the second sidewall.

19. The method for forming a split-gate flash memory according to claim 10, wherein The method for forming the source doping layer includes: performing a source ion implantation process on the substrate to form the source doping layer.

20. The method for forming a split-gate flash memory according to claim 15, wherein, The method for forming the source line layer includes: forming a source line material layer on the substrate, the source line material layer covering the first erasing gate structure, the second erasing gate structure, the first covering layer, the second covering layer, the first sidewall and the second sidewall; performing a planarization process on the source line material layer until the surfaces of the first covering layer and the second covering layer are exposed, to form an initial source line layer; performing a patterning etching process on the initial source line layer to form the source line layer.

21. The method for forming a split-gate flash memory according to claim 10, wherein, The first word line structure includes: a first word line oxide layer located on the sidewall of the first sidewall and the substrate surface, and a first word line layer located on the first word line oxide layer; the second word line structure includes: a second word line oxide layer located on the sidewall of the second sidewall and the substrate surface, and a second word line layer located on the second word line oxide layer.

22. The method for forming a split-gate flash memory according to claim 21, wherein, The forming method of the first word line structure and the second word line structure includes: forming a word line oxide material layer on the sidewall of the first sidewall, the sidewall of the second sidewall, and the substrate surface; forming a word line material layer on the word line oxide material layer; performing a patterning etching process on the word line oxide material layer and the word line material layer to form the first word line structure and the second word line structure.

23. The method for forming a split-gate flash memory according to claim 10, wherein, The forming method of the third sidewall and the fourth sidewall includes: forming a second sidewall material layer on the substrate; performing a patterning etching process on the second sidewall material layer to form the third sidewall and the fourth sidewall.

24. The method for forming a split-gate flash memory according to claim 10, wherein, The forming method of the first drain doping layer and the second drain doping layer includes: performing a drain ion implantation process on the substrate to form the first drain doping layer and the second drain doping layer.

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