Power mosfet with gate-source ESD diode structure

Abstract

The invention relates to a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a gate-source ESD diode structure. An apparatus includes: a drain and a source on opposite sides of an epitaxial layer; the grid electrodes are formed in the epitaxial layer; a source contact connected to the source electrode; a gate contact connected to the plurality of gates; a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact; and a breakdown voltage enhancement and leakage protection structure formed below the gate-source ESD diode structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to a power metal-oxide-semiconductor field-effect transistor (MOSFET), and in particular embodiments, to a power MOSFET having a gate-source ESD diode structure and a breakdown voltage enhancement and leakage protection structure. Background Art

[0002] As semiconductor technology has gradually developed, power MOSFETs have been widely used in various industrial applications. A power MOSFET is a voltage-controlled device. When a control voltage is applied to the gate of the power MOSFET and the control voltage is greater than the threshold of the power MOSFET, a conductive channel is established between the drain and the source of the power MOSFET. Thus, current flows between the drain and the source of the power MOSFET. On the other hand, when the control voltage is less than the threshold of the power MOSFET, the power MOSFET is correspondingly turned off.

[0003] Power MOSFETs can be divided into two main categories. One is the n-channel power MOSFET. The other is the p-channel power MOSFET. According to structural differences, power MOSFETs can be further divided into three sub-categories, namely planar power MOSFETs, lateral power MOSFETs, and vertical power MOSFETs.

[0004] Vertical power MOSFETs have been widely used in high-voltage and high-current applications due to their low gate drive power, fast switching speed, and low on-resistance. In a vertical power MOSFET, the drain and the source are placed on opposite sides of the wafer. A trench structure can be formed between the drain and the source of the vertical power MOSFET.

[0005] The input / output terminals of a vertical power MOSFET must be protected from electrostatic discharge (ESD) voltages. For example, the gate of a vertical power MOSFET is a critical component. An excessive voltage at the gate with respect to the source can cause breakdown and damage. To protect the gate of the vertical power MOSFET from ESD, a back-to-back ESD diode structure can be connected between the gate terminal and the source terminal of the vertical power MOSFET. The back-to-back ESD diode structure can be implemented as an array of doped p-regions and n+-regions arranged in an alternating manner. For example, the array can include a first p-type region, a first n+-region, a second p-type region, a second n+-region, and a third p-type region connected in cascade. Alternatively, the array can include a first n+-region, a first p-type region, a second n+-region, a second p-type region, and a third n+-region connected in cascade. The p-n+ structure is a common configuration for ESD protection diodes. The p-n+ structure helps form a structure with a low breakdown voltage, making the ESD diode structure suitable for clamping and diverting excessive voltages during an ESD event, thereby protecting the gate of the vertical power MOSFET from damage. Summary of the Invention

[0006] By the preferred embodiments of the present disclosure, these and other problems can generally be solved or avoided and technical advantages can generally be achieved. The preferred embodiments provide a power MOSFET having a gate-source ESD diode structure and a breakdown voltage enhancement and leakage protection structure.

[0007] According to one embodiment, a device includes: a drain and a source located on opposite sides of an epitaxial layer; a plurality of gates formed in the epitaxial layer; a source contact connected to the source; a gate contact connected to the plurality of gates; a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact; and a breakdown voltage enhancement and leakage protection structure formed below the gate-source ESD diode structure.

[0008] According to another embodiment, a method includes: growing an epitaxial layer over a substrate; forming a plurality of gates in the epitaxial layer; forming a body region and a breakdown voltage enhancement and leakage protection structure in the epitaxial layer; forming a source in the epitaxial layer and forming a gate-source ESD diode structure over the epitaxial layer; and forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, and a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure.

[0009] According to another embodiment, a power MOSFET includes: an epitaxial layer located above a substrate; a plurality of gates formed in the epitaxial layer; a body region formed in the epitaxial layer; a source formed in the body region; a gate-source ESD diode structure formed above the epitaxial layer; a body ring structure formed in the epitaxial layer and located below the gate-source ESD diode structure; an interlayer dielectric layer formed above the epitaxial layer, wherein the gate-source ESD diode structure is located in the interlayer dielectric layer; a plurality of source contact plugs, wherein at least one of the plurality of source contact plugs extends through the interlayer dielectric layer, the source, and partially through the body region; a gate contact plug that partially extends through the interlayer dielectric layer; a gate contact connected to the plurality of gates and a first terminal of the gate-source ESD diode structure through the gate contact plug; and a source contact connected to the source, the body region, and a second terminal of the gate-source ESD diode structure through the plurality of source contact plugs.

[0010] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure so that the detailed description of the present disclosure that follows may be better understood. Additional features and advantages of the present disclosure will be described hereinafter, which form the subject matter of the claims of the present disclosure. Those skilled in the art should understand that the disclosed concepts and specific embodiments may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To more fully understand the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying Figure 1 drawings, in which:

[0012] Figure 1 FIG. illustrates a cross-sectional view of a power MOSFET having a gate-source ESD diode structure and a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure;

[0013] Figure 2 FIG. illustrates a cross-sectional view of a semiconductor device after growing an epitaxial layer from a substrate according to various embodiments of the present disclosure;

[0014] Figure 3 FIG. illustrates a cross-sectional view of a semiconductor device shown after performing an etching process on a hard mask layer to define a pattern of the hard mask layer Figure 2 therein;

[0015] Figure 4 Cross-sectional views of semiconductor devices showing after forming three trenches in an epitaxial layer according to various embodiments of the present disclosure Figure 3 ;

[0016] Figure 5 Cross-sectional views of semiconductor devices showing after forming a thin dielectric layer in the trenches and over the epitaxial layer according to various embodiments of the present disclosure Figure 4 ;

[0017] Figure 6 Cross-sectional views of semiconductor devices showing after filling the trenches with gate electrode material according to various embodiments of the present disclosure Figure 5 ;

[0018] Figure 7 Cross-sectional views of semiconductor devices showing after applying an etch-back process to the top surface shown in Figure 6 ; Figure 6 ;

[0019] Figure 8 Cross-sectional views of semiconductor devices showing after forming a body region and a body ring structure in the epitaxial layer according to various embodiments of the present disclosure Figure 7 ;

[0020] Figure 9 Cross-sectional views of semiconductor devices showing after forming an ESD bottom dielectric layer and an ESD layer over the epitaxial layer according to various embodiments of the present disclosure Figure 8 ;

[0021] Figure 10 Cross-sectional views of semiconductor devices showing after applying an anisotropic etching process to the ESD bottom dielectric layer and the ESD layer according to various embodiments of the present disclosure Figure 9 ;

[0022] Figure 11 Cross-sectional views of semiconductor devices showing after forming a source region over the body region and an n+ region in the ESD layer according to various embodiments of the present disclosure Figure 10 ;

[0023] Figure 12 Cross-sectional views of semiconductor devices showing after forming a dielectric layer over the epitaxial layer according to various embodiments of the present disclosure Figure 11 ;

[0024] Figure 13 Cross-sectional views of semiconductor devices showing after applying an anisotropic etching process to the dielectric layer to form a plurality of trenches according to various embodiments of the present disclosureFigure 12 Cross-sectional view of a semiconductor device as shown therein;

[0025] Figure 14 Illustrating, after forming a p+ region at the bottom of each trench according to various embodiments of the present disclosure Figure 13 Cross-sectional view of a semiconductor device as shown therein;

[0026] Figure 15 Illustrating, after filling a metal material in the trenches of a semiconductor device according to various embodiments of the present disclosure Figure 14 Cross-sectional view of a semiconductor device as shown therein;

[0027] Figure 16 Illustrating, after forming source and gate contacts according to various embodiments of the present disclosure Figure 15 Cross-sectional view of a semiconductor device as shown therein;

[0028] Figure 17 Cross-sectional view illustrating a second embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure;

[0029] Figure 18 Cross-sectional view illustrating a third embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure;

[0030] Figure 19 Cross-sectional view illustrating a fourth embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure;

[0031] Figure 20 Cross-sectional view of a semiconductor device after the gate is covered by a dielectric layer, according to various embodiments of the present disclosure;

[0032] Figure 21 Illustrating, after forming a body region in an epitaxial layer according to various embodiments of the present disclosure Figure 20 Cross-sectional view of a semiconductor device as shown therein;

[0033] Figure 22 Illustrating, after forming a first n-type well in a first p-type well according to various embodiments of the present disclosure Figure 21 Cross-sectional view of a semiconductor device as shown therein;

[0034] Figure 23 Illustrating, after forming a second p-type well in a first n-type well according to various embodiments of the present disclosure Figure 22 Cross-sectional view of a semiconductor device as shown therein;

[0035] Figure 24Cross-sectional view of a semiconductor device showing after formation of a second n-type well in a p-type well according to various embodiments of the present disclosure Figure 23 as shown in;

[0036] Figure 25 Cross-sectional view of a fifth embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure

[0037] Figure 26 Cross-sectional view of a sixth embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure

[0038] Figure 27 Cross-sectional view of a seventh embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure

[0039] Figure 28 Cross-sectional view of an eighth embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure

[0040] Figure 29 Cross-sectional view of a ninth embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure

[0041] Figure 30 Diagrammatically illustrating for fabrication according to various embodiments of the present disclosure Figure 1 as shown in; and

[0042] Figure 31 is according to various embodiments of the present disclosure Figure 16 Cross-sectional view of a power MOSFET as shown in and a top view of a body ring structure

[0043] Corresponding numerals and symbols in different figures generally refer to corresponding components unless otherwise indicated. The figures are drawn to clearly illustrate relevant aspects of the various embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0044] The fabrication and use of the presently preferred embodiments are discussed in detail below. However, it should be understood that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of making and using the present disclosure and do not limit the scope of the present disclosure.

[0045] The present disclosure will describe preferred embodiments in a specific context, namely, a power MOSFET having a gate-source ESD diode structure and a breakdown voltage enhancement and leakage protection structure. However, the present disclosure can also be applied to various power transistors. In the following, various embodiments will be explained in detail with reference to the accompanying drawings.

[0046] Figure 1 A cross-sectional view of a power MOSFET having a gate-source ESD diode structure and a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure is illustrated. The power MOSFET 100 includes a substrate 102, an epitaxial layer 104, a plurality of gates 702, 704, and 706, a body including a first body region 802 and a second body region 804, a source including a first source region 912 and a second source region 914, a body ring structure 820, an interlayer dielectric layer 920, a plurality of source contact plugs 951, 952, and 953, a gate contact plug 954, a gate-source ESD diode structure 929, a source contact 962, a gate contact 964, and a drain contact 966.

[0047] As Figure 1 shown, the epitaxial layer 104 is formed over the substrate 102. The plurality of gates 702, 704, and 706 are formed in the epitaxial layer 104. The first body region 802 is formed in the epitaxial layer 104 and between the gates 702 and 704. The second body region 804 is formed in the epitaxial layer 104 and between the gates 704 and 706. It should be noted that although from the Figure 1 cross-sectional view shown, the body regions 802 and 804 may be two separate regions, from a top view, the body regions 802 and 804 may also be part of a continuous body region.

[0048] As Figure 1 shown, the first source region 912 is formed in the first body region 802 and between the gates 702 and 704. The second source region 914 is formed in the second body region 804 and between the gates 704 and 706. It should be noted that although from the Figure 1 cross-sectional view shown, the source regions 912 and 914 may be two separate regions, from a top view, the source regions 912 and 914 may also be part of a continuous source region.

[0049] An interlayer dielectric layer 920 is formed over the epitaxial layer 104. A gate-source ESD diode structure 929 is formed over the epitaxial layer and in the interlayer dielectric layer 920. The gate-source ESD diode structure 929 includes a plurality of n+ regions and a plurality of p-type regions arranged in an alternating manner. In some embodiments, the gate-source ESD diode structure 929 includes a first p-type region 921, a first n+ region 922, a second p-type region 923, a second n+ region 924, and a third p-type region 925 connected in cascade. The first p-type region 921 is connected to the gate contact 964. The third p-type region 925 is connected to the source contact 962.

[0050] A body ring structure 820 is formed in the epitaxial layer 104 and is located below the gate-source ESD diode structure 929. As Figure 1 seen from the cross-sectional view shown, the body ring structure 820 includes four pillars 822, 824, 826, and 828. In some embodiments, seen from a top view, the body ring structure 820 is a concentric ring structure formed in the epitaxial layer 104.

[0051] The body ring structure 820 serves as a breakdown voltage enhancement and leakage protection structure. In operation, the body ring structure 820 is configured to disperse the electric field on the gate-source ESD diode structure 929. The body ring structure 820 provides an electric field gradient that reduces the peak electric field at the edge of the gate-source ESD diode structure 929, thereby spreading the electric field more evenly. Accordingly, the breakdown voltage of the power MOSFET 100 can be increased, and the leakage of the power MOSFET 100 can be reduced.

[0052] As Figure 1 shown, a source contact plug 951 extends through the interlayer dielectric layer 920, the first source region 912, and partially through the first body region 802. A first terminal of the source contact plug 951 is connected to the source contact 962. A second terminal of the source contact plug 951 is connected to a first p+ region 942 formed in the first body region 802.

[0053] A source contact plug 952 extends through the interlayer dielectric layer 920, the second source region 914, and partially through the second body region 804. A first terminal of the source contact plug 952 is connected to the source contact 962. A second terminal of the source contact plug 952 is connected to a second p+ region 944 formed in the second body region 804.

[0054] The source contact plug 953 extends partially through the interlayer dielectric layer 920 and partially through the third p-type region 925. The first terminal of the source contact plug 953 is connected to the source contact 962. The second terminal of the source contact plug 953 is connected to the fourth p+-region 948 formed in the third p-type region 925.

[0055] The gate contact plug 954 extends partially through the interlayer dielectric layer 920 and partially through the first p-type region 921. The first terminal of the gate contact plug 954 is connected to the gate contact 964. The second terminal of the gate contact plug 954 is connected to the third p+-region 946 formed in the first p-type region 921.

[0056] In some embodiments, Figure 1 the power MOSFET shown in Figure 1 can be implemented as an n-type power MOSFET. The substrate 102 is an n+ substrate. The epitaxial layer 104 is an n-type layer. The doping concentration of the epitaxial layer 104 is lower than that of the substrate 102. The body region is a p-type region. The source is an n+-region. The body ring structure 820 is a p-type body ring structure. Figure 1 The n-type regions (e.g., source regions 912 and 914) in

[0057] are formed by implanting an n-type dopant such as phosphorus, arsenic, etc. Alternatively, the n-type regions can be formed by a diffusion process. Figure 1 The p-type regions (e.g., body regions 802 and 804) in

[0058] as shown in Figure 1 are formed by implanting a p-type doping material such as boron, gallium, aluminum, indium, combinations thereof, etc. Alternatively, the p-type regions can be formed by a diffusion process.

[0059] Figures 2 to 16 illustrates a cross-sectional view of an intermediate step in fabricating the power MOSFET shown in accordance with various embodiments of the present disclosure. Figure 1 in

[0060] Figure 2A cross-sectional view of a semiconductor device after growing an epitaxial layer from a substrate according to various embodiments of the present disclosure. According to an embodiment, the substrate 102 may be an n+ substrate doped with n-type impurities such as phosphorus, arsenic, etc.

[0061] An n-type epitaxial layer 104 is grown from the substrate 102. The epitaxial growth of the n-type epitaxial layer 104 can be implemented by using a suitable semiconductor manufacturing process such as chemical vapor deposition (CVD), ultra-high vacuum chemical vapor deposition (UHV-CVD), etc.

[0062] Figure 3 A cross-sectional view of a semiconductor device shown after performing an etching process on a hard mask layer to define a pattern of the hard mask layer according to various embodiments of the present disclosure Figure 2 A hard mask layer 106 is deposited on top of the epitaxial layer 104 by using a suitable manufacturing technique such as CVD. The hard mask layer 106 can be formed of a suitable material such as silicon nitride. The hard mask layer 106 serves as an etching mask.

[0063] A photoresist layer 108 is formed above the hard mask layer 106 by using spin-on deposition or the like. The photoresist layer 108 is patterned by using a suitable photolithography technique. Thereafter, the hard mask layer 106 is patterned in consideration of Figure 1 the positions of the multiple gates 702, 704, and 706 of the power MOSFET 100 shown.

[0064] Figure 4 A cross-sectional view of a semiconductor device shown after forming three trenches in the epitaxial layer according to various embodiments of the present disclosure Figure 3 The remaining photoresist layer 108 shown can be removed by using a suitable photoresist stripping technique such as chemical solvent cleaning, plasma ashing, dry stripping, etc. Photoresist stripping techniques are well known and are not discussed in more detail herein to avoid repetition. Thereafter, an etching process such as reactive ion etching (RIE) or other dry etching, anisotropic wet etching, or any other suitable anisotropic etching or patterning process is performed to form three trenches, namely a first trench 402, a second trench 404, and a third trench 406, in the epitaxial layer 104, as Figure 3 shown. Figure 4 shown.

[0065] Figure 5 A cross-sectional view of a semiconductor device shown after forming a thin dielectric layer in the trenches and above the epitaxial layer according to various embodiments of the present disclosure Figure 4 As Figure 5 shown, Figure 4The hard mask layer 106 shown in [reference] has been removed by a suitable hard mask layer removal process such as a wet etching process. The removal process is applied to the top surface of the semiconductor device until the epitaxial layer 104 is exposed.

[0066] The thin dielectric layer 502 is a gate dielectric layer. As shown in [reference], the thin dielectric layer 502 is formed on the bottoms and sidewalls of the trenches 402, 404, and 406. The thin dielectric layer 502 can be formed of common dielectric materials such as oxides, nitrides, oxynitrides, high-k materials, combinations thereof, and multi-layers thereof. Figure 5 The thin dielectric layer 502 is formed on the bottoms and sidewalls of the trenches 402, 404, and 406. The thin dielectric layer 502 can be formed of common dielectric materials such as oxides, nitrides, oxynitrides, high-k materials, combinations thereof, and multi-layers thereof.

[0067] According to an embodiment, the thin dielectric layer 502 is an oxide layer. The thin dielectric layer 502 can be formed by using suitable heat treatment techniques, wet processing techniques, or deposition techniques such as physical vapor deposition (PVD), CVD, atomic layer deposition (ALD), etc.

[0068] Figure 6 Illustrates a cross-sectional view of a semiconductor device according to various embodiments of the present disclosure after filling the trench with gate electrode material as shown in [reference]. The trench 402, 404, and 406 are filled with gate electrode material. The gate electrode material also forms a gate electrode layer 602 over the epitaxial layer 104. Figure 5 The trench 402, 404, and 406 are filled with gate electrode material. The gate electrode material also forms a gate electrode layer 602 over the epitaxial layer 104.

[0069] In some embodiments, the gate electrode material is polysilicon. According to an embodiment, the polysilicon layer is doped with n-type impurity ions to become a gate conductive layer. Although phosphorus is used as the n-type impurity ion, other n-type conductive ions can be used if desired or required. Doping the n-type impurity ions in the polysilicon layer is preferably performed by a separate n-type impurity ion doping process after the deposition of the polysilicon layer, or by depositing the polysilicon layer while doping the n-type impurity ions.

[0070] An annealing process is applied to the polysilicon layer. The annealing process is used to diffuse the n-type impurity ions into the polysilicon layer. The annealing process can be performed as a rapid thermal process.

[0071] Figure 7 Illustrates a cross-sectional view of a semiconductor device according to various embodiments of the present disclosure after applying an etch-back process to the top surface as shown in [reference]. A planarization process such as chemical mechanical polishing (CMP) or an etch-back step can be performed to planarize the upper surface of the gate electrode layer 602 until the thin dielectric layer is exposed. Thereafter, a polysilicon oxidation process is performed to form a dielectric layer 710 to cover the polysilicon material in the trench. As shown in [reference]. Figure 6 Illustrates a cross-sectional view of a semiconductor device according to various embodiments of the present disclosure after applying an etch-back process to the top surface as shown in [reference]. Figure 6 A planarization process such as chemical mechanical polishing (CMP) or an etch-back step can be performed to planarize the upper surface of the gate electrode layer 602 until the thin dielectric layer is exposed. Thereafter, a polysilicon oxidation process is performed to form a dielectric layer 710 to cover the polysilicon material in the trench. As shown in [reference]. Figure 7As shown in FIG. 7 , after the CMP process, three gates, namely, a first gate 702 , a second gate 704 , and a third gate 706 , may be formed in the epitaxial layer.

[0072] Figure 8 Schematic diagram of the process of forming a body region and a body ring structure in an epitaxial layer according to various embodiments of the present disclosure Figure 7 A photoresist layer 812 is formed over the top surface of the semiconductor device using spin coating deposition or the like. Considering Figure 1 , a photoresist layer 812 is patterned using a suitable photolithography technique at the location of the body ring structure of the power MOSFET 100 shown in FIG. Body regions 802 and 804 and body ring structure 820 may be formed in an upper portion of epitaxial layer 104. According to an embodiment, body regions 802 and 804 and body ring structure 820 may be formed by implanting appropriate p-type dopants such as boron, gallium, indium, etc.

[0073] In some embodiments, the main ring structure 820 is a concentric ring structure from a top view. As shown in the cross-sectional view, the main ring structure 820 has four pillars 822, 824, 826 and 828. In some embodiments, the bottommost surface of the main ring structure 820 is flush with the bottommost surface of the main regions 802 and 804, as shown in FIG. Figure 8 As shown in .

[0074] In operation, the main ring structure 820 acts as a breakdown voltage enhancement and leakage protection structure. Figure 11 Describe the functionality of the breakdown voltage enhancement and leakage protection structures.

[0075] Figure 9 An illustration of a method of forming an ESD bottom dielectric layer and an ESD layer over the epitaxial layer according to various embodiments of the present disclosure. Figure 8 A cross-sectional view of a semiconductor device shown in FIG. Figure 8 The remaining photoresist layer 812 shown in FIG. 8 can be removed by using a suitable photoresist stripping technique. Thereafter, an ESD bottom dielectric layer 902 is deposited over the top surface of the semiconductor device using a suitable deposition technique such as PVD, CVD, ALD, etc. The ESD bottom dielectric layer 902 can be formed of commonly used dielectric materials such as oxides, nitrides, oxynitrides, high-k materials, combinations thereof, and multilayers thereof.

[0076] The ESD layer 904 is deposited over the ESD bottom dielectric layer 902. The ESD layer 904 can be formed of polysilicon. According to an embodiment, the ESD layer 904 is doped with p-type impurity ions such as boron. Doping the ESD layer 904 with p-type impurity ions is preferably implemented by a separate p-type impurity ion doping process after the deposition of the ESD layer 904, or by depositing the ESD layer 904 while doping with p-type impurity ions.

[0077] Figure 10 FIG. illustrates a cross-sectional view of a semiconductor device shown after applying an anisotropic etching process to an ESD bottom dielectric layer and an ESD layer according to various embodiments of the present disclosure Figure 9 An etching process is applied to the semiconductor device. As Figure 10 shown, portions of the ESD bottom dielectric layer and the ESD layer above the gates 702, 704, and 706 have thus been removed.

[0078] Figure 11 FIG. illustrates a cross-sectional view of a semiconductor device shown after forming source regions over a body region and forming n+ regions in an ESD layer according to various embodiments of the present disclosure Figure 10 As Figure 11 shown, the n+ regions 912 and 914 are respectively formed over the body regions 802 and 804 by a suitable fabrication process such as an ion implantation process. According to an embodiment, the n+ regions 912 and 914 can be used as Figure 1 shown, the source regions of the power MOSFET 100. Meanwhile, n+ regions 922 and 924 are formed in the ESD layer 904 as Figure 10 shown. The n+ regions are formed by implanting suitable n-type dopants such as phosphorus, arsenic.

[0079] As described above with respect to Figure 9 once the ESD layer 904 is doped with p-type impurity ions, the ESD layer 904 is a p-type layer. Since the n+ regions 922 and 924 are formed in the ESD layer 904, three p-type regions 921, 923, and 925 are formed in the ESD layer 904.

[0080] As Figure 11 shown, the first p-type region 921, the first n+ region 922, the second p-type region 923, the second n+ region 924, and the third p-type region 925 are cascade-connected. The first p-type region 921, the first n+ region 922, the second p-type region 923, the second n+ region 924, and the third p-type region 925 form a gate-source ESD diode structure 929.

[0081] As Figure 11As shown, the n+ regions and the p-type regions are formed in an alternating manner. The n+ regions and the p-type regions form a back-to-back ESD diode structure. The arrangement of the n+ regions and the p-type regions described above is only an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, the back-to-back ESD diode structure may include a first n+ region, a first p-type region, a second n+ region, a second p-type region, and a third n+ region connected in cascade.

[0082] As Figure 11 shown, the gate-source ESD diode structure 929 and the body ring structure 820 are separated by the ESD bottom dielectric layer 902. The body ring structure 820 is configured to disperse the electric field on the gate-source ESD diode structure 929. The body ring structure 820 provides an electric field gradient that reduces the peak electric field at the edge of the gate-source ESD diode structure 929, thereby spreading the electric field more evenly. Therefore, the body ring structure 820 is capable of improving the performance of the power MOSFET 100.

[0083] Figure 12 illustrates a cross-sectional view of a semiconductor device after forming a dielectric layer over an epitaxial layer according to various embodiments of the present disclosure Figure 11 shown. The dielectric layer 920 is deposited over the epitaxial layer 104. The dielectric layer 920 may alternatively be referred to as an interlayer dielectric (ILD) layer. The dielectric layer 920 may be a low-k dielectric layer having a low dielectric constant (e.g., less than about 3.5). The dielectric layer 920 may also include a combination of materials such as silicon nitride, silicon oxynitride, high-k dielectrics, low-k dielectrics, CVD polysilicon, or other dielectrics. The dielectric layer 920 may be deposited using suitable deposition techniques such as sputtering, CVD, etc.

[0084] Figure 13 illustrates a cross-sectional view of a semiconductor device after applying an anisotropic etching process to the dielectric layer to form a plurality of trenches Figure 12 shown. A plurality of trenches 932, 934, 936, and 938 are formed by etching the dielectric layer 920 and the region below the dielectric layer 920.

[0085] In some embodiments, the trenches 932, 934, and 938 are source contact trenches. As Figure 13As shown, trench 932 extends through dielectric layer 920, source region 912, and partially through body region 802. Similarly, trench 934 extends through dielectric layer 920, source region 914, and partially through body region 804. Trench 936 partially extends through dielectric layer 920 and partially through the first p-type region 921. Trench 938 partially extends through dielectric layer 920 and partially through the third p-type region 925.

[0086] Figure 14 Illustrates a cross-sectional view of a semiconductor device as shown after forming p+ regions at the bottom of each trench according to various embodiments of the present disclosure. A suitable implantation process, such as blanket ion implantation, is performed. P-type impurity ions, such as boron ions, are implanted into body regions 802, 804, the first p-type region 921, and the third p-type region 925. As Figure 13 shown, four p+ regions 942, 944, 946, and 948 are thus formed in the trenches respectively. The p+ regions 942, 944, 946, and 948 are specifically designed to further reduce contact resistance. Figure 14

[0087] Figure 15 Figure 14 Illustrates a cross-sectional view of a semiconductor device as shown after filling metal materials in the trenches of the semiconductor device according to various embodiments of the present disclosure. Metal materials, including tungsten, titanium, aluminum, copper, any combination thereof, and / or the like, are filled into trenches 932, 934, 936, and 938 to form contact plugs 951, 952, 953, and 954. The metal material above the interlayer dielectric layer 920 forms a metal contact layer 950.

[0088] Figure 16 Figure 15 Figure 1 Illustrates a cross-sectional view of a semiconductor device as shown after forming source and gate contacts according to various embodiments of the present disclosure. Considering the positions of the source contact and the gate contact of the power MOSFET 100 as shown in, the metal contact layer 950 is patterned using a suitable etching technique.

[0089] Figure 16 ​​​​As shown, the first source contact plug 951 has a first terminal connected to the source contact 962, and a second terminal connected to the first source region 912, the p+ region 942, and the first body region 802. The second source contact plug 952 has a first terminal connected to the source contact 962, and a second terminal connected to the second source region 914, the p+ region 944, and the second body region 804. The gate contact plug 954 has a first terminal connected to the gate contact 964, and a second terminal connected to the p+ region 946 and the first terminal of the gate-source ESD diode structure 929. The third source contact plug 953 has a first terminal connected to the source contact 962, and a second terminal connected to the p+ region 948 and the second terminal of the gate-source ESD diode structure 929.

[0090] Figure 17 Cross-sectional view illustrating a second embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure. As Figure 17 shown, the breakdown voltage enhancement and leakage protection structure of the power MOSFET 200 is implemented as a body ring structure 820. Figure 17 The body ring structure 820 shown in Figure 16 is similar to the body ring structure shown in Figure 17 except that the body ring structure 820 shown in

[0091] has five pillars 822, 824, 825, 826, and 828. In some embodiments, the sidewall of pillar 822 is vertically aligned with the sidewall of the first p-type region 921. The sidewall of pillar 824 is vertically aligned with the sidewall of the first n+ region 922. The sidewall of pillar 825 is vertically aligned with the sidewall of the second p-type region 923. The sidewall of pillar 826 is vertically aligned with the sidewall of the second n+ region 924. The sidewall of pillar 828 is vertically aligned with the sidewall of the third p-type region 925.

[0092] It should be appreciated that although Figure 17 illustrates a breakdown voltage enhancement and leakage protection structure having five pillars 822, 824, 825, 826, and 828, the breakdown voltage enhancement and leakage protection structure can accommodate any number of pillars.

[0093] Figure 18 Cross-sectional view illustrating a third embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure. As Figure 18 shown, the breakdown voltage enhancement and leakage protection structure of the power MOSFET 300 is implemented as a body ring structure 820. Figure 18 The body ring structure 820 shown in Figure 16The body ring structure shown in, except that the four posts 822, 824, 826, and 828 of the body ring structure 820 are vertically aligned with the corresponding ESD diode regions.

[0094] In some embodiments, the sidewall of post 822 is vertically aligned with the first sidewall of the first n+ region 922. The sidewall of post 824 is vertically aligned with the second sidewall of the first n+ region 922. The sidewall of post 826 is vertically aligned with the first sidewall of the second n+ region 924. The sidewall of post 828 is vertically aligned with the second sidewall of the second n+ region 924.

[0095] Figure 19 A cross-sectional view illustrating a fourth embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure. The breakdown voltage enhancement and leakage protection structure of the power MOSFET 400 includes a plurality of n-type wells 974, 976 and a plurality of p-type wells 973, 975 arranged in an alternating manner. The plurality of n-type wells and the plurality of p-type wells are configured to disperse the electric field on the gate-source ESD diode structure 929. As Figure 19 shown in, the plurality of n-type wells and the plurality of p-type wells are separated from the gate-source ESD diode structure 929 by a dielectric layer.

[0096] Figure 19 The p-n-p-n-p well structure shown in can achieve a higher level of reliability and durability in the power MOSFET 400, thereby improving the ESD protection design.

[0097] The n-well and the arrangement of the wells described above are only examples and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, an n-p-n-p-n well structure can be used to replace Figure 19 the well structure shown in. The n-p-n-p-n well structure completely covers the region under the gate-source ESD diode structure 929. This is characterized by a plurality of p-n diodes that enhance the electrical characteristics of the power MOSFET 400, thereby providing stronger protection against ESD events.

[0098] Figures 20 to 24 A cross-sectional view illustrating an intermediate step of fabricating the breakdown voltage enhancement and leakage protection structure shown in according to various embodiments of the present disclosure. Figure 19 The cross-sectional view shown in

[0099] Figure 20 A cross-sectional view illustrating a semiconductor device after the gate is covered by a dielectric layer according to various embodiments of the present disclosure. Figure 20 The cross-sectional view shown in is similar to Figure 7The cross-sectional views shown therein are not discussed herein to avoid repetition.

[0100] Figure 21 Illustrates a cross-sectional view of a semiconductor device shown in the formation of body regions in an epitaxial layer according to various embodiments of the present disclosure Figure 20 after. The body regions 971, 972, and 973 are p-type regions. The p-type regions 971, 972, and 973 are formed in the epitaxial layer 104 by a suitable semiconductor doping technique such as an ion implantation process. In some embodiments, a suitable p-type dopant such as boron, gallium, indium, and / or the like is implanted into the epitaxial layer 104 to form the body regions 971, 972, and 973. The body region 973 is alternatively referred to as the first p-type well.

[0101] Figure 22 Illustrates a cross-sectional view of a semiconductor device shown in the formation of a first n-type well in the first p-type well according to various embodiments of the present disclosure Figure 21 after. A photoresist layer 991 is deposited over the semiconductor device using spin coating deposition or the like. The photoresist layer 991 is exposed and developed such that only the portion above the first n-type well 974 is removed.

[0102] The first n-type well 974 is formed by implanting an n-type dopant such as phosphorus, arsenic, etc. Alternatively, the first n-type well 974 can be formed by a diffusion process. As Figure 22 shown, the first n-type well 974 is surrounded by the first p-type well 973.

[0103] Figure 23 Illustrates a cross-sectional view of a semiconductor device shown in the formation of a second p-type well in the first n-type well according to various embodiments of the present disclosure Figure 22 after. A photoresist layer 992 is deposited over the semiconductor device using spin coating deposition or the like. The photoresist layer 992 is exposed and developed such that only the portion above the second p-type well 975 is removed.

[0104] The second p-type well 975 is formed by implanting a p-type dopant such as boron, gallium, aluminum, indium, etc. Alternatively, the second p-type well 975 can be formed by a diffusion process. As Figure 23 shown, the second p-type well 975 is surrounded by the first n-type well 974.

[0105] Figure 24 Illustrates a cross-sectional view of a semiconductor device shown in the formation of a second n-type well in a p-type well according to various embodiments of the present disclosure Figure 23 after. A photoresist layer 993 is deposited over the semiconductor device using spin coating deposition or the like. The photoresist layer 993 is exposed and developed such that only the portion above the second n-type well 976 is removed.

[0106] A second n-type well 976 is formed by implanting an n-type dopant such as phosphorus, arsenic, etc. Alternatively, the second n-type well 976 can be formed by a diffusion process. As Figure 24 shown, the second n-type well 976 is surrounded by a second p-type well 975.

[0107] Those skilled in the art will recognize that Figure 24 the diagram illustrates an ideal profile. After subsequent fabrication processes, the size of the well can vary.

[0108] Figure 25 Cross-sectional view illustrating a fifth embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure. The breakdown voltage enhancement and leakage protection structure of the power MOSFET 500 includes two n-type wells 981, 983 and one p-type well 982 arranged in an alternating manner. The n-type wells and the p-type well are configured to disperse the electric field on the gate-source ESD diode structure 929. The n-type wells and the p-type well are separated from the gate-source ESD diode structure 929 by a dielectric layer.

[0109] As Figure 25 shown, the first n-type well 981 is formed in the epitaxial layer 104. The first p-type well 982 is formed in the first n-type well 981. The width of the first p-type well 982 is equal to the width of the first n-type well 981. The second n-type well 983 is formed in the first p-type well 982. The width of the second n-type well 983 is equal to the width of the first p-type well 982.

[0110] It should be recognized that although Figure 25 the diagram illustrates a breakdown voltage enhancement and leakage protection structure with three wells 981, 982 and 983, the breakdown voltage enhancement and leakage protection structure can accommodate any number of wells arranged in an alternating manner.

[0111] Figure 26 Cross-sectional view illustrating a sixth embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure. The breakdown voltage enhancement and leakage protection structure of the power MOSFET 600 is a reduced surface field (RESURF) structure 990. The RESURF structure is a well-known mechanism for increasing the breakdown voltage of high-voltage MOSFETs.

[0112] As Figure 26 shown, the RESURF structure 990 is placed under the gate-source ESD diode structure 929. The RESURF structure 990 is separated from the gate-source ESD diode structure 929 by a dielectric layer. This RESURF structure 990 helps to disperse the electric field on the gate-source ESD diode structure 929, thereby reducing the risk of electrical breakdown and leakage.

[0113] Figure 27 Cross-sectional view illustrating a seventh embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure. The breakdown voltage enhancement and leakage protection structure of the power MOSFET 700 includes a RESURF structure 990 and a body ring structure 820.

[0114] The RESURF structure 990 and the body ring structure 820 are configured to disperse the electric field on the gate-source ESD diode structure 929. The body ring structure 820 is a concentric ring structure formed in the epitaxial layer 104. The RESURF structure 990 and the gate-source ESD diode structure 929 are separated by a dielectric layer. As Figure 27 shown, the RESURF structure 990 is located between the gate-source ESD diode structure 929 and the body ring structure 820.

[0115] Figure 28 Cross-sectional view illustrating an eighth embodiment of a breakdown voltage enhancement and leakage protection structure according to various embodiments of the present disclosure. The breakdown voltage enhancement and leakage protection structure of the power MOSFET 800 includes a plurality of n-type wells, a plurality of p-type wells, and a body ring structure 820. Figure 28 The plurality of n-type wells and the plurality of p-type wells shown in Figure 19 are similar to the plurality of n-type wells and the plurality of p-type wells shown in

[0116] and are therefore not described herein again.

[0117] Figure 29 The plurality of n-type wells and the plurality of p-type wells are arranged in an alternating manner. The plurality of n-type wells, the plurality of p-type wells, and the body ring structure 820 are configured to disperse the electric field on the gate-source ESD diode structure 929. The body ring structure 820 is a concentric ring structure formed in the epitaxial layer 104. The plurality of n-type wells and the plurality of p-type wells are separated from the gate-source ESD diode structure 929 by a dielectric layer. The plurality of n-type wells and the plurality of p-type wells are located between the gate-source ESD diode structure 929 and the body ring structure 820. Figure 29 The plurality of n-type wells and the plurality of p-type wells shown in Figure 25 are similar to the plurality of n-type wells and the plurality of p-type wells shown in

[0118] A plurality of n-type wells and a plurality of p-type wells are arranged in an alternating manner. The plurality of n-type wells, the plurality of p-type wells, and the body ring structure 820 are configured to disperse the electric field on the gate-source ESD diode structure 929. The body ring structure 820 is a concentric ring structure formed in the epitaxial layer 104. The plurality of n-type wells and the plurality of p-type wells are separated from the gate-source ESD diode structure by a dielectric layer. As Figure 29 shown, the plurality of n-type wells and the plurality of p-type wells are located between the gate-source ESD diode structure 929 and the body ring structure 820.

[0119] Figure 30 The flowchart illustrates a method for fabricating a Figure 1 power MOSFET as shown in accordance with various embodiments of the present disclosure. Figure 30 The flowchart shown is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, various steps shown can be added, removed, replaced, rearranged, and repeated Figure 30 as shown.

[0120] At step 3002, an epitaxial layer is grown over the substrate.

[0121] At step 3004, a plurality of gates are formed in the epitaxial layer.

[0122] At step 3006, a body region and a breakdown voltage enhancement and leakage protection structure are formed in the epitaxial layer.

[0123] At step 3008, a source is formed in the epitaxial layer and a gate-source ESD diode structure is formed over the epitaxial layer.

[0124] At step 3010, a source contact is formed to connect to the source and a first terminal of the gate-source ESD diode structure, and a gate contact is formed to connect to the plurality of gates and a second terminal of the gate-source ESD diode structure.

[0125] The step of forming a breakdown voltage enhancement and leakage protection structure in the epitaxial layer includes forming a RESURF structure by an implantation process, wherein the RESURF structure is located in an upper portion of the epitaxial layer, and the RESURF structure is separated from the gate-source ESD diode structure by a dielectric layer.

[0126] The step of forming a breakdown voltage enhancement and leakage protection structure in the epitaxial layer includes forming a body ring structure by an implantation process, wherein the body ring structure is a concentric ring structure, and the body ring structure is separated from the gate-source ESD diode structure by a dielectric layer.

[0127] The steps of forming a breakdown voltage enhancement and leakage protection structure in the epitaxial layer include: forming a first p-type well in the epitaxial layer; forming a first n-type well in the first p-type well, and wherein the first n-type well is surrounded by the first p-type well; forming a second p-type well in the first n-type well, and wherein the second p-type well is surrounded by the first n-type well; and forming a second n-type well in the second p-type well, and wherein the second n-type well is surrounded by the second p-type well.

[0128] The steps of forming a breakdown voltage enhancement and leakage protection structure in the epitaxial layer include: forming a first n-type well in the epitaxial layer; forming a first p-type well in the first n-type well, and wherein the width of the first p-type well is equal to the width of the first n-type well; and forming a second n-type well in the first p-type well, and wherein the width of the second n-type well is equal to the width of the first p-type well.

[0129] The steps of forming a gate-source ESD diode structure above the epitaxial layer include forming a plurality of n-type regions and a plurality of p-type regions in an alternating manner in an interlayer dielectric layer above the epitaxial layer.

[0130] The method further includes: forming an interlayer dielectric layer above the epitaxial layer; forming a plurality of trenches in the interlayer dielectric layer; forming a plurality of p+ regions at the bottoms of the corresponding trenches; performing a metal deposition process to fill the plurality of trenches, thereby forming a plurality of source contact plugs and gate contact plugs; and forming source contacts and gate contacts by an etching process.

[0131] Figure 31 is according to various embodiments of the present disclosure Figure 16 The cross-sectional view of the power MOSFET and the top view of the body ring structure shown in. The cross-sectional view is taken along line A-A'. The cross-sectional view of the power MOSFET has been described above with respect to Figure 16 and thus will not be discussed herein. As Figure 31 shown in the top view in, the source contact 962 is surrounded by an ESD polysilicon region (e.g., the gate-source ESD diode structure 929). The body ring structure 820 is a concentric ring structure. As Figure 31 shown in, the body ring structure 820 includes a first rectangle with rounded corners, a second rectangle with rounded corners, a third rectangle with rounded corners, and a fourth rectangle with rounded corners. In the cross-sectional view, the first rectangle is represented by the pillar 822. The second rectangle is represented by the pillar 824. The third rectangle is represented by the pillar 826. The fourth rectangle is represented by the pillar 828.

[0132] As Figure 31 shown in, the body ring structure 820 includes a plurality of rectangles with rounded corners. Within the scope and spirit of the present invention, the body ring structure 820 includes other shapes, such as but not limited to oval, rectangular, square, or circular.

[0133] Although embodiments of the present disclosure have been described in detail along with their advantages, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0134] Moreover, the scope of the present application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, components, methods, and steps described in this specification. Those skilled in the art will readily appreciate from the disclosure of the present disclosure that, in accordance with the present disclosure, processes, machines, manufactures, compositions of matter, components, methods, or steps performing substantially the same function or achieving substantially the same result as the corresponding embodiments described herein can be utilized using currently existing or later developed ones. Accordingly, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, components, methods, or steps within their scope.

Claims

1. An apparatus, comprising: A drain and a source located on opposite sides of an epitaxial layer; A plurality of gates formed in the epitaxial layer; A source contact connected to the source; A gate contact connected to the plurality of gates; A gate-source electrostatic discharge (ESD) diode structure connected between the gate contact and the source contact; And A breakdown voltage enhancement and leakage protection structure formed under the gate-source ESD diode structure.

2. The apparatus according to claim 1, wherein: The breakdown voltage enhancement and leakage protection structure is a reduced surface field (RESURF) structure, and wherein: The RESURF structure is configured to disperse an electric field on the gate-source ESD diode structure; and The RESURF structure and the gate-source ESD diode structure are separated by a dielectric layer.

3. The apparatus according to claim 1, wherein: The breakdown voltage enhancement and leakage protection structure is a body ring structure, and wherein: The body ring structure is a concentric ring structure formed in the epitaxial layer; The body ring structure is configured to disperse an electric field on the gate-source ESD diode structure; and The body ring structure and the gate-source ESD diode structure are separated by a dielectric layer.

4. The apparatus according to claim 1, wherein: The breakdown voltage enhancement and leakage protection structure includes a plurality of n-type wells and a plurality of p-type wells arranged in an alternating manner, and wherein: The plurality of n-type wells and the plurality of p-type wells are configured to disperse an electric field on the gate-source ESD diode structure; and The plurality of n-type wells and the plurality of p-type wells and the gate-source ESD diode structure are separated by a dielectric layer.

5. The apparatus according to claim 4, wherein: A first p-type well of the plurality of p-type wells is formed in the epitaxial layer; A first n-type well of the plurality of n-type wells is formed in the first p-type well, and wherein the first n-type well is surrounded by the first p-type well; A second p-type well of the plurality of p-type wells is formed in the first n-type well, and wherein the second p-type well is surrounded by the first n-type well; and A second n-type well of the plurality of n-type wells is formed in the second p-type well, and wherein the second n-type well is surrounded by the second p-type well.

6. The apparatus according to claim 4, wherein: A first n-type well of the plurality of n-type wells is formed in the epitaxial layer; A first p-type well of the plurality of p-type wells is formed in the first n-type well, and wherein the width of the first p-type well is equal to the width of the first n-type well; and A second n-type well of the plurality of n-type wells is formed in the first p-type well, and wherein the width of the second n-type well is equal to the width of the first p-type well.

7. The apparatus according to claim 1, wherein: The breakdown voltage enhancement and leakage protection structure includes a RESURF structure and a body ring structure, and wherein: The RESURF structure and the body ring structure are configured to disperse an electric field on the gate-source ESD diode structure; The body ring structure is a concentric ring structure formed in the epitaxial layer; The RESURF structure and the gate-source ESD diode structure are separated by a dielectric layer; and The RESURF structure is located between the gate-source ESD diode structure and the body ring structure.

8. The device according to claim 1, wherein: The breakdown voltage enhancement and leakage protection structure includes a plurality of n-type wells, a plurality of p-type wells, and a body ring structure, and wherein: The plurality of n-type wells and the plurality of p-type wells are arranged in an alternating manner; The plurality of n-type wells, the plurality of p-type wells, and the body ring structure are configured to disperse the electric field on the gate-source ESD diode structure; The body ring structure is a concentric ring structure formed in the epitaxial layer; The plurality of n-type wells and the plurality of p-type wells are separated from the gate-source ESD diode structure by a dielectric layer; and The plurality of n-type wells and the plurality of p-type wells are located between the gate-source ESD diode structure and the body ring structure.

9. The device according to claim 1, wherein: The gate-source ESD diode structure includes a first p-type region, a first n+ region, a second p-type region, a second n+ region, and a third p-type region connected in cascade, and wherein: The first p-type region is connected to the gate contact; and The third p-type region is connected to the source contact.

10. The device according to claim 1, wherein: The plurality of gates include a first gate trench, a second gate trench, and a third gate trench; and The source includes a first source region and a second source region, and wherein: The first source region is located between the first gate trench and the second gate trench; and The second source region is located between the second gate trench and the third gate trench.

11. The device according to claim 10, further comprising: A first body region and a second body region, wherein the first body region is located between the first gate trench and the second gate trench, and the second body region is located between the second gate trench and the third gate trench; A first source contact plug having a first terminal connected to the source contact and a second terminal connected to the first source region and the first body region; A second source contact plug having a first terminal connected to the source contact and a second terminal connected to the second source region and the second body region; A gate contact plug having a first terminal connected to the gate contact and a second terminal connected to the first terminal of the gate-source ESD diode structure; A third source contact plug having a first terminal connected to the source contact and a second terminal connected to the second terminal of the gate-source ESD diode structure; And An interlayer dielectric layer formed above the epitaxial layer, wherein the gate-source ESD diode structure is located in the interlayer dielectric layer.

12. A method, comprising: Growing an epitaxial layer above a substrate; Forming a plurality of gates in the epitaxial layer; A body region and a breakdown voltage enhancement and leakage protection structure are formed in the epitaxial layer; A source is formed in the epitaxial layer and a gate-source ESD diode structure is formed above the epitaxial layer; and A source contact connected to the source and a first terminal of the gate-source ESD diode structure, and a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure are formed.

13. The method according to claim 12, wherein the step of forming the breakdown voltage enhancement and leakage protection structure in the epitaxial layer includes: Forming a RESURF structure by an implantation process, wherein the RESURF structure is located in an upper portion of the epitaxial layer, and the RESURF structure and the gate-source ESD diode structure are separated by a dielectric layer.

14. The method according to claim 12, wherein the step of forming the breakdown voltage enhancement and leakage protection structure in the epitaxial layer includes: Forming a body ring structure by an implantation process, wherein the body ring structure is a concentric ring structure, and the body ring structure and the gate-source ESD diode structure are separated by a dielectric layer.

15. The method according to claim 12, wherein the step of forming the breakdown voltage enhancement and leakage protection structure in the epitaxial layer includes: Forming a first p-type well in the epitaxial layer; Forming a first n-type well in the first p-type well, and wherein the first n-type well is surrounded by the first p-type well; Forming a second p-type well in the first n-type well, and wherein the second p-type well is surrounded by the first n-type well; and Forming a second n-type well in the second p-type well, and wherein the second n-type well is surrounded by the second p-type well.

16. The method according to claim 12, wherein the step of forming the breakdown voltage enhancement and leakage protection structure in the epitaxial layer includes: Forming a first n-type well in the epitaxial layer; Forming a first p-type well in the first n-type well, and wherein the width of the first p-type well is equal to the width of the first n-type well; and Forming a second n-type well in the first p-type well, and wherein the width of the second n-type well is equal to the width of the first p-type well.

17. The method according to claim 12, wherein the step of forming the gate-source ESD diode structure above the epitaxial layer includes: Forming a plurality of n-type regions and a plurality of p-type regions in an alternating manner in an interlayer dielectric layer above the epitaxial layer.

18. The method according to claim 12, which further includes: Forming an interlayer dielectric layer above the epitaxial layer; Forming a plurality of trenches in the interlayer dielectric layer; Forming a plurality of p+ regions at bottoms of corresponding trenches; Performing a metal deposition process to fill the plurality of trenches, thereby forming a plurality of source contact plugs and gate contact plugs; and Forming the source contact and the gate contact by an etching process.

19. A power MOSFET, which includes: An epitaxial layer located above a substrate; A plurality of gates formed in the epitaxial layer; A body region formed in the epitaxial layer; A source electrode, which is formed in the body region; A gate-source ESD diode structure, which is formed above the epitaxial layer; A body ring structure, which is formed in the epitaxial layer and located below the gate-source ESD diode structure; An interlayer dielectric layer, which is formed above the epitaxial layer, wherein the gate-source ESD diode structure is located in the interlayer dielectric layer; A plurality of source contact plugs, wherein at least one of the plurality of source contact plugs extends through the interlayer dielectric layer, the source electrode and partially through the body region; A gate contact plug, which partially extends through the interlayer dielectric layer; A gate contact, which is connected to the plurality of gates and the first terminal of the gate-source ESD diode structure through the gate contact plug; And A source contact, which is connected to the source electrode, the body region and the second terminal of the gate-source ESD diode structure through the plurality of source contact plugs.

20. The power MOSFET according to claim 19, wherein: The substrate is an n-type substrate; The epitaxial layer is an n-type layer; The body region is a p-type region; The source electrode is an n-type region; The body ring structure is a p-type body ring structure; The body ring structure is a concentric ring structure formed in the epitaxial layer; and The gate-source ESD diode structure includes a first p-type region, a first n+ region, a second p-type region, a second n+ region and a third p-type region connected in cascade, and wherein the first p-type region is connected to the gate contact, and the third p-type region is connected to the source contact.

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