Processor chip power consumption testing method and testing system

Abstract

The application discloses a processor chip power consumption test method and a test system, and belongs to the technical field of processor chips.The method comprises the following steps: collecting real-time test data of a processor chip and processing the real-time test data to determine processor chip characteristic test data; training a processor chip power consumption test prediction model, analyzing the processor chip characteristic test data, predicting the power consumption of the processor chip, and determining a processor chip power consumption prediction result; displaying the processor chip power consumption test situation in a visual form, and controlling and managing the processor chip, wherein a dynamic adjustment coefficient is used to adjust a set dynamic power consumption threshold.The application solves the problem that the existing method cannot comprehensively evaluate the power consumption characteristics of a processor chip, cannot effectively control and manage the processor chip, and leads to poor processor chip power consumption test effect.The application can comprehensively evaluate the power consumption characteristics of a processor chip, can effectively control and manage the processor chip, and can improve the processor chip power consumption test effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processor chips, in particular to a processor chip power consumption test method and test system. BACKGROUND

[0002] Processor chips, while achieving powerful processing functions, their power consumption is also one of the key factors in measuring the performance of processor chips, therefore, it is necessary to test the power consumption of processor chips.

[0003] A Chinese patent with publication number CN118070740A discloses a processor chip preparation method, processor chip, electronic device and medium, comprising: obtaining a first IP core according to a first chip layout preparation, the first IP core is used to provide the core function of the processor chip; obtaining a second IP core according to a second chip layout preparation, the second IP core is used to provide the auxiliary function of the processor chip; the layout difference between the first chip layout corresponding to different first IP cores is greater than the layout difference between the second chip layout corresponding to different second IP cores. According to the performance characteristics and functional requirements of different IP cores, the corresponding chip layout is laid out, so that the layout difference between the first chip layout corresponding to different first IP cores is greater than the layout difference between the second chip layout corresponding to different second IP cores, which can avoid changing the chip layout at all levels, thereby reducing the manufacturing cost of the chip layout while ensuring the performance of the chip, to obtain a processor chip product that meets the application requirements; however, the patent has the following defects:

[0004] The existing technology cannot comprehensively evaluate the power consumption characteristics of the processor chip, and cannot effectively control the processor chip, resulting in poor processor chip power consumption test effect. SUMMARY

[0005] The purpose of the present application is to provide a processor chip power consumption test method and test system, which can comprehensively evaluate the power consumption characteristics of the processor chip, and can effectively control the processor chip, can improve the processor chip power consumption test effect, and solve the problems raised in the above background technology.

[0006] To achieve the above purpose, the present application provides the following technical solutions:

[0007] The processor chip power consumption test method comprises:

[0008] Collecting and processing real-time test data of the processor chip to determine processor chip feature test data;

[0009] Training a processor chip power consumption test prediction model, analyzing the processor chip feature test data, predicting the power consumption of the processor chip, and determining the processor chip power consumption prediction result;

[0010] The processor chip power consumption test situation is displayed in a visual form, and the processor chip is controlled;

[0011] The dynamic power consumption threshold is adjusted by using a dynamic adjustment coefficient.

[0012] Preferably, the real-time test data of the processor chip is collected, including:

[0013] The current and voltage of the processor chip in an idle state are monitored and collected in real time to obtain static test data of the processor chip.

[0014] The current and voltage of the processor chip under different loads are monitored and collected in real time to obtain dynamic test data of the processor chip.

[0015] The real-time test data of the processor chip is determined according to the static test data and the dynamic test data of the processor chip.

[0016] Preferably, the real-time test data of the processor chip is processed, including:

[0017] The real-time test data of the processor chip is cleaned, the integrity of the real-time test data of the processor chip is checked, and repeated values, missing values and abnormal values in the real-time test data of the processor chip are identified.

[0018] For repeated values in the real-time test data of the processor chip, the repeated values are removed, and only unique data records are retained.

[0019] For missing values in the real-time test data of the processor chip that are tested to be useless for processor chip power consumption testing, the missing values are removed; for missing values in the real-time test data of the processor chip that are tested to be useful for processor chip power consumption testing, the missing values are filled.

[0020] For abnormal values in the real-time test data of the processor chip that are tested to be useless for processor chip power consumption testing, the abnormal values are removed; for abnormal values in the real-time test data of the processor chip that are tested to be useful for processor chip power consumption testing, the abnormal values are replaced or corrected.

[0021] The filtered real-time test data of the processor chip is filtered based on a filtering algorithm to remove noise in the real-time test data of the processor chip, for reducing noise interference.

[0022] Preferably, the real-time test data of the processor chip is processed, further including:

[0023] The real-time test data of the processor chip is normalized to reduce the dimension difference of the real-time test data of the processor chip, and standardized real-time test data of the processor chip is determined.

[0024] The processor chip real-time test data is subjected to feature extraction, and features related to processor chip power consumption test are extracted from the processor chip real-time test data to determine processor chip feature test data.

[0025] Preferably, the processor chip power consumption test prediction model is trained, including:

[0026] The processor chip historical test data is collected, including historical current, voltage and power consumption;

[0027] The collected processor chip historical test data is divided to determine a training set and a test set;

[0028] Based on deep learning technology, the training set is used to train a deep learning model, so that the deep learning model autonomously learns processor chip power consumption test prediction behavior and predicts processor chip power consumption to determine a deep learning-based processor chip power consumption test prediction model;

[0029] The deep learning-based processor chip power consumption test prediction model is subjected to performance testing based on the test set to evaluate whether the deep learning-based processor chip power consumption test prediction model can achieve the expected effect;

[0030] When the deep learning-based processor chip power consumption test prediction model cannot achieve the expected effect, the parameters of the deep learning-based processor chip power consumption test prediction model are adjusted, and the deep learning-based processor chip power consumption test prediction model is continuously optimized until a processor chip power consumption test prediction model that can achieve the expected effect is determined.

[0031] Preferably, the processor chip feature test data is analyzed, including:

[0032] The processor chip power consumption test prediction model is obtained and deployed in an actual processor chip power consumption test prediction environment;

[0033] The processor chip feature test data is input into the processor chip power consumption test prediction model, the processor chip feature test data is analyzed according to the processor chip power consumption test prediction model, and the processor chip power consumption is predicted to determine a processor chip power consumption prediction result.

[0034] Preferably, the processor chip power consumption test situation is displayed in a visual form, and the processor chip is controlled, including:

[0035] According to the processor chip power consumption prediction result and in combination with the processor chip feature test data, a processor chip power consumption test report is formed, and the processor chip power consumption test report is displayed to the management personnel in a visual form;

[0036] The manager evaluates the power consumption performance of the processor chip according to the processor chip power consumption test report, and obtains a power consumption performance coefficient by combining the set dynamic power consumption threshold value, and outputs the power consumption performance coefficient as the power consumption performance evaluation result;

[0037] Intelligent management and control is performed on the processor chip according to the power consumption performance evaluation result, wherein the voltage and frequency of the processor chip are dynamically adjusted to reduce power consumption, and an upper limit of power consumption is set to enable the processor chip to operate within a budget, in a multi-core processor, tasks are distributed to the core with the highest energy efficiency to balance the load.

[0038] Preferably, it further comprises:

[0039] Periodically obtaining historical working temperature data, historical working condition data and historical load data of the processor chip within a preset time period;

[0040] According to the historical working temperature data, the historical working temperature extreme value and the historical working temperature average value of the processor chip are determined, and a temperature reference value is calculated;

[0041] The first temperature reference value of the processor chip in the current preset time period and the second temperature reference value of the last preset time period are analyzed, and a temperature change reference coefficient is obtained;

[0042] The historical working condition data and the historical load data are used to establish the working condition change curve and the load change curve of the processor chip within the current preset time period in time sequence;

[0043] After the working condition change curve and the load change curve of the processor chip within the current preset time period are divided in proportion, the first working condition sub-curve and the first load sub-curve are obtained, and the curve acquisition order of the first working condition sub-curve and the first load sub-curve is marked;

[0044] The sub-curves obtained by dividing the working condition change curve and the load change curve of the processor chip within the last preset time period in proportion are respectively marked as the second working condition sub-curve and the second load sub-curve, and the curve acquisition order of the second working condition sub-curve and the second load sub-curve is marked;

[0045] Using a set similarity algorithm, the first working condition sub-curve and the second working condition sub-curve of the same curve acquisition order are analyzed, and the target first working condition sub-curve and the target second working condition sub-curve with a similarity representation coefficient greater than a set similarity threshold value are marked as the first analysis condition sub-curve and the second analysis condition sub-curve;

[0046] The condition reference values of the first analysis condition sub-curve and the second analysis condition sub-curve of the same curve acquisition order are obtained, and a condition difference value is obtained by difference comparison.

[0047] The first load sub-curve and the second load sub-curve of the same curve acquisition sequence are subjected to similarity analysis, and the first load sub-curve and the second load sub-curve with a similarity representation coefficient greater than a set similarity threshold are marked as a first analysis load sub-curve and a second analysis load sub-curve;

[0048] The load reference values of the target first analysis load sub-curve and the target second analysis load sub-curve of the same curve acquisition sequence are obtained respectively, and a load difference value is obtained through difference comparison;

[0049] The condition difference value and the similarity representation coefficient of the first analysis condition sub-curve and the second analysis condition sub-curve of the same curve acquisition sequence, and the load difference value and the similarity representation coefficient of the first analysis load sub-curve and the second analysis load sub-curve, are combined with a temperature change reference coefficient to calculate a dynamic adjustment coefficient;

[0050] The dynamic adjustment coefficient is used to adjust a set dynamic power consumption threshold.

[0051] According to another aspect of the present application, a processor chip power consumption test system is provided for implementing the processor chip power consumption test method as described above, comprising:

[0052] A data acquisition module configured to acquire real-time test data of the processor chip;

[0053] A data processing module configured to process the acquired real-time test data of the processor chip to determine characteristic test data of the processor chip;

[0054] A model construction module configured to construct a processor chip power consumption test prediction model according to processor chip power consumption test requirements;

[0055] A power consumption prediction module configured to analyze the characteristic test data of the processor chip according to the processor chip power consumption test prediction model and predict the power consumption of the processor chip;

[0056] A display and control module configured to visually display the processor chip power consumption test situation and control the processor chip according to the displayed processor chip power consumption test situation.

[0057] Compared with the prior art, the present application has the following advantages:

[0058] The application determines the real-time test data of the processor chip by collecting the static test data and the dynamic test data of the processor chip, determines the characteristic test data of the processor chip by processing the real-time test data of the processor chip, constructs a power consumption test prediction model of the processor chip according to the power consumption test requirement of the processor chip, analyzes the characteristic test data of the processor chip based on the power consumption test prediction model of the processor chip, predicts the power consumption of the processor chip, determines the power consumption prediction result of the processor chip, and displays the power consumption test situation of the processor chip in a visual form, and effectively controls the processor chip, which can comprehensively evaluate the power consumption characteristics of the processor chip and effectively control the processor chip, and can improve the power consumption test effect of the processor chip. BRIEF DESCRIPTION OF DRAWINGS

[0059] Fig. 1 The flowchart of the processor chip power consumption test method of the application is shown in the figure.

[0060] Fig. 2 The module diagram of the processor chip power consumption test system of the application is shown in the figure. DETAILED DESCRIPTION

[0061] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the application.

[0062] To solve the problem that the existing method cannot comprehensively evaluate the power consumption characteristics of the processor chip and cannot effectively control the processor chip, resulting in poor power consumption test effect of the processor chip, please refer to Figs. 1-2 The technical solutions of the embodiments are as follows.

[0063] The processor chip power consumption test system comprises a data collection module, a data processing module, a model construction module, a power consumption prediction module and a display and control module.

[0064] Specifically, the real-time test data of the processor chip is collected by the data collection module.

[0065] Specifically, the real-time test data of the processor chip collected is processed by the data processing module to determine the characteristic test data of the processor chip.

[0066] Specifically, the power consumption test prediction model of the processor chip is constructed by the model construction module.

[0067] Specifically, the characteristic test data of the processor chip is analyzed by the power consumption prediction module, and the power consumption of the processor chip is predicted.

[0068] Specifically, the processor chip power consumption test situation is visualized and displayed by the display and control module, and the processor chip is controlled according to the displayed processor chip power consumption test situation.

[0069] It should be noted that through the interaction and communication among the data acquisition module, the data processing module, the model construction module, the power consumption prediction module and the display and control module, the power consumption characteristics of the processor chip can be comprehensively evaluated, and the processor chip can be effectively controlled, thereby improving the processor chip power consumption test effect. By measuring the power consumption of the processor chip under different workloads, the energy consumption level of the processor chip in the normal running state can be understood.

[0070] In order to better show the processor chip power consumption test process, the present embodiment provides a processor chip power consumption test method, which is realized based on the above-mentioned processor chip power consumption test system, comprising:

[0071] Collecting real-time test data of the processor chip;

[0072] In the present embodiment, collecting real-time test data of the processor chip comprises:

[0073] Real-time monitoring and collecting the current and voltage of the processor chip in the idle state to obtain static test data of the processor chip;

[0074] Real-time monitoring and collecting the current and voltage of the processor chip under different loads to obtain dynamic test data of the processor chip;

[0075] Among them, according to the static test data and the dynamic test data of the processor chip, the real-time test data of the processor chip is determined.

[0076] It should be noted that by real-time monitoring and collecting the current and voltage of the processor chip in the idle state to obtain the static test data of the processor chip, and by real-time monitoring and collecting the current and voltage of the processor chip under different loads to obtain the dynamic test data of the processor chip, and by collecting the static test data and the dynamic test data of the processor chip, the real-time test data of the processor chip is determined, which can facilitate subsequent comprehensive evaluation of the power consumption characteristics of the processor chip.

[0077] Processing the real-time test data of the processor chip to determine the characteristic test data of the processor chip;

[0078] In the present embodiment, processing the real-time test data of the processor chip comprises:

[0079] Cleaning the real-time test data of the processor chip, checking the integrity of the real-time test data of the processor chip, and identifying repeated values, missing values and abnormal values in the real-time test data of the processor chip;

[0080] For repeated values in the real-time test data of the processor chip, the repeated values are removed, and unique data records are retained;

[0081] For missing values in the real-time test data of the processor chip that are tested to be useless for the processor chip power consumption test, the missing values are removed; for missing values in the real-time test data of the processor chip that are tested to be useful for the processor chip power consumption test, the missing values are filled in;

[0082] For abnormal values in the real-time test data of the processor chip that are tested to be useless for the processor chip power consumption test, the abnormal values are removed; for abnormal values in the real-time test data of the processor chip that are tested to be useful for the processor chip power consumption test, the abnormal values are replaced or corrected;

[0083] The filtered real-time test data of the processor chip is filtered based on a filtering algorithm to remove noise in the real-time test data of the processor chip, for reducing noise interference.

[0084] It should be noted that, by cleaning and filtering the real-time test data of the processor chip, noise in the real-time test data of the processor chip and repeated values, missing values and abnormal values that are useless for the processor chip power consumption test can be removed, the processing speed and accuracy of the subsequent real-time test data of the processor chip can be improved, and the data quality can be improved.

[0085] In this embodiment, the real-time test data of the processor chip is processed, and the processing further includes:

[0086] The real-time test data of the processor chip is normalized to reduce the dimension difference of the real-time test data of the processor chip, and standardized real-time test data of the processor chip is determined;

[0087] The real-time test data of the processor chip is feature extracted to extract features related to the processor chip power consumption test from the real-time test data of the processor chip, and processor chip feature test data is determined.

[0088] It should be noted that, by normalizing and feature extracting the real-time test data of the processor chip, the processor chip feature test data can be determined, which facilitates subsequent analysis of the processor chip feature test data and prediction of the processor chip power consumption.

[0089] A processor chip power consumption test prediction model is trained;

[0090] In this embodiment, the processor chip power consumption test prediction model is trained, and the training includes:

[0091] Historical test data of the processor chip is collected, including historical current, voltage and power consumption;

[0092] The collected processor chip historical test data is divided to determine a training set and a test set;

[0093] Based on deep learning technology, the training set is used to train a deep learning model, so that the deep learning model autonomously learns the processor chip power consumption test prediction behavior and predicts the processor chip power consumption to determine a deep learning-based processor chip power consumption test prediction model;

[0094] The deep learning-based processor chip power consumption test prediction model is tested based on the test set to evaluate whether the deep learning-based processor chip power consumption test prediction model can achieve the expected effect;

[0095] When the deep learning-based processor chip power consumption test prediction model cannot achieve the expected effect, the parameters of the deep learning-based processor chip power consumption test prediction model are adjusted, and the deep learning-based processor chip power consumption test prediction model is continuously optimized until a processor chip power consumption test prediction model that can achieve the expected effect is determined.

[0096] The processor chip feature test data is analyzed to predict the processor chip power consumption and determine the processor chip power consumption prediction result;

[0097] In this embodiment, the analysis of the processor chip feature test data includes:

[0098] The processor chip power consumption test prediction model is obtained and deployed in an actual processor chip power consumption test prediction environment;

[0099] The processor chip feature test data is input into the processor chip power consumption test prediction model, the processor chip feature test data is analyzed according to the processor chip power consumption test prediction model, and the processor chip power consumption is predicted to determine the processor chip power consumption prediction result.

[0100] It should be noted that the processor chip feature test data is analyzed by the processor chip power consumption test prediction model, and the processor chip power consumption is predicted to determine the processor chip power consumption prediction result, which facilitates comprehensive evaluation of the power consumption characteristics of the processor chip.

[0101] The processor chip power consumption test situation is displayed in a visual form, and the processor chip is controlled.

[0102] In this embodiment, the processor chip power consumption test situation is displayed in a visual form, and the processor chip is controlled, including:

[0103] According to the processor chip power consumption prediction result and in combination with the processor chip characteristic test data, a processor chip power consumption test report is formed, and the processor chip power consumption test report is displayed to the manager in a visual form;

[0104] The manager evaluates the power consumption performance of the processor chip according to the processor chip power consumption test report, and obtains a power consumption performance coefficient by combining the set dynamic power consumption threshold value, and outputs the power consumption performance coefficient as the power consumption performance evaluation result;

[0105] According to the power consumption performance evaluation result, the processor chip is intelligently controlled, wherein the voltage and frequency of the processor chip are dynamically adjusted to reduce power consumption, and an upper limit of power consumption is set to enable the processor chip to operate within the budget, and in a multi-core processor, tasks are distributed to the core with the highest energy efficiency to balance the load.

[0106] In the embodiment, the calculation formula of the power consumption performance coefficient is as follows:

[0107]

[0108] In the formula, P represents the power consumption performance coefficient; x1 represents the processor chip power consumption prediction result; x0 represents the set dynamic power consumption threshold value; ω1 represents the influence weight of the power consumption prediction result compliance condition on the analysis of the power consumption performance of the processor chip, and the value range is (0, 1); x i represents the actual power consumption of the processor chip at the i-th moment, wherein i = 1, 2, 3; Δt i represents the time interval between the i-th moment and the corresponding prediction moment of the processor chip power consumption prediction result; ω2 represents the influence weight of the difference degree between the past actual power consumption and the predicted power consumption of the processor chip on the analysis of the power consumption performance of the processor chip, and the value range is (0, 1); ω1+ω2=1; e represents a constant, and the value is 2.7.

[0109] In the embodiment, the weights ω1 and ω2 given to the power consumption prediction result compliance condition and the difference degree between the past actual power consumption and the predicted power consumption are obtained by solving the matrix constructed after the two-by-two comparison and scoring by using the analytic hierarchy process.

[0110] In the embodiment, for example, there is a corresponding prediction moment 1 of the processor chip power consumption prediction result 1, and the time interval between the current moment and the corresponding prediction moment 1 is 20s;

[0111] At this time, the first moment is the current moment, the second moment is the past moment with a time interval of 20s from the current moment, and the third moment is the past moment with a time interval of 20s from the second moment.

[0112] In the embodiment, the dynamic power consumption threshold refers to a standard for measuring whether the power consumption prediction result of the processor chip meets the standard.

[0113] The technical scheme has the beneficial effects that the power consumption performance coefficient is calculated by quantifying the power consumption performance of the processor chip, thereby providing a direct and comparable evaluation index for the management personnel, which can help the management personnel quickly understand the current power consumption status of the chip and provide scientific data basis for subsequent intelligent management and control, thereby realizing effective management of the power consumption of the processor chip.

[0114] In the embodiment, the method further comprises:

[0115] Periodically acquiring historical working temperature data, historical working condition data and historical load data of the processor chip in a preset time period;

[0116] According to the historical working temperature data, determining a historical working temperature extreme value and a historical working temperature average value of the processor chip, and calculating a temperature reference value;

[0117] Differentially analyzing a first temperature reference value of the processor chip in a current preset time period and a second temperature reference value of the processor chip in a previous preset time period, to obtain a temperature change reference coefficient;

[0118] Using the historical working condition data and the historical load data to respectively establish, in time sequence, a working condition change curve and a load change curve of the processor chip in the current preset time period;

[0119] After the working condition change curve and the load change curve of the processor chip in the current preset time period are divided in equal proportions, a first working condition sub-curve and a first load sub-curve are obtained, and the first working condition sub-curve and the first load sub-curve are marked with a curve acquisition order;

[0120] After the working condition change curve and the load change curve of the processor chip in the previous preset time period are divided in equal proportions, a second working condition sub-curve and a second load sub-curve are obtained, and the second working condition sub-curve and the second load sub-curve are marked with a curve acquisition order;

[0121] Using a set similarity algorithm, the first working condition sub-curve and the second working condition sub-curve of the same curve acquisition order are subjected to similarity analysis, and target first working condition sub-curves and target second working condition sub-curves with a similarity representation coefficient greater than a set similarity threshold are marked as a first analysis condition sub-curve and a second analysis condition sub-curve;

[0122] Condition reference values of the first analysis condition sub-curve and the second analysis condition sub-curve of the same curve acquisition order are respectively obtained, and a condition difference value is obtained through difference comparison;

[0123] The first load sub-curve and the second load sub-curve of the same curve acquisition sequence are subjected to similarity analysis, and the first load sub-curve and the second load sub-curve with a similarity representation coefficient greater than a set similarity threshold are marked as a first analysis load sub-curve and a second analysis load sub-curve;

[0124] The load reference values of the target first analysis load sub-curve and the target second analysis load sub-curve of the same curve acquisition sequence are obtained respectively, and a load difference value is obtained through difference comparison;

[0125] The condition difference value and the similarity representation coefficient of the first analysis condition sub-curve and the second analysis condition sub-curve of the same curve acquisition sequence, and the load difference value and the similarity representation coefficient of the first analysis load sub-curve and the second analysis load sub-curve, are combined with a temperature change reference coefficient to calculate a dynamic adjustment coefficient;

[0126] The set dynamic power consumption threshold is adjusted by using the dynamic adjustment coefficient.

[0127] In the embodiment, the preset time period refers to a time range set in advance for collecting historical working temperature, historical working condition and historical load; the historical working condition data refers to historical voltage data, historical current data and historical frequency data; the historical working temperature data refers to temperature records of the processor chip in the past preset time period; and the historical load data refers to load records of the processor chip in the past preset time period, such as the number of tasks.

[0128] In the embodiment, the historical working temperature extreme value refers to the maximum working temperature and the minimum working temperature in the historical working temperature data; and the temperature reference value refers to a value for representing the average temperature level of the processor chip in a certain time period, and the calculation formula is represented as: In the formula, b1 represents the temperature reference value of the current preset time period; y avg represents the average working temperature in the current preset time period; y max represents the maximum working temperature in the current preset time period; y min represents the minimum working temperature in the current preset time period.

[0129] In the embodiment, the first temperature reference value refers to the temperature reference value of the current preset time period; and the second temperature reference value refers to the temperature reference value of the previous preset time period.

[0130] In the embodiment, the temperature change reference coefficient is obtained by subtracting the second temperature reference value from the first temperature reference value, and then dividing the difference by the first temperature reference value.

[0131] In the embodiment, the working condition refers to voltage, current and frequency; the working condition change curve is a curve for indicating the change of the working condition of the processor chip with time, which is established according to historical working condition data in time sequence, and specifically refers to a voltage change curve, a current change curve or a frequency change curve; the load change curve refers to a curve for indicating the change of the load of the processor chip with time, which is established according to historical load data in time sequence.

[0132] In the embodiment, the first working condition sub-curve is a smaller curve segment obtained by equally dividing the corresponding working condition change curve of the current preset time period; the first load sub-curve is a smaller curve segment obtained by equally dividing the corresponding load change curve of the current preset time period.

[0133] In the embodiment, the second working condition sub-curve is a smaller curve segment obtained by equally dividing the corresponding working condition change curve of the previous preset time period; the second load sub-curve is a smaller curve segment obtained by equally dividing the corresponding load change curve of the previous preset time period.

[0134] In the embodiment, the curve acquisition sequence refers to the arrangement sequence of the sub-curves on the time axis after equally dividing the working condition change curve or the load change curve of the processor chip.

[0135] In the embodiment, the similarity algorithm is used to quantify the similarity between curves, and generally refers to a dynamic time warping algorithm; the similarity representation coefficient is a value obtained by normalizing the value obtained by using the similarity algorithm, and is used to represent the similarity between curves, and the value range is between 0 and 1, and the smaller the similarity representation coefficient is, the higher the similarity between curves is; the similarity threshold is pre-set, and generally is 0.25.

[0136] In the embodiment, for example, the similarity representation coefficient between the first working condition sub-curve L1 and the second working condition sub-curve L2 under the same curve acquisition sequence is 0.35, which is greater than the similarity threshold 0.25;

[0137] At this time, the first working condition sub-curve L1 is marked as the first analysis condition sub-curve, and the second working condition sub-curve L2 is marked as the second analysis condition sub-curve.

[0138] In the embodiment, for example, the similarity representation coefficient between the first load sub-curve L3 and the second load sub-curve L4 under the same curve acquisition sequence is 0.15, which is less than the similarity threshold 0.25;

[0139] At this time, the first load sub-curve L3 is not marked as the first analysis load sub-curve, and the second load sub-curve L4 is not marked as the second analysis load sub-curve.

[0140] In the present embodiment, the condition reference value is represented as In the present embodiment, the condition reference value is represented as avg In the present embodiment, the condition reference value is represented as max In the present embodiment, the condition reference value is represented as min In the present embodiment, the condition reference value is represented as

[0141] In the present embodiment, the load reference value is represented as In the present embodiment, the load reference value is represented as avg In the present embodiment, the load reference value is represented as max In the present embodiment, the load reference value is represented as min In the present embodiment, the load reference value is represented as

[0142] In the present embodiment, the dynamic adjustment coefficient is calculated according to the following formula:

[0143]

[0144] In the present embodiment, the dynamic adjustment coefficient is calculated according to the following formula: j In the present embodiment, the condition reference value is represented as j In the present embodiment, the condition reference value is represented as max In the present embodiment, the condition reference value is represented as ja curve time starting point of the corresponding first analysis condition sub-curve or second analysis condition sub-curve representing the jth condition difference value of the current working condition, a time interval from the current time; γ 3 represents an influence weight of the load change condition on the calculation of the dynamic adjustment coefficient, and the value range is (0, 1); γ 1 + γ 2 + γ 3 = 1; wr represents the rth load difference value, wherein r = 1, 2, …, q; q represents the total number of the obtained load difference values; a r a similarity representation coefficient of the corresponding first analysis load sub-curve and second analysis load sub-curve representing the rth condition difference value; a max a maximum value in the similarity representation coefficients of the corresponding first analysis load sub-curve and second analysis load sub-curve representing the same curve acquisition sequence of all the load difference values; Δ o r a curve time starting point of the corresponding first analysis load sub-curve or second analysis load sub-curve representing the rth load difference value, a time interval from the current time; e represents a constant, and the value is 2.7.

[0145] In the embodiment, the weights of the temperature change condition, the working condition change condition and the load change condition, i.e. γ 1, γ 2 and γ 3, are obtained by solving a matrix constructed after two-by-two comparison and relative importance scoring by using the analytic hierarchy process.

[0146] In the embodiment, for example, there is a set dynamic power consumption threshold u 0, the set dynamic power consumption threshold u 0 is adjusted by using the dynamic adjustment coefficient s 1, and a dynamic power consumption threshold u 1 is obtained. In the formula, u 1 represents the adjusted set dynamic power consumption threshold u 0; e represents a constant, and the value is 2.7.

[0147] The beneficial effects of the above technical solution are as follows: the temperature change reference coefficient, the condition difference value and the load difference value are obtained by deeply analyzing the historical working temperature, working condition and load data of the processor chip obtained periodically; then the intelligent adjustment of the set dynamic power consumption threshold is realized based on the obtained temperature change reference coefficient, condition difference value and load difference value, which can provide an effective basis for accurately obtaining the power consumption performance coefficient, improve the accuracy of power consumption performance evaluation, and further provide strong support for subsequent intelligent management and control, so as to ensure the stable operation of the processor chip in a complex and changeable working environment.

[0148] The working principle of the above technical solution is that: first, the historical data of the processor chip is collected, including temperature, working condition and load, then the historical working temperature data collected is analyzed to obtain a temperature reference value and a temperature change reference coefficient for representing the temperature change; the working condition and load change curve established by the historical working condition data and the historical load data is proportionally divided, and the similarity representation coefficient comparison and difference analysis of the sub-curves are performed; the condition difference value and the load difference value are determined through the difference analysis result; finally, the condition difference value and the load difference value are combined with the temperature change reference coefficient to calculate a dynamic adjustment coefficient to adjust the set dynamic power consumption threshold.

[0149] In summary, by collecting the static test data and the dynamic test data of the processor chip, the real-time test data of the processor chip is determined, the processor chip feature test data is determined by processing the real-time test data of the processor chip, the processor chip power consumption test prediction model is constructed according to the power consumption test requirements of the processor chip, the processor chip feature test data is analyzed based on the processor chip power consumption test prediction model, the power consumption of the processor chip is predicted, the power consumption prediction result of the processor chip is determined, and the power consumption test situation of the processor chip is displayed in a visual form. The processor chip can be effectively controlled, the power consumption characteristics of the processor chip can be comprehensively evaluated, and the processor chip power consumption test effect can be improved.

[0150] It should be noted that, in this document, the terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device.

[0151] Although the embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions and variations can be made to the embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A method of testing power consumption of a processor chip, characterized by, Comprise: The acquisition processor chip real-time test data and processing, determine the processor chip characteristic test data; Train processor chip power consumption test prediction model, analyze the processor chip characteristic test data, predict the power consumption of processor chip, determine the processor chip power consumption prediction result; In the form of visualization display processor chip power consumption test situation, and control of processor chip, including: According to the processor chip power consumption prediction result and combining the processor chip characteristic test data, form the processor chip power consumption test report, and show the processor chip power consumption test report to the management personnel in the form of visualization; Management personnel according to the processor chip power consumption test report evaluation processor chip power consumption performance, and through the combination of set dynamic power threshold get power consumption performance coefficient, the power consumption performance coefficient as the power consumption performance evaluation result output; According to the power consumption performance evaluation result of intelligent control of processor chip, wherein, dynamically adjust the voltage and frequency of processor chip, for reducing power consumption, and set the upper limit of power consumption, make the processor chip run within the budget, in multicore processor, the task is allocated to the core with the highest energy efficiency, make load balancing; Also include: Periodically obtain the historical working temperature data, historical working condition data and historical load data of the processor chip in the preset time period; According to the historical working temperature data, determine the historical working temperature extreme value and the historical working temperature average value of the processor chip, and calculate the temperature reference value; The first temperature reference value of the processor chip in the current preset time period and the second temperature reference value of the last preset time period are analyzed, and the temperature change reference coefficient is obtained; The working condition change curve and the load change curve of the processor chip in the current preset time period are established in time sequence respectively by using the historical working condition data and the historical load data; The working condition change curve and the load change curve of the processor chip in the current preset time period are divided in proportion respectively, and the first working condition sub curve and the first load sub curve are obtained, and the curve acquisition order of the first working condition sub curve and the first load sub curve is labeled; The working condition change curve and the load change curve of the processor chip in the last preset time period are divided in proportion respectively, and the sub curve is obtained, and the second working condition sub curve and the second load sub curve are labeled respectively, and the curve acquisition order of the second working condition sub curve and the second load sub curve is labeled; Using the set similarity algorithm, the first working condition sub curve and the second working condition sub curve of the same curve acquisition order are analyzed, and the target first working condition sub curve and the target second working condition sub curve with the similarity representation coefficient greater than the set similarity threshold are marked as the first analysis condition sub curve and the second analysis condition sub curve; The condition reference value of the first analysis condition sub curve and the second analysis condition sub curve of the same curve acquisition order is obtained respectively, and the condition difference value is obtained by difference comparison; The first load sub-curve and the second load sub-curve of the same curve acquisition sequence are subjected to similarity analysis, and the first load sub-curve and the second load sub-curve with a similarity representation coefficient greater than a set similarity threshold are marked as a first analysis load sub-curve and a second analysis load sub-curve; The load reference values of the target first analysis load sub-curve and the target second analysis load sub-curve of the same curve acquisition sequence are acquired respectively, and a load difference value is obtained through difference comparison; The condition difference value and the similarity representation coefficient of the first analysis condition sub-curve and the second analysis condition sub-curve of the same curve acquisition sequence, and the load difference value and the similarity representation coefficient of the first analysis load sub-curve and the second analysis load sub-curve are combined with a temperature change reference coefficient to calculate a dynamic adjustment coefficient; The set dynamic power consumption threshold is adjusted by using the dynamic adjustment coefficient.

2. The processor chip power consumption test method of claim 1, wherein, The real-time test data of the processor chip is collected, including: The current and voltage of the processor chip in an idle state are monitored and collected in real time to obtain static test data of the processor chip; The current and voltage of the processor chip under different loads are monitored and collected in real time to obtain dynamic test data of the processor chip; The real-time test data of the processor chip is determined according to the static test data and the dynamic test data of the processor chip.

3. The processor chip power consumption testing method of claim 1, wherein, The real-time test data of the processor chip is processed, including: The real-time test data of the processor chip is cleaned, the integrity of the real-time test data of the processor chip is checked, and repeated values, missing values and abnormal values in the real-time test data of the processor chip are identified; For repeated values in the real-time test data of the processor chip, the repeated values are removed and only unique data records are retained; For missing values in the real-time test data of the processor chip that are tested to be useless for processor chip power consumption testing, the missing values are removed; for missing values in the real-time test data of the processor chip that are tested to be useful for processor chip power consumption testing, the missing values are filled; For abnormal values in the real-time test data of the processor chip that are tested to be useless for processor chip power consumption testing, the abnormal values are removed; for abnormal values in the real-time test data of the processor chip that are tested to be useful for processor chip power consumption testing, the abnormal values are replaced or corrected; The filtered real-time test data of the processor chip is filtered based on a filtering algorithm to remove noise in the real-time test data of the processor chip.

4. The processor chip power consumption test method of claim 3, wherein, The real-time test data of the processor chip is processed, further including: The real-time test data of the processor chip is normalized to reduce the dimension difference of the real-time test data of the processor chip, and standardized real-time test data of the processor chip is determined; The real-time test data of the processor chip is feature extracted to extract features related to processor chip power consumption testing from the real-time test data of the processor chip, and processor chip feature test data is determined.

5. The processor chip power dissipation testing method of claim 1, wherein, The processor chip power consumption test prediction model is trained, including: Historical test data of the processor chip is collected, including historical current, voltage and power consumption; The collected historical test data of the processor chip is divided to determine a training set and a test set; Based on the deep learning technology, the training set is used to train the deep learning model, so that the deep learning model can learn the processor chip power consumption test prediction behavior independently, and predict the processor chip power consumption, and determine the deep learning-based processor chip power consumption test prediction model; Based on the test set, the performance of the deep learning-based processor chip power consumption test prediction model is tested, and whether the deep learning-based processor chip power consumption test prediction model can achieve the expected effect is evaluated; When the deep learning-based processor chip power consumption test prediction model cannot achieve the expected effect, the parameters of the deep learning-based processor chip power consumption test prediction model are adjusted, and the deep learning-based processor chip power consumption test prediction model is continuously optimized until the processor chip power consumption test prediction model that can achieve the expected effect is determined.

6. The processor chip power dissipation testing method of claim 5, wherein, The processor chip feature test data is analyzed, including: Obtaining the processor chip power consumption test prediction model and deploying the processor chip power consumption test prediction model in the actual processor chip power consumption test prediction environment; The processor chip feature test data is input into the processor chip power consumption test prediction model, the processor chip feature test data is analyzed according to the processor chip power consumption test prediction model, and the processor chip power consumption is predicted to determine the processor chip power consumption prediction result.

7. A processor chip power consumption test system for implementing the processor chip power consumption test method according to any one of claims 1-6, characterized by, Including: The data acquisition module is configured to collect real-time test data of the processor chip; The data processing module is configured to process the collected real-time test data of the processor chip to determine the processor chip feature test data; The model construction module is configured to construct the processor chip power consumption test prediction model according to the processor chip power consumption test requirement; The power consumption prediction module is configured to analyze the processor chip feature test data according to the processor chip power consumption test prediction model, and predict the processor chip power consumption; The display control module is configured to visually display the processor chip power consumption test situation, and control the processor chip according to the displayed processor chip power consumption test situation.

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