Method for cleaning SOI (Silicon On Insulator) substrate

Abstract

The invention provides a method for cleaning an SOI substrate, and the method comprises the steps: providing a supporting substrate and a device substrate which comprises a stripping layer; bonding the supporting substrate and the device substrate; stripping the device substrate from the stripping layer; and carrying out ultrasonic cleaning on the stripped surface, wherein the ultrasonic frequency is 5-25 KHz. The surface appearance after injection and stripping is special, and the density of dangling bonds is larger than that of a common silicon substrate surface, so that the cleaning frequency of 25kHz-1MHz does not reduce the surface defects, but increases the surface defects. According to the technical scheme, the ultrasonic frequency is reduced to 5-25 kHz, and the surface defects can be obviously reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor processes, and particularly to a method for cleaning an SOI substrate. Background Art

[0002] In the semiconductor manufacturing process, wafer cleaning is a crucial step. With its unique advantages, ultrasonic cleaning technology plays an important role in removing contaminants on the wafer surface.

[0003] Ultrasonic cleaning generates cavitation effects in liquids based on high-frequency vibrations (20 kHz - 1 MHz). The change in acoustic pressure causes tiny bubbles in the liquid to rapidly expand and burst, releasing a powerful shock wave to peel off the dirt on the wafer surface. Under the action of ultrasonic waves, sparse and dense parts are formed inside the liquid medium. Near-vacuum cavity bubbles are generated in the sparse part. When the cavity bubbles disappear, a powerful local pressure is generated nearby, promoting the desorption of impurities on the wafer surface. When the ultrasonic frequency reaches resonance with the vibration frequency of the cavity bubbles, the mechanical force reaches its maximum, a large amount of heat energy accumulates in the bubbles, the temperature rises, and further promotes chemical reactions to assist the cleaning process.

[0004] When manufacturing an SOI wafer using the bonding - peeling method, since there are many powdery particulate substances on the surfaces of the two wafers after peeling, if the subsequent cleaning process cannot remove these particles to the greatest extent possible, it will lead to an increased risk of surface defects and a reduced yield. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for cleaning an SOI substrate that can improve the removal efficiency of surface defects.

[0006] To solve the above problems, the present invention provides a method for cleaning an SOI substrate, including: providing a support substrate and a device substrate, wherein the device substrate includes a peeling layer; bonding the support substrate and the device substrate; peeling the device substrate from the peeling layer position; performing ultrasonic cleaning on the peeled surface, and the ultrasonic frequency used is 5 - 25 KHz.

[0007] Optionally, the cleaning liquid for the ultrasonic cleaning, the cleaning temperature range, and the cleaning time range.

[0008] Optionally, the support substrate and the device substrate are silicon substrates.

[0009] Optionally, the bonding uses room-temperature or low-temperature bonding technology.

[0010] Optionally, the peeling step includes annealing the bonded wafer.

[0011] Due to the special surface topography after injection and stripping, the density of dangling bonds is higher than that of the ordinary silicon substrate surface. Therefore, the cleaning frequency of 25 kHz - 1 MHz will not reduce the surface defects but increase them instead. However, reducing the ultrasound to 5 - 25 kHz in the above technical solution will significantly reduce the surface defects. Brief Description of the Drawings

[0012] The Figure 1 The following shows a schematic diagram of the implementation steps of the cleaning method for the SOI substrate according to a specific embodiment of the present invention.

[0013] The Figure 2A to the Figure 2C The following shows a process flow diagram of the cleaning method for the SOI substrate according to a specific embodiment of the present invention.

[0014] The Figure 3 The following shows a schematic diagram of the test results of the cleaning method for the SOI substrate according to a specific embodiment of the present invention. Specific Embodiment

[0015] The following will give a detailed description of the specific embodiment of the cleaning method for the SOI substrate provided by the present invention with reference to the drawings.

[0016] The Figure 1 The following shows a schematic diagram of the implementation steps of the cleaning method for the SOI substrate according to a specific embodiment of the present invention. Step S10: Provide a support substrate and a device substrate, where the device substrate includes a stripping layer; Step S11: Bond the support substrate and the device substrate; Step S12: Strip the device substrate from the position of the stripping layer; Step S13: Perform ultrasonic cleaning on the stripped surface, and the ultrasonic frequency used is 5 - 25 KHz.

[0017] The Figure 2A to the Figure 2C The following shows the process flow diagram of this specific embodiment.

[0018] The Figure 2A As shown in the figure, referring to Step S10, provide a support substrate 10 and a device substrate 20, where the device substrate 20 includes a stripping layer 21. In this specific embodiment, the support substrate 10 and the device substrate 20 are silicon substrates. Single-crystalline silicon is widely used in various integrated circuits, such as microprocessors, memory chips, logic chips, etc., and is currently the most important substrate material in the semiconductor industry. In other specific embodiments, common substrate materials such as silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), sapphire (AlO), gallium arsenide (GaAs), indium phosphide (InP), etc. are applicable to this technical solution. The silicon wafer should have high purity, low defect density, and good crystal structure.

[0019] Using techniques such as chemical vapor deposition (CVD), an oxide layer is deposited on the surface of at least one of the support substrate 10 and the device substrate 20 to form a silicon oxide layer 11. This process requires precise control of deposition conditions, such as reaction temperature, gas flow rate, and pressure. Taking thermal oxidation as an example, the silicon wafer is usually heated to 900 - 1100 °C, oxygen or water vapor is introduced, and after a certain reaction time, an oxide layer with the required thickness grows on the surface of the silicon wafer. This oxide layer will subsequently become the key insulating layer in the SOI structure, and its thickness is generally between dozens of nanometers and several micrometers, and the specific value depends on the design requirements of the target SOI product.

[0020] The device substrate 20 includes a separation layer 21. Hydrogen ions can be implanted using an ion implantation device. The ion implantation process is carried out in a high-vacuum environment, and the hydrogen ions are accelerated by an electric field to obtain sufficient energy to bombard the silicon wafer. Parameters such as implantation energy, dose, and angle need to be precisely adjusted according to the expected SOI layer thickness and performance. After hydrogen ion implantation, a buried layer with a specific depth is formed in the silicon wafer. The position of this buried layer is crucial. It will become the separation layer 21 in the subsequent steps, and its depth is determined by the implantation energy and the characteristics of the silicon wafer material. By adjusting the implantation energy, the depth of the separation layer can be precisely controlled, and thus the thickness of the final SOI layer can be determined.

[0021] As Figure 2B shown, referring to step S11, the support substrate 10 and the device substrate 20 are bonded. Before bonding, the surfaces of the two silicon wafers need to be strictly cleaned and pretreated to remove impurities such as surface contaminants, particles, and organic substances, ensuring the cleanliness and flatness of the bonding interface. The cleaning process usually includes steps such as chemical cleaning, deionized water rinsing, and drying.

[0022] A special wafer bonding device is used for the bonding operation. During the bonding process, a certain pressure and temperature are applied to promote the tight combination of the two silicon wafers. For common room-temperature or low-temperature bonding techniques, the pressure is generally controlled between a few N / cm 2 and dozens of N / cm 2 , and the temperature is between room temperature and about 200 °C; for high-temperature bonding techniques, the temperature may be as high as 800 - 1200 °C, and the pressure is adjusted accordingly. By precisely controlling these parameters, the two silicon wafers are connected to each other at the atomic scale to form a strong bonding interface.

[0023] As Figure 2CAs shown, referring to step S12, the device substrate 20 is peeled off from the position of the release layer 21. The bonded wafer is placed in a high-temperature furnace for annealing treatment. The annealing temperature and time are key parameters. Generally, the annealing temperature is between 400 - 600 °C, and the time ranges from several tens of minutes to several hours. During the high-temperature annealing process, the bubbles formed by the previously implanted hydrogen ions will gradually expand and merge with each other, eventually forming cracks. Due to the action of stress, the silicon wafer separates along the layer where hydrogen ions are implanted. This step retains a thin device layer or the so-called top silicon 12 on the support substrate 10, and the cleaved silicon wafer, that is, the remaining part of the device substrate 20, if the surface quality and crystal structure are not severely damaged, can be reused in the above process after appropriate treatment, realizing the effective recycling of materials.

[0024] Step S13, ultrasonically clean the peeled surface, and the ultrasonic frequency used is 5 - 25 kHz.

[0025] Generally speaking, ultrasonic cleaning is based on the cavitation effect generated by high-frequency vibration (25 kHz - 1 MHz) in a liquid. The change in acoustic pressure prompts the rapid expansion and rupture of tiny bubbles in the liquid, releasing a powerful shock wave to peel off the dirt on the silicon wafer surface. Under the action of ultrasonic waves, sparse and dense parts are formed inside the liquid medium. In the sparse part, near-vacuum cavity bubbles are generated. When the cavity bubbles disappear instantaneously, a powerful local pressure is generated near them, prompting the desorption of impurities on the silicon wafer surface. When the ultrasonic frequency reaches resonance with the vibration frequency of the cavity bubbles, the mechanical force reaches the maximum, a large amount of heat energy accumulates in the bubbles, the temperature rises, and then it promotes the occurrence of chemical reactions to assist the cleaning process. In this specific embodiment, it is experimentally found that due to the special surface morphology after implantation and peeling, the density of dangling bonds is greater than that of the surface of an ordinary silicon substrate. Therefore, a cleaning frequency of 25 kHz - 1 MHz will not only not reduce surface defects but will instead increase surface defects. While reducing the ultrasonic frequency to 5 - 25 kHz will significantly reduce surface defects.

[0026] Appendix Figure 3The figure shows the test results of the above cleaning method. (a) shows the surface defect test results after cleaning with a frequency of more than 25kHz, and (b) shows the surface defect test results after cleaning with a frequency of 5 to 25kHz. The test was conducted using the surface defect detection system SP1 of the KLA-Tencor Surfscan SP1 series. The SP1 series detection system can accurately detect and identify these surface defects through a variety of optical detection technologies, such as bright field and dark field imaging, and provide detailed defect information, such as the location, size, and shape of the defects, to help semiconductor manufacturers to promptly discover process problems and take corresponding measures to improve them, so as to improve the yield and quality of products. The surface defects detected by the equipment include particles, scratches, polishing mist, COP (crystal native particles), hillocks, and orange peel. Particles: tiny solid particles on the surface of silicon wafers. Scratches are scratches caused by contact or friction between tools, fixtures, etc. and the surface of silicon wafers during the processing of silicon wafers. Polishing mist is a thin layer of mist-like defects that may form on the surface of silicon wafers if the polishing parameters are not properly controlled. COP (Crystal Origin Particle) is a native defect formed during the growth of silicon wafer crystals, usually a tiny void or impurity accumulation area. Hillocks are tiny protrusions that appear in local areas on the surface of silicon wafers. Orange peel is a rough texture similar to orange peel on the surface of silicon wafers.

[0027] SP1 can conduct a comprehensive assessment of the above surface defects. Figure 3 It can be seen from the test results that reducing the ultrasonic wave to 5-25kHz will significantly reduce surface defects.

[0028] After the above cleaning, it also undergoes CMP polishing and annealing processes.

[0029] CMP is an ultra-precision surface processing technology that combines chemical etching and mechanical grinding. During the polishing process, specific polishing pads and polishing liquids are required. The polished wafer is subjected to high-temperature annealing again. The annealing temperature is generally between 1000-1200°C, and the time is from tens of minutes to hours. The main purpose of this step is to eliminate the residual stress introduced during the polishing process, repair the defects in the crystal structure, and make the silicon layer and the oxide layer on the oxide layer more stable. At the same time, the quality of the bonding interface is further improved, the bonding strength between the two silicon wafers is enhanced, and the structural stability of the entire SOI wafer and the reliability of the electrical performance are ensured. At this point, the SOI wafer preparation is completed and can be used for the manufacture of high-performance electronic devices.

[0030] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A cleaning method for an SOI substrate, characterized in that, Including: Providing a support substrate and a device substrate, wherein the device substrate includes a release layer; Bonding the support substrate and the device substrate; Peeling the device substrate from the position of the release layer; Performing ultrasonic cleaning on the peeled surface, and the ultrasonic frequency used is 5 - 25 KHz.

2. The method according to claim 1, wherein The cleaning solution for the ultrasonic cleaning, the cleaning temperature range, and the cleaning time range.

3. The method according to claim 1, characterized in that The support substrate and the device substrate are silicon substrates.

4. The method according to claim 1, wherein The bonding adopts room temperature or low temperature bonding technology.

5. The method according to claim 1, wherein The peeling step includes annealing the bonded wafer.

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