Structure including semiconductor layer formed by lateral epitaxial growth

Abstract

The invention relates to structures including semiconductor layers formed by lateral epitaxial growth. Structures including semiconductor layers formed by lateral epitaxial growth and methods of forming such structures are disclosed. The structure includes a first semiconductor layer including a first segment and a second segment adjacent to the first segment, a second semiconductor layer including a segment and a semiconductor region protruding from the second segment of the first semiconductor layer to the segment of the second semiconductor layer, and a dielectric layer, the dielectric layer is disposed between the first segment of the first semiconductor layer and the segment of the second semiconductor layer. The segment of the second semiconductor layer and the semiconductor region comprise one or more single crystal semiconductor materials.

Description

Technical Field

[0001] This application generally relates to semiconductor devices and integrated circuit manufacturing, and more particularly to structures including semiconductor layers formed by lateral epitaxial growth and methods of forming such structures. Background Art

[0002] Solid-phase epitaxy refers to a type of growth that occurs when a semiconductor material undergoes a transformation from an amorphous phase to a single-crystalline phase. Typically, the material is deposited in an amorphous phase on a single-crystalline substrate that has a crystal structure which serves as a crystallization template during the transformation to the single-crystalline phase. Lateral solid-phase epitaxy involves forming epitaxial semiconductor material over a dielectric layer. Conventional lateral solid-phase epitaxy processes are limited by the effective distance of crystallization in a horizontal direction over the dielectric layer.

[0003] There is a need for improved structures including semiconductor layers formed by lateral epitaxial growth and methods of forming such structures. Summary of the Invention

[0004] In one embodiment of the present invention, a structure includes a first semiconductor layer, a second semiconductor layer, and a dielectric layer. The first semiconductor layer includes a first segment and a second segment adjacent to the first segment. The second semiconductor layer includes a segment and a semiconductor region that projects from the second segment of the first semiconductor layer to the segment of the second semiconductor layer. The dielectric layer is disposed between the first segment of the first semiconductor layer and the segment of the second semiconductor layer. The segment and the semiconductor region of the second semiconductor layer include one or more single-crystalline semiconductor materials.

[0005] In one embodiment of the present invention, a method includes forming a first segment and a second segment of a first semiconductor layer, and forming a second semiconductor layer that includes a segment and a semiconductor region that projects from the second segment of the first semiconductor layer to the segment of the second semiconductor layer. The second segment of the first semiconductor layer is adjacent to the first segment of the first semiconductor layer. The segment and the semiconductor region of the second semiconductor layer include one or more single-crystalline semiconductor materials, and a dielectric layer is disposed between the first segment of the first semiconductor layer and the segment of the second semiconductor layer. Brief Description of the Drawings

[0006] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.

[0007] Figures 1-5 A cross-sectional view showing a structure in a successive manufacturing stage of a processing method according to an embodiment of the present invention.

[0008] Figures 6-7 A cross-sectional view showing a structure in a continuous manufacturing stage of a processing method according to an alternative embodiment of the present invention.

[0009] Figure 8 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.

[0010] Figures 9-10 A cross-sectional view showing a structure in a continuous manufacturing stage of a processing method according to an alternative embodiment of the present invention.

[0011] Figure 11 A cross-sectional view showing a structure according to an alternative embodiment of the present invention. Detailed Description

[0012] Please refer to Figure 1 According to an embodiment of the present invention, a silicon-on-insulator (SOI) substrate including a semiconductor layer 12, a buried insulator layer 14, and a semiconductor substrate 16 can be used to form the structure 10. In one embodiment, the semiconductor layer 12 can be composed of a semiconductor material, such as single-crystalline silicon. The buried insulator layer 14 can be composed of a dielectric material (such as silicon dioxide), which is an electrical insulator. The semiconductor substrate 16 can be composed of a semiconductor material, such as single-crystalline silicon. The buried insulator layer 14 is disposed between the semiconductor layer 12 and the semiconductor substrate 16. The buried insulator layer 14 has a lower interface that interfaces with the semiconductor substrate 16 and an upper interface that interfaces with the semiconductor layer 12. In one embodiment, the semiconductor layer 12 can be significantly thinner than the semiconductor substrate 16. In one embodiment, the semiconductor layer 12 can have a thickness in the range of about 30 nanometers to about 300 nanometers between the upper and lower interfaces.

[0013] Shallow trench isolation regions 18, 20 are formed that penetrate through the semiconductor layer 12 to reach the buried insulator layer 14. The shallow trench isolation regions 18, 20 can be formed by patterning shallow trenches using photolithography and etching processes, depositing a dielectric material (such as silicon dioxide) to fill the shallow trenches, and planarizing and / or recessing the dielectric material.

[0014] A section 22 of the semiconductor layer 12 is laterally disposed in the space between the shallow trench isolation region 18 and the shallow trench isolation region 20. The section 22 of the semiconductor layer 12 has a width dimension W1, which can be equal to the spacing between the shallow trench isolation region 18 and the shallow trench isolation region 20. The semiconductor layer 12 includes a section 21 that is adjacent to the section 22 and is separated from the section 22 by the shallow trench isolation regions 18, 20.

[0015] A dielectric layer 24 is formed as a coating on the top surface 11 of the semiconductor layer 12 and the shallow trench isolation regions 18, 20. The dielectric layer 24 may be composed of a dielectric material (such as silicon dioxide or silicon nitride), which is an electrical insulator. In one embodiment, the dielectric layer 24 may have a uniform thickness.

[0016] A semiconductor layer 26 is formed on the dielectric layer 24 covering the top surface 11 of the semiconductor layer 26. The semiconductor layer 26 may be composed of a semiconductor material, such as silicon, silicon germanium, or germanium, and the semiconductor layer 26 may include multiple sub-layers and / or composition gradients. In one embodiment, the semiconductor layer 26 may be composed of an amorphous semiconductor material, such as amorphous silicon, amorphous silicon germanium, or amorphous germanium. In one embodiment, the semiconductor layer 26 may be composed of a semiconductor material different from that of the semiconductor layer 12. In one embodiment, the semiconductor layer 26 may be composed of the same semiconductor material as that of the semiconductor layer 12.

[0017] A hard mask layer 28 may be formed on the semiconductor layer 26. The hard mask layer 28 (which may be composed of one or more dielectric materials such as silicon dioxide and / or silicon nitride) is patterned by photolithography and etching processes to define an opening aligned with a portion of the segment 22 of the semiconductor layer 12. The opening located in the hard mask layer 28 is narrower than the width dimension W1 of the segment 22 of the semiconductor layer 12.

[0018] Please refer to Figure 2 wherein like reference numerals represent Figure 1 like features in

[0019] Please refer to Figure 3 wherein like reference numerals represent Figure 2 like features in and in the next manufacturing stage, a semiconductor layer 32 is formed, which includes being disposed in the opening 30 (Figure 2 ) The inner segment 34. The segment 34 of the semiconductor layer 32 can be in direct contact with the segment 22 of the semiconductor layer 12 at the bottom of the opening 30. The semiconductor layer 32 can be formed by a non-selective epitaxial growth process. Due to the presence of the segment 22 of the semiconductor layer 12 that acts as a single-crystal seed during this non-selective epitaxial growth process, during the formation of the semiconductor layer 32, the segment 34 of the semiconductor layer 32 can grow into a single-crystal material. During the formation of the semiconductor layer 32, another segment 36 of the semiconductor layer 32 (which is adjacent to the segment 34 of the semiconductor layer 32) can grow into an amorphous material. The segment 34 of the semiconductor layer 32 protrudes above the dielectric layer 24 from the segment 22 of the semiconductor layer 12.

[0020] The semiconductor layer 32 can be composed of a semiconductor material (such as silicon, silicon-germanium, or germanium) and can include multiple sub-layers and / or compositional gradients. In one embodiment, the segment 34 of the semiconductor layer 32 can be composed of a single-crystal semiconductor material, such as single-crystal silicon, single-crystal silicon-germanium, or single-crystal germanium. In one embodiment, the segment 36 of the semiconductor layer 32 can be composed of an amorphous semiconductor material, such as amorphous silicon, amorphous silicon-germanium, or amorphous germanium. In one embodiment, the semiconductor layer 32 can be composed of a semiconductor material different from that of the semiconductor layer 26. In one embodiment, the semiconductor layer 32 can be composed of the same semiconductor material as that of the semiconductor layer 26.

[0021] If the lattice structure has long-range order and does not have grain boundaries associated with polycrystalline semiconductor materials, then the semiconductor material (such as the semiconductor material of the segment 34 of the semiconductor layer 32) can be referred to as single-crystal. Even if crystal defects (such as dislocations) are included as defects, the semiconductor material can still be regarded as single-crystal. If there is no long-range order in the lattice structure, then the semiconductor material (such as the semiconductor material of the segment 36 of the semiconductor layer 32) can be referred to as amorphous.

[0022] Please refer to Figure 4 in which like reference numerals represent Figure 3features similar to those in, and in the next manufacturing stage, patterning segments 36 of semiconductor layer 32, segments 34 of semiconductor layer 32, and segments 22 of semiconductor layer 12 by photolithography and anisotropic etching processes to define an opening 38 that extends into the buried insulator layer 14. The opening 38 divides segment 36 of semiconductor layer 32 into semiconductor regions 33 and 35. The opening 38 divides segment 34 of semiconductor layer 32 into semiconductor regions 29 and 31. The opening 38 divides segment 22 of semiconductor layer 12 into smaller segments 13 and 15. This patterning of semiconductor layer 32 exposes the hard mask layer 28, and the hard mask layer is removed from the top surfaces of semiconductor layers 25 and 27 by an etching process. Semiconductor regions 29, 33, and segment 13 of semiconductor layer 12 extend together (i.e., share a boundary) with different portions of the opening 38, and semiconductor regions 31, 35, and segment 15 of semiconductor layer 12 also extend together with different portions of the opening 38.

[0023] The opening 38 has a width dimension W3 that is less than the width dimension W2 of segment 22 of semiconductor layer 12 and less than the width dimension W1 of the opening 30. Semiconductor region 29 is stacked with segment 13 of semiconductor layer 12 and semiconductor region 33. Semiconductor region 29 is disposed between segment 13 of semiconductor layer 12 and semiconductor region 33. Semiconductor region 31 of semiconductor layer 32 is stacked with segment 15 of semiconductor layer 12 and semiconductor region 35. Semiconductor region 31 is disposed between segment 15 of semiconductor layer 12 and semiconductor region 35.

[0024] In an alternative embodiment, the opening 38 may only extend through segment 22 of semiconductor layer 12 and terminate within segment 22. In another embodiment, a portion 32 of segment 36 of semiconductor layer 32 located above the hard mask layer 28 may be removed by a polishing process.

[0025] Please refer to Figure 5 wherein like reference numerals denote Figure 4 features similar to those in, and in the next manufacturing stage, converting semiconductor layers 25 and 27 and semiconductor regions 33 and 35 from amorphous semiconductor material to single-crystalline semiconductor material using a lateral solid-phase epitaxy process. In one embodiment, semiconductor layers 25 and 27 and semiconductor regions 33 and 35 may be converted to single-crystalline semiconductor material. In an embodiment, the lateral solid-phase epitaxy process may include thermal annealing in an inert gas environment at a substrate temperature of about 600 °C for a given annealing time. In an embodiment, the lateral solid-phase epitaxy process may include rapid thermal annealing.

[0026] The semiconductor region 29 is disposed adjacent to the edge of the dielectric layer 24, and the semiconductor region 29 is adjacent to (i.e., co - extends with) a portion of the opening 38. The semiconductor region 31 is disposed adjacent to the edge of the dielectric layer 24, and the semiconductor region 31 is adjacent to a portion of the opening 38. When the opening 38 is patterned, these edges of the dielectric layer 24 are formed. The semiconductor region 29 provides a single - crystal bridge that connects the segment 13 of the semiconductor layer 12 to the semiconductor layer 25 and the semiconductor region 33. The semiconductor region 31 provides a single - crystal bridge that connects the segment 15 of the semiconductor layer 12 to the semiconductor layer 27 and the semiconductor region 35.

[0027] The semiconductor regions 29, 31 provide corresponding connectors for connecting to the seeds formed by the segments 13, 15 of the semiconductor layer 12 to implement the lateral solid - phase epitaxy process. The semiconductor region 29 protrudes from the segment 13 of the semiconductor layer 12 through the edge of the dielectric layer 24 and reaches the semiconductor layer 25. The semiconductor region 31 protrudes from the segment 15 of the semiconductor layer 12 through the edge of the dielectric layer 24 and reaches the semiconductor layer 27. The semiconductor layer 25 and the semiconductor region 33 undergo a transformation from an amorphous phase to a single - crystal phase based on the crystal structure of the segment 13 of the semiconductor layer 12, which is achieved by the semiconductor region 29. The semiconductor layer 27 and the semiconductor region 35 undergo a transformation from an amorphous phase to a single - crystal phase based on the crystal structure of the segment 15 of the semiconductor layer 12, which is achieved by the semiconductor region 31. During this solid - phase epitaxy process, the amorphous / crystalline interface advances forward from each of the semiconductor regions 29, 31, as indicated schematically by the curved single arrows.

[0028] The single - crystal semiconductor material of the semiconductor layer 25 is separated from the single - crystal semiconductor material of the segment 21 of the semiconductor layer 12 adjacent to the shallow trench isolation region 18 by a segment of the dielectric layer 24. The single - crystal semiconductor material of the semiconductor layer 27 is separated from the single - crystal semiconductor material of the segment 21 of the semiconductor layer 12 adjacent to the shallow trench isolation region 20 by a segment of the dielectric layer 24. In one embodiment, the single - crystal semiconductor material included in each of the semiconductor layers 25, 27 may laterally extend a distance greater than or equal to 200 nanometers above the segment 21 of the semiconductor layer 12 and below the corresponding segment of the dielectric layer 24 and beyond the opening 38.

[0029] The semiconductor layer 25, the semiconductor region 29, and the semiconductor region 33 may form a segment of a seamless semiconductor layer because the crystal structures of their respective single - crystal semiconductor materials are continuous. In one embodiment, the segment 13 of the semiconductor layer 12 may also be included in this segment of the seamless semiconductor layer. The semiconductor layer 27, the semiconductor region 31, and the semiconductor region 35 may form a segment of a seamless semiconductor layer because the crystal structures of their respective single - crystal semiconductor materials are continuous. In one embodiment, the segment 15 of the semiconductor layer 12 may also be included in this segment of the seamless semiconductor layer. The pair of seamless semiconductor layers are laterally separated by the intermediate opening 38.

[0030] The lateral solid phase epitaxy process can be used to form semiconductor layers 25, 27 as single crystal semiconductor material segments on and above dielectric material segments of dielectric layer 24. The lateral solid phase epitaxy process can exhibit long-range crystallization, where the lateral extent (with limited defects) of the single crystal semiconductor material of semiconductor layers 25, 27 exceeds the conventional limit of lateral growth above the dielectric layer of less than 200 nanometers.

[0031] Structure 10 can be used to form different types of device structures. For example, structure 10 can be used to form an electro-optical modulator. In an alternative embodiment, a bulk substrate rather than a silicon-on-insulator substrate can be used to form structure 10.

[0032] Please refer to Figure 6 And according to an alternative embodiment, the lateral solid phase epitaxy process can be performed immediately after forming semiconductor layer 32. Segments 36 of semiconductor layer 32 and semiconductor layers 25, 27 are crystallized by the lateral solid phase epitaxy process. Hard mask layer 28 remains as a dielectric layer disposed between the single crystal semiconductor material of semiconductor layers 25, 27 and the single crystal semiconductor material of semiconductor layer 32.

[0033] Please refer to Figure 7 , where like reference numerals denote Figure 6 like features in, and in a next manufacturing stage, semiconductor layer 32 can be planarized and hard mask layer 28 can be removed to retain segment 34 and that portion of segment 36 located inside opening 30 ( Figure 2 ). In an alternative embodiment, opening 38 can be formed after planarization.

[0034] Please refer to Figure 8 And according to an alternative embodiment, after performing the lateral solid phase epitaxy process, segments 13, 15, semiconductor regions 29, 31, and semiconductor regions 33, 35 can be patterned and removed to define opening 40. In one embodiment, the formed opening 40 can be filled with an electrically insulating dielectric material.

[0035] Please refer to Figure 9According to an alternative embodiment, structure 10 may include a plurality of semiconductor layers 41, 43 similar to semiconductor layer 25, a plurality of semiconductor layers 42, 44 similar to semiconductor layer 27, and a plurality of dielectric layers 46, 48 similar to dielectric layer 24. A segment of dielectric layer 46 is disposed between semiconductor layer 25 and semiconductor layer 41, and a segment of dielectric layer 48 is disposed between semiconductor layer 41 and semiconductor layer 43. A layer stack is defined that includes semiconductor layer 25, this segment of dielectric layer 46, semiconductor layer 41, this segment of dielectric layer 48, and semiconductor layer 43. A segment of dielectric layer 46 is disposed between semiconductor layer 27 and semiconductor layer 42, and a segment of dielectric layer 48 is disposed between semiconductor layer 42 and semiconductor layer 44. A layer stack is defined that includes semiconductor layer 27, this segment of dielectric layer 46, semiconductor layer 42, this segment of dielectric layer 48, and semiconductor layer 44.

[0036] In one embodiment, dielectric layer 24, dielectric layer 46, and / or dielectric layer 48 may have different thicknesses. In one embodiment, dielectric layer 24, dielectric layer 46, and / or dielectric layer 48 may have the same thickness. In one embodiment, semiconductor layer 26, semiconductor layer 42, and / or semiconductor layer 44 may have different thicknesses. In one embodiment, semiconductor layer 26, semiconductor layer 42, and / or semiconductor layer 44 may have the same thickness.

[0037] Deposit semiconductor layer 32 and form opening 38, and then remove hard mask layer 28. Semiconductor regions 33 (adjacent to each of semiconductor layers 41, 43) extend from segment 13 through semiconductor layer 41 to semiconductor layer 43. Semiconductor regions 35 (adjacent to each of semiconductor layers 42, 44) extend from segment 15 through semiconductor layer 42 to semiconductor layer 44.

[0038] In one embodiment, semiconductor layer 26, semiconductor layers 41, 42, and / or semiconductor layers 43, 44 may be doped by ion implantation during or after deposition. In one embodiment, semiconductor layers 25, 27, 41, 42, 43, and / or semiconductor layer 44 may be doped to have the same conductivity type. In one embodiment, semiconductor layers 25, 27, 41, 42, 43, and / or semiconductor layer 44 may be doped to have different conductivity types.

[0039] Please refer to Figure 10 wherein like reference numerals denote Figure 9Similar features, and in the next manufacturing stage, a lateral solid-phase epitaxy process is performed to cause the semiconductor materials of semiconductor regions 33, 35, semiconductor layers 25, 27, semiconductor layers 41, 42, and semiconductor layers 43, 44 to undergo a transformation from an amorphous phase to a single-crystalline phase. Semiconductor regions 29, 31 provide local connectors for this solid-phase epitaxy process to connect with the single-crystalline seeds defined by segments 13, 15 of semiconductor layer 12. Among them, the semiconductor materials of semiconductor regions 33, 35, semiconductor layers 25, 27, semiconductor layers 41, 42, and semiconductor layers 43, 44 crystallize during this lateral solid-phase epitaxy process. Segment 33 defines a segment extending through dielectric layers 46, 48 and adjacent to the single-crystalline semiconductor material columns of semiconductor layers 41, 43, so that semiconductor region 33 provides an extension of the connection provided by semiconductor region 29, thereby realizing the lateral solid-phase epitaxy of the amorphous semiconductor materials of semiconductor layers 41, 43. Semiconductor region 35 defines a segment extending through dielectric layers 46, 48 and adjacent to the single-crystalline semiconductor material columns of semiconductor layers 42, 44, so that semiconductor region 35 provides an extension of the connection provided by semiconductor region 31, thereby realizing the lateral solid-phase epitaxy of the amorphous semiconductor materials of semiconductor layers 42, 44.

[0040] Semiconductor layer 41 and semiconductor layer 43 are included as additional segments of the seamless semiconductor layer including semiconductor layer 25, semiconductor region 29, and semiconductor region 33. Semiconductor layer 42 and semiconductor layer 44 are included as additional segments of the seamless semiconductor layer including semiconductor layer 27, semiconductor region 31, and semiconductor region 35.

[0041] Please refer to Figure 11 And according to an alternative embodiment, this part of structure 10 including semiconductor regions 29, 31 can be replicated so that multiple positions have different segments 13, 15 of semiconductor layer 12, thereby providing single-crystalline seeds for the lateral solid-phase epitaxy process and resulting in the formation of single-crystalline semiconductor materials. Dielectric regions 50 can be formed in semiconductor layer 26, dielectric regions 52 can be formed in semiconductor layer 42, and dielectric regions 54 can be formed in semiconductor layer 44. Dielectric regions 50, 52, 54 can be composed of a dielectric material (such as silicon dioxide), which is an electrical insulator. Dielectric regions 50, 52, 54 can have a thickness T1 greater than the thickness T2 of dielectric layers 24, 46, 48. In one embodiment, semiconductor layer 26 can have a thickness equal to the thickness T1 of dielectric region 50, semiconductor layer 42 can have a thickness equal to the thickness T1 of dielectric region 52, and semiconductor layer 44 can have a thickness equal to the thickness T1 of dielectric region 54.

[0042] Dielectric regions 50, 52, 54 may be formed at various different positions within semiconductor layers 26, 42, 44. In one embodiment, dielectric regions 50, 52, 54 may be arranged such that portions of two or more of the semiconductor layers 26, 42, 44 in different levels overlap. In one embodiment, portions of the semiconductor layers 26, 42, 44 in different levels are separated by one or more of the dielectric regions 50, 52, 54.

[0043] The method as described above is used for the manufacture of integrated circuit chips. The manufacturer may distribute the resulting integrated circuit chips in the form of an original wafer (e.g., as a single wafer having a plurality of unpackaged chips), as bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product. The final product may be any product including an integrated circuit chip, such as a computer product or a smart phone having a central processing unit.

[0044] Terms herein that are modified by approximate language such as "about," "substantially," and "essentially" are not limited to the specified exact value. The approximate language may correspond to the precision of the instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may represent + / - 10% of the stated value.

[0045] Terms such as "vertical," "horizontal," etc. are cited herein as examples to establish a reference frame and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to a direction perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0046] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or there may be one or more intermediate features. If there are no intermediate features, the feature may be "directly connected" or "directly coupled" to the other feature. If there is at least one intermediate feature, the feature may be "indirectly connected" or "indirectly coupled" to the other feature. A feature that is "on" or in "contact" with another feature may be directly on or in direct contact with the other feature, or there may be one or more intermediate features. If there are no intermediate features, the feature may be directly "on" or in "direct contact" with the other feature. If there is at least one intermediate feature, the feature may be "not directly" on or in "not direct contact" with the other feature. Different features may "overlap" if one feature extends over and covers a portion of another feature, either in direct contact or not in direct contact.

[0047] The description of the various embodiments of the present invention is for illustrative purposes only and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application, or the technological improvements over the technology known in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure, characterized in that, Comprising: A first semiconductor layer including a first segment and a second segment adjacent to the first segment; A second semiconductor layer including a first segment and a semiconductor region protruding from the second segment of the first semiconductor layer to the first segment of the second semiconductor layer, and the first segment and the semiconductor region of the second semiconductor layer include one or more single-crystalline semiconductor materials; And A first dielectric layer disposed between the first segment of the first semiconductor layer and the first segment of the second semiconductor layer.

2. The structure according to claim 1, wherein Further comprising: A shallow trench isolation region disposed between the first segment and the second segment of the first semiconductor layer.

3. The structure according to claim 2, wherein, The first dielectric layer is disposed above the first segment of the first semiconductor layer and below the first segment of the second semiconductor layer, and the first dielectric layer extends across the shallow trench isolation region.

4. The structure according to claim 3, wherein, The first dielectric layer extends above a portion of the second segment of the first semiconductor layer.

5. The structure according to claim 2, characterized in that, Further comprising: An opening at least partially passing through the first semiconductor layer and through the second semiconductor layer, wherein the second segment of the first semiconductor layer is laterally disposed between the opening and the shallow trench isolation region.

6. The structure according to claim 5, characterized in that, Further comprising: A second dielectric layer, wherein the first segment and the second segment of the first semiconductor layer are disposed on the second dielectric layer, and the opening completely passes through the first semiconductor layer to reach the second dielectric layer.

7. The structure according to claim 5, wherein, The semiconductor region and a portion of the opening extend together.

8. The structure according to claim 1, characterized in that, The semiconductor region of the second semiconductor layer protrudes from the second segment of the first semiconductor layer above the first dielectric layer.

9. The structure according to claim 1, characterized in that, Further comprising: A second dielectric layer located above the first segment of the second semiconductor layer, wherein the second semiconductor layer includes a second segment located above the second dielectric layer, and the second segment of the second semiconductor layer includes a single-crystalline semiconductor material.

10. The structure according to claim 9, wherein, The second dielectric layer is disposed between the first segment and the second segment of the second semiconductor layer.

11. The structure according to claim 10, characterized in that, The semiconductor region of the second semiconductor layer abuts against a side of the second segment of the second semiconductor layer.

12. The structure according to claim 10, characterized in that, Further comprising: An opening passing through the second semiconductor layer, wherein the semiconductor region of the second semiconductor layer and the opening extend together.

13. The structure according to claim 12, wherein The semiconductor region of the second semiconductor layer is disposed between the first segment and the opening of the second semiconductor layer.

14. The structure according to claim 13, characterized in that, The semiconductor region of the second semiconductor layer is disposed between the second segment and the opening of the second semiconductor layer.

15. The structure according to claim 14, wherein, The second segment of the first semiconductor layer is disposed between the first segment and the opening of the first semiconductor layer.

16. The structure according to claim 9, wherein Further comprising: A dielectric region located in a portion of the second segment of the second semiconductor layer.

17. The structure according to claim 1, characterized in that, The first segment of the second semiconductor layer laterally extends a distance greater than or equal to 200 nanometers above the first dielectric layer.

18. A method, characterized in that, Comprising: Forming a first segment and a second segment of a first semiconductor layer, wherein the second segment is adjacent to the first segment; and Form a second semiconductor layer that includes a segment and a semiconductor region that protrudes from the second segment of the first semiconductor layer to the segment of the second semiconductor layer, wherein the segment of the second semiconductor layer includes single-crystalline semiconductor material, the semiconductor region of the second semiconductor layer includes single-crystalline semiconductor material, and a dielectric layer is disposed between the first segment of the first semiconductor layer and the segment of the second semiconductor layer.

19. The method according to claim 18, wherein Forming the second semiconductor layer that includes the segment and the semiconductor region that protrudes from the second segment of the first semiconductor layer to the segment of the second semiconductor layer includes: Forming an amorphous semiconductor layer over the dielectric layer; and Performing a solid-phase epitaxial process to convert the amorphous semiconductor layer into the single-crystalline semiconductor material of the segment of the second semiconductor layer.

20. The method according to claim 19, wherein The semiconductor region of the second semiconductor layer connects the segment of the second semiconductor layer to the amorphous layer as a seed for the solid-phase epitaxial process.

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