Channel multiplexing coding and decoding circuit applied to gate driver

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to a channel multiplexing coding and decoding circuit applied to a gate driver. The circuit comprises an encoder, a multiplexer, an isolation transmission path and a decoder, the encoder converts the two error state indication signals into bit selection signals and enable signals of the multiplexer, the multiplexer is controlled to output a return signal containing two error state information, and after the return signal is transmitted to the opposite side of the chip through the isolation transmission path, the two error state indication signals are restored through the decoder. According to the invention, single-channel transmission of three different signals and two error states is realized, an asynchronous coding strategy based on a trigger is utilized, the influence of factors such as a process corner and temperature in a clock synchronization process is reduced, and the decoding reliability is ensured through a deburring technology.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and particularly relates to a channel multiplexing encoding and decoding circuit applied to a gate driver. Background Art

[0002] In integrated circuits, encoding and decoding circuits are important circuits. Taking the data feedback circuit in an isolated gate driver as an example, the secondary side of the chip continuously transmits a PWM feedback signal to the primary side. At the same time, when an error state such as overcurrent, oversaturation, or undervoltage occurs on the secondary side of the chip, the corresponding signal state inside the chip changes, and the error signal is encoded and transmitted back to the primary side through isolation to control the upper computer to make a response. Currently, common isolation transmission schemes include using multiple isolation transmission paths to transmit different signals respectively, or performing encoding and decoding based on a clock synchronization circuit to achieve multiplexing of isolation transmission channels. However, the channel-independent transmission scheme increases the chip area and the design and manufacturing costs; the encoding and decoding scheme based on the clock synchronization circuit is complex in design and is easily affected by process corners and temperature, resulting in potential decoding errors. Therefore, it is of great significance to research a simple and reliable channel multiplexing encoding and decoding circuit. Summary of the Invention

[0003] The present invention proposes a simple and reliable channel multiplexing encoding and decoding circuit, which can cooperate with common digital isolator circuits to achieve single-channel transmission of three different signals and two error states.

[0004] The technical solution of the present invention is as follows:

[0005] A channel multiplexing encoding and decoding circuit applied to a gate driver includes an encoder, a multiplexer, an isolation transmission path, and a decoder; the encoder converts two error state indication signals into a bit selection signal and an enable signal of the multiplexer, controls the multiplexer to output a feedback signal containing two error state information, and after the feedback signal is transmitted to the other side of the chip through the isolation transmission path, the decoder restores the two error state indication signals;

[0006] The encoder includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a first NAND gate, a second NAND gate, a third NAND gate, a first inverter, and a second inverter; the D input terminal of the first D flip-flop is connected to the power supply, the clock signal terminal is connected to the error type signal, the reset signal terminal is connected to the Q output terminal of the second D flip-flop, and the Q output terminal of the first D flip-flop is connected to one input terminal of the first NAND gate; the other input terminal of the first NAND gate is connected to the Q-bar output terminal of the second D flip-flop; the D input terminal of the second D flip-flop is connected to the power supply, the clock signal terminal is connected to the first timing signal, and the reset signal terminal is connected to the output terminal of the first NAND gate; the D input terminal of the third D flip-flop is connected to the power supply, the clock signal terminal is connected to the enable type signal, the reset signal terminal is connected to the inverted signal of the output terminal of the second NAND gate, and the Q output terminal of the third D flip-flop is connected to one input terminal of the third NAND gate; the other input terminal of the third NAND gate is connected to the output of the first inverter, and the input terminal of the first inverter is connected to the Q output terminal of the first D flip-flop; the D input terminal of the fourth flip-flop is connected to the power supply, the clock signal terminal is connected to the second timing signal, the reset signal terminal is connected to the output terminal of the third NAND gate, the Q output terminal of the fourth D flip-flop is connected to one input terminal of the second NAND gate, the other input terminal of the second NAND gate is connected to the output terminal of the second inverter, and the input terminal of the second inverter is connected to the enable type signal; the error type signal and the enable type signal constitute two error status indication signals; the output terminal of the first NAND gate is connected to the bit selection signal terminal of the multiplexer, and the output terminal of the third NAND gate is connected to the enable signal terminal of the multiplexer;

[0007] The two input signals of the multiplexer are the error code and the feedback signal respectively. When the output of the first NAND gate is high, the multiplexer outputs the feedback signal. When the output of the first NAND gate is low, that is, when the error type signal is high, the multiplexer outputs the error code; when the output of the third NAND gate is high, the multiplexer is enabled. When the output of the third NAND gate is low, that is, when the enable type signal is high, the multiplexer stops working;

[0008] The decoder includes a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, an eighth D flip-flop, a ninth D flip-flop, a tenth D flip-flop, an eleventh D flip-flop, and a third inverter; the D input terminal of the fifth D flip-flop is connected to the power supply, the clock signal terminal is connected to the output of the isolation transmission path, and the output of the isolation transmission path corresponds to the output of the multiplexer. The reset signal terminal of the fifth D flip-flop is connected to the third timing signal; the D input terminal of the sixth D flip-flop is connected to the Q output terminal of the fifth D flip-flop, the clock signal terminal of the sixth D flip-flop is connected to the output of the isolation transmission path, and the reset signal terminal is connected to the third timing signal; the D input terminal of the seventh D flip-flop is connected to the Q output terminal of the sixth D flip-flop, the clock signal terminal of the seventh D flip-flop is connected to the output of the isolation transmission path, and the reset signal terminal is connected to the third timing signal. The Q output terminal of the seventh D flip-flop is the error type signal indication signal; the input terminal of the third inverter is connected to the output of the isolation transmission path; the D input terminal of the eighth D flip-flop is connected to the power supply, the clock signal terminal is connected to the reference clock signal, and the reset signal terminal is connected to the output terminal of the third inverter; the D input terminal of the ninth D flip-flop is connected to the Q output terminal of the eighth D flip-flop, the clock signal terminal of the ninth D flip-flop is connected to the reference clock signal, and the reset signal terminal is connected to the output terminal of the third inverter; the D input terminal of the tenth D flip-flop is connected to the Q output terminal of the ninth D flip-flop, the clock signal terminal of the tenth D flip-flop is connected to the reference clock signal, and the reset signal terminal is connected to the output terminal of the third inverter; the D input terminal of the eleventh D flip-flop is connected to the power supply, the clock signal terminal is connected to the fourth timing signal, and the reset signal terminal is connected to the Q output terminal of the tenth flip-flop. The Q output terminal of the eleventh D flip-flop is the indication signal of the enable type signal.

[0009] The beneficial effects of the present invention are as follows: realizing single-channel transmission of three different signals and two error states, using an asynchronous coding strategy based on flip-flops, reducing the influence of factors such as process corners and temperature during clock synchronization, and ensuring the reliability of decoding through deburring technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a structural block diagram of a channel multiplexing encoding and decoding circuit applied to a gate driver;

[0011] Figure 2 is a schematic structural diagram of a channel multiplexing encoding circuit;

[0012] Figure 3 is a schematic structural diagram of a channel multiplexing decoding circuit;

[0013] Figure 4 is a functional timing diagram of a channel multiplexing encoding and decoding circuit applied to a gate driver. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings:

[0015] Figure 1 It is a block diagram of a channel multiplexing encoding and decoding circuit applied to a gate driver, which includes an encoder, a MUX, an isolation transmission part, and a decoder. Among them, the encoder converts two error status indication signals into the bit selection signal and the enable signal of the MUX, and controls the MUX to output a feedback signal containing two error status information. After the signal is transmitted to the other side of the chip through isolation transmission, the decoder restores the two error status indication signals, and this signal can drive the chip to perform error reporting, or control the response and shutdown of internal modules of the chip, etc.

[0016] In common applications, the feedback signal is a PWM signal with a fixed frequency, such as an APWM (Analog-to-PWM) signal, and this signal represents an analog quantity through the pulse width.

[0017] Figure 2Schematic diagram of the channel multiplexing encoding circuit structure. The error status indication signal is divided into two types: error type signal and enable type signal. For a common gate driver, the error type signals include overcurrent indication signal (OC), desaturation indication signal (DESAT), etc., and the enable type signals include secondary side undervoltage (UVLO) indication signal, etc. In the schematic diagram, the error type signal is SIG1, which flips from low to high when an error status occurs; the enable type signal is SIG2, which also flips from low to high when an error status occurs. For the error type signal, when SIG1 shows an error status, SIG1 is first sampled by a D flip-flop (DFF), and logically ANDed with the signal SIG1_OVER_N indicating whether the previous detection is completed to generate SIG1_FLAG_for_ENCODE. SIG1_FLAG_for_ENCODE is used to unlock another DFF, and the current state is latched through a timer TIMER1. After TIMER1 finishes timing, it generates a pulse, which is sampled by the DFF and resets the state of the DFF for sampling SIG1. At this time, the next detection of the SIG1 error status can be performed. For the error type signal, generally, being detected only once will cause the driving transistor to turn off, and the entire chip enters an error status that cannot be automatically cleared. For the enable type signal, when SIG2 shows an error status, SIG2 is also sampled by a DFF, and logically ANDed with the sampled SIG1 to generate EN_for_ENCODE. The purpose of this step is to ensure the priority of SIG1 when both error statuses occur simultaneously. EN_for_ENCODE is used to unlock another DFF, and the current state is latched through a timer TIMER2. After TIMER2 finishes timing, it generates a pulse, which is sampled by the DFF to generate SIG2_OVER. SIG2_OVER needs to be logically ANDed with SIG2 before being used for the reset of sampling, that is, the minimum error status hold-off delay of SIG2 is the smaller value of the error status time of SIG2 and a fixed time TIMER2. For the enable type signal, since the error status can be automatically cleared, the shortest response time for the system to restore from the error status to the initial state can be set through TIMER2 to ensure the reliability of the system. SIG1_FLAG_for_ENCODE is initially high, and the MUX outputs the feedback signal data. When SIG1 flips from low to high, SIG1_FLAG_for_ENCODE flips low, and the MUX outputs the error code fault_code. The frequency of the error code is much higher than that of the feedback signal. Therefore, the transmission of the error code hardly affects the transmission of the feedback signal. EN_for_ENCODE is initially high, and the MUX is enabled. When SIG2 flips from low to high, EN_for_ENCODE flips low and stops wave generation. Through the above method, single-channel encoding of three different signals and two error statuses is achieved.

[0018] Figure 3 It is a schematic diagram of the channel multiplexing decoding circuit structure. The demodulated signal passes through three cascaded DFFs. If three rising edges can be sampled before the end of the timing of TIMER3 and SIG1_OUT goes high, it is determined that the error state corresponding to the error type signal has occurred. TIMER3 should be set to a timing value greater than the time required to effectively sample three cycle error codes under normal circumstances but less than the timing time of two cycle feedback signals to distinguish high-frequency error codes and feedback signals. Sampling the third rising edge to determine the occurrence of the error state is for deburring. Another signal is applied to the Rst terminal of three cascaded DFFs, and a reference clock ref_clock is introduced at the Clk terminal. When the input is high, that is, after unlocking the DFF, if three rising edges of the reference clock can be sampled, RDY goes high and locks the last DFF, indicating that the wave can still be detected at this time and there is no need to perform the detection of the error state corresponding to the enable type signal. Detecting three rising edges is also for deburring. When the input is low, RDY is pulled low to unlock the last DFF, and at the same time TIMER4 starts timing. If RST does not flip after the end of the timing time, it is considered that the wave has stopped for a long time and SIG2_OUT goes high, and it is determined that the error state corresponding to the enable type signal has occurred.

[0019] Figure 4 It is the functional timing diagram of the channel multiplexing encoding and decoding circuit applied to the gate driver. When SIG1 goes high, SIG1_FLAG_for_ENCODE goes high and remains high for a duration of t TIMER1 and ENCODE_OUT outputs the error code. When the opposite side can detect three rising edges of the error code within the time of t TIMER3 , SIG1_OUT is pulled high, and the high state of SIG1_OUT needs to be manually released. When SIG1 goes high when SIG2 is high, the wave stop state is released and the error code is sent. When SIG2 goes high, EN_for_ENCODE is pulled low and SIG2_OUT is pulled high after t TIMER4 . The shortest delay to release the state where EN_for_ENCODE is pulled low is t TIMER2 .

[0020] Through the above method, the correct encoding and decoding of two error signals can be realized, and the single-channel transmission of three different signals and two error states in the gate driver can be realized. In summary, the present invention realizes a simple and reliable channel multiplexing encoding and decoding circuit structure.

Claims

1. A channel multiplexing encoding and decoding circuit applied to a gate driver, characterized in that It includes an encoder, a multiplexer, an isolation transmission path, and a decoder; the encoder converts two error status indication signals into the bit selection signal and the enable signal of the multiplexer, controls the multiplexer to output a feedback signal containing the two error status information, and after the feedback signal is transmitted to the other side of the chip through the isolation transmission path, the two error status indication signals are restored by the decoder; The encoder includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a first NAND gate, a second NAND gate, a third NAND gate, a first inverter, and a second inverter; the D input terminal of the first D flip-flop is connected to the power supply, the clock signal terminal is connected to the error type signal, the reset signal terminal is connected to the Q output terminal of the second D flip-flop, and the Q output terminal of the first D flip-flop is connected to one input terminal of the first NAND gate; the other input terminal of the first NAND gate is connected to the Q-bar output terminal of the second D flip-flop; the D input terminal of the second D flip-flop is connected to the power supply, the clock signal terminal is connected to the first timing signal, the reset signal terminal is connected to the output terminal of the first NAND gate; the D input terminal of the third D flip-flop is connected to the power supply, the clock signal terminal is connected to the enable type signal, the reset signal terminal is connected to the inverted signal of the output terminal of the second NAND gate, and the Q output terminal of the third D flip-flop is connected to one input terminal of the third NAND gate; the other input terminal of the third NAND gate is connected to the output of the first inverter, and the input terminal of the first inverter is connected to the Q output terminal of the first D flip-flop; the D input terminal of the fourth flip-flop is connected to the power supply, the clock signal terminal is connected to the second timing signal, the reset signal terminal is connected to the output terminal of the third NAND gate, the Q output terminal of the fourth D flip-flop is connected to one input terminal of the second NAND gate, the other input terminal of the second NAND gate is connected to the output terminal of the second inverter, and the input terminal of the second inverter is connected to the enable type signal; the error type signal and the enable type signal constitute two error status indication signals; the output terminal of the first NAND gate is connected to the bit selection signal terminal of the multiplexer, and the output terminal of the third NAND gate is connected to the enable signal terminal of the multiplexer; The two input signals of the multiplexer are the error code and the feedback signal respectively, and when the output of the first NAND gate is at a high level, the multiplexer outputs the feedback signal, and when the output of the first NAND gate is at a low level, that is, when the error type signal is at a high level, the multiplexer outputs the error code; when the output of the third NAND gate is at a high level, the multiplexer is enabled, and when the output of the third NAND gate is at a low level, that is, when the enable type signal is at a high level, the multiplexer stops working; The decoder includes a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, an eighth D flip-flop, a ninth D flip-flop, a tenth D flip-flop, an eleventh D flip-flop, and a third inverter; the D input terminal of the fifth D flip-flop is connected to the power supply, the clock signal terminal is connected to the output of the isolation transmission path, and the output of the isolation transmission path corresponds to the output of the multiplexer. The reset signal terminal of the fifth D flip-flop is connected to the third timing signal; the D input terminal of the sixth D flip-flop is connected to the Q output terminal of the fifth D flip-flop, the clock signal terminal of the sixth D flip-flop is connected to the output of the isolation transmission path, and the reset signal terminal is connected to the third timing signal; the D input terminal of the seventh D flip-flop is connected to the Q output terminal of the sixth D flip-flop, the clock signal terminal of the seventh D flip-flop is connected to the output of the isolation transmission path, and the reset signal terminal is connected to the third timing signal. The Q output terminal of the seventh D flip-flop is the error class signal indication signal; the input terminal of the third inverter is connected to the output of the isolation transmission path; The D input terminal of the eighth D flip-flop is connected to the power supply, the clock signal terminal is connected to the reference clock signal, and the reset signal terminal is connected to the output terminal of the third inverter; The D input terminal of the ninth D flip-flop is connected to the Q output terminal of the eighth D flip-flop, the clock signal terminal of the ninth D flip-flop is connected to the reference clock signal, and the reset signal terminal is connected to the output terminal of the third inverter; The D input terminal of the tenth D flip-flop is connected to the Q output terminal of the ninth D flip-flop, the clock signal terminal of the tenth D flip-flop is connected to the reference clock signal, and the reset signal terminal is connected to the output terminal of the third inverter; the D input terminal of the eleventh D flip-flop is connected to the power supply, the clock signal terminal is connected to the fourth timing signal, and the reset signal terminal is connected to the Q output terminal of the tenth flip-flop. The Q output terminal of the eleventh D flip-flop is the indication signal of the enable class signal.

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