Comparator direct current offset background calibration circuit and implementation method

Abstract

The invention provides a comparator direct-current offset background calibration circuit and an implementation method, which are applied to the technical field of digital-analog mixed signals, and are characterized in that a logic difference circuit is used for extracting difference signals of the last two bits of an SAR ADC conversion period in real time, and an averaging circuit is combined for counting the polarity of the difference; a single-end calibration code word is generated and mapped into a complementary differential code word, finally, an offset calibration array is driven to dynamically adjust a direct-current offset compensation value of a Ping-Pong comparator until the offset difference of two paths is converged within a preset threshold value, additional calibration time slots or complex digital logic do not need to be added, and the offset compensation value of the Ping-Pong comparator can be adjusted only through a low-power-consumption digital circuit and a symmetric mapping rule. Therefore, the offset difference of the two comparators can be continuously eliminated at the background, the area and the power consumption are remarkably reduced, the signal-to-noise ratio and the significant digits of the system are improved, and high-precision and low-overhead direct-current offset real-time calibration is realized.

Description

Technical Field

[0001] This application relates to the field of digital-analog hybrid signal technology, and particularly to a comparator DC offset background calibration circuit and an implementation method thereof. Background Art

[0002] In the field of digital-analog hybrid signal technology, an Analog-Digital Converter (ADC) is a key component for realizing the conversion between analog signals and digital signals. Among them, the Successive-Approximation-Register ADC (SAR ADC) has been widely used in many applications due to its advantages such as simple structure, low power consumption, and high speed.

[0003] SAR ADC usually adopts a Ping-Pong comparator to improve the conversion speed. During the successive approximation process, the Ping and Pong comparators are alternately used, which can effectively save the comparator reset time to accelerate the conversion process. However, the DC offsets of the two comparators in the Ping-Pong comparator will deteriorate the quantization noise.

[0004] Currently, the common calibration technology is to add a time slot in the timing and a Charge Pump and an Auxiliary Differential-pair in the circuit for calibrating the two comparators simultaneously after the conversion ends. However, this calibration technology has the following problems:

[0005] First, the increase in the calibration time slot leads to an increase in the quantization time and a decrease in the sampling rate.

[0006] Second, the additional calibration circuit continuously tracks in the background, increasing the power consumption, area, and design complexity.

[0007] Based on this, a new comparator DC offset background calibration circuit and an implementation method are needed. Summary of the Invention

[0008] In view of this, the embodiments of this specification provide a comparator DC offset background calibration circuit and an implementation method, which can eliminate Digital Synthesis, with extremely low area and power consumption costs and achieve high precision.

[0009] The embodiments of this specification provide the following technical solutions:

[0010] An embodiment of this specification provides a comparator DC offset background calibration circuit, which is applied to the Ping-Pong comparator system in a successive approximation analog-to-digital converter, and includes: a difference circuit, an averaging circuit, a codeword generation circuit, a calibration codeword mapping circuit, and an offset calibration array;

[0011] The difference circuit is connected to the output end of the successive approximation analog-to-digital converter, and is used for performing a difference operation on the last two bits output in each conversion cycle to generate a difference signal;

[0012] The averaging circuit is connected to the difference circuit, and is used for performing a polarity statistic on the trigger event with the difference signal being 1, and outputting an average polarity signal;

[0013] The codeword generation circuit is connected to the averaging circuit, and is used for generating a single-ended calibration codeword according to the average polarity signal;

[0014] The calibration codeword mapping circuit is located between the codeword generation circuit and the offset calibration array, and is used for converting the single-ended calibration codeword into a complementary differential codeword;

[0015] The offset calibration array is respectively connected to the Ping comparator and the Pong comparator, receives the differential codeword, and adjusts the DC offset compensation values of the Ping comparator and the Pong comparator based on the differential codeword until the difference between the DC offset values of the Ping comparator and the Pong comparator is not greater than a preset threshold.

[0016] Preferably, the difference circuit includes an exclusive OR gate;

[0017] The input end of the exclusive OR gate receives the last two bits, and the output end outputs the difference signal;

[0018] When the last two bits are different, the difference signal outputs 1, triggers the averaging circuit, and selects the last bit as the polarity indication signal of the difference between the last two bits, and inputs it into the averaging circuit;

[0019] When the last two bits are the same, the difference signal outputs 0, and the averaging circuit does not perform a statistical operation.

[0020] Preferably, the averaging circuit includes: a first counter;

[0021] The first counter is used for counting the trigger events with the difference signal being 1;

[0022] When the difference signal is 1, perform an addition or subtraction operation on the first counter according to the polarity indication signal. After the statistics are completed, extract the sign bit of the first counter as the average polarity.

[0023] Preferably, the averaging circuit further includes: a frequency divider;

[0024] The frequency divider is used to set a statistical period, where the statistics include: a fixed value or a programmable frequency division mode;

[0025] When the number of statistical periods reaches a preset value, a jump clock is output, triggering the averaging circuit to complete the current statistical process and output an average value polarity.

[0026] Preferably, the codeword generation circuit includes: a second counter, which is used to accumulate or decrement according to the average value polarity signal output by the first counter to generate a single-ended calibration codeword.

[0027] Preferably, the calibration codeword mapping circuit performs the operation of converting the single-ended calibration codeword into a differential codeword according to a preset mapping rule, and the differential codeword includes: a positive branch codeword and a negative branch codeword, which are respectively used to control the DC offset calibration of the Ping comparator and the Pong comparator.

[0028] Preferably, the mapping rule includes:

[0029] Taking the median value of the single-ended codeword as the core, the codeword range is divided into two symmetric branch codewords. Through the complementary increase and decrease of the positive branch codeword and the negative branch codeword, the offset difference gradually converges from the extreme value to a preset threshold.

[0030] Preferably, the mapping rule is implemented through a mapping table; the mapping table stores the symmetric allocation relationship between the single-ended codeword and the differential codeword, and the difference of the differential codeword changes linearly with the single-ended codeword until it converges to zero.

[0031] Preferably, the offset calibration array includes: a decoding circuit and a timing synchronization circuit;

[0032] The decoding circuit is used to generate a corresponding calibration signal according to the differential codeword;

[0033] The timing synchronization circuit is used to transmit the updated differential codeword to the decoding circuit before the start of the conversion phase of the next cycle after each update of the differential codeword.

[0034] The embodiment of this specification also provides a calibration method for the DC offset background calibration circuit of a comparator, which is applied to the DC offset background calibration circuit of the comparator described in this application. The calibration method of the DC offset background calibration circuit of the comparator includes:

[0035] After the end of each conversion cycle of the successive approximation analog-to-digital converter, extract the last two bits output by the successive approximation analog-to-digital converter;

[0036] Input the last two bits into a difference circuit for difference processing to generate a difference signal;

[0037] When the difference signal is 1, trigger an averaging circuit to perform polarity statistics and output an average polarity signal;

[0038] Input the average polarity signal into a codeword generation circuit to generate a single-ended calibration codeword;

[0039] Input the single-ended calibration codeword into the calibration codeword mapping circuit to convert it into a complementary differential codeword;

[0040] Write the differential codewords into the offset calibration arrays of the Ping comparator and the Pong comparator respectively, adjust the DC offset compensation values of the Ping comparator and the Pong comparator respectively, and repeat the operation until the difference between the DC offset values of the Ping comparator and the Pong comparator is less than a preset threshold.

[0041] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of this specification at least include:

[0042] By using a logic difference circuit to extract the difference signal of the last two bits in the conversion cycle of the SAR ADC in real time, combining an averaging circuit to statistically analyze the difference polarity, generating a single-ended calibration codeword and mapping it into a complementary differential codeword, and finally driving the offset calibration array to dynamically adjust the DC offset compensation values of the Ping-Pong comparators until the offset difference between the two paths converges within the preset threshold, without adding additional calibration time slots or complex digital logic. Only through low-power digital circuits and symmetric mapping rules, the offset difference between the two comparators can be continuously eliminated in the background, significantly reducing the area and power consumption, improving the system signal-to-noise ratio and effective number of bits, and realizing high-precision and low-overhead real-time DC offset calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0044] Figure 1 is a schematic diagram of the statistical principle of the existing calibration scheme;

[0045] Figure 2 is a system block diagram in the present application;

[0046] Figure 3 is the decoding circuit of the DC offset calibration array in the present application;

[0047] Figure 4 is the ADC output spectrum before and after calibration in this application;

[0048] Figure 5 is the convergence curve of the DC offset in this application. Detailed implementation manners

[0049] The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0050] The following uses specific specific examples to illustrate the implementation manners of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. This application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of this application.

[0051] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be obvious that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on this application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects described herein can be used to implement the device and / or practice the method. Additionally, this device and / or this method can be implemented using other structures and / or functionality in addition to one or more of the aspects described herein.

[0052] It also needs to be noted that the drawings provided in the following embodiments only illustrate the basic concept of this application in a schematic manner. The drawings only show the components related to this application, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be an arbitrary change, and the component layout type may also be more complex.

[0053] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the examples can be practiced without these specific details.

[0054] In a successive approximation analog-to-digital converter (SAR ADC), using a Ping-Pong comparator is a common means to speed up the conversion. By alternately using two comparators, the conversion speed is increased. The principle is as follows: the successive approximation process is to make the residue voltage of the capacitive digital-to-analog converter (CDAC) gradually converge to 0. However, due to the existence of DC offset, this voltage will converge to the DC offset. If there are two DC offsets, Ping and Pong, at the quantization moments of the odd and even orders (corresponding to the Ping and Pong comparators respectively) during the conversion process, the convergence directions of the residues will diverge, resulting in an increase in quantization error and deterioration of the signal-to-noise ratio (SNR) and the effective number of bits (ENOB).

[0055] Currently, to solve these problems, in the existing solutions, one calibration scheme is to add a time slot in the timing after the conversion ends, and add a charge pump and an auxiliary differential pair in the circuit to calibrate the two comparators simultaneously. The specific calibration steps are as follows:

[0056] First, short-circuit the inputs of the two comparators and enable the comparators. Due to the existence of DC offset, the output polarity will be biased to one side;

[0057] Then, adjust the charge pump voltage according to the polarity and apply the voltage to the auxiliary differential pair to generate a reverse DC offset;

[0058] Finally, after the DC offset magnitude is canceled within one step, the comparator output will flip up and down between 0 and 1, and the calibration converges. The calibration operation needs to work in the background all the time to track the temperature drift of the DC offset.

[0059] However, this scheme requires the calibration circuit to continuously operate in the background to track the temperature drift, which not only increases the power consumption area but also improves the design complexity. At the same time, the added calibration time slot extends the quantization time and reduces the sampling rate.

[0060] The second scheme is based on statistical principles. By analyzing the statistical characteristics of the least significant bit of the SAR ADC, the offset difference is inferred. For example, reference [1] points out that: as Figure 1 shown, if the DC offsets of the Ping-Pong comparators are the same, then the top plate voltage of the SAR ADC (i.e., the residue) will only converge to the same DC offset value, and the overall presents a system DC offset that does not increase the quantization error, and the average values of the last two bits are both 0.5, which is equivalent to the coincidence of the instantaneous residue average values corresponding to these two bits.

[0061] If there are two different DC offsets, assuming Vos1 < Vos2 (label 1 represents the Ping comparator and 2 represents the Pong comparator), when the SAR ADC quantifies to the last two bits, the instantaneous residuals correspond to Vres1 and Vres2, and there should be Corresponding to ( (represents taking the statistical average of □). The above analysis is reversible, that is, Vos1 < Vos2 can be deduced conversely. The same is true for other cases and will not be elaborated here.

[0062] After obtaining the relative relationship of the DC offsets of the two comparators through the above statistical inequality, the offset calibration arrays of the two comparators are adjusted in the reverse direction to reduce the offset difference until it becomes 0. Finally, the two comparators reach the same DC offset.

[0063] Although the statistical principle is proposed, it fails to solve the engineering problems of calibration codeword mapping and dynamic convergence.

[0064] References:

[0065] [1]Tao, Y., et al. (2024). 22.4A 4.8GS / s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration. 2024 IEEE International Solid-State Circuits Conference (ISSCC).

[0066] In view of this, the inventors have found through research and improvement exploration that: during odd and even conversions, the residual voltage shifts in different directions due to offset differences, resulting in convergence divergence. In existing calibration schemes, some require adding extra calibration time slots, extending the quantization time, reducing the sampling rate, and the continuously operating charge pump and auxiliary differential pairs in the background significantly increase power consumption and area; some have difficulties in engineering the statistical principle.

[0067] Based on this, the embodiments of this specification propose a background calibration circuit for the DC offset of a comparator: as Figure 2As shown in the figure, the overall idea is as follows: The last two bits output in each conversion cycle of the SAR ADC are processed by a logical subtraction circuit to generate a difference signal. Subsequently, an averaging circuit performs a polarity statistic on the events where the difference signal is 1 to obtain an average polarity signal. The codeword generation circuit generates a single-ended calibration codeword based on this signal. Then, the calibration codeword mapping circuit converts the single-ended calibration codeword into a complementary differential codeword. Finally, the offset calibration array uses the differential codeword to adjust the DC offsets of the Ping and Pong comparators respectively until the difference between their offsets does not exceed a preset threshold, thereby realizing a high-precision background calibration function, significantly improving the system signal-to-noise ratio and effective number of bits, reducing the area and power consumption, and achieving high-precision and low-overhead real-time DC offset calibration.

[0068] The following will describe the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.

[0069] As Figure 2 shown, an embodiment of this specification provides a DC offset background calibration circuit for a comparator, which is applied to a Ping-Pong comparator system in a successive approximation analog-to-digital converter. It is characterized by including: a subtraction circuit, an averaging circuit, a codeword generation circuit, a calibration codeword mapping circuit, and an offset calibration array;

[0070] The subtraction circuit is connected to the output end of the successive approximation analog-to-digital converter and is used to perform a subtraction process on the last two bits output in each conversion cycle to generate a difference signal;

[0071] The averaging circuit is connected to the subtraction circuit and is used to perform a polarity statistic on the triggering events where the difference signal is 1 and output an average polarity signal;

[0072] The codeword generation circuit is connected to the averaging circuit and is used to generate a single-ended calibration codeword according to the average polarity signal;

[0073] The calibration codeword mapping circuit is located between the codeword generation circuit and the offset calibration array and is used to convert the single-ended calibration codeword into a complementary differential codeword;

[0074] The offset calibration array is respectively connected to the Ping comparator and the Pong comparator, receives the differential codeword, and adjusts the DC offset compensation values of the Ping comparator and the Pong comparator based on the differential codeword until the difference between the DC offset values of the Ping comparator and the Pong comparator is not greater than a preset threshold.

[0075] In implementation, after each conversion cycle of a successive approximation analog-to-digital converter (SAR ADC), the last two bits, namely the least significant bit (LSB) and the second least significant bit (LSB+1), are extracted. These bits are synchronized and latched by a conversion indication signal to ensure that the signals of the last two bits are captured at the correct time points.

[0076] The last two bits are input into a difference circuit to determine whether these two bits are different. Only when they are different is the output 1, indicating the influence of DC offset, and the output of the difference circuit is used as an asynchronous trigger clock for averaging, that is, when the output is 1, the data is statistically averaged.

[0077] And the least significant bit is selected as the polarity indication signal of the difference between these two bits and input into the averaging circuit to determine the direction of DC offset when calculating the subsequent statistical average value.

[0078] The calculated average value is passed to a codeword generation circuit to generate a single-ended calibration codeword. Before the single-ended calibration codeword is output to the Ping and Pong path comparators, it needs to go through codeword mapping, changing from a single-ended codeword to a differential codeword (differential P and N respectively correspond to the Ping comparator and the Pong comparator). The calibration codewords are respectively written into the DC offset calibration arrays of the Ping comparator and the Pong comparator to complete one iteration.

[0079] Repeat the iteration until the two DC offset values tend to be consistent, as Figure 5 shown.

[0080] In some embodiments, the difference circuit includes an exclusive OR gate;

[0081] The input terminals of the exclusive OR gate receive the last two bits, and the output terminal outputs the difference signal;

[0082] When the last two bits are different, the difference signal outputs 1, triggering the averaging circuit, and the least significant bit is selected as the polarity indication signal of the difference between the last two bits and input into the averaging circuit;

[0083] When the last two bits are the same, the difference signal outputs 0, and the averaging circuit does not perform statistical operations.

[0084] In implementation, as Figure 2 shown, the last two bits pass through an exclusive OR gate to obtain the absolute value of the difference result. If the result is 1, it is determined that the result of this cycle can be included in the averaged data. At this time, the LSB+1 bit is used to represent the difference polarity, and the pulse with a high exclusive OR is used as the input clock of the averaging counter.

[0085] In some embodiments, the averaging circuit includes: a first counter;

[0086] The first counter is used to count the trigger events where the difference signal is 1;

[0087] When the difference signal is 1, the first counter is incremented or decremented according to the polarity indication signal. After the counting is completed, the sign bit of the first counter is extracted as the average polarity.

[0088] In some embodiments, the statistical length for averaging is given by a selection circuit, which is similar to a frequency divider and is used to set the statistical period. In the N - frequency - division mode, an output clock for judging the average value is given every 2^N cycles. When the number of statistical periods reaches the target value, a jump clock is output, which is used to sample the output of the averaging counter, and the average value is 0 or 1. 0 represents a negative average value, and 1 represents a positive average value.

[0089] When the number of statistical periods reaches the preset value, a jump clock is output, triggering the averaging circuit to complete the current statistical process and output the average polarity.

[0090] For example, in the frequency - divider configuration: N = 1, the statistical period is 2^1 = 2 triggers, that is, an average value is output and the counter is reset every 2 accumulative triggers.

[0091] In some embodiments, the code - word generation circuit includes: a second counter (Up / Dn counter), which is used to increment or decrement according to the average - polarity signal output by the first counter to generate a single - ended calibration code - word.

[0092] In implementation, it can be that when the last bit = 0, the first counter is decremented by 1; when the last bit = 1, the first counter is incremented by 1.

[0093] In some embodiments, after the average polarity is determined, it is output to an accumulative counter 2, and 1 is added or subtracted from the previous result to generate a calibration code - word.

[0094] In some embodiments, the calibration code - word mapping circuit performs the operation of converting the single - ended calibration code - word into a differential code - word according to a preset mapping rule. The differential code - word includes: a positive - branch code - word and a negative - branch code - word, which are respectively used to control the DC offset calibration of the Ping comparator and the Pong comparator.

[0095] In some embodiments, the mapping rule includes: taking the median value of the single - ended code - word as the core, dividing the code - word range into two symmetric branch code - words, and through the complementary increase and decrease of the positive - branch code - word and the negative - branch code - word, the offset difference gradually converges to a preset threshold.

[0096] In some embodiments, the mapping rule is implemented through a mapping table; the mapping table stores the symmetric distribution relationship between the single - ended code - word and the differential code - word, and the difference of the differential code - word changes linearly with the single - ended code - word until it converges to zero.

[0097] During implementation, as Figure 3 shown, in represents a single-ended codeword, i.e., the original value of the calibration codeword; p represents a differential P codeword, i.e., the positive differential codeword after mapping; n represents a differential N codeword, i.e., the negative differential codeword after mapping; delta represents the difference between p and n; in bin represents the binary representation of in; p bin and n bin are the binary representations of p and n respectively.

[0098] The calibration codewords are respectively written into the DC offset calibration arrays of Ping and Pong to complete one iteration, and the iteration is repeated until the two DC offset values tend to be the same, as Figure 5 shown.

[0099] In some embodiments, the offset calibration array includes: a decoding circuit and a timing synchronization circuit;

[0100] The decoding circuit is used to generate corresponding calibration signals according to the differential codewords;

[0101] The timing synchronization circuit is used to transmit the updated differential codewords to the decoding circuit before the start of the conversion phase of the next cycle after each update of the differential codewords.

[0102] The decoding circuit controls the calibration arrays of the Ping and Pong comparators to generate specified DC offset compensation values respectively.

[0103] To verify the results, two different DC offsets [Vos1, Vos2] = [6.3m, -2.6m] are artificially added to a 10-bit SAR ADC circuit model based on a Ping-Pong comparator, and its spectrum is as Figure 4 shown, and the calibration circuit is implemented according to the implementation scheme described in the present invention.

[0104] Before calibration, the effective bit is 6.44 bits, and after calibration, the effective bit can reach 9.9 bits. Figure 5 Shows the convergence process of the DC offsets of the Ping / Pong two paths.

[0105] Based on the same inventive concept, the present application also provides a calibration method for a comparator DC offset background calibration circuit, which is characterized in that the comparator DC offset background calibration circuit described in claims 1-9 is applied, and the calibration method of the comparator DC offset background calibration circuit includes:

[0106] After each conversion cycle of the successive approximation analog-to-digital converter, extract the last two bits output by the successive approximation analog-to-digital converter;

[0107] Input the last two bits into a difference circuit for difference processing to generate a difference signal;

[0108] When the difference signal is 1, trigger the averaging circuit to perform polarity statistics and output an average polarity signal;

[0109] Input the average polarity signal into the codeword generation circuit to generate a single-ended calibration codeword;

[0110] Input the single-ended calibration codeword into the calibration codeword mapping circuit to convert it into a complementary differential codeword;

[0111] Write the differential codeword into the offset calibration arrays of the Ping comparator and the Pong comparator respectively, and adjust the DC offset compensation values of the Ping comparator and the Pong comparator respectively. Repeat the operation until the difference between the DC offset values of the Ping comparator and the Pong comparator is less than a preset threshold.

[0112] In this specification, for the same and similar parts among the various embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and for the relevant parts, reference can be made to the partial descriptions of the foregoing embodiments.

[0113] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A comparator DC offset background calibration circuit is applied to the Ping-Pong comparator system in a successive approximation analog-to-digital converter, characterized in that Comprising: A difference circuit, an averaging circuit, a codeword generation circuit, a calibration codeword mapping circuit, and an offset calibration array; The difference circuit is connected to the output end of the successive approximation analog-to-digital converter, and is used for performing a difference operation on the last two bits output in each conversion cycle to generate a difference signal; The averaging circuit is connected to the difference circuit, and is used for performing a polarity statistic on the trigger event with the difference signal being 1, and outputting an average polarity signal; The codeword generation circuit is connected to the averaging circuit, and is used for generating a single-ended calibration codeword according to the average polarity signal; The calibration codeword mapping circuit is located between the codeword generation circuit and the offset calibration array, and is used for converting the single-ended calibration codeword into a complementary differential codeword; The offset calibration array is respectively connected to the Ping comparator and the Pong comparator, receives the differential codeword, and adjusts the DC offset compensation values of the Ping comparator and the Pong comparator based on the differential codeword until the difference between the DC offset values of the Ping comparator and the Pong comparator is not greater than a preset threshold.

2. The comparator DC offset background calibration circuit according to claim 1, characterized in that The difference circuit includes an exclusive OR gate; The input end of the exclusive OR gate receives the last two bits, and the output end outputs the difference signal; When the last two bits are different, the difference signal is output as 1, triggering the averaging circuit, and selecting the last bit as the polarity indication signal of the difference between the last two bits, and inputting it into the averaging circuit; When the last two bits are the same, the difference signal is output as 0, and the averaging circuit does not perform a statistical operation.

3. The comparator DC offset background calibration circuit according to claim 2, characterized in that The averaging circuit includes: a first counter; The first counter is used for counting the trigger events with the difference signal being 1; When the difference signal is 1, the first counter is incremented or decremented according to the polarity indication signal. After the statistics are completed, the sign bit of the first counter is extracted as the average polarity.

4. The comparator DC offset background calibration circuit according to claim 3, characterized in that, The averaging circuit further includes: a frequency divider; The frequency divider is used for setting a statistical period, wherein the statistics include: a fixed value or a programmable frequency division mode; When the number of statistical periods reaches a preset value, a jump clock is output, triggering the averaging circuit to complete the current statistical process, and outputting an average polarity.

5. The comparator DC offset background calibration circuit according to claim 1, wherein The codeword generation circuit includes: a second counter, which is used for incrementing or decrementing according to the average polarity signal output by the first counter to generate a single-ended calibration codeword.

6. The comparator DC offset background calibration circuit according to claim 1, wherein The calibration codeword mapping circuit performs the operation of converting the single-ended calibration codeword into a differential codeword according to a preset mapping rule. The differential codeword includes: a positive branch codeword and a negative branch codeword, which are respectively used for controlling the DC offset calibration of the Ping comparator and the Pong comparator.

7. The comparator DC offset background calibration circuit according to claim 6, characterized in that, The mapping rule includes: Taking the median value of the single-ended codeword as the core, dividing the codeword range into two symmetric branch codewords, and through the complementary increase and decrease of the positive branch codeword and the negative branch codeword, making the offset difference gradually converge to a preset threshold from an extreme value.

8. The comparator DC offset background calibration circuit according to claim 6, characterized in that, The mapping rule is implemented through a mapping table; The mapping table stores the symmetric allocation relationship between the single-ended codeword and the differential codeword, and the difference of the differential codeword changes linearly with the single-ended codeword until it converges to zero.

9. The comparator DC offset background calibration circuit according to claim 1, wherein The offset calibration array includes: a decoding circuit and a timing synchronization circuit; The decoding circuit is configured to generate a corresponding calibration signal according to the differential codeword; The timing synchronization circuit is configured to transmit the updated differential codeword to the decoding circuit before the start of the conversion phase of the next cycle after each update of the differential codeword.

10. A calibration method for a comparator DC offset background calibration circuit, characterized in that, Applying the comparator DC offset background calibration circuit according to claims 1-9, the calibration method of the comparator DC offset background calibration circuit includes: After the end of each conversion cycle of the successive approximation analog-to-digital converter, extract the last two bits output by the successive approximation analog-to-digital converter; Input the last two bits into a difference circuit for difference processing to generate a difference signal; When the difference signal is 1, trigger an averaging circuit to perform polarity statistics and output an average polarity signal; Input the average polarity signal into a codeword generation circuit to generate a single-ended calibration codeword; Input the single-ended calibration codeword into the calibration codeword mapping circuit to convert it into a complementary differential codeword; Write the differential codeword into the offset calibration arrays of the Ping comparator and the Pong comparator respectively, and adjust the DC offset compensation values of the Ping comparator and the Pong comparator respectively. Repeat the operation until the difference between the DC offset values of the Ping comparator and the Pong comparator is less than a preset threshold.

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