Low-stress high-temperature pressure sensor chip and processing method

Abstract

The invention relates to the technical field of pressure sensors, in particular to a low-stress high-temperature pressure sensor chip and a processing method thereof, and the low-stress high-temperature pressure sensor chip comprises a silicon carbide epitaxial wafer, a passivation layer, a metal electrode layer and a silicon carbide sealing wafer. An n-type silicon carbide device layer, a p-type silicon carbide isolation layer and an n-type silicon carbide substrate layer in the silicon carbide epitaxial wafer are sequentially connected from top to bottom; the n-type silicon carbide device layer is etched to form an n-type silicon carbide pressure sensitive resistor, a sealing region and an isolation channel; the passivation layer comprises a silicon dioxide layer and a silicon nitride layer, and the silicon dioxide layer and the silicon nitride layer are provided with stress release regions; the bottom of the n-type silicon carbide substrate layer is etched to form a pressure cavity, the p-type silicon carbide isolation layer and the n-type silicon carbide substrate layer in an area right above the pressure cavity form a pressure sensitive diaphragm, and the stress release area is arranged on the upper surface of the pressure sensitive diaphragm, so that the problem of low reliability of the low-stress high-temperature pressure sensor chip is solved.

Description

Technical Field

[0001] The present application relates to the technical field of pressure sensors, and particularly relates to a low-stress high-temperature pressure sensor chip and a processing method thereof. Background Art

[0002] Microelectromechanical system (MEMS) pressure sensors based on silicon carbide materials exhibit key application values under extreme high-temperature working conditions. Especially in scenarios such as high-temperature gas monitoring in aerospace propulsion systems, downhole tool measurement and control in deep-earth resource exploration, and pressure feedback in nuclear reactor cooling circuits, sensors are required to work stably for a long time in an environment above 500°C. Such applications pose dual requirements for pressure-sensitive elements: they must withstand the harsh working conditions of high-temperature oxidation and thermal shock, and at the same time ensure the accurate conversion of deformation signals of sensitive structures within a wide temperature range.

[0003] To solve the problems of dielectric protection and electrical stability in high-temperature environments, in related technologies, a silicon dioxide / silicon nitride composite passivation layer structure is adopted. Among them, the silicon nitride layer realizes mechanical protection and electrical isolation with a hardness of 9.5 GPa and a resistivity of >10 9 Ω·cm. The silicon dioxide layer increases the dielectric breakdown field strength to 8 MV / cm by filling lattice defects, and at the same time can reduce the leakage current caused by particle contamination by two orders of magnitude.

[0004] However, the difference in the thermal expansion coefficients of silicon carbide and the passivation layer material results in significant film stress within a wide temperature range from -55°C to 600°C. This stress is transmitted to the pressure-sensitive resistor, causing abnormal changes in the resistance value and seriously affecting the stability of the sensor output signal. Especially in low-range pressure measurements, the film stress has a more prominent interference on the deformation of the sensitive diaphragm, becoming the core problem restricting the reliability of high-temperature pressure sensors. Summary of the Invention

[0005] The present application provides a low-stress high-temperature pressure sensor chip and a processing method thereof to solve the problem of low reliability of low-stress high-temperature pressure sensor chips.

[0006] The first aspect of the present application provides a low-stress high-temperature pressure sensor chip, including: a silicon carbide epitaxial wafer, a passivation layer, a metal electrode layer, and a silicon carbide sealing wafer; The silicon carbide epitaxial wafer includes an n-type silicon carbide device layer, a p-type silicon carbide isolation layer, and an n-type silicon carbide substrate layer, and the n-type silicon carbide device layer, the p-type silicon carbide isolation layer, and the n-type silicon carbide substrate layer are connected in sequence from top to bottom; The n-type silicon carbide device layer is etched to form an n-type silicon carbide pressure-sensitive resistor, a sealing area, and an isolation channel; wherein, the n-type silicon carbide pressure-sensitive resistor is isolated from the sealing area through the isolation channel; The passivation layer includes a silicon dioxide layer and a silicon nitride layer. The silicon dioxide layer is located on the upper surfaces of the n-type silicon carbide pressure sensor resistor and the isolation channel, and the silicon nitride layer is located on the upper surface of the silicon dioxide layer. Stress relief regions are provided on the silicon dioxide layer and the silicon nitride layer. The bottom of the n-type silicon carbide substrate layer is etched to form a pressure cavity. The p-type silicon carbide isolation layer and the n-type silicon carbide substrate layer in the region directly above the pressure cavity form a pressure sensor diaphragm, and the stress relief regions are provided on the upper surface of the pressure sensor diaphragm. The metal electrode layer is provided on the sealing region and is electrically connected to the n-type silicon carbide pressure sensor resistor. The silicon carbide sealing wafer is bonded to the top of the silicon carbide epitaxial wafer.

[0007] Silicon dioxide and silicon nitride are grown on the surface of the pressure sensor chip as the passivation layer. In terms of physical protection, it can prevent mechanical damage and contaminants; in terms of chemical protection, it can resist moisture, ion migration, and acid-base corrosion; in terms of electrical protection, it provides insulation, suppresses leakage current, and stabilizes interface states; in terms of thermal protection, it matches the coefficient of thermal expansion and can withstand high-temperature environments; in terms of long-term reliability, it delays metal migration and structural aging. At the same time, stress relief regions are respectively provided along the edge of the pressure sensor diaphragm and the edge of the n-type silicon carbide pressure sensor resistor on the passivation layer of the pressure sensor diaphragm, removing part of the silicon dioxide layer and the silicon nitride layer, which can release the film stress brought by the large-area passivation layer, significantly reducing the influence of the film stress on the pressure sensor chip, thereby improving the stability and reliability of the chip.

[0008] Optionally, the silicon carbide epitaxial wafer is a double-polished wafer with a thickness of 300 μm - 500 μm; the thickness of the n-type silicon carbide device layer is 200 nm - 2 μm, and the doping concentration of the n-type silicon carbide device layer is 1E19 cm -3 ~3E20 cm -3 ; the thickness of the p-type silicon carbide isolation layer is 2 μm - 10 μm, and the doping concentration of the p-type silicon carbide isolation layer is 3E15 cm -3 ~3E18 cm -3 ; the thickness of the silicon dioxide layer is 50 nm - 200 nm; the thickness of the silicon nitride layer is 50 nm - 200 nm; the thickness of the metal electrode layer is 500 nm - 1 μm; the thickness of the pressure sensor diaphragm is 50 μm - 200 μm.

[0009] The silicon carbide epitaxial wafer adopts a double-polished wafer structure with a thickness controlled within the range of 300 μm - 500 μm. Among them, the thickness of the n-type silicon carbide device layer is 200 nm - 2 μm and the doping concentration is 1E19 cm -3 ~3E20 cm -3The thickness of the p-type silicon carbide isolation layer is 2μm~10μm and the doping concentration is 3E15cm -3 ~3E18cm -3 , combined with a silicon dioxide layer and a silicon nitride layer with a thickness of 50nm~200nm, a metal electrode layer with a thickness of 500nm~1μm, and a pressure-sensitive diaphragm with a thickness of 50μm~200μm, this structural design helps to optimize the carrier transport characteristics, improve the uniformity of stress distribution, reduce the interface defect density, and improve the working stability of the device in high temperature and high pressure environments, while ensuring the mechanical strength and sensitivity of the pressure-sensitive diaphragm.

[0010] Optionally, the number of the n-type silicon carbide pressure sensitive resistors is four, and the four n-type silicon carbide pressure sensitive resistors are distributed along the four sides of the pressure sensitive diaphragm. The four n-type silicon carbide pressure sensitive resistors are isolated from each other by the isolation channel and form a closed bridge Wheatstone bridge.

[0011] Four n-type silicon carbide pressure-sensitive resistors are distributed around the pressure-sensitive diaphragm, isolated from each other by isolation channels and forming a closed-bridge Wheatstone bridge. The differential output structure is used to enhance sensitivity and achieve temperature self-compensation, thereby accurately detecting tiny resistance changes. The symmetrical design helps to alleviate common-mode interference and improve measurement stability in complex environments. Its micromachining process compatibility facilitates integration into micro-sensor systems, while providing conditions for hardware compensation and algorithm optimization to improve overall accuracy.

[0012] Optionally, the stress release region is formed by etching the silicon dioxide layer and the silicon nitride layer, and the stress release region is distributed in a ring shape at an edge region of the pressure sensitive diaphragm or around the n-type silicon carbide pressure sensitive resistor.

[0013] The stress release area is formed by etching the silicon dioxide layer and the silicon nitride layer, and is distributed in a ring structure at the edge area of the pressure-sensitive diaphragm or around the n-type silicon carbide pressure-sensitive resistor. It helps to alleviate stress concentration between materials, improve the mechanical stability of the sensor, and reduce the interface stress caused by differences in thermal expansion coefficients, thereby improving the long-term reliability and measurement accuracy of the device.

[0014] Optionally, the stress release zone includes a plurality of concentric annular regions. If there are multiple concentric annular regions, the interval between two adjacent concentric annular regions is 10 μm-50 μm, and the width of each concentric annular region is 20 μm-200 μm.

[0015] The stress release zone adopts a structure of multiple concentric annular areas, with the interval between adjacent annular areas being 10μm-50μm and the width of each annular area being 20μm-200μm. This can optimize the local film stress distribution of the n-type silicon carbide pressure sensitive resistor, alleviate stress concentration, improve the stress matching characteristics of the sensor, thereby reducing measurement errors caused by uneven stress, and at the same time enhance the structural reliability and long-term stability of the device.

[0016] Optionally, a through hole is formed on the silicon carbide sealing wafer near the metal electrode layer; and a blind groove is formed on the silicon carbide sealing wafer near the pressure sensitive diaphragm.

[0017] The silicon carbide sealing wafer is provided with a through hole near the metal electrode layer to facilitate filling with conductive paste to realize electrical signal transmission. At the same time, a blind groove is opened near the pressure-sensitive diaphragm to provide deformation space for the pressure-sensitive diaphragm. This structural design helps to improve the reliability of signal transmission, reduce the impact of packaging stress on sensitive components, and improve the sensor's detection accuracy of tiny deformations.

[0018] A second aspect of the present application provides a low-stress, high-temperature pressure sensor chip processing method, which is used to process the low-stress, high-temperature pressure sensor chip described in the first aspect. The method comprises: An npn double-throw silicon carbide epitaxial wafer is selected as the silicon carbide epitaxial wafer to be processed; wherein the top layer of the silicon carbide epitaxial wafer is an n-type silicon carbide device layer; the middle layer of the silicon carbide epitaxial wafer is a p-type silicon carbide isolation layer; and the bottom layer of the silicon carbide epitaxial wafer is an n-type silicon carbide substrate layer; Etching the n-type silicon carbide device layer using an inductively coupled plasma etching process or a reactive ion etching process to form an n-type silicon carbide pressure sensitive resistor, a sealing area, and an isolation channel; preparing a silicon dioxide layer and a silicon nitride layer on the upper surface of the silicon carbide epitaxial wafer by chemical vapor deposition; Etching the silicon nitride layer and the silicon dioxide layer by using one or a combination of inductively coupled plasma etching, reactive ion etching, and wet etching to form a stress relief area; forming a metal electrode layer on the sealing area by electron beam evaporation; Etching the bottom of the n-type silicon carbide substrate layer using a deep silicon carbide etching process to form a pressure cavity; A silicon carbide sealing wafer is sealed on top of the silicon carbide epitaxial wafer.

[0019] On the basis of including all the beneficial effects of the low-stress high-temperature pressure sensor chip described in the first aspect, the above processing method selects an n-p-n type double-polished silicon carbide epitaxial wafer as the substrate, and uses inductively coupled plasma etching or reactive ion etching process to form an n-type silicon carbide pressure-sensitive resistor and isolation channels. It combines chemical vapor deposition to prepare silicon dioxide and silicon nitride layers, then forms a stress release area through an etching process, and uses electron beam evaporation to fabricate a metal electrode layer. Finally, deep silicon carbide etching is performed to form a pressure cavity and bond it to a silicon carbide sealing wafer, which helps to reduce the influence of thermal stress during the processing, improve the stress matching between device layers, enhance the stability of the sensor in a high-temperature environment, and at the same time ensure a reliable connection between the n-type silicon carbide pressure-sensitive resistor and the electrode, enhancing the overall performance of the chip.

[0020] Optionally, the etching gas for the inductively coupled plasma etching process and the reactive ion etching process is at least one of tetrafluoromethane, sulfur hexafluoride, and trifluoromethane; the assist gas for the inductively coupled plasma etching process and the reactive ion etching process is at least one of oxygen, argon, and nitrogen, and the volume ratio of tetrafluoromethane is 60%-80%.

[0021] Using at least one of tetrafluoromethane, sulfur hexafluoride, and trifluoromethane as the main etching gas, combined with oxygen, argon, or nitrogen as the assist gas, with the volume ratio of tetrafluoromethane controlled at 60%-80%, by regulating the gas component concentration gradient of the plasma chemical reaction, optimizing the free radical transport path and ion bombardment energy, an etching process with high anisotropy characteristics is formed, which can achieve precise control of sub-micron feature sizes, thereby improving the stability and accuracy of the etching process.

[0022] Optionally, the wet etching process uses a buffered oxide etchant, and the buffered oxide etchant is prepared by mixing a 40% ammonium fluoride solution and a 49% hydrofluoric acid solution in a volume ratio of 6:1.

[0023] The wet etching process uses a buffered oxide etchant prepared by mixing a 40% ammonium fluoride solution and a 49% hydrofluoric acid solution in a volume ratio of 6:1, which can adjust the etching rate and reaction activity, improve the stability of the etching process, reduce the risk of over-etching caused by too high a hydrofluoric acid concentration, and at the same time helps to obtain a more uniform etched surface morphology, improving the controllability and repeatability of the etching process.

[0024] Optionally, the process gas for the deep silicon carbide etching process is one or more of octafluorocyclobutane, tetrafluoromethane, sulfur hexafluoride, oxygen, and argon, and the etching mask for the deep silicon carbide etching process is metallic nickel.

[0025] The deep silicon carbide etching process uses one or more of perfluorocyclobutane, tetrafluoromethane, sulfur hexafluoride, oxygen, and argon as process gases, and uses metallic nickel as an etching mask. This combination can optimize the etching selectivity and etching rate of silicon carbide materials, improve the perpendicularity of the etched sidewalls and the surface roughness, thereby reducing device damage during etching, improving the structural accuracy and dimensional consistency of the pressure chamber, and facilitating enhancing the performance stability of the sensor.

[0026] As can be seen from the above technical solutions, the present application provides a low-stress high-temperature pressure sensor chip and a processing method. The chip includes: a silicon carbide epitaxial wafer, a passivation layer, a metal electrode layer, and a silicon carbide bonding wafer; the silicon carbide epitaxial wafer includes an n-type silicon carbide device layer, a p-type silicon carbide isolation layer, and an n-type silicon carbide substrate layer, and the n-type silicon carbide device layer, the p-type silicon carbide isolation layer, and the n-type silicon carbide substrate layer are connected in sequence from top to bottom; the n-type silicon carbide device layer is etched to form an n-type silicon carbide pressure-sensitive resistor, a bonding region, and an isolation channel; wherein, the n-type silicon carbide pressure-sensitive resistor is isolated from the bonding region through the isolation channel; the passivation layer includes a silicon dioxide layer and a silicon nitride layer, the silicon dioxide layer is located on the upper surfaces of the n-type silicon carbide pressure-sensitive resistor and the isolation channel, the silicon nitride layer is located on the upper surface of the silicon dioxide layer, and stress release regions are formed on the silicon dioxide layer and the silicon nitride layer; the bottom of the n-type silicon carbide substrate layer is etched to form a pressure chamber, and the p-type silicon carbide isolation layer and the n-type silicon carbide substrate layer in the region directly above the pressure chamber constitute a pressure-sensitive diaphragm, and the stress release regions are arranged on the upper surface of the pressure-sensitive diaphragm; the metal electrode layer is arranged on the bonding region, and the metal electrode layer is electrically connected to the n-type silicon carbide pressure-sensitive resistor; the silicon carbide bonding wafer is bonded to the top of the silicon carbide epitaxial wafer to solve the problem of low reliability of the low-stress high-temperature pressure sensor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0028] Figure 1 The planar process plate in the low-stress high-temperature pressure sensor chip processing method provided by the embodiment of the present application Figure 1 ; Figure 2 The planar process plate in the low-stress high-temperature pressure sensor chip processing method provided by the embodiment of the present application Figure 2 ; Figure 3Schematic diagram of the structure of a silicon carbide epitaxial wafer in the processing method of a low-stress high-temperature pressure sensor chip provided by an embodiment of the present application; Figure 4 Schematic diagram of the structure for forming a pressure-sensitive resistor, a sealing area, and an isolation channel in the processing method of a low-stress high-temperature pressure sensor chip provided by an embodiment of the present application; Figure 5 Schematic diagram of the structure for forming a passivation layer in the processing method of a low-stress high-temperature pressure sensor chip provided by an embodiment of the present application; Figure 6 Schematic diagram of the structure for forming a stress release area in the processing method of a low-stress high-temperature pressure sensor chip provided by an embodiment of the present application; Figure 7 Schematic diagram of the structure for forming a metal electrode layer in the processing method of a low-stress high-temperature pressure sensor chip provided by an embodiment of the present application; Figure 8 Schematic diagram of the structure for forming a pressure cavity in the processing method of a low-stress high-temperature pressure sensor chip provided by an embodiment of the present application; Figure 9 Schematic diagram of the structure after bonding a silicon carbide sealing wafer and a silicon carbide epitaxial wafer in the processing method of a low-stress high-temperature pressure sensor chip provided by an embodiment of the present application.

[0029] Illustration: Among them, 1 - n-type silicon carbide device layer; 2 - p-type silicon carbide isolation layer; 3 - n-type silicon carbide substrate layer; 4 - n-type silicon carbide pressure-sensitive resistor; 5 - sealing area; 6 - isolation channel; 7 - silicon dioxide layer; 8 - silicon nitride layer; 9 - stress release area; 10 - metal electrode layer; 11 - pressure cavity; 12 - pressure-sensitive diaphragm; 13 - silicon carbide sealing wafer. Detailed implementation manners

[0030] Hereinafter, the embodiments will be described in detail, and the examples are shown in the drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following embodiments do not represent all implementation manners consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application.

[0031] Microelectromechanical system (MEMS) pressure sensors based on silicon carbide materials exhibit key application values under extreme high-temperature working conditions. Especially in scenarios such as high-temperature gas monitoring in aerospace propulsion systems, downhole tool measurement and control in deep-earth resource exploration, and pressure feedback in nuclear reactor cooling circuits, sensors are required to work stably for a long time in an environment above 500 °C. Such applications pose dual requirements for pressure-sensitive elements: they must withstand the harsh working conditions of high-temperature oxidation and thermal shock, and ensure the accurate conversion of deformation signals of sensitive structures within a wide temperature range.

[0032] To solve the problems of medium protection and electrical stability in high-temperature environments, in related embodiments, a silicon dioxide / silicon nitride composite passivation layer structure is adopted. Among them, the silicon nitride layer achieves mechanical protection and electrical isolation with a hardness of 9.5 GPa and a resistivity of >10 9 Ω·cm. The silicon dioxide layer raises the dielectric breakdown field strength to 8 MV / cm by filling lattice defects, and at the same time can reduce the leakage current caused by particle contamination by two orders of magnitude. However, the difference in the thermal expansion coefficients of silicon carbide and the passivation layer material results in significant film stress in the wide temperature range from -55°C to 600°C. This stress is transmitted to the pressure-sensitive resistor, causing abnormal changes in the resistance value and seriously affecting the stability of the sensor output signal. Especially in low-range pressure measurements, the deformation interference of the film stress on the sensitive diaphragm is more prominent, becoming the core problem restricting the reliability of high-temperature pressure sensors.

[0033] To solve the problem of low reliability of low-stress high-temperature pressure sensor chips, refer to Figures 1-9 , some embodiments of the present application provide a low-stress high-temperature pressure sensor chip, including: a silicon carbide epitaxial wafer, a passivation layer, a metal electrode layer 10, and a silicon carbide sealing wafer 13; the silicon carbide epitaxial wafer includes an n-type silicon carbide device layer 1, a p-type silicon carbide isolation layer 2, and an n-type silicon carbide substrate layer 3, and the n-type silicon carbide device layer 1, the p-type silicon carbide isolation layer 2, and the n-type silicon carbide substrate layer 3 are connected in sequence from top to bottom; the n-type silicon carbide device layer 1 is etched to form an n-type silicon carbide pressure-sensitive resistor 4, a sealing area 5, and an isolation channel 6; wherein, the n-type silicon carbide pressure-sensitive resistor 4 is isolated from the sealing area 5 through the isolation channel 6.

[0034] It should be understood that both the silicon carbide epitaxial wafer and the silicon carbide sealing wafer 13 of the sensor chip adopt 4H-silicon carbide materials. The n-type silicon carbide pressure-sensitive resistor 4 and the p-type silicon carbide isolation layer 2 are electrically isolated through a PN junction and can be applied to high-temperature environments above 600°C.

[0035] The passivation layer includes a silicon dioxide layer 7 and a silicon nitride layer 8. The silicon dioxide layer 7 is located on the upper surfaces of the n-type silicon carbide pressure-sensitive resistor 4 and the isolation channel 6, the silicon nitride layer 8 is located on the upper surface of the silicon dioxide layer 7, and stress release areas 9 are provided on the silicon dioxide layer 7 and the silicon nitride layer 8.

[0036] It should be understood that the passivation layer is designed with a composite dielectric structure. Among them, the silicon dioxide layer 7 is directly grown on the surface of the silicon carbide epitaxial wafer by chemical vapor deposition and completely covers the sensitive area of the n-type silicon carbide pressure-sensitive resistor 4 to achieve carrier migration inhibition and surface state defect repair; the silicon nitride layer 8 is deposited on the surface of the silicon dioxide layer 7 by chemical vapor deposition to enhance the passivation and isolation protection of the passivation layer. In terms of physical protection, the passivation layer can prevent mechanical damage and pollutants; in terms of chemical protection, it can resist moisture, ion migration, and acid-base corrosion; in terms of electrical protection, it can insulate, inhibit leakage current, and stabilize interface states; in terms of thermal protection, it can match the thermal expansion coefficient and withstand high-temperature environments; in terms of long-term reliability, it can delay metal migration and structural aging.

[0037] A pressure cavity 11 is etched at the bottom of the n-type silicon carbide substrate layer 3. The p-type silicon carbide isolation layer 2 and the n-type silicon carbide substrate layer 3 in the area directly above the pressure cavity 11 form a pressure-sensitive diaphragm 12. The stress release area 9 is arranged on the upper surface of the pressure-sensitive diaphragm 12 to sense external pressure signals.

[0038] It should be understood that the cross-section of the pressure cavity 11 is rectangular. The pressure cavity 11 is prepared by a deep silicon carbide etching process, which has the characteristics of low cost, batch production, and good consistency. The stress release area 9 is arranged on the pressure-sensitive diaphragm 12, and at the same time, no passivation layer is arranged in the stress release area 9 to solve the film layer stress mismatch existing in the pressure sensor chip, reduce the influence of the film layer stress on the pressure sensor chip, and improve the reliability and stability of the pressure sensor chip; at the same time, no passivation layer is arranged in the sealing area 5 to avoid the influence of the passivation layer on the sealing effect. By removing part of the silicon dioxide layer 7 and the silicon nitride layer 8 in the stress release area 9, the film layer stress brought by the large-area passivation layer can be released, significantly reducing the influence of the film layer stress on the pressure sensor chip, thereby improving the stability and reliability of the chip.

[0039] The metal electrode layer 10 is arranged on the sealing area 5, and the metal electrode layer 10 is electrically connected to the n-type silicon carbide pressure-sensitive resistor 4; the silicon carbide sealing wafer 13 is bonded to the top of the silicon carbide epitaxial wafer.

[0040] It should be understood that the silicon carbide sealing wafer 13 and the silicon carbide epitaxial wafer are front-bonded to form a positive packaging structure, which can realize a leadless packaging structure of the sensor, improve the natural frequency of the sensor, reduce the size of the whole sensor, and at the same time can increase the application temperature of the sensor to above 400°C.

[0041] Silicon dioxide and silicon nitride are grown on the surface of the pressure sensor chip as a passivation layer. In terms of physical protection, it can prevent mechanical damage and contaminants; in terms of chemical protection, it can resist moisture, ion migration, and acid-base corrosion; in terms of electrical protection, it provides insulation, suppresses leakage current, and stabilizes interface states; in terms of thermal protection, it matches the coefficient of thermal expansion and withstands high-temperature environments; in terms of long-term reliability, it delays metal migration and structural aging. At the same time, stress release regions 9 are respectively arranged along the edge of the pressure-sensitive diaphragm 12 and the edge of the n-type silicon carbide pressure-sensitive resistor 4 on the passivation layer of the pressure-sensitive diaphragm 12, removing part of the silicon dioxide layer 7 and silicon nitride layer 8, which can release the film stress brought by the large-area passivation layer, significantly reduce the influence of the film stress on the pressure sensor chip, and thus improve the stability and reliability of the chip.

[0042] In some embodiments, the silicon carbide epitaxial wafer is a double-polished wafer, and the thickness of the silicon carbide epitaxial wafer is 300 μm - 500 μm; The thickness of the n-type silicon carbide device layer 1 is 200 nm - 2 μm, and the doping concentration of the n-type silicon carbide device layer 1 is 1E19 cm -3 ~3E20 cm -3 ; the thickness of the p-type silicon carbide isolation layer 2 is 2 μm - 10 μm, and the doping concentration of the p-type silicon carbide isolation layer 2 is 3E15 cm -3 ~3E18 cm -3 。

[0043] It should be understood that the n-type silicon carbide device layer 1 with a thickness of 200 nm - 2 μm and a doping concentration of 1E19 cm -3 ~3E20 cm -3 can ensure the thickness of the n-type silicon carbide pressure-sensitive resistor 4 and the sensitivity output of the chip; the p-type silicon carbide isolation layer 2 with a thickness of 2 μm - 10 μm and a doping concentration of 3E15 cm -3 ~3E18 cm -3 can ensure sufficient breakdown voltage and isolation effect when formed with the n-type silicon carbide device layer 1.

[0044] In some embodiments, the thickness of the silicon dioxide layer 7 is 50 nm - 200 nm; the thickness of the silicon nitride layer 8 is 50 nm - 200 nm.

[0045] It should be understood that the silicon dioxide layer 7 with a thickness range of 50 nm - 200 nm can solidify the mobile ions and interface defects at the silicon carbide and silicon dioxide interface, resist micro-mechanical scratches and particle impacts, form a smooth interface layer with a surface roughness <5 nm, and effectively reduce the stress concentration coefficient to below 0.3; the silicon nitride layer 8 with a thickness range of 50 nm - 200 nm can enhance the protection of the device layer, block H2O, Cl -Penetration of corrosive media is prevented, the insulation barrier is enhanced, and the leakage current is reduced.

[0046] In some embodiments, the thickness of the metal electrode layer 10 is 500 nm to 1 μm; the thickness of the pressure-sensitive diaphragm 12 is 50 μm to 200 μm.

[0047] It should be understood that the thickness of the pressure-sensitive diaphragm 12 of 50 μm to 200 μm can cover chips with a range specification of 100 kPa - 100 MPa, achieving a high sensitivity output and meeting the application requirements of different scenarios.

[0048] In some embodiments, the number of the n-type silicon carbide pressure-sensitive resistors 4 is four. The four n-type silicon carbide pressure-sensitive resistors 4 (R1, R2, R3, R4) are distributed along the perimeter of the pressure-sensitive diaphragm 12. The four n-type silicon carbide pressure-sensitive resistors 4 are isolated from each other through the isolation channels 6 and form a Wheatstone bridge in a closed-bridge form.

[0049] It should be understood that when an external pressure acts on the pressure-sensitive diaphragm 12, the pressure-sensitive diaphragm 12 undergoes a slight deformation, transferring the pressure to the n-type silicon carbide pressure-sensitive resistor 4, and further causing the Wheatstone bridge to generate an electrical signal that varies with the pressure.

[0050] Four n-type silicon carbide pressure-sensitive resistors 4 distributed along the perimeter of the pressure-sensitive diaphragm 12 are isolated from each other through the isolation channels 6 and form a Wheatstone bridge in a closed-bridge form. The differential output structure is used to improve the sensitivity and achieve temperature self-compensation, thereby accurately detecting minute resistance changes; the symmetric design helps to mitigate common-mode interference and improve the measurement stability in complex environments. Its compatibility with microfabrication processes facilitates integration into a micro sensor system, and at the same time provides conditions for hardware compensation and algorithm optimization to improve the overall accuracy.

[0051] In some embodiments, the stress release region 9 is formed by etching the silicon dioxide layer 7 and the silicon nitride layer 8. The stress release region 9 is annularly distributed in the edge region of the pressure-sensitive diaphragm 12 or around the n-type silicon carbide pressure-sensitive resistor 4.

[0052] Specifically, in some embodiments, as Figure 1 shown, the stress release region 9 is located on the pressure-sensitive diaphragm 12 and extends inward sequentially along the edge of the pressure-sensitive diaphragm 12, being annularly distributed, for optimizing the overall film stress of the pressure-sensitive diaphragm 12.

[0053] In some other embodiments, as Figure 2 shown, the stress release region 9 is located on the pressure-sensitive diaphragm 12 and extends outward sequentially along the edge of the n-type silicon carbide pressure-sensitive resistor 4, being annularly distributed, for optimizing the local film stress of the n-type silicon carbide pressure-sensitive resistor 4.

[0054] The stress release region 9 is formed by etching the silicon dioxide layer 7 and the silicon nitride layer 8, and is distributed in a ring structure at the edge area of the pressure sensitive diaphragm 12 or around the n-type silicon carbide pressure sensitive resistor 4, which helps to relieve stress concentration between materials, improve the mechanical stability of the sensor, and reduce the interface stress caused by the difference in thermal expansion coefficient, thereby improving the long-term reliability and measurement accuracy of the device.

[0055] In some embodiments, the stress release zone 9 includes a plurality of concentric annular regions. If there are multiple concentric annular regions, the interval between two adjacent concentric annular regions is 10 μm-50 μm, and the width of each concentric annular region is 20 μm-200 μm.

[0056] It should be understood that several concentric annular areas can meet the design requirements of chips of different sizes and different range specifications, adjust the stress to the optimal value, and maximize the chip reliability.

[0057] The stress release zone 9 adopts a structure of multiple concentric annular areas, with the interval between adjacent annular areas being 10μm-50μm and the width of each annular area being 20μm-200μm. This can optimize the local film stress distribution of the n-type silicon carbide pressure sensitive resistor 4, alleviate stress concentration, improve the stress matching characteristics of the sensor, thereby reducing the measurement error caused by uneven stress, and at the same time enhance the structural reliability and long-term stability of the device.

[0058] In some embodiments, a through hole is formed on the silicon carbide sealing wafer 13 near the metal electrode layer 10 ; and a blind groove is formed on the silicon carbide sealing wafer 13 near the pressure sensitive diaphragm 12 .

[0059] The silicon carbide sealing wafer 13 is provided with a through hole near the metal electrode layer 10 to facilitate filling with conductive paste to realize electrical signal transmission. At the same time, a blind groove is opened near the pressure-sensitive diaphragm 12 to provide deformation space for the pressure-sensitive diaphragm 12. This structural design helps to improve the reliability of signal transmission, reduce the impact of packaging stress on sensitive components, and improve the sensor's detection accuracy of small deformations.

[0060] Some embodiments of the present application further provide a method for processing a low-stress, high-temperature pressure sensor chip, which is used to process the low-stress, high-temperature pressure sensor chip described in the above embodiments. The method includes: An npn double-throw silicon carbide epitaxial wafer is selected as the silicon carbide epitaxial wafer to be processed.

[0061] Among them, the top layer of the silicon carbide epitaxial wafer is an n-type silicon carbide device layer 1; the middle layer of the silicon carbide epitaxial wafer is a p-type silicon carbide isolation layer 2; the bottom layer of the silicon carbide epitaxial wafer is an n-type silicon carbide substrate layer 3 to achieve electrical isolation, and the thickness range of the silicon carbide epitaxial wafer is 300 μm - 500 μm.

[0062] Use inductively coupled plasma etching process or reactive ion etching process to etch the n-type silicon carbide device layer 1 to form an n-type silicon carbide pressure sensitive resistor 4, a sealing area 5, and an isolation channel 6.

[0063] Specifically, before etching the n-type silicon carbide device layer 1, a photoresist can be used as an etching mask on the top of the n-type silicon carbide device layer 1 for photolithography, etching the thickness of the n-type silicon carbide device layer 1 until it reaches the p-type silicon carbide isolation layer 2 and then stopping, and finally removing the photoresist.

[0064] Use chemical vapor deposition to prepare a silicon dioxide layer 7 and a silicon nitride layer 8 on the upper surface of the silicon carbide epitaxial wafer.

[0065] Specifically, the thickness range of the silicon dioxide layer 7 is 50 nm - 200 nm; the thickness range of the silicon nitride layer 8 is 50 nm - 200 nm.

[0066] In some embodiments, the process parameters for preparing the silicon dioxide layer 7 are as follows: precursor gas: silane (5%) / nitric oxide = 1:4 (v / v), radio frequency power: 300 W (13.56 MHz), deposition temperature: 300 - 350 °C, chamber pressure: 900 mTorr; the process parameters for preparing the silicon nitride layer 8 are as follows: precursor gas: silane / ammonia / helium = 1:5:20, radio frequency power: 400 W, deposition temperature: 200 - 400 °C, chamber pressure: 1.2 Torr. Use PECVD process to prepare a silicon dioxide / silicon nitride stack, and cooperate with in-situ H2 plasma treatment to eliminate dangling bonds, which can reduce the interface state density to 1×10 10 cm -2 ·eV -1 level, meeting the long-term reliability requirements under high temperature and high pressure environments.

[0067] Use one or a combination of inductively coupled plasma etching process, reactive ion etching process, and wet etching process to etch the silicon nitride layer 8 and the silicon dioxide layer 7 to form a stress release area 9.

[0068] Specifically, before etching the passivation layer, a photoresist is used as an etching mask on the top for photolithography. First, etch the silicon nitride layer 8, then etch the silicon dioxide layer 7 until it reaches the silicon carbide layer and then stop, and finally remove the photoresist.

[0069] Use electron beam evaporation to form a metal electrode layer 10 on the sealing area 5.

[0070] It should be understood that the pre-processed metal electrode layer 10 can be treated by high-temperature annealing to form an ohmic contact and realize the connection between the metal electrode layer 10 and the n-type silicon carbide pressure-sensitive resistor 4. Specifically, by using the Lift-off process, first, negative photoresist is spin-coated, exposed, and developed to complete the preparation of the photoresist patterning; second, the metal electrode layer 10 is deposited by electron beam evaporation; then, the photoresist is removed with a stripping solution to complete the patterning of the metal electrode; finally, high-temperature annealing treatment is performed to form an ohmic contact between the metal electrode layer 10 and silicon carbide.

[0071] In some embodiments, the metal electrode layer 10 can be titanium / tungsten / gold / nickel, the annealing conditions are 900~1100 °C, and the atmosphere is vacuum or inert gases such as nitrogen and argon.

[0072] The Lift-off process can avoid the toxicity and harm caused by chemical wet etching, and can achieve precise transfer of metal patterning. Metals such as titanium / tungsten / gold / nickel have high melting points, high hardness, and high corrosion resistance, and have good thermal stability and chemical stability; the annealing environment of vacuum or inert gas can avoid metal electrode contamination and oxidation.

[0073] The bottom of the n-type silicon carbide substrate layer 3 is etched by a deep silicon carbide etching process to form a pressure cavity 11.

[0074] Specifically, the mask used for etching silicon carbide is nickel. First, a nickel seed layer is prepared; second, a nickel layer is grown by electroplating, and the thickness can be 10~20 μm; then, the nickel layer is patterned; then, silicon carbide etching is performed, and the etching gas is a mixed gas of sulfur hexafluoride, oxygen, argon, hydrogen bromide, etc.; finally, the nickel layer is removed.

[0075] In some embodiments, the process gas of the deep silicon carbide etching process is one or more of perfluorocyclobutane, tetrafluoromethane, sulfur hexafluoride, oxygen, and argon, and the etching mask of the deep silicon carbide etching process is metal nickel.

[0076] The deep silicon carbide etching process uses one or more of perfluorocyclobutane, tetrafluoromethane, sulfur hexafluoride, oxygen, and argon as the process gas and uses metal nickel as the etching mask. This combination can optimize the etching selectivity and etching rate of silicon carbide materials, improve the perpendicularity of the etched sidewalls and the surface roughness, thereby reducing device damage during etching, improving the structural accuracy and dimensional consistency of the pressure cavity 11, and being beneficial to enhancing the performance stability of the sensor.

[0077] The silicon carbide sealing wafer 13 is sealed on the top of the silicon carbide epitaxial wafer.

[0078] The above processing method selects an n-p-n type double-polished silicon carbide epitaxial wafer as the substrate, uses inductively coupled plasma etching or reactive ion etching process to form an n-type silicon carbide pressure-sensitive resistor 4 and an isolation channel 6, combines chemical vapor deposition to prepare a silicon dioxide and silicon nitride layer 8, then forms a stress release region 9 through an etching process, and uses electron beam evaporation to fabricate a metal electrode layer 10. Finally, a pressure cavity 11 is formed through deep silicon carbide etching and bonded to a silicon carbide sealing wafer 13, which helps to reduce the influence of thermal stress during the processing, improve the stress matching between device layers, improve the stability of the sensor in a high-temperature environment, ensure a reliable connection between the pressure-sensitive resistor and the electrode, and enhance the overall performance of the chip.

[0079] In some embodiments, the etching gas for the inductively coupled plasma etching process and the reactive ion etching process is at least one of tetrafluoromethane, sulfur hexafluoride, and trifluoromethane; the assist gas for the inductively coupled plasma etching process and the reactive ion etching process is at least one of oxygen, argon, and nitrogen, and the volume ratio of tetrafluoromethane is 60%-80%.

[0080] It should be understood that the etching power of the inductively coupled plasma etching process and the reactive ion etching process can be selected from 1200-1500W, the RF bias can be selected from 150-300W, and the working pressure can be selected from 5-20mTorr.

[0081] Based on the high chemical activity potential energy of the tetrafluoromethane / sulfur hexafluoride / trifluoromethane ternary gas phase system, an advanced etching process with strong anisotropic characteristics can be constructed. Through the regulation mechanism of plasma chemical reactions and establishing a gas component concentration gradient model, atomic-level precision etching control of sub-micron feature sizes can be achieved. This hybrid process not only forms an ideal steep sidewall morphology with an angle of 88°±1° through the synergistic mechanism of optimizing the radical transport path and modulating the ion bombardment energy, but also ensures a process stability with a batch-to-batch repeatability ≤1.5nm.

[0082] In some embodiments, the wet etching process uses a buffered oxide etchant, which is prepared by mixing a 40% ammonium fluoride solution and a 49% hydrofluoric acid solution in a volume ratio of 6:1.

[0083] The wet etching process using a buffered oxide etchant prepared by mixing a 40% ammonium fluoride solution and a 49% hydrofluoric acid solution in a volume ratio of 6:1 can adjust the etching rate and reaction activity, improve the stability of the etching process, reduce the risk of over-etching caused by too high a hydrofluoric acid concentration, and at the same time helps to obtain a more uniform etched surface morphology, improving the controllability and repeatability of the etching process.

[0084] As can be seen from the above technical solutions, the embodiments of the present application provide a low-stress high-temperature pressure sensor chip and a processing method. The chip includes: a silicon carbide epitaxial wafer, a passivation layer, a metal electrode layer 10, and a silicon carbide sealing wafer 13; the silicon carbide epitaxial wafer includes an n-type silicon carbide device layer 1, a p-type silicon carbide isolation layer 2, and an n-type silicon carbide substrate layer 3, and the n-type silicon carbide device layer 1, the p-type silicon carbide isolation layer 2, and the n-type silicon carbide substrate layer 3 are connected in sequence from top to bottom; the n-type silicon carbide device layer 1 is etched to form an n-type silicon carbide pressure-sensitive resistor 4, a sealing area 5, and an isolation channel 6; wherein, the n-type silicon carbide pressure-sensitive resistor 4 is isolated from the sealing area 5 through the isolation channel 6; the passivation layer includes a silicon dioxide layer 7 and a silicon nitride layer 8, the silicon dioxide layer 7 is located on the upper surfaces of the n-type silicon carbide pressure-sensitive resistor 4 and the isolation channel 6, the silicon nitride layer 8 is located on the upper surface of the silicon dioxide layer 7, and stress release areas 9 are formed on the silicon dioxide layer 7 and the silicon nitride layer 8; a pressure cavity 11 is formed by etching the bottom of the n-type silicon carbide substrate layer 3, and the p-type silicon carbide isolation layer 2 and the n-type silicon carbide substrate layer 3 in the area directly above the pressure cavity 11 constitute a pressure-sensitive diaphragm 12, and the stress release areas 9 are arranged on the upper surface of the pressure-sensitive diaphragm 12; the metal electrode layer 10 is arranged on the sealing area 5, and the metal electrode layer 10 is electrically connected to the n-type silicon carbide pressure-sensitive resistor 4; the silicon carbide sealing wafer 13 is bonded to the top of the silicon carbide epitaxial wafer to solve the problem of low reliability of the low-stress high-temperature pressure sensor chip.

[0085] For the similar parts between the embodiments provided in the present application, reference can be made to each other. The specific embodiments provided above are only several examples under the general concept of the present application and do not constitute a limitation on the protection scope of the present application. For those skilled in the art, any other embodiments extended based on the solutions of the present application without creative efforts belong to the protection scope of the present application.

Claims

1. A low-stress high-temperature pressure sensor chip, characterized in that, Comprising: A silicon carbide epitaxial wafer, a passivation layer, a metal electrode layer (10), and a silicon carbide sealing wafer (13); The silicon carbide epitaxial wafer includes an n-type silicon carbide device layer (1), a p-type silicon carbide isolation layer (2), and an n-type silicon carbide substrate layer (3), and the n-type silicon carbide device layer (1), the p-type silicon carbide isolation layer (2), and the n-type silicon carbide substrate layer (3) are connected in sequence from top to bottom; The n-type silicon carbide device layer (1) is etched to form an n-type silicon carbide pressure-sensitive resistor (4), a sealing area (5), and an isolation channel (6); wherein, the n-type silicon carbide pressure-sensitive resistor (4) is isolated from the sealing area (5) through the isolation channel (6); The passivation layer includes a silicon dioxide layer (7) and a silicon nitride layer (8), the silicon dioxide layer (7) is located on the upper surfaces of the n-type silicon carbide pressure-sensitive resistor (4) and the isolation channel (6), the silicon nitride layer (8) is located on the upper surface of the silicon dioxide layer (7), and a stress release area (9) is formed on the silicon dioxide layer (7) and the silicon nitride layer (8); a pressure cavity (11) is formed by etching the bottom of the n-type silicon carbide substrate layer (3), and the p-type silicon carbide isolation layer (2) and the n-type silicon carbide substrate layer (3) in the area directly above the pressure cavity (11) form a pressure-sensitive diaphragm (12), and the stress release area (9) is arranged on the upper surface of the pressure-sensitive diaphragm (12); The metal electrode layer (10) is arranged on the sealing area (5), and the metal electrode layer (10) is electrically connected to the n-type silicon carbide pressure-sensitive resistor (4); The silicon carbide sealing wafer (13) is bonded to the top of the silicon carbide epitaxial wafer.

2. The low-stress high-temperature pressure sensor chip according to claim 1, wherein The silicon carbide epitaxial wafer is a double-polished wafer, and the thickness of the silicon carbide epitaxial wafer is 300μm - 500μm; the thickness of the n-type silicon carbide device layer (1) is 200nm to 2μm, and the doping concentration of the n-type silicon carbide device layer (1) is 1E19cm -3 ~3E20cm -3 ; the thickness of the p-type silicon carbide isolation layer (2) is 2μm to 10μm, and the doping concentration of the p-type silicon carbide isolation layer (2) is 3E15cm -3 ~3E18cm -3 ; the thickness of the silicon dioxide layer (7) is 50nm to 200nm; the thickness of the silicon nitride layer (8) is 50nm to 200nm; the thickness of the metal electrode layer (10) is 500nm to 1μm; the thickness of the pressure-sensitive diaphragm (12) is 50μm to 200μm.

3. The low-stress high-temperature pressure sensor chip according to claim 1, characterized in that The number of the n-type silicon carbide pressure-sensitive resistors (4) is four, the four n-type silicon carbide pressure-sensitive resistors (4) are distributed along the periphery of the pressure-sensitive diaphragm (12), and the four n-type silicon carbide pressure-sensitive resistors (4) are isolated from each other through the isolation channel (6) and form a Wheatstone bridge in a closed-bridge form.

4. The low-stress high-temperature pressure sensor chip according to claim 1, characterized in that, The stress release area (9) is formed by etching the silicon dioxide layer (7) and the silicon nitride layer (8), and the stress release area (9) is annularly distributed in the edge area of the pressure-sensitive diaphragm (12) or around the n-type silicon carbide pressure-sensitive resistor (4).

5. The low-stress high-temperature pressure sensor chip according to claim 4, characterized in that, The stress release area (9) includes a plurality of concentric annular areas. If there are multiple concentric annular areas, the interval between two adjacent concentric annular areas is 10 μm - 50 μm, and the width of each concentric annular area is 20 μm - 200 μm.

6. The low-stress high-temperature pressure sensor chip according to claim 1, wherein A through hole is formed at a position of the silicon carbide sealing wafer (13) close to the metal electrode layer (10); a blind groove is formed at a position of the silicon carbide sealing wafer (13) close to the pressure-sensitive diaphragm (12).

7. A processing method for a low-stress high-temperature pressure sensor chip, characterized in that, For processing the low-stress high-temperature pressure sensor chip according to any one of claims 1 - 6, the method includes: Select an n-p-n type double-polished silicon carbide epitaxial wafer as the silicon carbide epitaxial wafer to be processed; wherein, the top layer of the silicon carbide epitaxial wafer is an n-type silicon carbide device layer (1); the middle layer of the silicon carbide epitaxial wafer is a p-type silicon carbide isolation layer (2); the bottom layer of the silicon carbide epitaxial wafer is an n-type silicon carbide substrate layer (3); Use inductively coupled plasma etching process or reactive ion etching process to etch the n-type silicon carbide device layer (1) to form an n-type silicon carbide pressure sensitive resistor (4), a sealing area (5), and an isolation channel (6); Prepare a silicon dioxide layer (7) and a silicon nitride layer (8) on the upper surface of the silicon carbide epitaxial wafer by chemical vapor deposition; Use one or a combination of inductively coupled plasma etching process, reactive ion etching process, and wet etching process to etch the silicon nitride layer (8) and the silicon dioxide layer (7) to form a stress release area (9); Form a metal electrode layer (10) on the sealing area (5) by electron beam evaporation; Use deep silicon carbide etching process to etch the bottom of the n-type silicon carbide substrate layer (3) to form a pressure cavity (11); Seal a silicon carbide sealing wafer (13) on the top of the silicon carbide epitaxial wafer.

8. The processing method of the low-stress high-temperature pressure sensor chip according to claim 7, characterized in that The etching gases of the inductively coupled plasma etching process and the reactive ion etching process are at least one of tetrafluoromethane, sulfur hexafluoride, and trifluoromethane; the assist gases of the inductively coupled plasma etching process and the reactive ion etching process are at least one of oxygen, argon, and nitrogen, wherein the volume ratio of tetrafluoromethane is 60%-80%.

9. The processing method of the low-stress high-temperature pressure sensor chip according to claim 7, characterized in that The wet etching process uses a buffered oxide etchant, and the buffered oxide etchant is prepared by mixing a 40% ammonium fluoride solution and a 49% hydrofluoric acid solution in a volume ratio of 6:

1.

10. The processing method of the low-stress high-temperature pressure sensor chip according to claim 7, wherein The process gas of the deep silicon carbide etching process is one or more of octafluorocyclobutane, tetrafluoromethane, sulfur hexafluoride, oxygen, and argon, and the etching mask of the deep silicon carbide etching process is metallic nickel.

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