Silicon carbide device and method for forming silicon carbide device

Abstract

The invention relates to a silicon carbide device and a method for forming a silicon carbide device. A silicon carbide device includes a silicon carbide substrate; comprising nickel, silicon and aluminum; comprising titanium and tungsten; and a metallization layer comprising copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a portion of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.

Description

Technical Field

[0001] The examples relate to silicon carbide devices and methods for forming silicon carbide devices. Other aspects described herein relate to power semiconductor devices having improved thermal robustness, such as silicon carbide devices. Background Art

[0002] In the development of power devices, increasingly higher power densities may be required. While there are limitations regarding silicon-based power devices due to material limitations, for silicon carbide devices, power densities that are 5 to 10 times higher may be achievable.

[0003] There may be a need to provide improved concepts for silicon carbide devices, which enable silicon carbide devices to have reduced lateral dimensions. Furthermore, there may be a need for further improvements, particularly in improving the thermal robustness of wide bandgap power devices, such as silicon carbide devices. Summary of the Invention

[0004] Some embodiments relate to silicon carbide devices including a silicon carbide substrate. The silicon carbide device includes a contact layer containing nickel, silicon, and aluminum. The contact layer is located on the silicon carbide substrate. The silicon carbide device includes a barrier layer structure containing titanium and tungsten. The contact layer is located between the silicon carbide substrate and at least a portion of the barrier layer structure. The silicon carbide device includes a copper-containing metallization layer. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.

[0005] Some embodiments relate to methods for forming silicon carbide devices. The method includes forming a contact layer containing nickel, silicon, and aluminum on a silicon carbide substrate of a silicon carbide device. The method includes forming a barrier layer structure containing titanium and tungsten after forming the contact layer structure. The method includes forming a copper-containing metallization layer after forming the barrier layer structure. An ohmic connection is formed between a doped region of the silicon carbide substrate and the metallization layer via the barrier layer structure and the contact layer.

[0006] According to one embodiment, a power semiconductor device includes a semiconductor substrate having a first surface, wherein the semiconductor substrate includes a wide bandgap semiconductor material having an intrinsic temperature. An insulating layer is located above the first surface of the semiconductor substrate, wherein the insulating layer includes at least one opening extending through the insulating layer in a vertical direction. A pre-metallization is above the insulating layer, wherein the insulating layer is inserted between the pre-metallization and the first surface of the semiconductor substrate. A metal connection is disposed in the opening of the insulating layer and electrically connects the pre-metallization to the semiconductor substrate. The pre-metallization includes at least one layer or consists essentially of one layer, wherein at least one layer consists essentially of a metal or metal alloy having a melting temperature higher than the intrinsic temperature of the semiconductor material.

[0007] According to one embodiment, a power semiconductor device includes a semiconductor substrate having a first surface, wherein the semiconductor substrate comprises a single-crystalline semiconductor material selected from the group consisting of SiC, GaN, AlN, and Ga2O3. An insulating layer is located on the first surface of the semiconductor substrate, wherein the insulating layer includes a plurality of openings extending therethrough. A front metallization is on the insulating layer, wherein the insulating layer is inserted between the front metallization and the first surface of the semiconductor substrate. The front metallization extends through the respective openings of the insulating layer and forms respective metal connections disposed in the respective openings of the insulating layer, wherein the metal connections form respective electrical connections to the semiconductor substrate. The front metallization comprises or consists essentially of one or more metals and / or metal alloys having a melting temperature higher than 1100 °C. Description of the Drawings

[0008] Some examples of the device and / or method will be described hereinafter only by way of example and with reference to the drawings, wherein: Figure 1 A schematic cross-section showing a part of a silicon carbide device according to one embodiment; Figure 2 Another schematic cross-section showing a part of a silicon carbide device according to one embodiment, the silicon carbide device including a barrier layer structure having a plurality of barrier layers; Figure 3a and 3b A schematic cross-section showing an embodiment of a silicon carbide metal-oxide-semiconductor field-effect transistor; Figure 4a and 4b A schematic diagram showing a bonding wire bonded to a contact pad of a silicon carbide device according to an embodiment; Figure 5 A flowchart showing a method for forming a silicon carbide device according to one embodiment; Figures 6a to 6e A schematic cross-section showing a part of a silicon carbide device according to one embodiment at various stages of forming the silicon carbide device; Figure 7 A cross-sectional view showing a power semiconductor device according to one embodiment; Figure 8 An enlarged view showing a power semiconductor device with front metallization according to one embodiment; Figure 9 An enlarged view showing a power semiconductor device with front metallization according to one embodiment; Figure 10 An enlarged view showing a power semiconductor device with front metallization according to one embodiment; Figure 11 An illustration showing a power semiconductor device with front metallization according to one embodiment; Figure 12 Illustrate the dependence of the destructive avalanche current and conversion energy during avalanche with respect to the driving inductance; Figure 13 Illustrate an example of the destructive avalanche test of a SiC-MOSFET; and Figure 14 Illustrate the AlCu phase diagram. Detailed implementation manners

[0009] Various examples will now be described more fully with reference to the accompanying drawings, in which some examples are illustrated. In the accompanying drawings, for clarity, the thickness of lines, layers, and / or regions may be exaggerated.

[0010] Accordingly, while other examples may have various modifications and alternative forms, some specific examples thereof are shown in the accompanying drawings and will subsequently be described in detail. However, this detailed description does not limit further examples to the specific forms described. Further examples may cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure. Throughout the description of the drawings, the same or similar numerals refer to the same or similar elements, which may be implemented identically or in a modified form when compared to each other, while providing the same or similar functions.

[0011] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled or via one or more intermediate elements. Further, if an element is located or positioned "on" another element (e.g., a layer is "on" another layer or on a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., if the layer is "on" the substrate, another layer may be located between the layer and the substrate). If two elements A and B are combined using "or", it should be understood that all possible combinations are disclosed, i.e., only A, only B, and A and B, if not otherwise explicitly or implicitly defined. Alternative wordings for the same combination are "at least one of A and B" or "A and / or B". The same applies, mutatis mutandis, to combinations of more than two elements.

[0012] The terms used herein to describe specific examples are not intended to limit other examples. Whenever the singular forms such as "a", "an", and "the" are used and only a single element is neither explicitly nor implicitly defined as mandatory, other examples may also implement the same function using multiple elements. Similarly, when a function is subsequently described as being implemented using multiple elements, other examples may implement the same function using a single element or a processing entity. It will be further understood that the terms "comprising", "comprises", "including", and / or "includes", when used, specify the presence of the stated features, integers, steps, operations, processes, acts, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, acts, elements, components, and / or any group thereof.

[0013] In this specification, the second surface of the semiconductor substrate is considered to be formed by the lower or back surface, while the first surface is considered to be formed by the upper surface, front surface, or main surface of the semiconductor substrate. Thus, the terms "above" and "below" used in this specification describe the relative positions of structural features with respect to another structural feature, taking into account this orientation.

[0014] The terms "electrically connected" and "is electrically connected" describe an ohmic connection or a connection through a Schottky contact between two elements.

[0015] The term "consisting essentially of" describes that the material of an element or a structural part mainly consists of the indicated composition or the indicated components, and the content of the components not mentioned (such as impurities) is less than 1% based on the total weight of the element or the structural part.

[0016] Furthermore, if a physical value is stated with "about" (such as, for example, "about 600 °C"), this should be interpreted within the typical error margins, in particular such that typical measurement errors and / or rounding conventions for the last decimal place are included.

[0017] Unless otherwise defined, all terms (including technical and scientific terms) are used herein in their ordinary meaning in the field to which the examples belong.

[0018] Figure 1 A schematic cross-section of a part of a silicon carbide device 100 is shown. The silicon carbide device 100 may include a silicon carbide substrate 102. The silicon carbide substrate 102 may extend in a lateral direction along a main extension plane, which may extend substantially along the front surface of the silicon carbide substrate. Perpendicular to the lateral direction, in the vertical direction, the silicon carbide substrate 102 may have a thickness that is smaller compared to the extension of the silicon carbide substrate 102 in the lateral direction.

[0019] For example, the silicon carbide device 100 can be a power semiconductor device. The examples relate to a power semiconductor device that includes a semiconductor substrate having a wide bandgap semiconductor material, for example, as an alternative to or in addition to the silicon carbide substrate 102.

[0020] The silicon carbide (chemical symbol: SiC) device 100 can further include a contact layer 104. The contact layer can include nickel (chemical symbol: Ni), silicon (chemical symbol: Si), and aluminum (chemical symbol: Al). The contact layer 104 can be located on the silicon carbide substrate 102. For example, the contact layer 104 is directly located on the silicon carbide substrate 102. For example, the contact layer 104 can provide an ohmic contact with the silicon carbide substrate 102.

[0021] The contact layer 104 can be composed of Ni, Si, and Al. Here and hereinafter, if a component "is composed of" a chemical element or several chemical elements, this means that the (one or more) main components of the component are (one or more) of the said chemical elements, except for impurities due to manufacturing tolerances. For example, if a component "is composed of" a chemical element or several chemical elements, the component contains at most 0.1% (or at most 0.05%, or at most 0.01%) by volume of other chemical elements.

[0022] Within the contact layer 104, the chemical elements Ni, Si, and Al can be uniformly distributed. That is, the chemical composition of the contact layer 104 (especially the atomic ratio of the chemical elements) can vary by at most ±5% in the vertical direction and / or the lateral direction. However, the chemical composition of the contact layer 104 (especially the atomic ratio of the chemical elements) may also vary at least in the vertical direction. For example, the content of Si can decrease as the distance from the silicon carbide substrate 102 increases.

[0023] The silicon carbide device 100 (e.g., a power semiconductor device) can include a barrier layer structure 106, for example, including titanium (chemical symbol: Ti) and tungsten (chemical symbol: W). As an alternative to or in addition to the barrier layer structure 106, the silicon carbide device 100 can include, for example, an adhesion promoting layer. For example, instead of providing or in addition to providing the barrier layer structure 106, an adhesion promoting layer can be provided in the silicon carbide device 100. The contact layer 104 can be located (e.g., vertically located) between the silicon carbide substrate 102 and at least a part (e.g., the adhesion promoting layer) of the barrier layer structure 106.

[0024] The silicon carbide device 100 may include a metallization layer 108, for example including copper (chemical symbol: Cu). For example, the metallization layer 108 may include or may be composed of a power metal. For example, instead of providing or in addition to providing the metallization layer 108, a power metal may be provided in the silicon carbide device 100. A barrier layer structure 106 may be located (e.g., vertically) between the silicon carbide substrate 102 and the metallization layer 108 (e.g., the power metal).

[0025] The barrier layer structure 106 (e.g., an adhesion promoting layer) may function as or be a diffusion barrier layer, which may be suitable for preventing the copper (e.g., the power metal) of the metallization structure 108 from diffusing into the silicon carbide substrate 102. This may enable the use of a copper-based metallization layer, which may include a high melting temperature and thus may allow for silicon carbide devices with high power density and low footprint. At a low footprint, the capacitance of the silicon carbide device may be reduced and the yield (at a constant defect density) may increase.

[0026] For example, the barrier layer structure 106 may be a diffusion barrier between the metallization layer 108 and the silicon carbide substrate 102. The barrier layer 106 may be suitable for preventing copper from diffusing into the silicon carbide substrate 102.

[0027] In various examples, the barrier layer structure 106 may be a single barrier layer. The single barrier layer may fabricate the silicon carbide device with reduced complexity and / or at reduced cost. The single barrier layer may contact (i.e., directly contact) the contact layer 104 and the metallization layer 108. In other words, the single barrier layer may be positioned adjacent (e.g., vertically adjacent) to the contact layer 104 and the metallization layer 108.

[0028] For example, the barrier layer structure 106 may be a TiW (titanium tungsten) layer. The TiW layer may provide a diffusion barrier between the metallization layer 108 and the silicon carbide substrate 108. Alternatively, the barrier layer structure 106 may be a TiWN (titanium tungsten nitride) layer. The TiWN layer may provide stabilization of the barrier layer structure 106. For example, the TiW layer or the TiWN layer may contact the metallization layer 108. In other words, the TiW layer or the TiWN layer may be positioned adjacent (e.g., vertically adjacent) to the metallization layer 108. Additionally or alternatively, the TiW layer or the TiWN layer may contact the contact layer 104. In other words, the TiW layer or the TiWN layer may be positioned adjacent (e.g., vertically adjacent) to the contact layer 104.

[0029] Or, as Figure 2 shown, the barrier layer structure 106 may include a barrier layer stack. The barrier layer structure 106 (or the barrier layer stack) may include a plurality of barrier layers. For example, the barrier layer structure 106 may include one or more layers from the group of Ti / TiN (titanium - titanium nitride) layers, TiW layers, TiWN layers, and MoN (molybdenum nitride) layers.

[0030] For example, the barrier layer structure 106 (e.g., the barrier layer stack) may include a TiW layer. The TiW layer may provide a diffusion barrier between the metallization layer 108 and the silicon carbide substrate 102. Additionally or alternatively, the barrier layer structure 106 (and / or the barrier layer stack) may include a TiWN layer. For example, TiWN may be formed using sputtering. Within the TiWN layer, the chemical elements Ti, W, and N may be uniformly distributed. That is, the chemical composition of the TiWN layer (especially the atomic ratio of the chemical elements) may vary by up to ±5% in the vertical direction and / or the lateral direction. However, it is also possible for the chemical composition of the TiWN layer (especially the atomic ratio of the chemical elements) to vary at least in the vertical direction. For example, the TiWN layer may be formed from a portion of the TiW layer of the barrier layer structure. For example, the nitrogen in the TiWN layer may be non-uniformly (i.e., unevenly) distributed along the vertical direction of the TiWN layer. The TiWN layer may provide stabilization of the barrier layer structure 106. The barrier layer structure 106 may include a TiW layer and a TiWN layer. For example, the TiW layer may be positioned vertically closer to the silicon carbide substrate 102 than the TiWN layer. For example, the TiWN layer may be (directly) in contact with the metallization layer 108. In other words, the TiWN layer may be positioned adjacent to the metallization layer 108 (e.g., vertically adjacent). The TiW layer may be (directly) in contact with the contact layer 104. In other words, the TiW layer may be positioned adjacent to the contact layer (e.g., vertically adjacent).

[0031] For example, the barrier layer structure 106 (e.g., the barrier layer stack) may include a first TiW layer, a second TiW layer, and a TiWN layer. The TiWN layer may be located (e.g., vertically located) between the first TiW layer and the second TiW layer. For example, the first TiW layer may be positioned vertically closer to the silicon carbide substrate 102 than the second TiW layer. The second TiW layer may be in contact with the metallization layer 108. In other words, the second TiW layer may be positioned adjacent to the metallization layer 108 (e.g., vertically adjacent). A barrier layer including two TiW layers and a TiWN layer may provide a good diffusion barrier and good adhesion. For example, the barrier layer structure may include or consist of a Ti / TiN layer, a first TiW layer, a second TiW layer, and a TiWN layer. The TiWN layer may be located (e.g., vertically located) between the first TiW layer and the second TiW layer. For example, the first TiW layer may be in contact with the Ti / TiN layer. In other words, the first TiW layer may be positioned adjacent to the Ti / TiN layer (e.g., vertically adjacent). The second TiW layer may be in contact with the metallization layer 108. In other words, the second TiW layer may be positioned adjacent to the metallization layer 108 (e.g., vertically adjacent).

[0032] For example, the barrier layer structure 106 (e.g., a barrier layer stack) may include a Ti / TiN layer (i.e., a Ti / TiN layer structure). For example, the Ti / TiN layer may include a titanium (Ti) layer and a titanium nitride (TiN) layer. The titanium layer may be in contact with the titanium nitride layer. The titanium layer may be in contact with the contact layer 104. The titanium layer may be positioned vertically closer to the semiconductor substrate 102 than the titanium nitride layer. The titanium nitride layer may be located on the titanium layer. The Ti / TiN layer may provide hydrogen barrier. For example, the Ti / TiN layer may be (directly) in contact with the contact layer 104. In other words, the Ti / TiN layer may be positioned adjacent to the contact layer 104, e.g., vertically adjacent. For example, the barrier layer structure 106 may include a Ti / TiN layer and at least one of a TiW layer and a TiWN layer. For example, the barrier layer stack of the barrier layer structure 106 may include a Ti / TiN layer and a TiW layer, where the Ti / TiN layer is in contact with the contact layer 104. For example, the barrier layer stack of the barrier layer structure 106 may include a Ti / TiN layer, a TiW layer, and a TiWN layer (in this order), where the Ti / TiN is in contact with the contact layer 104. For example, the metal layer stack may include or consist of: a NiAl layer (e.g., the contact layer 104) - a Ti / TiN layer - a TiW layer - an optional TiWN layer - Cu (e.g., the metallization layer 108). The Ti / TiN layer, the TiW layer, and the optional TiWN layer may form the barrier layer structure 106.

[0033] For example, the barrier layer structure 106 may include a Ti / TiN layer and a TiW layer or consist of a Ti / TiN layer and a TiW layer. The TiW layer may be formed (e.g., deposited) on the Ti / TiN layer.

[0034] Alternatively, the barrier layer structure may include a Ti / TiN layer and a TiWN layer or consist of a Ti / TiN layer and a TiWN layer. The TiWN layer may be formed using reactive sputtering.

[0035] For example, the vertical thickness of the barrier layer structure 106 may be at least 50 nm (or at least 80 nm, at least 100 nm, at least 150 nm, at least 200 nm, at least 250 nm, at least 350 nm) and / or at most 1000 nm (or at most 800, at most 600 nm, at most 400 nm). If the barrier layer structure includes a Ti / TiN layer, the vertical thickness of the barrier structure 106 other than the Ti / TiN layer may be at least 50 nm (or at least 80 nm, at least 100 nm, at least 150 nm, at least 200 nm, at least 250 nm, at least 350 nm) and / or at most 600 nm (or at most 500 nm, at most 400 nm).

[0036] The silicon carbide device 100 may include a contact layer 104 comprising nickel, silicon, and aluminum. For example, the contact layer 104 may be a NiSiAl layer. The contact layer may be a nickel-silicon-aluminum alloy layer. For example, a NiAl layer may be formed on the silicon carbide substrate 102. The NiAl layer may be processed using a high-temperature treatment and may subsequently form a NiSiAl layer together with the SiC of the silicon carbide substrate 102. For example, the contact layer 104 may include an alloy formed from a portion of the silicon carbide substrate and a layer comprising nickel and aluminum. The contact layer may be or may include an alloy comprising nickel, silicon, and aluminum or consisting of nickel, silicon, and aluminum.

[0037] For example, the contact layer 104 may include at least 1% (or at least 2%, at least 3%, at least 5%, at least 8%, at least 10%) and / or at most 30% (or at most 25%, at most 20%, at most 15%, at most 10%) silicon by volume. The contact layer may include at least 0.05% (or at least 0.1%, at least 0.2%, at least 0.5%, at least 1%, at least 5%, at least 10%, at least 15%, at least 20%) and / or at most 30% (or at most 25%, at most 20%, at most 15%) aluminum by volume. The contact layer 104 may include at least 1% (or at least 2%, at least 5%) and / or at most 10% (or at most 8%, at most 5%) carbon inclusions by volume.

[0038] For example, the contact layer may be formed by depositing at least 20 nm (or at least 30 nm, at least 40 nm, at least 50 nm, at least 80 nm, at least 100 nm) and / or at most 150 nm (or at most 120 nm, at most 100 nm, at most 80 nm, at most 50 nm) of NiAl on the silicon carbide substrate 102 and performing a high-temperature treatment.

[0039] The contact layer may include a vertical thickness of at least 20 nm (or at least 30 nm, at least 40 nm, at least 50 nm, at least 80 nm, at least 100 nm) and / or at most 150 nm (or at most 120 nm, at most 100 nm, at most 80 nm, at most 50 nm). The contact layer 104 may be located on the silicon carbide substrate 102. For example, the contact layer 104 may be located on the front surface of the silicon carbide substrate 102. The contact layer 104 may be (directly) in contact with the silicon carbide substrate 102. For example, the contact layer 104 may be (directly) in contact with the barrier layer structure 106.

[0040] For example, the contact layer 104 can be an ohmic contact layer. For example, the contact layer 104 can form an ohmic connection (i.e., a conductive connection) to the silicon carbide substrate 102. For example, the silicon carbide device 100 can include an ohmic connection between a doped region of the silicon carbide substrate and the metallization layer 108 via the barrier layer structure 106 and the contact layer 104. The contact layer 104 can be in ohmic contact with a first doped region (e.g., the source region of a transistor) of the silicon carbide substrate 102 and a second doped region (e.g., the body region of a transistor) of the silicon carbide substrate 102. The first doped region can include a first conductivity type (e.g., p-doped), while the second doped region can include a second conductivity type (e.g., n-doped).

[0041] The silicon carbide device 100 can include a metallization layer 108 that includes copper. Using a copper metallization layer can achieve a high current-carrying capacity. In combination with copper bond wires, the copper metallization layer 108 can allow for a higher load cycle capacity and can improve heat diffusion and heat dissipation. For example, the metallization layer 108 can include copper as the main material. For example, the metallization layer 108 can include at least 60% (or at least 70%, at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%) copper by volume. For example, the vertical thickness of the metallization layer can be at least 5 μm (or at least 10 μm, at least 15 μm, at least 20 μm, at least 30 μm, at least 40 μm) and / or at most 100 μm (or at most 80 μm, at most 70 μm, at most 60 μm, at most 50 μm, at most 40 μm, at most 30 μm, at most 20 μm, at most 15 μm, at most 10 μm). Copper sputtering can be used to form the metallization layer 108 for a vertical thickness of 5 μm to 10 μm. Copper electroplating can be used to form the metallization layer 108 for a vertical thickness of 20 μm to 100 μm.

[0042] Alternatively, the metallization layer 108 can be a metal layer that includes a copper-based metal alloy. For example, the metallization layer 108 can include aluminum and copper, such as an aluminum-copper alloy. The metallization layer 108 can be an AlCu layer. For example, the metallization layer 108 can contain at most 20% (or at most 15%, at most 10%, at most 5%) and / or at least 0.1% (or at least 0.5%, at least 1%, at least 2%, at least 3%, at least 5%) copper by volume.

[0043] The metallization layer 108 can be located on the barrier layer structure 106 (e.g., via direct contact or via an additional layer). The metallization layer 108 can be in contact with the barrier layer structure 106, for example, positioned adjacent to the barrier layer structure, for example, vertically adjacent. For example, in a top view of the silicon carbide device 100, the lateral surface area of the barrier layer structure 106 can (completely) cover the lateral surface area of the metallization layer 108.

[0044] For example, the silicon carbide device 100 may also include (at least partially) a passivation layer located on at least a portion of the metallization layer 108.

[0045] The metallization layer 108 may form one or more contact pads of the silicon carbide device 100. For example, one or more contact pads may be formed at least partially by the metallization layer. For example, the metallization layer may be deposited and configured to form one or more contact pads of the silicon carbide device, which are electrically connected to one or more doped regions of the silicon carbide substrate 102. The minimum lateral dimension of the contact pads of the silicon carbide device may be at most 400 μm (or at most 300 μm, at most 250 μm, at most 200 μm, at most 150 μm, at most 100 μm, at most 80 μm, at most 60 μm, at most 50 μm, at most 40 μm, at most 30 μm). For example, the contact pad may be a gate contact pad (i.e., a contact pad connected to the gate of the transistor structure of the silicon carbide device) or a sense contact pad of the silicon carbide device (i.e., a contact pad for obtaining a sense reading of the silicon carbide device). The lateral surface area of the contact pad may be at most 200 μm × 200 μm (or at most 150 μm × 150 μm, at most 100 μm × 100 μm, at most 80 μm × 80 μm, at most 60 μm × 60 μm, at most 40 μm × 50 μm, at most 30 μm × 30 μm). For example, the contact pad connected to the gate of the transistor structure of the silicon carbide device may include a lateral dimension of at most 200 μm × 200 μm (or at most 150 μm × 150 μm, at most 100 μm × 100 μm, at most 80 μm × 80 μm, at most 60 μm × 60 μm). For example, the maximum lateral dimension of the largest source contact pad may be at most 10000 μm (e.g., at most 5000 μm, at most 2000 μm) or at most 1000 μm (e.g., at most 800 μm, at most 600 μm, at most 500 μm, e.g., at most 250 μm) and / or at least 250 μm (or at least 500 μm, at least 1000 μm, at least 2000 μm, at least 5000 μm). For example, the contact pad may be suitable for bonding a bonding wire to the contact pad using nail head bonding.

[0046] For example, the silicon carbide device may include an interconnect structure, such as a copper interconnect structure. The interconnect structure may be in contact with the metallization layer. For example, the interconnect structure may be electrically connected to the metallization layer. For example, the interconnect structure may include a bonding wire, such as a copper bonding wire.

[0047] For example, a silicon carbide device may include bonding wires (e.g., one or more bonding wires) bonded to a metallization layer 108. For example, the bonding wire(s) may be bonded to one of one or more contact pads of the metallization layer 108. The bonding wire may be bonded to the metallization layer 108 using one of tape bonding, wedge bonding, and ball bonding. For example, the bonding wire may be further connected to a package structure of the silicon carbide device (e.g., DCB (direct copper bonding), AMB (active metal brazing), or lead frame). For example, the bonding wire may be a copper bonding wire. For example, the bonding wire may contain copper as a main material. For example, the bonding wire may contain at least 60% (or at least 70%, at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%) copper by volume. Using a copper bonding wire on a copper-containing metallization layer can provide stable interconnects with improved load cycle capabilities, improved thermal spreading, and thermal dissipation. This can enable higher short-circuit robustness and higher maximum current flow. Alternatively or additionally, one or more contact pads may be contacted by a copper clamping mechanism (e.g., a spacer, e.g., a copper spacer or a molybdenum spacer). Or, the bonding wire may be a silver (chemical symbol: Ag) bonding wire. For example, the bonding wire may contain silver as a main material. For example, the bonding wire may contain at least 60% (or at least 70%, at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%) silver by volume. Or, the bonding wire may be a gold (chemical symbol: Au) bonding wire. For example, the bonding wire may contain gold as a main material. For example, the bonding wire may contain at least 60% (or at least 70%, at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%) gold by volume.

[0048] For example, the bonding wire can have a diameter of at most 150 μm (or at most 120 μm, or at most 100 μm, or at most 80 μm, or at most 60 μm, or at most 40 μm, at most 20 μm). For example, the bonding wire can have a diameter of at least 20 μm (or at least 30 μm, or at least 40 μm). For example, the bonding wire can have a diameter of 75 μm or 50 μm. The bonding wire can be a fine wire bonding wire. A bonding wire with a reduced diameter (it may be feasible to use copper as the main material of the bonding wire) can enable the contact pad to have a reduced lateral surface area, which can result in a reduced footprint of the silicon carbide device. The bonding wire can be bonded to the metallization layer 108 using a nail head (i.e., thermosonic - ball - wedge) bond. The size of the nail head of the nail head bond can be 2 to 4 times the diameter of the bonding wire, for example 3 times. Alternatively, the bonding wire can be bonded to the metallization layer 108 using a wedge bond or a tape bond. The bonding wire can be a thick wire bonding wire. For example, the bonding wire can have a diameter of at least 100 μm (or at least 150 μm, or at least 200 μm, at least 300 μm, at least 400 μm, at least 500 μm, at least 750 μm, at least 1000). For example, a bonding wire bonded to the source contact pad of the silicon carbide device can be similar to (e.g., can include a similar or the same diameter) a bonding wire bonded to the gate contact pad or the sense contact pad of the silicon carbide device. For example, multiple bonding wires can be bonded to the contact pads of the silicon carbide device, for example or at least 2 bonding wires, at least 5 bonding wires, at least 10 bonding wires, at least 15 bonding wires, at least 20 bonding wires, at least 50 bonding wires, at least 100 bonding wires, at least 200 bonding wires, or at least 500 bonding wires.

[0049] For example, the size of the entire lateral surface of the silicon carbide substrate 102 can be at most 200 mm 2 (e.g., at most 150 mm 2 , at most 100 mm 2 , at most 50 mm 2 ), at most 20 mm 2 (e.g., at most 10 mm 2 , at most 5 mm 2 , at most 1.5 mm 2 ), or at most 1 mm 2 (e.g., at most 0.8 mm 2 , at most 0.6 mm 2 , at most 0.5 mm 2 , at most 0.4 mm 2 , at most 0.3 mm 2 ). For example, the size of the entire lateral surface of the silicon carbide substrate can be at least 0.3 mm 2 (or at least 0.5 mm 2, at least 0.8 mm 2 , at least 1 mm 2 , at least 2 mm 2 , at least 5 mm 2 ) or at least 10 mm 2 (e.g., at least 50 mm 2 , at least 100 mm 2 , at least 200 mm 2 , at least 500 mm 2 ). The small overall lateral surface of the silicon carbide substrate 102 can enable high yields at a constant defect density.

[0050] For example, the silicon carbide device can include a package structure, such as a transistor outline (TO) package, a surface mount device (SMD) package, a molded power module, an intelligent power module, a power module. For example, the package structure can be based on chip embedding (e.g., embedded on a PCB (printed circuit board) or embedded at the wafer level).

[0051] The silicon carbide substrate 102 can be a semiconductor substrate based on a silicon carbide semiconductor material. The silicon carbide substrate 102 can be, for example, a silicon carbide die. The silicon carbide substrate 102 can include at least one of a silicon carbide wafer and an epitaxially grown silicon carbide body. For example, during manufacturing, the silicon carbide body can be epitaxially grown on the silicon carbide wafer, and at least a part of the silicon carbide wafer can be removed, for example, by a separation process, after the epitaxial growth.

[0052] The silicon carbide device 100 can include a transistor structure and / or a diode structure. For example, the silicon carbide device 100 can be or include a silicon carbide metal oxide semiconductor field effect transistor. For example, the transistor structure can be an insulated gate bipolar transistor (IGBT) or a field effect transistor (FET). For example, the transistor structure can be a vertical transistor arrangement. The transistor structure can be a vertical MOSFET (metal oxide semiconductor - FET) or an IGBT. For example, the vertical transistor arrangement can be an electrical structure that enables vertical current flow. For example, the transistor structure of the silicon carbide device 100 can control and / or conduct and / or block the current flow between the front side and the back side of the silicon carbide device.

[0053] For example, the transistor of the silicon carbide device can include a trench gate. The trench gate can include a gate electrode and a gate insulating layer, both of which are located in the trench. The trench can extend from the front side surface of the silicon carbide substrate into the silicon carbide substrate. For example, the transistor (e.g., a transistor cell) can be arranged at only one side of the trench gate (e.g., as Figure 3aas shown in FIGS. 3a and / or 3b; also referred to hereinafter as an asymmetric transistor cell arrangement) or on both sides of the trench gate such that the body regions can be located at two opposite sides of the trench gate (also referred to hereinafter as a symmetric transistor cell arrangement). For example, the body regions can be in contact with the sidewalls of the trench gate (e.g., the gate insulating layer of the trench gate). In the case of a symmetric transistor cell arrangement, each body region can be in contact with a respective sidewall of the trench gate.

[0054] The semiconductor device can include a shielding doped region. The shielding doped region can have a second conductivity type. The shielding doped region can be located below the trench including the trench gate. For example, the shielding doped region can be positioned adjacent to the bottom of the trench and / or directly below the trench. Additionally or alternatively, the shielding doped region can be located between adjacent gate trenches of adjacent transistor cells. Adjacent shielding doped regions of adjacent transistor cells can form a JFET for shielding the gate insulating layer (especially the corner of the gate insulating layer between the sidewall and the bottom of the trench) from a high electric field, which may cause breakdown of the gate insulating layer.

[0055] The shielding doped region can be connected to a voltage different from that of the gate electrode. In particular, the shielding doped region can be electrically connected to the source region and the body region. The shielding doped region can be located only below or beneath the trench. In this case, in addition to the gate electrode, the trench can include a second electrode that is in electrical contact with the shielding doped region. The second electrode can be located, for example, at the bottom of the trench or can be laterally surrounded by the gate electrode. Alternatively, the second electrode can be located outside the trench, e.g., between adjacent gate trenches of adjacent transistor cells. The second electrode can electrically connect the shielding doped region to the voltage different from that of the gate electrode (e.g., the source voltage). Or, especially in the case of an asymmetric transistor cell arrangement, the upper portion of the shielding doped region can extend along the sidewall of the trench gate opposite to the sidewall in contact with the body region. The upper portion can be in contact with and / or electrically connected to the body region and / or the source region. The upper portion of the shielding doped region can have a higher doping concentration than the lower portion of the shielding doped region located near the bottom of the trench.

[0056] The transistor structure of the silicon carbide device 100 can be a transistor cell among a plurality of transistor cells of a transistor arrangement. For example, the transistor cell can include one or more source regions (e.g., distributed or positioned along the gate), at least one body region, and a gate (e.g., a trench gate located in a trench extending into the semiconductor substrate). Additionally, the transistor cells among the plurality of transistor cells can share a common (mutual) drift region and / or a common drain region (e.g., the transistor cells are MOSFET cells) or a common collector region (e.g., the transistor cells are IGBT cells).

[0057] The silicon carbide substrate may include a cell region (or active region) laterally surrounded by an edge termination region. The cell region may be a region of the silicon carbide substrate that conducts more than 90% of the current through the semiconductor substrate in the on-state or conducting state of a transistor arrangement including a plurality of transistor cells. For example, the cell region may be a region that includes all vertical transistors and / or all transistors and / or all source regions of the transistor arrangement of a semiconductor device. The edge termination region may be located between the edge of the silicon carbide substrate and the cell region to support or block or reduce or dissipate the maximum voltage applied between the front side surface and the back side surface of the semiconductor substrate in the cell region that is laterally directed towards the edge of the silicon carbide substrate.

[0058] For example, the transistor structure and / or diode structure of the silicon carbide device 100 may have a breakdown voltage greater than 100V, such as greater than 200V, greater than 500V, greater than 1000V. The silicon carbide device 100 may be a power silicon carbide device. For example, the power silicon carbide device, the electrical component arrangement, and / or the transistor structure of the power silicon carbide device may have a breakdown voltage greater than 100V (e.g., a breakdown voltage of 200V, 300V, 400V, or 500V) or greater than 500V (e.g., a breakdown voltage of 600V, 700V, 800V, or 1000V) or greater than 1000V (e.g., a breakdown voltage of 1200V, 1500V, 1700V, 2000V, 3300V, or 6500V) or a blocking voltage.

[0059] For example, the vertical direction and the vertical dimension or thickness of the layer may be measured orthogonally to the front side surface of the silicon carbide substrate 102 along the vertical direction of the silicon carbide substrate 102, and the lateral direction and the lateral dimension may be measured along the lateral direction of the silicon carbide substrate 102 parallel to the front side surface of the silicon carbide substrate 102. The front side of the silicon carbide substrate may be a side different from the back side of the silicon carbide substrate for implementing more refined and complex structures (e.g., the gate of a transistor or a transistor cell) because the process parameters (e.g., temperature) and processing may be limited for the back side if a structure has been formed on one side of the silicon carbide substrate. The layer stack of the silicon carbide device 100 including the contact layer 102, the barrier layer structure 106, and the metallization layer 108 may be located at the front side of the silicon carbide substrate 102.

[0060] In combination with the proposed concept or one or more examples described above or below (e.g., Figures 2 to 14 ) more details and aspects of the silicon carbide device 100 are mentioned. The silicon carbide device 100 may include one or more additional optional features corresponding to one or more aspects of the proposed concept or one or more examples described above or below.

[0061] Figure 2A schematic cross-section of a portion of a silicon carbide device 200 is shown. For example, the silicon carbide device 200 can be a power semiconductor device. A silicon carbide device 200 similar to Figure 1 can be implemented. The silicon carbide device 200 can include a silicon carbide substrate 102. The silicon carbide device 200 can also include a contact layer 104, which includes nickel, silicon, and aluminum. The contact layer 104 can be located on the silicon carbide substrate 102. The silicon carbide device 200 can include a barrier layer structure 106 (and / or adhesion promoting layer) that includes titanium and tungsten. The contact layer 104 can be located (e.g., vertically) between the silicon carbide substrate 102 and at least a portion of the barrier layer structure 106. The silicon carbide device 200 can include a metallization layer 108 (and / or power metal) that includes copper. The barrier layer structure 106 can be located (e.g., vertically) between the silicon carbide substrate 102 and the metallization layer 108. The barrier layer structure 106 of the silicon carbide device 200 can include a plurality of barrier layers 202, 204, and 206.

[0062] More details and aspects of the silicon carbide device 200 are mentioned in connection with the concepts presented or above or below (e.g., Figure 1 , Figures 3a to 14 ). The silicon carbide device 200 can include one or more additional optional features corresponding to one or more aspects of the concepts presented or one or more examples described above or below.

[0063] The embodiments can also relate to additional silicon carbide devices. Additional silicon carbide devices similar to those presented in connection with Figure 1 and Figure 2 can be implemented. Instead of including the barrier layer structure 106 that includes titanium and tungsten, an additional silicon carbide device can include a barrier layer structure that includes molybdenum and nitrogen, such as a MoN layer. The additional silicon carbide device can include a silicon carbide substrate, which can be implemented similarly to the silicon carbide substrate 102 presented in connection with Figure 1 and Figure 2 . The silicon carbide device can include a contact layer that includes nickel, silicon, and aluminum, which can be implemented similarly to the contact layer 104 presented in connection with Figure 1 and / or Figure 1 The contact layer can be located on the silicon carbide substrate. The additional silicon carbide device can include a barrier layer structure that includes molybdenum and nitrogen. The contact layer can be located between the silicon carbide substrate and at least a portion of the barrier layer structure (e.g., vertically therebetween). The silicon carbide device can include a metallization layer that includes copper, which can be implemented similarly to the metallization layer 108 presented in connection with Figure 2 . The barrier layer structure can be located between the silicon carbide substrate and the metallization layer (e.g., vertically therebetween).

[0064] In at least some embodiments, an implementation similar to that presented in connection withFigure 1 and / or a barrier layer structure of another silicon carbide device as introduced in 2, wherein the barrier layer structure may not necessarily include titanium and tungsten. For example, the barrier layer structure can be like Figure 1 the barrier layer structure 106 of 2 and / or 2, where a MoN layer is used instead of the TiW layer. For example, the barrier layer structure can include a Ti / TiN layer. For example, the barrier layer structure can include a Ti / TiN layer and a MoN layer. The MoN layer can be in contact with the metallization layer. The Ti / TiN layer can be in contact with the contact layer. The barrier layer structure can include a TiWN layer.

[0065] Another silicon carbide device can include a transistor structure and / or a diode structure. For example, another silicon carbide device can be or include a silicon carbide metal-oxide-semiconductor field-effect transistor. For example, the transistor structure can be an insulated-gate bipolar transistor (IGBT) or a field-effect transistor (FET). For example, the transistor structure can be a vertical transistor arrangement. The transistor structure can be a vertical MOSFET (metal-oxide-semiconductor - FET) or an IGBT. For example, the vertical transistor arrangement can be an electrical structure that enables vertical current flow. For example, the transistor structure of another silicon carbide device can control and / or conduct and / or block the current flow between the front side and the back side of the silicon carbide device.

[0066] In combination with the proposed concept or the above or below (e.g., Figure 1 , Figures 3a to 14 ) more details and aspects of another silicon carbide device are mentioned in connection with one or more examples described. Another silicon carbide device can include one or more additional optional features corresponding to one or more aspects of the proposed concept or one or more examples described above or below.

[0067] Figure 3a and 3b shows a schematic cross-section of silicon carbide devices 300a; 300b, which can be silicon carbide metal-oxide-semiconductor field-effect transistors. The silicon carbide devices 300a; 300b can be implemented similar to the silicon carbide devices 100; 200 introduced in combination with Figure 1 and Figure 2 . The silicon carbide devices 300a; 300b include a contact layer 104, a (TiW) barrier layer structure 106, and a metallization layer 108. The contact layer 104, the barrier layer structure 106, and / or the metallization layer 108 can be implemented similar to the corresponding components of the silicon carbide devices 100; 200. The silicon carbide devices 300a; 300b include a transistor, which includes a vertically located highly n-doped n+ source region 310a; 310b and a slightly n-doped drift region 330b ( Figure 3b of the silicon carbide device 300b) and / or a current spreading region n2330a (Figure 3a body regions 320a; 320b therebetween.

[0068] The silicon carbide devices 300a; 300b include a trench gate structure. For example, the gate insulating layers 342a; 342b of the gate structure are located between the gate electrodes 340a; 340b positioned in the trenches and the body regions 320a; 320b. In the operating mode of the transistor, the current flowing through the channel region of the transistor can be controlled by the gate voltage applied to the gate electrodes 340a; 340B.

[0069] The (highly) p-doped regions 350a; 350b (p+ top / p-emitter) of the silicon carbide devices 300a; 300b can be positioned adjacent to the gate insulating layers 342a; 342b at a side of the gate structure opposite to the sidewalls of the gate structure and adjacent to the body region of the transistor. The highly p-doped regions 350a; 350b extend from the bottom of the trench gate structure along the sidewalls of the trench gate structure to the highly n-doped regions 370a; 370B. In addition, in Figure 3a a p-doped shielding region 360a (p-buried) can be located at the bottom of the trench structure. The highly n-doped regions 370a; 370b extend along the sidewalls of the trench gate from within the highly p-doped regions 350a; 350b to the front-side surface of the silicon carbide substrate. The highly n-doped regions 370a; 370b can be formed simultaneously with the highly n-doped n+ source regions 310a; 310b. The highly n-doped regions 370a; 370b can be connected to the highly n-doped n+ source regions 310a, 310b. For example, a highly n-doped interconnect region can be located between the highly n-doped n+ source regions 310a; 310b and the highly n-doped regions 370a; 370b (not shown in the cross-section of Figure 3a and 3b . The highly n-doped regions 370a; 370b and / or the highly n-doped source regions 310; 310b can extend along the trench in the lateral direction, particularly perpendicular to the lateral direction of the cross-section shown in Figure 3a and 3b .

[0070] More details and aspects of the silicon carbide devices 300a; 300b are mentioned in connection with the proposed concepts or one or more examples described above or below (e.g., Figure 1 , 2 , 4a to 14). The silicon carbide devices 300a; 300b can include one or more additional optional features corresponding to one or more aspects of the proposed concepts or one or more examples described above or below.

[0071] Figure 4a and 4b show a schematic diagram of a bonding wire bonded to a contact pad of a silicon carbide device.Figure 4a An embodiment of a silicon carbide device including contact pads 404 (source) and 406 (gate) is shown. The contact pads 404 and 406 may be formed at least in part from a metallization layer of the silicon carbide device. Figure 4a Bonding wires 402 are also shown, which are bonded to the contact pads using wedge bonding. On contact pad 404, double wedge bonding is used, and on contact pad 406, (single) wedge bonding is used. Figure 4b Another embodiment of a silicon carbide device including contact pads 414 (source) and 416 (gate) is shown. The contact pads 414 and 416 may be formed at least in part from a metallization layer of the silicon carbide device. Figure 4b Bonding wires 412 are further shown, which are bonded to the contact pads using nail head (or thermosonic ball wedge) bonding.

[0072] More details and aspects of the silicon carbide device are mentioned in connection with the concepts presented or one or more of the examples described above or below (e.g., [[ID=4 \7]]Figures 1 to 3b , Figures 5 to 14 ). The silicon carbide device may include one or more additional optional features corresponding to one or more aspects of the concepts presented or one or more of the examples described above or below.

[0073] Some embodiments relate to semiconductor devices having a layer stack as described with respect to Figure 1 . In these examples, the layer stack may be disposed on a silicon substrate or another wide bandgap semiconductor substrate rather than silicon carbide. For example, the wide bandgap semiconductor substrate may have a bandgap greater than 2.5 eV, e.g., greater than 3 eV. For example, the wide bandgap semiconductor substrate may be a diamond (C) substrate or a gallium nitride (GaN)-based semiconductor substrate.

[0074] Figure 5 A flowchart of a method 500 for forming a silicon carbide device is shown. Alternatively, for example, a power semiconductor device may be formed according to method 500. The silicon carbide device may be implemented similarly to the silicon carbide devices introduced in connection with Figures 1 to 4b . Method 500 may include forming 110 a contact layer 104 including nickel, silicon, and aluminum on a silicon carbide substrate 102 of the silicon carbide device. Method 500 may include forming 120 a barrier layer structure 106 including titanium and tungsten after forming the contact layer 104. As an alternative or addition to forming the barrier layer structure 106, for example, an adhesion promoting layer may be formed. Method 500 may include forming 130 a metallization layer 108 including copper after forming the barrier layer structure 106. As an alternative or addition to forming the metallization layer 108, for example, a power metal may be formed. An ohmic connection (e.g., an ohmic path) may be formed between the metallization layer and a doped region of the silicon carbide substrate (e.g., the source region of the silicon carbide substrate or the body region of the silicon carbide substrate) via (i.e., through) the barrier layer structure 106 and the contact layer 104.

[0075] The contact layer 104 may be located (e.g., vertically) between the silicon carbide substrate 102 and at least a portion of the barrier layer structure 106 (and / or e.g., an adhesion promoting layer). The barrier layer structure 106 may be located (e.g., vertically) between the silicon carbide substrate 102 and the metallization layer 108 (and / or e.g., a power metal).

[0076] For example, the formation 110 of the contact layer 104 may include depositing a layer including NiAl on the silicon carbide substrate 102. For example, NiAl may be deposited in a single step using a sputtering process. Alternatively, NiAl may be deposited by depositing Ni and Al layers adjacently. For example, the Al content of the NiAl layer may be at least 0.1% (or at least 0.2%, at least 0.5%, at least 1%, at least 2%, at least 5%, at least 10%, at least 15%) and / or at most 30% (or at most 25%, at most 20%, at most 15%, at most 10%, at most 5%, at most 2%, at most 1%) by volume. The NiAl layer may have a vertical thickness of at least 20 nm (or at least 30 nm, at least 40 nm, at least 50 nm, at least 80 nm, at least 100 nm) and / or at most 150 nm (or at most 120 nm, at most 100 nm, at most 80 nm, at most 50 nm). The formation 110 of the contact layer 104 may further include performing a high temperature treatment on the silicon carbide substrate 102 and the NiAl to form a NiSiAl contact layer 104 that provides an ohmic connection to the silicon carbide substrate 102. The method may include alloying a region of the silicon carbide substrate 102 and the NiAl layer to form the NiSiAl contact layer. For example, the front surface of the silicon carbide substrate 102 may be cleaned before depositing the layer including NiAl. For example, the formation 110 of the contact layer may include cleaning the front surface of the silicon carbide substrate 102. For example, the barrier layer structure 106 may be deposited on the contact layer 104. For example, the method may further include cleaning the front side of the silicon carbide device using, for example, wet chemical cleaning or dry cleaning after forming the contact layer (e.g., after forming the ohmic contact). For example, the barrier layer structure 106 may be further deposited on a portion of the silicon carbide substrate (e.g., see Figures 6a to 6e 600a of). For example, the formation 120 of the barrier layer structure may include forming a Ti / TiN layer.

[0077] For example, the metallization layer 108 may include depositing a (copper) metallization layer in situ on, for example, the barrier layer structure 106 by using sputtering or subsequently using copper electroplating. The method may further include forming a passivation layer on the metallization layer.

[0078] In combination with the proposed concept or above or below (e.g., Figure 1 to 4, Figures 6a to 14)One or more of the described examples mention more details and aspects of method 500. Method 500 may include one or more additional optional features corresponding to one or more aspects of the proposed concept or one or more of the examples described above or below.

[0079] For example, ultra-small SiC chips can be used. Using conventional connection techniques based on Al (aluminum) front-side metallization and Al wire bonding, this may be almost impossible because there may be limitations due to the Al wire thickness in order to comply with bonding rules. Otherwise, in order to be able to place the corresponding Al wire, it may be necessary to provide an unnecessary larger SiC area. Due to the high area / space-related costs, very small chips can be designed, which contradicts the diameter of the Al wire. In addition, there may be limitations on static load relative to Al Cu (aluminum copper) and Al wire. SiC devices may require a new metallization system. On the other hand, overloads occur, such as short circuits, and especially surge current events, which may occur more frequently in applications. For SiC, only a very small top area (3 - 10 μm) of the chip may be electrically strained. Therefore, especially the front-side metallization may become very hot. The low melting point of aluminum may be an obstacle here. Premature aging (e.g., recrystallization) may occur.

[0080] At least some methods may be based on Si IGBT (insulated gate bipolar transistor), here on the one hand as Al(Si)Cu (aluminum silicon copper) metallization including Al wire bonding, and on the other hand as a further improvement, pure Cu front-side metallization including Cu wire bonding can be used. In the case of AlCu front-side metallization, a diffusion barrier may not necessarily be required, and typically Ti (titanium) or TiN (titanium nickel) can be used as a liner (adhesive). In the case of Cu front-side metallization, a Cu diffusion barrier may be required to prevent Cu diffusion into the Si. Here, a TiW / W (titanium tungsten / tungsten)-based barrier can be used. The Al-based metallization system can be integrated without a barrier and can be used in at least some semiconductor devices. However, with these products, an increasing number of interconnections (Al(Si)Cu front-side metal Al wire) may limit the product performance regarding power cycling and short-circuit robustness, the latter also based on weaker thermal diffusion, the reduced specific heat capacity and melting temperature of Al. In addition, there may be high manufacturing costs to accommodate Al wedge wires on the chip.

[0081] Since a 5 - to 10-fold higher power density can be possible for material reasons in the case of SiC devices, the AlCu - Al bond may not be considered for further shrinkage if the advantages of the base material are to be utilized. However, this may be possible by using Cu-based front-side metallization in the context of Cu wire bonding.

[0082] At least some embodiments can provide a combined ohmic contact-barrier-copper-front-side-metallization for increasing the power density of SiC MOSFETs. Embodiments can be based on the use of a combined front-side layer set for SiC devices. The combined front-side layer set for SiC devices can consist of or include a NiAl contact layer (e.g., contact layer 104), a TiW diffusion barrier (e.g., barrier structure 106), and a final Cu metallization (e.g., metallization layer 108). The difference compared to Si can be the first NiAl contact layer, which can form an ohmic contact with the semiconductor body. While one Ti(W) layer may be sufficient for highly doped Si to achieve a low-ohmic metal-semiconductor tunneling contact, this may not be feasible for SiC due to the significantly larger bandgap (3.3 eV instead of 1.1 eV). As a starting material, a Ni-based metal alloy can be used, with an Al content of 0.1% to 30% and a thickness of 20 to 150 nm. NiAl can be deposited in one step using a sputtering process, where a NiAl composite target with a given composition can be used here. It may also be possible to deposit the Ni and Al layers next to each other. In this case, the NiAl composition can be freely selected. By a subsequent high-temperature step, the NiAl layer forms an ohmic contact for n-SiC and for p-SiC. Here, a mixture of semiconductor (e.g., SiC substrate 102) and metal (e.g., contact layer 104) can be produced. Thus, an ohmic contact can be obtained. This process step can be crucial because the metal-semiconductor interface can react highly sensitively to the metal composition (for n-SiC, the Al content in NiAl is typically lower, while for p-SiC it is higher), doping, and alloying temperature. It may be important that the SiC surface is free of impurities before depositing NiAl.

[0083] In the next step, a TiW-based Cu barrier (e.g., the barrier layer structure 106) and the power Cu (e.g., the metallization layer 108) itself can be deposited. The power Cu can be deposited in-situ with a TiW barrier (by sputtering techniques) or later by Cu electroplating. The latter can be made very thick, up to 20 - 100 μm, while in the case of sputtering Cu alone, there may be a limit of about 5 - 10 μm. A passivation / protection layer can be used as protection for the Cu metallization. Thus, very small SiC chips can be possible, which can include lower capacitance and higher electrical yield (with a constant defect density) simply due to their area. Cu wires can be applied using proven fine wire techniques (Cu stud bonding) or thick wire techniques (wedge bonding). Fine Cu wires can provide maximum flexibility as well as high current-carrying capacity. Essentially more stable Cu / Cu interconnects can achieve higher load cycle capabilities. Additionally, due to Cu (Cu and Cu wires), better thermal diffusion and heat dissipation can be possible from the SiC front side. Thereby, higher short-circuit robustness and higher current ratings can be achieved. Front-side interconnects (FSI) can be applied by current (embedded) or by Cu clips or Cu blocks instead of Cu wires. The Cu fine wire connection technique can be more space-saving than the Al wedge connection technique. Thus, the gate pads can be reduced to a size of, for example, 60 μm × 60 μm. This can reduce costs, for example, when considering the high space cost of SiC or having other sensing pads (temperature, current, etc.).

[0084] In an embodiment, a silicon carbide device can include an ohmic contact layer, a barrier, and Cu metallization. For example, a silicon carbide device can include an ohmic contact layer, a barrier, Cu metallization, and Cu bond wires. For example, a silicon carbide device can include a NiAl ohmic contact layer, a barrier, Cu metallization, and Cu bond wires. For example, a silicon carbide device can include an ohmic contact layer, a TiW barrier, Cu metallization, and Cu bond wires. For example, a silicon carbide device can include a NiAl ohmic contact layer, a TiW barrier, Cu metallization, and Cu bond wires. For example, a silicon carbide device can include a nickel-based ohmic contact layer, a barrier, Cu metallization, and Cu bond wires. Alternatively, a silicon carbide device can include a titanium-based ohmic contact layer, a barrier, Cu metallization, and Cu bond wires. For example, a silicon carbide device can include an ohmic contact layer, a barrier including Ti / TiN, Cu metallization, and Cu bond wires. Alternatively or additionally, a silicon carbide device can include an ohmic contact layer, a barrier including MoN, Cu metallization, and Cu bond wires.

[0085] As a basis for at least some embodiments, a SiC diode or also a SiC MOSFET can be used, where device-specific details can be omitted hereinafter. The main elements of the FEOL (front end of the line) process flow are illustrated in Figures 6a to 6e and start with the process block ohmic NiAl contact (Figure 6a and 6b , such as contact layer 104), followed by a TiW barrier ( Figure 6c , such as a barrier layer structure 106 including a single TiW layer), and then the fabrication of the Cu metallization ( Figure 6d sputtering process, such as metallization layer 108). Using device passivation (here: imide 602, Figure 6e ), the front-side process can be completed, and the front-end (FE) process can be completed by a back-side process (grinding, back-side contact, not shown).

[0086] Figures 6a to 6e Schematic cross-sections of portions of silicon carbide devices 600a; 600b at various stages of forming silicon carbide devices are shown. Silicon carbide devices 600a; 600b can be implemented similar to the silicon carbide devices described in connection with Figures 1 to 5 . Silicon carbide devices 600a; 600b include a silicon carbide substrate 102, a contact layer 104 containing NiAl, a barrier layer structure 106 containing TiW, and a metallization layer 108 containing copper. The silicon carbide substrate 102, contact layer 104, barrier layer structure 106, and / or metallization layer 108 can be implemented similar to the corresponding components of silicon carbide described in connection with Figures 1 to 5 . Silicon carbide devices 600a and 600b differ in that the barrier layer structure 106 of silicon carbide device 600a covers (the entire) contact layer 104, while the barrier layer structure 106 of silicon carbide device 600b (only) partially covers contact layer 104.

[0087] Figure 6a Schematic cross-sections of the SiC semiconductor body (including silicon carbide substrate 102 of silicon carbide devices 600a; 600b) are shown after depositing and patterning the ohmic NiAl metallization 104 (such as contact layer 104) to contact p- and n-SiC regions (not specified in the figure).

[0088] Figure 6b Schematic cross-sections of the SiC semiconductor body are shown after alloying the NiAl contact 104 by RTP (rapid thermal processing).

[0089] Figure 6c Schematic cross-sections of the SiC semiconductor body are shown after depositing and patterning the TiW barrier 106 (or for example another barrier layer structure 106 and / or adhesion promotion layer). In silicon carbide device 600a, the TiW layer is smaller than the NiAl layer, and in silicon carbide device 600b, the NiAl contact layer is completely covered by the TiW layer.

[0090] Figure 6dShows a schematic cross-section of a SiC semiconductor body after deposition and structuring of the Cu pad metallization 108 (e.g., metallization layer 108 and / or power metal).

[0091] Figure 6e Shows a schematic cross-section of a SiC semiconductor body after deposition and structuring of the imide passivation 602.

[0092] In connection with the concepts proposed or described above or below (e.g., Figures 1 to 5 , Figures 7 to 14 ) refer to more details and aspects of the examples shown in Figures 6a to 6e . The method 500 may include one or more additional optional features corresponding to one or more aspects of the concepts proposed or one or more of the examples described above or below.

[0093] Figure 7 Illustrates a cross-sectional view of a power semiconductor device 1100 having a semiconductor substrate 1110. The power semiconductor device 1100 may include, for example, a silicon carbide device, and / or the semiconductor substrate 1110 may be, for example, a silicon carbide substrate. Hereinafter, the power semiconductor device (e.g., a silicon carbide device) is also simply referred to as a power device. By way of example only, Figure 7 the power semiconductor device 1100 in Figure 7 is depicted as a vertical transistor with a trench gate and a so-called trench contact. However, those skilled in the art should understand that certain concepts explained in connection with the embodiments shown in Figures 7 to 11 and the embodiments shown in Figures 7 to 11 apply to various types of power semiconductor devices, such as, for example, field effect transistors (FETs; e.g., MOSFETs or JFETs), IGBTs or diodes (e.g., integrated pin Schottky diodes or integrated pin heterojunction diodes), where each of said power semiconductor devices may optionally include a so-called superjunction structure (also referred to as a "charge compensation structure"). In particular, the various concepts explained in connection with the embodiments of Figures 7 to 11 may apply to lateral transistors, transistors with planar gate contacts and / or transistors with planar source contacts. Additionally, the various concepts explained in connection with the embodiments of

[0094] The semiconductor substrate 1110 (e.g., a silicon carbide substrate) can be made of any wide-bandgap semiconductor material suitable for manufacturing semiconductor components. Typically, the semiconductor substrate 1110 includes silicon carbide (SiC) as the main material. Generally, the semiconductor substrate 1110 can include SiC, GaN, AlN, or Ga2O3, more specifically SiC, GaN, or AlN as the main material. Typically, the semiconductor substrate 1110 is composed of any one of these wide-bandgap materials, which contains typical unintentional impurities and intentional dopants. In other words, the main material of the semiconductor substrate can be the corresponding wide-bandgap material, such as SiC (including any of its crystal variants), GaN, AlN, or Ga2O3, especially SiC or AlN. Hereinafter, the main material of a layer or substrate can be those atoms that form a compound or alloy.

[0095] Although generally wide-bandgap materials, especially SiC, can have a higher intrinsic temperature, the use of wide-bandgap semiconductor materials as substrate materials should not be regarded as an essential feature of the power semiconductor device 1100. Instead, the semiconductor substrate 1110 (e.g., a silicon carbide substrate) can include any other suitable material for power semiconductor devices, such as silicon (Si).

[0096] According to one embodiment, the semiconductor substrate 1110 is mainly formed of SiC, especially 4H-SiC, that is, the main material or main part of the semiconductor substrate 1110 has a 4H-SiC crystal structure.

[0097] The semiconductor substrate (e.g., a silicon carbide substrate) can be a semiconductor wafer and / or an epitaxially grown semiconductor body. For example, the semiconductor substrate can include a semiconductor body that has been epitaxially grown on a semiconductor wafer. Here, after epitaxial growth, at least a part of the wafer can be removed (e.g., by thinning or cutting).

[0098] The semiconductor substrate 1110 (e.g., a silicon carbide substrate) includes a first surface 1111 and a second surface 1112. The first surface 1111 defines a first side of the power device 1100, and the second surface 1112 is disposed opposite to the first surface 1111 and defines a second side of the power device 1100.

[0099] The power device 1100 includes an active region 1103. The active region 1103 is a region of the semiconductor substrate 1110 that mainly carries the load current passing through the power device 1100. In the case of a three-terminal device such as a MOSFET or an IGBT, the active region 1103 is defined by a plurality of active transistor units, and each active transistor unit is configured to carry a part of the load current. In particular, the active region 1103 can include at least one channel of the active transistor units, and the at least one channel can be configured to carry a part of the load current.

[0100] The power device 1100 may optionally include a lateral outer edge 1105 and an edge termination region 1104 disposed between the active region 1103 and the lateral outer edge 1105. Different from the active region 1103, when the power device 1100 is in the blocking mode, the edge termination region 1104 provides a controlled release of the blocking voltage in the peripheral region of the semiconductor substrate 1100. The edge termination region 1104 includes structures such as field rings and field electrodes to shape the electric field and avoid local exaggeration of the electric field intensity.

[0101] Figure 7 Schematically illustrated are vertical transistor cells formed by respective gate trenches and formed between the respective gate trenches. Each gate trench includes a gate electrode 1132 that is electrically insulated from the surrounding semiconductor material by a respective gate dielectric 1131. The gate trench extends from the first surface 1111 to a given depth in the semiconductor substrate 1110. The gate trench particularly extends through a first doped region 1121 where a respective source region may be formed, a second doped region 1122 where a respective body region may be formed, and into a third doped region 1123 where a common drift region for forming active transistor cells may be formed. A fourth doped region 1124 may be formed at the second surface 1112 of the semiconductor substrate 1110. The fourth doped region 1124 may form a drain region in the case of a MOSFET and an emitter region in the case of an IGBT.

[0102] The first doped region 1121, the second doped region 1122, the third doped region 1123, and the fourth doped region 1124 may be formed in the semiconductor substrate 1110 in this order from the first surface 1111 to the second surface 1112. Each of the transistor cells may include at least one additional doped region that is not shown in Figure 7 . For example, a diode region (sometimes also referred to as a "shielding region") may be located below at least some of the gate trenches (see also Figure 11 ).

[0103] In the case of a MOSFET, the source region 1121, the drift region 1123, and the drain region 1124 have a first conductivity type such as n-type, while the body region 1122 has a second conductivity type such as p-type. In the case of an IGBT, the source region 1121 (sometimes also referred to as the emitter region) and the drift region 1123 have the first conductivity type, while the body region 1123 and the emitter region 1124 have the second conductivity type.

[0104] The insulating layer 1140 is disposed on the first surface 1111 of the semiconductor substrate 1110. The insulating layer 1140 may be formed of a single layer or a stack of layers including different materials. For example, the insulating layer 1140 may be in direct contact with the semiconductor substrate 1110, such as in direct contact with the entire first surface 1110 of the semiconductor substrate 1110. In other embodiments ( Figure 7 not shown), the metallization may be in direct contact with at least a portion of the first surface 1110. Typically, the insulating layer 1140 is formed of silicon oxide, which is deposited by chemical vapor deposition.

[0105] The insulating layer 1140 may also form a so-called inter-metal dielectric, which is an insulating layer between different levels of conductive layers, such as between a lower polysilicon layer and an upper metal layer.

[0106] An opening 1141 is formed in the insulating layer 1140. The material of the insulating layer 1140 may surround the corresponding opening 1141, for example. The opening 1141 generally extends from the upper surface of the insulating layer 1140 to the lower surface of the insulating layer 1140, which faces the first surface 1111 of the semiconductor substrate 1110.

[0107] In Figure 7 embodiments, the opening 1141 is depicted as a trench having a width (i.e., the lateral extent along the first surface 1111) that is substantially less than the width of the corresponding transistor cell (i.e., the lateral distance between adjacent gate trenches). For example, the width of the opening 1141 may be at most 50% of the width of the transistor cell, typically at most 20% or at most 10%.

[0108] However, in other embodiments, the width of the opening 1141 may be at least 70%, typically at least 80% of the width of the corresponding transistor cell (see, for example, Figure 11 embodiments). In such a case, a substantially planar contact (e.g., metallization) from a conductive material may be used to make electrical contact with the first doped region 1121 and / or the second doped region 1122, for example, via an ohmic connection.

[0109] For example, an etch mask may be used ( Figure 7Openings 1141 are formed by one or more etching processes (not shown in the figure). According to an exemplary embodiment, the etching process is also adapted to etch a portion of the semiconductor substrate 1110 to form contact trenches that extend through the first doped region 1121 and / or into the second doped region 1122 of the corresponding active transistor unit. If the first doped region 1121 is a source region, such a contact extending into the first doped region and / or the second doped region 1122 may also be referred to as a source trench. In other embodiments, the etching process stops at the first surface 1111 of the semiconductor substrate 1110. In this case, a planar contact can be formed at the first surface 1111 together with the first doped region 1121 and / or the second doped region 1122.

[0110] Each opening 1141 and the corresponding contact trench are filled with a conductive material that forms the corresponding plugs 1171, 1172, 1173. The conductive material can form an electrical connection (typically an ohmic connection) with the first doped region 1121 and the second doped region 1122. In other embodiments ( Figure 7 not shown in the figure), the conductive material can be coated as a layer on the first surface 1111 of the semiconductor substrate 1110. Generally, the conductive material can form an electrical connection (ohmic or Schottky) with at least one doped region of the semiconductor substrate 1110.

[0111] Figure 7 Different types of plugs are shown. The semiconductor device 1100 described herein may include only one or several different types of the plugs shown. However, as previously mentioned, other types of connectors are also possible. The concepts described in connection with Figure 7 the trench plugs can also be applied to other types of connectors, such as planar connectors. The plug 1171 completely fills the opening 1141 including the contact trench. The material of the plug 1171 can be different from the material of the subsequently formed pre-metalization 1150. The pre-metalization 1150 can include, for example, two or more layers, such as a contact layer and / or a barrier layer structure and / or a metallization layer. Alternatively, as shown by 1172, the plug can be integrated with the pre-metalization 1150 and have the same material as the pre-metalization 1150. The plug 1172 can be formed together with the pre-metalization 1150. In another variant, the plug 1173 is also formed of a material different from the material of the pre-metalization 1150 and contacts the fifth doped region 1125 formed in the second doped region 1122. The fifth doped region 1125 has the same conductivity type as the second doped region 1122 but is typically doped much higher than the second doped region 1122 to provide a low-ohmic contact between the plug 1173 and the second doped region 1122. The fifth doped region 1125 is generally referred to as a body contact region because it provides contact with the body region 1122.

[0112] Plugs 1171, 1172, 1173 disposed in respective openings 1141 of the insulating layer 1140 provide metal connections that conductively connect the front metallization 1150 to the semiconductor substrate 1110, for example, conductively connect to the first doped region 1121 and the second doped region 1122 of the semiconductor substrate 1110.

[0113] The front metallization 1150 is disposed on or above the insulating layer 1140 and is generally in contact with the insulating layer 1140. The plugs 1171, 1172, and 1173 extend from the front metallization 1152 to the semiconductor substrate 1110 and provide respective ohmic contacts with the respective doped regions of the semiconductor substrate 1110. Thus, the insulating layer 1140 is inserted between the front metallization and the first surface 1111 of the semiconductor substrate 1110.

[0114] The back metallization 1160 is formed on and in contact with the second surface 1112 of the semiconductor substrate 1110.

[0115] The front metallization 1150 and the back metallization 1160 include a metal or a metal alloy. The material for the front metallization 1150, particularly the material of the power metal of the front metallization, and the back metallization 1160 can be the same or can be different. In addition, both the front metallization 1150 and the back metallization 1160 can be formed of a single material layer or can include at least two material layers formed of different metals.

[0116] According to one embodiment, the semiconductor substrate 1110 is a so-called wide-bandgap semiconductor material made of, for example, SiC, GaN, AlN, and Ga2O3. Particular interest lies in SiC and AlN. The semiconductor material of the semiconductor substrate 1110 has a given intrinsic temperature, which is generally at least 600 °C, such as at least 1100 °C. According to one embodiment, the material for forming at least one layer of the front metallization 1150, particularly the front metallization 1150, is selected such that its melting temperature is higher than the intrinsic temperature of the semiconductor material of the semiconductor substrate 1110. Selecting a metal or a metal alloy or a layer stack of a metal and a metal alloy having a high melting temperature ensures the robustness of the power device is not affected by the metallization. This will be described in further detail below with reference to Figures 12 to 14 be described in further detail.

[0117] According to one embodiment, the front metallization 1150 or at least one layer of the front metallization 1150 contains a metal having a melting temperature lower than the intrinsic temperature of the semiconductor material of the semiconductor substrate 1110 and less than 1% by weight relative to the total amount of the front metallization. For example, the front metallization 1150 may contain no aluminum or only less than 1% by weight of aluminum.

[0118] In addition, in some embodiments, the pre-metallization 1150 may also be copper-free (except for impurities due to manufacturing) or less than 1% by weight of copper. Both aluminum and copper are widely used materials for forming thick pre-metallization as well as post-metallization. However, both metals (including alloys formed from these metals) have relatively low melting temperatures, which are typically lower than the inherent temperature of wide-bandgap semiconductor materials. This may be particularly true for SiC as the main material of the semiconductor substrate.

[0119] According to one embodiment, the pre-metallization 1150 comprises or consists essentially of one or more metals or metal alloys selected from the group consisting of Ti, TiN, TiW, V, Nb, Ta, TaN, Mo, W, WN, NiAl, Mo, MoN, Cu, Hf, HfN, and combinations of their layers or alloy compositions.

[0120] In connection with the concepts presented or one or more examples described above or below (e.g., Figures 1 to 6e 8 to 14) mention more details and aspects of the examples shown Figure 7 in. In connection with Figure 7 The examples shown may include one or more additional optional features corresponding to one or more aspects of the concepts presented or one or more examples described above or below.

[0121] Regarding Figure 8 , a magnified portion of a power device having a pre-metallization 1250 according to one embodiment is shown. An insulating layer 1240, which may be a silicon dioxide layer, is disposed on or above a first surface 1211 of a semiconductor substrate 1210. In variants of this and other embodiments, the insulating layer 1240 may be disposed on a conductive layer such as a polysilicon layer or a metal layer, and in such cases an intermetal dielectric is formed.

[0122] An opening 1241 is formed in the insulating layer 1240 and extends to and exposes the first surface 1211 of the semiconductor substrate 1210 within the opening 1241. When viewed in a vertical cross-section perpendicular to the first surface 1211 of the semiconductor substrate 1210, the opening 1241 has a given width w. The width w may correspond to the diameter of the opening 1241. The insulating layer 1240 may have a given thickness h in a vertical direction perpendicular to the first surface 1211 of the semiconductor substrate 1110.

[0123] According to one embodiment, the thickness h of the insulating layer 1240 may be about 1 μm, and more typically between about 800 nm and about 2 μm. The width w of the opening 1241 may be from about 200 nm to about 1 μm, and more typically from about 150 nm to about 2 μm.

[0124] As Figure 8As shown, the front metallization 1250 includes an integral plug or metal connection that extends through the opening 1241 to contact the first surface 1211 of the semiconductor substrate 1210. Even in Figure 8 an integral plug is shown in the embodiment, but other types of plugs are possible.

[0125] According to one embodiment, the front metallization 1250 includes at least one contact layer 1253 (e.g., a contact layer as shown in connection with Figure 1 ), a adhesion promoting layer 1252 different from the contact layer 1253 on the contact layer 1253 (e.g., a barrier layer structure as shown in connection with Figure 1 ), and a power metal 1251 on and in contact with the adhesion promoting layer 1252 (e.g., a metallization layer as shown in Figure 1 ), where the power metal is at least five times thicker than each of the contact layer 1253 and the adhesion promoting layer 1252. Instead of or in addition to providing the adhesion promoting layer 1252, a barrier layer structure can be provided, for example, in the front metallization 1250. As an alternative or addition to providing the power metal 1251, a metallization layer can be provided, for example, in the front metallization 1250.

[0126] In a more specific embodiment, the front metallization 1250 includes three material layers. The lower layer in direct contact with the semiconductor substrate 1210 forms a so-called contact layer 1253. On the contact layer 1253, an adhesion layer 1252 (and / or a barrier layer structure) is disposed, followed by a so-called power metal 1251 (and / or a metallization layer). Thus, the adhesion layer 1252 is inserted between the contact layer 1253 and the power metal 1251. In other embodiments, the metallization 1250 can include more material layers (e.g., additional barrier layer structures and / or additional metallization layers). For example, an additional adhesion layer (e.g., an additional barrier layer structure) can be inserted between the contact layer 1253 and the power metal 1251. In still other embodiments, the metallization 1250 can include fewer material layers. According to the embodiment as shown in Figure 8 , the contact layer 1253 is formed in the opening 1141 and on the insulating layer 1140, particularly on the sidewalls of the opening 1141 and the upper surface of the insulating layer 1140. In an embodiment, the contact layer 1253 can be formed only in the opening 1141.

[0127] According to one embodiment, the power metal 1251 can be formed of a metal or metal alloy selected from the group including Ti, Mo, W, Hf, nitrides of these metals, and combinations of their layers or alloy compounds. The power metal can be substantially free of aluminum, such as having an aluminum content of less than 1% by weight, for example less than 0.5% by weight. The power metal 1251 forms a relatively thick metal layer, which is much thicker than each of the adhesion layer 1252 and the contact layer 1253, respectively. For example, the power metal 1251 can have a thickness of about at least 3 μm, typically in the range of about 3 μm to about 30 μm.

[0128] More generally, the pre-metallization 1250 can include at least one layer having a thickness of at least 1 μm, particularly at least 2 μm, and more particularly at least 3 μm. The at least one layer can be formed of a metal or metal alloy selected from the group including Ti, Mo, W, Hf, nitrides of these metals, and combinations of their layers or alloy compositions. The at least one metal layer can be the power metal 1251.

[0129] The above-mentioned metals and metal nitrides have high melting temperatures. For example, the melting temperature of Ti is 1668 °C, the melting temperature of Mo is 2623 °C, the melting temperature of W is 3422 °C, the melting temperature of Hf is 2233 °C, the melting temperature of TiN is 2950 °C, and the melting temperature of MoN is 1750 °C.

[0130] In at least one embodiment, copper (Cu) can be used as the pre-metallization. In this case, the semiconductor material typically has an intrinsic temperature of at least 600 °C but at most 1000 °C. For example, the semiconductor material can then be GaAs or Si. The melting temperature of Cu is 1084 °C, and it can also be used in principle, provided that an Al-free intermediate layer is used.

[0131] In addition to the high melting temperature provided by the above-mentioned metals, another benefit can be seen in the fact that the above-mentioned metals (including their alloys) have a thermal expansion coefficient similar to that of the semiconductor material (e.g., SiC). Since the operating temperature of the power device can vary significantly and can reach high temperatures, it is desirable to have a proper match between the thermal expansion coefficients of the thick power metal 1251 and the semiconductor substrate 1210 to reduce the mechanical stress caused by transient thermal shock. In addition to this, the adhesion layer 1252 can partially absorb the mismatch in the thermal expansion coefficients of the power metal 1251 and the semiconductor substrate 1210. This further reduces the mechanical stress caused by varying thermal conditions.

[0132] For example, the thermal expansion coefficient of Mo is about 4.8×10 -6 K -1 , and the thermal coefficient of W is about 4.3×10 -6 K -1, and the thermal coefficient of 4H-SiC is about 4.5×10 -6 K -1 , which makes Mo and W particularly suitable for SiC-based and 4H-SiC-based power devices having a semiconductor substrate 1210 formed of SiC or 4H-SiC. In addition, the conductivity of Mo and W is high enough (about 50% relative to the conductivity of aluminum) to be suitable for power metallization.

[0133] According to one embodiment, the adhesion layer 1252 (e.g., a barrier layer structure) can be formed of a metal or metal alloy selected from the group including TiN, TiW, MoN, Ta, and combinations of their layers or alloy compositions. The thickness of the adhesion layer 1252 can be relatively small, e.g., in the range of about 20 nm to about 500 nm, particularly in the range of about 50 nm to about 500 nm. The main purpose of the adhesion layer 1252 is to improve the adhesion between the power metal 1251 and the contact layer 1253.

[0134] According to one embodiment, a thin barrier layer can optionally be disposed between the adhesion layer 1252 and the contact layer 1253. For example, the barrier layer can have a thickness of about 5 nm. In a further embodiment, no additional barrier layer is required because the material of the adhesion layer 1252 can also serve as a barrier against unwanted metal diffusion.

[0135] According to one embodiment, the contact layer 1253 is formed of a metal or metal alloy selected from the group including Ti, V, Nb, Ta, Mo, W, Ni, NiAl, and combinations of their layers or alloy compositions. Typically, the adhesion layer 1252 and the contact layer 1253 are formed of different metals or metal alloys. The contact layer 1253 can be thinner than the adhesion layer 1252. For example, the contact layer 1253 can have a thickness of about 100 nm, more typically in the range of about 20 nm to about 140 nm.

[0136] The material of the contact layer 1253 can be selected such that it allows the formation of a binary, ternary, or quaternary alloy system of at least one chemical element of the material forming the contact layer 1253 and at least one chemical element of the semiconductor material of the semiconductor substrate 1210. Such an alloy system can be directly located between the semiconductor substrate 1210 and the contact layer 1253. By allowing the formation of such an alloy system, the contact resistance between the semiconductor material of the semiconductor substrate 1210 and the contact layer 1253 can be reduced, thereby achieving a low-ohmic contact. Instead of providing an ohmic contact, in certain embodiments described herein, it is also desirable to form a Schottky contact between the contact layer 1253 and the semiconductor substrate 1210.

[0137] For example, in the case where SiC is used as a semiconductor material, the chemical elements of the semiconductor material are Si and C, or in the case where GaN is used as a semiconductor material, the chemical elements of the semiconductor material are Ga and N. The chemical elements of the material of the contact layer 1253 can be Ni and Al for NiAl as an exemplary material of the contact layer 1253, or can be Ti and W for TiW as an exemplary material of the contact layer 1253. For example, in the case where SiC is used as a semiconductor material, so-called silicidation of the material of the contact layer 1253 may occur.

[0138] The contact layer 1253 may include NiAl having a relatively low aluminum content. It is possible that the relatively low aluminum content reduces or prevents the contact layer 1253 from melting at a temperature below the inherent temperature of the semiconductor substrate 1210. For example, the aluminum content can be less than 1% (by weight) of the total weight of the contact layer 1253.

[0139] As Figure 8 shown, the contact layer 1253 conforms to the shape of the insulating layer 1240 and covers the upper surface of the insulating layer 1240 and the sidewalls of the opening 1241. The contact layer 1253 is also in direct contact with the upper surface 1211 of the semiconductor substrate, without any other layer being inserted between the contact layer 1253 and the upper surface 1211. The adhesion layer 1252 completely covers the contact layer 1253 and thus is also formed on the upper surface of the insulating layer 1240 and the sidewalls of the opening 1241. The power metal 1251 is formed on the adhesion layer 1252 and extends into the opening 1241. The portion of the pre-metallization 1250 that extends into the opening 1241 can be described as a bulk plug or bulk metal connection of the pre-metallization 1250. As described further above in connection with Figure 7 it is also possible to form plugs or metal connections that are separate from the pre-metallization 1250.

[0140] Each of the contact layer 1253 and the adhesion layer 1252 can be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, reactive sputtering, or an atomic layer deposition (ALD) process. The power metal 1251 can be formed by a CVD or physical vapor deposition (PVD) process. For example, V and Mo are typically deposited using a PVD process, while W is deposited using a CVD process, where WF6 is the tungsten source gas. Ti and TiN can be deposited using PVD or CVD, for example.

[0141] According to one embodiment, a suitable metal layer stack for the contact layer 1253, the adhesion layer 1252, and the power metal 1251 does not contain metal nitrides for the power metal 1251. Exemplary metal layer stacks include Ti for the contact layer 1253; TiN, TiW, or Ta for the adhesion layer 1252; and V, W, or Mo for the power metal 1251.

[0142] According to a further variant, solder, such as a sinterable solder material, is formed on the power metal 1251 to facilitate external connection to the power metal 1251.

[0143] Different from the previous methods, Ti, Mo, W, Hf, and nitrides of these metals are used as the power metal 1251. In the previous methods, these metals were specifically used for barrier layers or adhesion layers, as in the case of, for example, copper metallization. The power metal 1251 is formed relatively thick and is typically at least five times as thick as each of the contact layer 1253 and the adhesion layer 1252. In a further embodiment, the power metal layer 1251 is formed to be at least 10 times as thick as each of the contact layer 1253 and the adhesion layer 1252.

[0144] According to the embodiments described herein, a temporarily strong increase in the temperature of the semiconductor device 1240 is absorbed by the pre-metallization 1250, which is substantially composed of a metal having a melting temperature higher than the intrinsic temperature of the semiconductor substrate 1210. Thus, even a strong temperature increase does not cause partial melting of the pre-metallization 1250. The transient temperature increase mainly occurs at or near the first surface 1211 of the semiconductor substrate 1210, and thus the pre-metallization 1250 is particularly subjected to strong temperature variations. To absorb a more persistent temperature increase, the post-metallization can also be formed of a metal or metal alloy having a melting temperature higher than the intrinsic temperature of the semiconductor substrate 1210. Alternatively, the post-metallization 1160 can be made particularly thick such that the post-metallization 1160 serves as a heat sink with improved heat dissipation.

[0145] In the previous methods, the pre-metallization 1250 was made relatively thick to absorb or balance the temporary temperature increase. The thicker pre-metallization has a larger volume and can thus absorb more energy. This effectively improves heat dissipation. However, these methods are only partially effective because when the temperature peak is higher or lasts longer, the material used for the pre-metallization may start to melt. Thus, providing a thick pre-metallization may only partially solve the problem and may cause other problems due to the thickness of the metallization.

[0146] In contrast thereto, the method proposed herein provides a pre-metallization that can withstand even persistent and high temperature peaks because the metals and metal alloys used to form the pre-metallization are high melting point metals. Thus, different from the previous methods, the expected robustness of the power device may not be affected by the metallization used. It is believed that power devices employing high melting point metals as described herein can better withstand temperature peaks than power devices employing other metals.

[0147] In addition to the pre-metallization, the aforementioned metals used for the pre-metallization 1250 can also be used to form the gate electrodes or other metal structures of the power device. It is desirable that all metal structures of the power device be formed of or consist of metals, metal alloys, and metal nitrides having a melting temperature higher than the inherent temperature of the semiconductor material of the semiconductor substrate. For example, all metal structures of the power device may be free of aluminum or have an aluminum content of less than 1% by weight.

[0148] If the gate electrode is formed of any of these high melting point metals or metal alloys, the gate electrode can be formed as a metal layer stack as described above in connection with the pre-metallization. Alternatively, the gate electrode can include only two metal layers or only a single metal layer, since the gate electrode generally does not make direct contact with the semiconductor substrate and is electrically insulated from the semiconductor substrate by at least a gate dielectric.

[0149] Furthermore, the power device can include a plurality of gate electrodes electrically insulated from the semiconductor substrate by corresponding gate dielectrics and / or at least one metal structure selected from the group consisting of gate runners, gate pads, source runners, source pads, field electrodes, channel cutoff electrodes, and combinations thereof, wherein the gate electrodes and / or the at least one metal structure includes or consists essentially of one or more metals or metal alloys selected from the group consisting of Ti, TiN, TiW, V, Nb, Ta, TaN, Mo, W, WN, NiAl, Mo, MoN, Cu, Hf, HfN and combinations of their layers or alloy compositions. In particular, each metal structure can be substantially free of aluminum, for example having an aluminum content of less than 1% or less than 0.5% by weight relative to the total amount of the corresponding metal structure. More generally, the content of metals having a melting temperature below 1100 °C can be less than 1% or less than 0.5% by weight relative to the total amount of the corresponding metal structure.

[0150] According to an embodiment described herein, the pre-metallization 1150 includes or consists essentially of one or more metals and / or metal alloys having a melting temperature higher than 1100 °C.

[0151] According to an embodiment described herein, the power device further includes a plurality of gate electrodes 1132 electrically insulated from the semiconductor substrate 1110 by corresponding gate dielectrics 1131, wherein each gate electrode 1132 includes or consists essentially of one or more metals or metal alloys having a melting temperature higher than 1100 °C.

[0152] According to an embodiment described herein, the pre-metallization 1150 extends through corresponding openings 1141 in the insulating layer 1140 and forms corresponding metal connections 1171, 1172, 1173 disposed in the corresponding openings 1141 of the insulating layer 1140. The metal connections 1171, 1172, 1172 form corresponding electrical connections to the semiconductor substrate 1110. Each conductive structure formed or disposed at the first surface 1111 of the semiconductor substrate 1110 may be substantially composed of a metal or metal alloy having a melting temperature higher than 1100 °C.

[0153] According to an embodiment described herein, each metal structure of the semiconductor device comprises less than 1% by weight of a metal having a melting temperature lower than 1100 °C relative to the total amount of the corresponding metal structure.

[0154] The pre-metallization 1150 may be substantially composed of one or more metals or metal alloys selected from the group consisting of Ti, TiN, TiW, V, Nb, Ta, TaN, Mo, W, WN, NiAl, Mo, MoN, Cu, Hf, HfN and their layer combinations or alloy compositions.

[0155] Combined with the proposed concepts of one or more examples described above or below (e.g., Figures 1 to 7 , Figures 9 to 14 ) more details and aspects of the examples shown in Figure 8 are mentioned. The examples shown in combination with Figure 8 may include one or more additional optional features corresponding to one or more aspects of the proposed concepts or one or more examples described above or below.

[0156] Figure 9 Illustrates a variant of the embodiment of Figure 8 . The contact layer 1353 is formed only in the opening 1141 of the insulating layer 1140, more specifically only at the bottom of the opening 1341 to be in direct contact with the first surface 1311 not covered by the insulating layer 1340 around the opening. Therefore, the adhesion layer 1352 (e.g., a barrier layer structure) contacts the material of the insulating layer 1340 at the sidewall of the opening 1341. The power metal 1351 (e.g., a metallization layer) is formed on and in contact with the adhesion layer 1352. Similar to the embodiment of Figure 8 , the power metal 1351, the adhesion layer 1352 and the contact layer 1353 together form the pre-metallization 1350.

[0157] Combined with the proposed concepts of one or more examples described above or below (e.g., Figures 1 to 8 , Figures 10 to 14 ) more details and aspects of the examples shown in Figure 9 are mentioned. The examples shown in combination with Figure 9The illustrated examples may include one or more additional optional features corresponding to one or more aspects of the proposed concept or one or more of the examples described above or below.

[0158] Figure 10 illustrates Figure 8 A further variation of the embodiment of. During the etching of the opening 1441, the exposed semiconductor substrate 1410 is also partially etched such that the opening 1441 extends into the semiconductor substrate 1410 to form a contact trench. The bottom of the contact trench is below the first surface 1411 of the semiconductor substrate 1410. The contact layer 1453 completely covers the insulating layer 1440, the sidewalls of the opening 1441 and the sidewalls of the contact trench, and the bottom of the contact trench. The adhesion layer 1453 (e.g., a barrier layer) is completely formed on and covers the contact layer 1453, and is in turn completely covered by the power metal 1451 (e.g., a metallization layer).

[0159] in connection with the proposed concept of one or more of the examples described above or below (e.g., Figures 1 to 9 11 to 14) mentions Figure 10 more details and aspects of the examples shown in. In connection with Figure 10 The illustrated examples may include one or more additional optional features corresponding to one or more aspects of the proposed concept or one or more of the examples described above or below.

[0160] Figure 11 illustrates a vertical cross - sectional view of a power device, particularly a vertical semiconductor device and more specifically a vertical power transistor device having an optional integrated diode. The semiconductor device includes a semiconductor substrate 1510 and at least two transistor cells 1581, 1582 integrated in the semiconductor substrate 1510. In Figure 11 only two transistor cells 1581, 1582 are illustrated. However, the power device may include more than two transistor cells, with each transistor cell disposed in the active region of the power device.

[0161] Each transistor cell 1581, 1582 includes a drift region 1523, a source region 1521, and a body region 1522. The body region 1522 is disposed between the source region 1521 and the drift region 1523. In Figure 11 the embodiment of, as in Figure 13 the embodiment of, the respective transistor cells 1581, 1582 have a common drift region 1523.

[0162] Each transistor cell 1581, 1582 may optionally include a diode region 1590. The diode region 1590 may shield the gate dielectric 1531 of the gate electrode 1532 from the high electric fields present during operation of the power device, particularly by reducing the electric field at the gate dielectric 1531 via utilization of the JFET effect.

[0163] A pn junction is formed between the optional diode region 1590 and the drift region 1523. The diode region 1590 may be a p-doped region. The diode region 1590 (when present) may include a first diode region 1591 and a second diode region 1592 above the first diode region 1591. However, different from the embodiment shown in Figure 11 , the diode region 1590 may be a single region having a doping profile that varies, particularly along the vertical direction. For example, the diode region 1590 may have a high doping concentration in the upper region (i.e., closer to the first surface 1511), rather than in the lower region (i.e., closer to the bottom of the trench in which the gate electrode 1532 is disposed). For example, the upper region corresponds to the second doped region 1592, while the lower region corresponds to the first doped region 1591.

[0164] Although Figure 11 illustrates that the second diode region 1592 is laterally larger than the first diode region 1591, according to one embodiment, both the first diode region 1591 and the second diode region 1592 may have the same lateral extent in the Figure 11 cross-sectional view. In another variation of the embodiments described herein, the first diode region 1591 and the second diode region 1592 may be formed as a single common diode region.

[0165] The common diode region, or at least one of the first diode region 1591 and the second diode region 1592, or both the first diode region 1591 and the second diode region 1592 may also be partially or completely disposed below the trench.

[0166] Each transistor cell 1581, 1582 further includes a gate electrode 1532, which is disposed in a trench and is dielectrically insulated from the body region 1522, the (optional) diode region 1590, and the drift region 1523 by a gate dielectric 1531. The trench may extend along a direction projected onto the drawing plane. The trenches having the gate electrodes 1532 of each transistor cell 1581, 1582 are in Figure 11The cross-section shown has a first sidewall, a second sidewall opposite the first sidewall, and a bottom. The body regions 1522 of each transistor cell 1581, 1582 are adjacent to the first sidewall of the corresponding trench, the (optional) diode region 1590 is adjacent to the second sidewall of the corresponding trench, and the pn junction between the drift region 1523 and the (optional) diode region 1590 is adjacent to the bottom of the corresponding trench. The source regions 1521 of the corresponding transistor cells can be arranged laterally on both sides of the trench to contact the gate dielectric 1531. Alternatively, the source regions 1521 of the corresponding transistor cells can be formed only on one side of the trench, for example, at the corresponding left side of the trench opposite to the side where the second diode region 1592 is formed.

[0167] The channel region 1533 extends in the body region 1522 along the first sidewall of the corresponding trench of the transistor cells 1581, 1582.

[0168] The (optional) diode region 1590 of each transistor cell 1581, 1582 extends from the first surface 1511 of the semiconductor substrate 1510 adjacent to the body regions 1522 and source regions 1521 of the adjacent transistor cells into the drift region 1523 where the pn junction is formed. The electrically insulating layer (insulating layer) 1540 covers the first surface 1511 and the gate electrode 1532. The insulating layer 1540 has an opening 1541, where the insulating layer 1540 exposes the (optional) second diode region 1592 and the source regions 1521 of the respective transistor cells 1581, 1582.

[0169] Different from the Figure 11 embodiment shown, the diode region 1590 can also extend along the entire trench or be completely located below the trench at a part of the trench. In this case, the channel region 1533 can extend along the first sidewall and along the second sidewall opposite to the first sidewall of the trench. For example, the diode region 1590 below the trench can be in contact with a conductive material located in the trench and electrically insulated from the gate electrode 1532. The conductive material can be at least partially located below the gate electrode 1532 and / or adjacent to the gate electrode along the extension direction of the gate electrode 1532.

[0170] In other embodiments of the power device, the diode region 1590 can be located at different positions, particularly spaced apart from the trench having the gate electrode 1532. For example, the diode region 1590 can be located between adjacent trenches. In this case, the bottom of the diode region 1590 can have a greater distance to the first surface 1511 than the bottom of the trench having the gate electrode 1532. That is, the diode region 1590 can have a greater vertical extent than the trench having the gate electrode 1532.

[0171] A pre-metallization including a power metal 1551, an adhesion layer 1552, and a contact layer 1553 is formed on the insulating layer 1540 and extends into the opening 1541 to contact the second diode region 1592 and the source region 1521.

[0172] The pre-metallization contacts the source terminal S. The gate electrode 1532 contacts the gate terminal G. The drain region 1524 formed at the second surface of the semiconductor substrate 1510 contacts the drain terminal D.

[0173] Reference Figures 12 to 14 , refer to SiC power devices for explanations of other aspects.

[0174] In connection with the proposed concepts of one or more examples described above or below (e.g., Figures 1 to 10 , 12 to 14), more details and aspects of the examples shown in Figure 11 are mentioned. In connection with Figure 11 the examples shown may include one or more additional optional features corresponding to one or more aspects of the proposed concepts or one or more examples described above or below.

[0175] Figure 12 Illustrates the measurement of the avalanche breakdown current J AS and energy E AS supplied to a common power device by an inductive load during avalanche. The resulting dependencies roughly correspond to the expected dependencies on the inductive load, which can be described by the following relationship: where I AS is the avalanche current, A is the effective chip area roughly corresponding to the active region, T i is the junction temperature, T0 is the ambient temperature, L is the avalanche inductive load, BV i is the rated breakdown voltage of the power device, and V dd is the voltage of the voltage source.

[0176] Figure 13 Illustrates the destructive avalanche measurement. Using the electrical values provided by the measurement and the material parameters of SiC, the increase in temperature during the avalanche pulse can be estimated. This also allows the estimation of the temperature at which the power device is destroyed according to the following relationship: where T j，max is the maximum junction temperature, t av is the time during avalanche, k is the specific heat conductivity of SiC, c is the specific heat capacity of SiC, and ρ is the density of SiC.

[0177] Using the above relationships and the material properties of SiC, particularly 4H-SiC, the breakdown temperature is estimated to be from about 600 °C to about 650 °C. This temperature is far below the intrinsic temperature of SiC, at which intrinsic conduction dominates, which leads to the breakdown of power devices. The reduction in the breakdown temperature is attributed to the use of low melting point metals such as aluminum in common SiC power devices.

[0178] For illustrative purposes, the phase diagram of an AlCu alloy is shown in Figure 14 which shows that a common AlCu alloy with a high Al content (as shown by the dashed ellipse) has a relatively low melting temperature far below the intrinsic temperature of SiC.

[0179] Therefore, when using inappropriate metallization, the benefits provided by SiC and other wide bandgap materials cannot be fully utilized.

[0180] The present invention aims to overcome this drawback by using high melting point metals and metal alloys, which allows the full utilization of the capabilities of wide bandgap materials. The robustness of power devices can be significantly improved.

[0181] In particular, by using only high melting point materials for the front metallization, the robustness against a single thermal spike caused by, for example, avalanche breakdown and short circuit can be improved. To further improve the robustness against, for example, repetitive avalanches (repetitive avalanche), the back metallization can also consist only of high melting point materials.

[0182] Further examples relate to other aspects of the present invention.

[0183] Example 1 relates to a power semiconductor device, comprising: a semiconductor substrate 1110 having a first surface 1111, the semiconductor substrate 1110 comprising a wide bandgap semiconductor material having an intrinsic temperature; an insulating layer 1140 above the first surface 1111 of the semiconductor substrate 1110, the insulating layer 1140 comprising at least one opening 1141 extending vertically through the insulating layer 1140; a front metallization 1150 above the insulating layer 1140, wherein the insulating layer 1140 is inserted between the front metallization 1150 and the first surface 1111 of the semiconductor substrate 1110; metal connections 1171, 1172, 1173, which are arranged in the opening 1141 of the insulating layer 1140 and conductively connect the front metallization 1150 to the semiconductor substrate 1110, wherein the front metallization 1150 comprises at least one layer or consists essentially of one layer, and wherein at least one layer consists essentially of a metal or metal alloy having a melting temperature higher than the intrinsic temperature of the semiconductor material.

[0184] Example 2 relates to the power semiconductor device of Example 1, wherein the intrinsic temperature of the semiconductor material is at least 600 °C, particularly at least 1100 °C.

[0185] Example 3 relates to the power semiconductor device of Example 1, wherein the intrinsic temperature of the semiconductor material is at least 600 °C and less than 1000 °C.

[0186] Example 4 relates to the power semiconductor device of any one of Examples 1 to 3, wherein the semiconductor substrate comprises SiC as a main material.

[0187] Example 5 relates to the power semiconductor device of any one of Examples 1 to 4, wherein the pre-metallization 1150 contains less than 1% by weight of the total amount of the pre-metallization of a metal having a melting temperature lower than the intrinsic temperature.

[0188] Example 6 relates to the power semiconductor device of any one of Examples 1 to 5, wherein the pre-metallization 1250 includes at least one contact layer 1253 in direct contact with the semiconductor substrate 1110, an adhesion promoting layer 1252 different from the contact layer 1253 on the contact layer 1253, and a power metal 1251 on and in contact with the adhesion promoting layer 1252, the power metal being at least 5 times as thick as each of the contact layer 1253 and the adhesion promoting layer 1252.

[0189] Example 7 relates to the power semiconductor device of Example 6, wherein the contact layer 1253 is formed only in the opening 1141 of the insulating layer 1140.

[0190] Example 8 relates to the power semiconductor device of Example 6, wherein the contact layer 1253 is formed in the opening 1141 and on the insulating layer 1140.

[0191] Example 9 relates to the power semiconductor device of any one of Examples 6 to 8, wherein the contact layer 1253 is formed of a metal or metal alloy selected from the group consisting of Ti, V, Nb, Ta, Mo, W, Ni, NiAl, and layer combinations or alloy compositions thereof.

[0192] Example 10 relates to the power semiconductor device of any one of Examples 6 to 9, wherein the adhesion promoting layer 1252 is formed of a metal or metal alloy selected from the group consisting of TiN, TiW, MoN, Ta, and layer combinations or alloy compositions thereof.

[0193] Example 11 relates to the power semiconductor device of any one of Examples 6 to 10, wherein the power metal 1251 is formed of a metal or metal alloy selected from the group consisting of Cu, Ti, Mo, W, Hf, nitrides of these metals, and layer combinations or alloy compositions thereof.

[0194] Example 12 relates to a power semiconductor device according to any of the foregoing examples, further comprising a plurality of gate electrodes 1132 electrically insulated from the semiconductor substrate 1110 by corresponding gate dielectrics 1131, wherein each gate electrode 1132 comprises or consists essentially of one or more metals or metal alloys selected from the group consisting of Ti, TiN, TiW, V, Nb, Ta, TaN, Mo, W, WN, NiAl, Mo, MoN, Cu, Hf, HfN, and layer combinations or alloy compositions thereof.

[0195] Example 13 relates to a power semiconductor device according to any of the foregoing examples, further comprising at least one metal structure selected from the group consisting of a gate runner, a gate pad, a source runner, a source pad, a field electrode, a channel cutoff electrode, and combinations thereof, wherein the at least one metal structure comprises or consists essentially of one or more metals or metal alloys selected from the group consisting of Ti, TiN, TiW, V, Nb, Ta, TaN, Mo, W, WN, NiAl, Mo, MoN, Cu, Hf, HfN, and layer combinations or alloy compositions thereof.

[0196] Example 14 relates to a power semiconductor device according to any of the foregoing examples, wherein at least one layer of the pre-metalization 1150 has a thickness of at least 1 μm.

[0197] Example 15 relates to a power semiconductor device, comprising: a semiconductor substrate 1110 having a first surface 1111, the semiconductor substrate 1110 comprising a single-crystalline semiconductor material selected from the group consisting of SiC, GaN, AlN, and Ga2O3; an insulating layer 1140 on the first surface 1111 of the semiconductor substrate 1110, the insulating layer 1140 comprising a plurality of openings 1141 extending through the insulating layer 1140; a pre-metalization 1150 on the insulating layer 1140, wherein the insulating layer 1140 is inserted between the pre-metalization 1150 and the first surface 1111 of the semiconductor substrate 1110, the pre-metalization 1150 extending through the corresponding openings 1141 of the insulating layer 1140 and forming corresponding metal connections 1171, 1172, 1173 disposed in the corresponding openings 1141 of the insulating layer 1140, the metal connections 1171, 1172, 1173 forming corresponding electrical connections to the semiconductor substrate 1110, wherein the pre-metalization 1150 comprises or consists essentially of one or more metals and / or metal alloys having a melting temperature higher than 1100 °C.

[0198] Example 16 relates to the power semiconductor device of Example 15, further comprising a plurality of gate electrodes 1132 electrically insulated from the semiconductor substrate 1110 by corresponding gate dielectrics 1131, wherein each gate electrode 1132 comprises or consists essentially of one or more metals or metal alloys having a melting temperature higher than 1100 °C.

[0199] Example 17 relates to the power semiconductor device of Example 15 or 16, wherein each conductive structure formed or disposed at the first surface 1111 of the semiconductor substrate 1110 consists essentially of a metal or metal alloy having a melting temperature higher than 1100 °C.

[0200] Example 18 relates to the power semiconductor device of any one of Examples 15 to 17, wherein the pre-metallization 1150 consists essentially of one or more metals or metal alloys selected from the group consisting of Ti, TiN, TiW, V, Nb, Ta, TaN, Mo, W, WN, NiAl, Mo, MoN, Cu, Hf, HfN, and layer combinations or alloy compositions thereof.

[0201] Example 19 relates to the power semiconductor device of any one of Examples 15 to 18, further comprising at least one metal structure selected from the group consisting of a gate runner, a gate pad, a source runner, a source pad, a field electrode, a channel cut-off electrode, and combinations thereof, wherein the at least one metal structure comprises or consists essentially of one or more metals or metal alloys selected from the group consisting of Ti, TiN, TiW, V, Nb, Ta, TaN, Mo, W, WN, NiAl, Mo, MoN, Cu, Hf, HfN, and layer combinations or alloy compositions thereof.

[0202] Example 20 relates to the power semiconductor device of any one of Examples 15 to 19, wherein each metal structure of the semiconductor device comprises less than 1% by weight of a metal having a melting temperature lower than 1100 °C relative to the total amount of the corresponding metal structure.

[0203] Aspects and features mentioned and described in connection with one or more of the previously detailed examples and appended Figure One may also be combined with one or more other examples in order to replace similar features of other examples or in order to additionally introduce features to other examples.

[0204] The example can further be or relate to a computer program having program code for performing one or more of the above - mentioned methods when the computer program is executed on a computer or a processor. The steps, operations or processes of the various above - mentioned methods can be performed by a programmed computer or processor. The example can also cover a program storage device such as a digital data storage medium, which is machine, processor or computer - readable and encodes a program of machine - executable, processor - executable or computer - executable instructions. The instructions execute or cause the execution of some or all of the actions of the above - mentioned methods. The program storage device can include or be, for example, a digital memory, a magnetic storage medium such as magnetic disks and tapes, a hard disk drive, or an optically readable digital data storage medium. Further examples can also cover a computer, a processor or a control unit programmed to perform the actions of the above - mentioned methods, or a (field) programmable logic array ((F)PLA) or a (field) programmable gate array ((F)PGA) programmed to perform the actions of the above - mentioned methods.

[0205] The description and the drawings merely illustrate the principles of the disclosure. In addition, all of the examples described herein are mainly and explicitly intended only for illustrative purposes to help the reader understand the principles of the disclosure and the concepts contributed by the inventor to the art. All statements of the principles, aspects and examples of the disclosure described herein, as well as their specific examples, are intended to cover their equivalents.

[0206] A functional block that performs a specific function represented as a "component for..." can refer to a circuit configured to perform the specific function. Thus, a "component for..." can be implemented as a "component configured or adapted for...", such as a device or a circuit configured or adapted for the corresponding task.

[0207] The functions of the various elements shown in the figures (including any functional blocks labeled as "component", "component for providing a signal", "component for generating a signal", etc.) can be implemented in the form of dedicated hardware (such as a "signal provider", "signal processing unit", "processor", "controller", etc.) and hardware capable of executing software associated with appropriate software. When provided by a processor, the functions can be provided by a single dedicated processor, by a single shared processor, or by multiple individual processors, some or all of which can be shared. However, the terms "processor" or "controller" so far are not limited to hardware specifically capable of executing software, but can include digital signal processor (DSP) hardware, network processors, application - specific integrated circuits (ASICs), field - programmable gate arrays (FPGAs), read - only memories (ROMs) for storing software, random - access memories (RAMs) and non - volatile storage devices. It can also include other conventional and / or custom hardware.

[0208] It should be understood that, unless explicitly or implicitly stated otherwise for technical reasons, for example, the disclosure of multiple acts, processes, operations, steps, or functions in the specification or claims may not be construed as being in a particular order. Thus, the disclosure of multiple acts or functions does not limit these to a particular order, unless these acts or functions are not interchangeable for technical reasons. In addition, in some examples, a single act, function, process, operation, or step may include or may be separately divided into multiple sub-acts, functions, processes, operations, or steps. Such sub-acts may be included and are part of the disclosure of the single act, unless explicitly excluded.

[0209] In addition, the following claims are hereby incorporated into the detailed description, where each claim may stand alone as a separate example. Although each claim may stand alone as a separate example, it should be noted that although a dependent claim may refer to a particular combination with one or more other claims in the claims, other examples may also include combinations of the dependent claim with the subject matter of each other dependent claim or independent claim. Such combinations are expressly set forth herein unless it is stated that no particular combination is intended. In addition, it is intended that the features of a claim be included in any other independent claim, even if that claim does not directly depend on the independent claim.

Claims

1. A silicon carbide device (100; 200; 300a; 300b; 600a; 600b), comprising: A silicon carbide substrate (102); A contact layer (104), wherein the contact layer (104) is located on the silicon carbide substrate (102); A barrier layer structure (106) formed of a metal or metal alloy selected from the group consisting of TiN, TiW, MoN, Ta, and combinations of its layers or alloy compositions, wherein the contact layer (104) is located between the silicon carbide substrate (102) and at least a part of the barrier layer structure (106); and A metallization layer (108) including copper, wherein the barrier layer structure (106) is located between the silicon carbide substrate (102) and the metallization layer (108), wherein the metallization layer is configured as a contact pad of the silicon carbide device.

2. The silicon carbide device according to claim 1, wherein, The contact layer (104) is formed of a metal or metal alloy selected from the group consisting of Ti, V, Nb, Ta, Mo, W, Ni, NiAl, and combinations of its layers or alloy compositions.

3. The silicon carbide device according to claim 1, wherein the contact layer (104) comprises at least one of Ti, V, Nb, Ta, Mo, W, Ni, Si, Al.

4. The silicon carbide device according to claim 1, wherein the contact layer (104) comprises nickel and silicon.

5. The silicon carbide device according to claim 1, wherein the contact layer (104) is directly located on the silicon carbide substrate (102).

6. The silicon carbide device according to claim 1, wherein the barrier layer structure (106) comprises at least one of TiN, TiW, MoN, Ta.

7. The silicon carbide device according to claim 1, wherein the barrier layer structure (106) comprises titanium and tungsten.

8. The silicon carbide device according to claim 1, wherein the lateral dimension of the contact pad is at least 100 μm, and the vertical thickness of the contact pad is at most 100 μm.

9. The silicon carbide device according to claim 1, wherein the barrier layer structure (106) comprises a TiW layer.

10. The silicon carbide device according to claim 2, wherein the TiW layer is in contact with the metallization layer (108).

11. The silicon carbide device according to claim 1, wherein the barrier layer structure (106) comprises a TiWN layer.

12. The silicon carbide device according to claim 4, wherein the TiWN layer is in contact with the metallization layer (108).

13. The silicon carbide device according to any one of claims 1 to 5, wherein the barrier layer structure (106) is in contact with the contact layer (104).

14. The silicon carbide device according to any one of claims 1 to 5, wherein the barrier layer structure (106) comprises one or more layers from the group consisting of a Ti / TiN layer, a TiW layer, a TiWN layer, and a MoN layer.

15. The silicon carbide device according to any one of claims 1 to 5, wherein the barrier layer structure (106) comprises a Ti / TiN layer.

16. The silicon carbide device according to claim 8, wherein the Ti / TiN layer is in contact with the contact layer (104).

17. The silicon carbide device according to claim 8, wherein the barrier layer structure (106) comprises a Ti / TiN layer and at least one of a TiW layer and a TiWN layer.

18. The silicon carbide device according to claim 8, wherein the titanium layer of the Ti / TiN layer is in contact with the contact layer (104).

19. The silicon carbide device according to any one of claims 1 to 5, wherein the vertical thickness of the barrier layer structure (106) is at least 100 nm and at most 600 nm.

20. The silicon carbide device according to any one of claims 1 to 5, wherein the contact layer (104) is a NiSiAl layer.

21. The silicon carbide device according to any one of claims 1 to 5, wherein the contact layer (104) contains at least 1% and at most 20% silicon by volume.

22. The silicon carbide device according to any one of claims 1 to 5, wherein the contact layer (104) contains at most 10% carbon inclusions by volume.

23. The silicon carbide device according to any one of claims 1 to 5, wherein the contact layer (104) makes an ohmic contact with a first doped region of the silicon carbide substrate (102) and / or with a second doped region of the silicon carbide substrate (102), wherein the first doped region has a first conductivity type, and wherein the second doped region has a second conductivity type.

24. The silicon carbide device according to any one of claims 1 to 5, wherein the metallization layer (108) contains at least 60% copper by volume.

25. The silicon carbide device according to any one of claims 1 to 5, wherein the metallization layer (108) is at least 5 times as thick as each of the contact layer (104) and the barrier layer structure (106).

26. The silicon carbide device according to any one of claims 1 to 5, further comprising a bonding wire that is bonded to the metallization layer (108).

27. The silicon carbide device according to claim 26, wherein the bonding wire is bonded to the metallization layer (108) using a stitch bond.

28. The silicon carbide device according to claim 26, wherein the bonding wire has a diameter of at most 100 μm.

29. The silicon carbide device according to claim 26, wherein the bonding wire is a copper bonding wire.

30. The silicon carbide device according to any one of claims 1 to 5, wherein the silicon carbide device includes a contact pad, wherein the contact pad is a gate contact pad or a sense contact pad of the silicon carbide device, wherein the contact pad is at least partially formed by the metallization layer (108), and wherein the lateral surface area of the contact pad is at most 200 μm × 200 μm.

31. The silicon carbide device according to any one of claims 1 to 5, wherein at least one of the transistor structure and / or the diode structure of the silicon carbide device has a breakdown voltage greater than 100 V.

32. A method (500) for forming a silicon carbide device, comprising: forming a contact layer (104) on a silicon carbide substrate (102) of the silicon carbide device; after forming the contact layer (104), forming a barrier layer structure (106) comprising titanium and tungsten; and after forming the barrier layer structure (106), forming a metallization layer (108) comprising copper, An ohmic connection is formed between the metallization layer (108) and the doped region of the silicon carbide substrate (102) via the barrier layer structure (106) and the contact layer (104), wherein the metallization layer is configured as a contact pad of the silicon carbide device.

33. A power semiconductor device, comprising: A semiconductor substrate, comprising a wide bandgap semiconductor material and a first surface; An insulating layer above the first surface of the semiconductor substrate, the insulating layer comprising at least one opening extending vertically through the insulating layer; A front metallization above the insulating layer, wherein the insulating layer is inserted between the front metallization and the first surface of the semiconductor substrate; And A metal connection disposed in the opening of the insulating layer and electrically connecting the front metallization to the semiconductor sublayer; wherein the front metallization comprises at least one layer, and the at least one layer is a metal or metal alloy having a melting temperature higher than the intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.

34. The power semiconductor device according to claim 33, wherein the intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate is at least 600 °C.

35. The power semiconductor device according to claim 34, wherein the intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate is at least 600 °C and less than 1000 °C.

36. The power semiconductor device according to claim 33, wherein the semiconductor substrate is a SiC substrate.

37. The power semiconductor device according to claim 33, wherein the front metallization comprises a metal having a melting temperature lower than the intrinsic temperature in an amount less than 1% by weight relative to the total amount of the front metallization.

38. The power semiconductor device according to claim 33, wherein the front metallization comprises at least one contact layer in direct contact with the semiconductor substrate, an adhesion promoting layer different from the contact layer and disposed on the contact layer, and a power metal disposed on and in contact with the adhesion promoting layer, and the power metal is at least 5 times as thick as each of the contact layer and the adhesion promoting layer.

39. The power semiconductor device according to claim 38, wherein the contact layer is formed only in the opening of the insulating layer.

40. The power semiconductor device according to claim 38, wherein the contact layer is formed in the opening and on the insulating layer.

41. The power semiconductor device according to claim 38, wherein the contact layer is formed of a metal or metal alloy selected from the group consisting of Ti, V, Nb, Ta, Mo, W, Ni, NiAl, and layer combinations or alloy compositions thereof.

42. The power semiconductor device according to claim 38, wherein the adhesion promoting layer is formed of a metal or metal alloy selected from the group consisting of TiN, TiW, MoN, Ta, and layer combinations or alloy compositions thereof.

43. The power semiconductor device according to claim 38, wherein the power metal is formed of a metal or metal alloy selected from the group consisting of Cu, Ti, Mo, W, Hf, nitrides of these metals, and layer combinations or alloy compositions thereof.

44. The power semiconductor device according to claim 33 further includes a plurality of gate electrodes electrically insulated from the semiconductor substrate through respective gate dielectrics, wherein each gate electrode includes one or more metals or metal alloys selected from the group consisting of Ti, TiN, TiW, V, Nb, Ta, TaN, Mo, W, WN, NiAl, Mo, MoN, Cu, Hf, HfN and layer combinations or alloy compositions thereof.

45. The power semiconductor device according to claim 33 further includes at least one metal structure selected from the group consisting of a gate runner, a gate pad, a source runner, a source pad, a field electrode, a channel cutoff electrode, and combinations thereof, wherein the at least one metal structure includes one or more metals or metal alloys selected from the group consisting of Ti, TiN, TiW, V, Nb, Ta, TaN, Mo, W, WN, NiAl, Mo, MoN, Cu, Hf, HfN and layer combinations or alloy compositions thereof.

46. The power semiconductor device according to claim 33, wherein at least one layer of the pre-metallization has a thickness of at least 1 μm.

47. A power semiconductor device includes: a semiconductor substrate having a first surface, the semiconductor substrate including a single crystal semiconductor material selected from the group consisting of SiC, GaN, AlN, and Ga2O3; an insulating layer on the first surface of the semiconductor substrate, the insulating layer including a plurality of openings extending through the insulating layer; and a pre-metallization on the insulating layer, wherein the insulating layer is inserted between the pre-metallization and the first surface of the semiconductor substrate; the pre-metallization extends through the respective openings of the insulating layer and forms respective metal connections disposed in the respective openings of the insulating layer, and the metal connections form respective electrical connections with the semiconductor substrate; wherein the pre-metallization includes one or more metals and / or metal alloys having a melting temperature higher than 1100 °C.

48. The power semiconductor device according to claim 47 further includes a plurality of gate electrodes electrically insulated from the semiconductor substrate through respective gate dielectrics, wherein each gate electrode includes one or more metals or metal alloys having a melting temperature higher than 1100 °C.

49. The power semiconductor device according to claim 47, wherein each conductive structure formed or disposed at the first surface of the semiconductor substrate is a metal or metal alloy having a melting temperature higher than 1100 °C.

50. The power semiconductor device according to claim 49, wherein the pre-metallization includes one or more metals or metal alloys selected from the group consisting of Ti, TiN, TiW, V, Nb, Ta, TaN, Mo, W, WN, NiAl, Mo, MoN, Cu, Hf, HfN and layer combinations or alloy compositions thereof.

51. The power semiconductor device according to claim 47 further comprises at least one metal structure selected from the group consisting of a gate runner, a gate pad, a source runner, a source pad, a field electrode, a channel cutoff electrode, and combinations thereof, wherein the at least one metal structure comprises one or more metals or metal alloys selected from the group consisting of Ti, TiN, TiW, V, Nb, Ta, TaN, Mo, W, WN, NiAl, Mo, MoN, Cu, Hf, HfN, and combinations of layers or alloy compositions thereof.

52. The power semiconductor device according to claim 47, wherein each metal structure of the semiconductor device comprises less than 1% by weight, relative to the total amount of the corresponding metal structure, of a metal having a melting temperature below 1100 °C.

53. A power semiconductor device comprising: a semiconductor substrate comprising a wide bandgap semiconductor material; an insulating layer above a first surface of the semiconductor substrate, the insulating layer comprising at least one opening extending vertically through the insulating layer; a contact layer located on the silicon carbide substrate, disposed within the opening, and forming an ohmic connection with the semiconductor substrate; a barrier layer structure disposed on the contact layer and within the opening; and a front metallization located above the insulating layer and conductively connected to the semiconductor substrate via the contact layer and the barrier layer structure disposed within the opening, wherein the front metallization comprises at least one layer that is a metal or metal alloy having a melting temperature higher than the intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate, and wherein the front metallization is configured as a contact pad of the semiconductor device.

54. The power semiconductor device according to claim 53 further comprises a bonding wire bonded to the metallization layer.

55. The power semiconductor device according to claim 54, wherein the bonding wire has a diameter of at most 100 μm.

56. The power semiconductor device according to claim 54, wherein the bonding wire is a copper bonding wire.

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