Circuit board hole plating process

Abstract

The invention relates to the technical field of circuit board hole plating, and discloses a circuit board hole plating process, which comprises the following steps of: carrying out film pasting treatment on a circuit board after copper deposition and flash plating, exposing and developing the circuit board, placing the exposed and developed circuit board in an electrocoppering solution, covering the circuit board with the area of an anode, and enabling the anode to be parallel to the circuit board; holes are plated in a copper-iron system pulse electroplating mode, in the forward and reverse pulse electroplating process, the forward pulse time T1 is 0-100 milliseconds, the reverse pulse time T2 is not larger than 50 milliseconds, and preferably, the forward pulse time T1 is 100 milliseconds, and the reverse pulse time T2 is 10 milliseconds. In the whole technological process, the concentration difference of Fe < 3 + > exists between the hole opening of the through hole of the circuit board and the position in the through hole of the circuit board, the concentration of Fe < 3 + > is changed under the condition of positive and negative current exchange, thin copper electroplating copper at the hole opening and thick copper electroplating copper in the hole can be formed, subsequent procedure production is facilitated, quality scrapping is reduced, and the reliability of the circuit board is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board hole plating, in particular to a circuit board hole plating process. Background Art

[0002] With the advent of the 5G commercial era, the construction of network infrastructure such as 5G base stations is accelerating, placing higher demands and increasing demand on communication printed circuit boards (PCBs), significantly driving the rapid development of the PCB industry. In 5G base stations, the communication backplane is the largest circuit board in the mobile base station. The development trend of communication backplanes is to increase the number of sub-boards and reduce signal loss, driving the development of backplanes towards larger sizes, more layers, thicker boards, smaller apertures, and denser wiring. The thickness and number of layers of multi-layer communication backplanes are increasing (up to 10mm / 56 layers), while the apertures are decreasing (as low as 200μm to 500μm). This leads to an increasing aspect ratio, making copper plating of tiny through-holes increasingly difficult, posing greater challenges to communication backplane through-hole interconnection technology. Electroplating copper for high aspect ratio through-holes is a key technology for achieving interlayer interconnection in multi-layer communication backplanes and a long-standing technical difficulty for PCB industry researchers.

[0003] In order to meet the copper thickness requirements of high-aspect ratio (thickness-to-diameter ratio) multilayer boards with a thickness-to-diameter ratio of 8:1 or more, the company's approach is to process the circuit board after flash copper plating with a film, expose it, and then perform traditional DC electroplating after development to plate copper on the inner wall of the through hole of the circuit board. The hole is then filled with resin through the resin plugging process. After the resin is cured, copper is reduced and the board is ground. The process steps are as follows: Figure 1 shown.

[0004] In the above process, after the dry film is applied to the circuit board, it is necessary to screen out the through-hole positions that need to be thickened. After exposure and development, the window positions are relatively scattered, so the circuit board is unevenly plated. In the traditional DC electroplating process, the circuit board is unevenly plated due to the uneven current dispersion. The electroplated copper is thin in the relatively densely plated areas, and thick in the relatively dispersed areas. The uneven thickness of the electroplated copper can easily cause the electroplated copper layer inside the through hole to be thin, the electroplated copper layer thickness and the aperture of the hole to become smaller, the copper plating bulge at the hole ring, the copper plating film, etc. Figure 2 and Figure 3 As shown, these situations can lead to:

[0005] 1. When plugging the hole with resin, the convex hole ring causes the gasket of the resin plugging hole and the surface of the circuit board to not overlap, causing the resin to overflow onto the surface of the circuit board during the resin plugging. The hole diameter becomes smaller, making it difficult for the resin to enter the through hole, resulting in poor plugging.

[0006] 2. During the panel grinding process, due to the raised hole rings, the panel needs to be ground multiple times. During this process, uneven surface copper may occur, making it difficult to etch the circuit, exposing the base material on the panel surface, deforming the board, etc., resulting in quality scrap. In the long run, there is a great risk to the reliability of the circuit board.

[0007] Based on this, the present application proposes a circuit board plating process to solve the above problems. Summary of the Invention

[0008] (I) Technical problems to be solved

[0009] Aiming at the deficiencies of the prior art, the present invention provides a circuit board plating process. This process uses a copper-iron system pulse electroplating method to plate holes, taking advantage of the concentration difference of Fe within milliseconds to form a thin copper layer at the hole opening and a thick copper layer inside the hole. Since the copper layer at the hole opening is thin, it facilitates the production of subsequent processes, reduces quality scrap, and enhances the reliability of the circuit board. 3+

[0010] (II) Technical solutions

[0011] To achieve the above object, the present invention provides the following technical solutions: A circuit board plating process. After the circuit board after electroless copper flash plating is subjected to film pasting treatment, exposed, and developed, the exposed and developed circuit board is placed in an electroplating copper solution, such that the anode region covers the circuit board and the anode is parallel to the circuit board, and a copper-iron system pulse electroplating method is used to plate holes.

[0012] Preferably, during the forward and reverse pulse electroplating process, the pulse voltage is 0.8 - 12V, and the forward current density is 5 - 35 ASF.

[0013] Preferably, the pulse current is a forward and reverse pulse current, and the time of the pulse current consists of consecutive pulse current periods T.

[0014] Preferably, during the forward and reverse pulse electroplating process, the amplitude ratio of the forward pulse current to the reverse pulse current is 50:200 - 50:500.

[0015] Preferably, the pulse current period T includes a forward pulse time T1, a reverse pulse time T2, a forward pulse time T3, a pulse stop time T4, and a reverse pulse time T5.

[0016] Preferably, during the forward and reverse pulse electroplating process, the forward pulse time T1 is 0 - 100 milliseconds, the reverse pulse time T2 is not more than 50 milliseconds, the forward pulse time T3 is not more than 100 milliseconds, the pulse stop time T4 is not more than 4 milliseconds, and the reverse pulse time T5 is not more than 8 milliseconds.

[0017] Preferably, during the forward and reverse pulse electroplating process, the forward pulse time T1 is 100 milliseconds, and the reverse pulse time T2 is 10 milliseconds.

[0018] Preferably, at 100ms (forward current time), the circuit board acts as a cathode and the titanium mesh acts as an anode; at 10ms (reverse current time), the circuit board acts as an anode and the titanium mesh acts as a cathode.

[0019] (3) Beneficial effects

[0020] Compared with the prior art, the present invention provides a circuit board hole plating process with the following beneficial effects:

[0021] During the entire process, there is Fe between the opening of the circuit board through hole and the inside of the circuit board through hole. 3+ When the rectifier output is positive, the Fe 3+ The concentration is high. During the circulation of the solution, the Fe 3+ The concentration of Fe in the potion at the through-hole of the circuit board decreases gradually. Relatively speaking, the current value at the through-hole of the circuit board is smaller than the current value inside the through-hole of the circuit board. When the rectifier output is reverse, the Fe in the potion at the through-hole of the circuit board 3+ The concentration of Fe 2+ Losing electrons at the anode increases the Fe 3+ The concentration of Fe is relatively low, and the copper ions precipitated from the pores are higher than those precipitated from the pores. In the case of positive and negative current exchange, Fe 3+ The concentration of copper is also changing, resulting in thin copper plating at the hole mouth and thick copper plating inside the hole, which facilitates subsequent production processes, reduces quality scrap, and enhances the reliability of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The following is a flow chart of the copper plating process for multilayer boards in the prior art;

[0023] Figure 2 A schematic diagram of a plate surface with unevenly distributed plated areas in the prior art;

[0024] Figure 3 This is a slice diagram of a plated hole in a circuit board in the prior art;

[0025] Figure 4 Schematic diagram of the waveform of the pulse current period T of the forward and reverse pulse current of the present invention;

[0026] Figure 5 Schematic diagram of the reaction of the present invention at 100ms (forward current time);

[0027] Figure 6 Schematic diagram of the reaction of the present invention at 10ms (reverse current time);

[0028] Figure 7 Schematic diagram of the reaction of the rectifier of the present invention under different forward and reverse output currents;

[0029] Figure 8 Schematic diagram of the circuit board surface with unevenly distributed plating areas under the plating hole process of the present invention;

[0030] Figure 9 Cross-sectional view of the circuit board plating hole under the plating hole process of the present invention;

[0031] Figure 10 Schematic diagram for characterizing the uniformity of through-hole plating layer of the present invention. Detailed implementation manners

[0032] Next, in combination with the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0033] A circuit board plating hole process, in which the circuit board after electroless copper flash plating is subjected to film pasting treatment, and after exposure and development, the exposed and developed circuit board is placed in an electroplated copper solution, so that the anode area covers the circuit board and the anode is parallel to the circuit board, and the plating hole is carried out by means of copper-iron system pulse electroplating.

[0034] The anode and the circuit board are electrically connected to the positive and negative electrodes of the power supply device respectively, and the power supply device electroplates the circuit board through a pulsed current. The pulsed current is a positive and negative pulsed electroplating, and the process conditions are:

[0035] The pulsed voltage is 0.8 - 12V, the forward current density is 5 - 35 ASF, and the amplitude ratio of the forward pulsed current to the reverse pulsed current is 50:200 - 50:500.

[0036] It should be noted that the pulsed time is composed of a continuous pulsed current period T. The pulsed current period T includes a forward pulsed time T1 for applying a forward pulsed current, a reverse pulsed time T2 for applying a reverse pulsed current, a forward pulsed time T3 for applying a forward pulsed current, a pulsed stop time T4 for stopping the application of the pulsed current, and a reverse pulsed time T5 for applying a reverse pulsed current, as Figure 4 shown.

[0037] In the positive and negative pulsed electroplating process of the present invention, the forward pulsed time T1 is 0 - 100 milliseconds, the reverse pulsed time T2 is not greater than 50 milliseconds, the forward pulsed time T3 is not greater than 100 milliseconds, the pulsed stop time T4 is not greater than 4 milliseconds, and the reverse pulsed time T5 is not greater than 8 milliseconds.

[0038] Preferably, the forward pulse time T1 is 100 milliseconds, and the reverse pulse time T2 is 10 milliseconds.

[0039] During the entire reaction process:

[0040] ① At 100ms (forward current time), the circuit board acts as the cathode and the titanium mesh acts as the anode. There are two chemical reactions in the circuit board area:

[0041] a. Priority reaction (ferric ions are reduced to divalent iron ions Fe by electrons on the cathode circuit board) 3+ +e - →Fe 2 + );

[0042] b. Main reaction (divalent copper ions obtain two electrons at the cathode and are reduced to copper element and deposited on the cathode circuit board Cu 2+ +2e - →Cu);

[0043] Because of the existence of the preferential reaction, during the circulation of the solution, the Fe 3+ The concentration is higher than the Fe in the through hole of the circuit board 3+ The concentration is high, the current at the hole of the circuit board is relatively low, and the current inside the hole is relatively high, which makes the copper at the hole thin, the copper inside the hole thick, and the hole ring has no protrusion. The reaction process is as follows Figure 5 As shown;

[0044] ② At 10ms (reverse current time), the circuit board acts as the anode and the titanium mesh acts as the cathode. There are two chemical reactions in the circuit board area:

[0045] a. Priority reaction (ferrous ions lose electrons and oxidize to trivalent ferrous ions Fe 2+ →Fe 3+ +e - );

[0046] b. Main reaction (deposited copper on the through-hole wall and Fe 3+ Oxidation-reduction reaction occurs Cu→Cu 2+ +2e - );

[0047] Under the action of the liquid medicine circulation, due to the priority reaction, when the circuit board is the anode, the Fe 2+ It loses electrons at the anode and is oxidized to Fe 3+； , Fe in the through-hole of the circuit board 3+ The pore opening is relatively low, so there is less reaction in the pore; then according to the principle of redox reaction (2Fe 3+ +Cu→Cu 2++2Fe 2+ ), the Cu precipitated at the orifice 2+ is relatively more than that in the hole; and because the reverse pulse time is short and the chemical solution concentration exchange is not timely, etc.; the copper precipitated on the circuit board can be ignored, and the reaction process is as Figure 6 shown;

[0048] Thus, it can be known that there is a concentration difference of Fe 3+ between the orifice of the through-hole of the circuit board and the inside of the through-hole of the circuit board. When the output of the rectifier is positive, the concentration of Fe 3+ at the orifice of the circuit board is high. During the chemical solution circulation process, the concentration of Fe 3+ in the solution flowing from the orifice of the circuit board to the inside of the hole gradually decreases. Relatively speaking, the current value at the orifice of the through-hole of the circuit board is less than the current value inside the through-hole of the circuit board; when the output of the rectifier is negative, the concentration of Fe 3+ in the chemical solution at the orifice of the through-hole of the circuit board increases because Fe 2+ loses electrons at the anode, and the concentration of Fe 3+ inside the through-hole of the circuit board is relatively low. The entire reaction process is as Figure 7 shown, and the copper ions precipitated at the orifice are higher than those precipitated inside the hole. In the case of positive and negative current exchange, the concentration of Fe 3+ also changes, thus forming a thin copper plating at the orifice and a thick copper plating inside the hole, which is convenient for subsequent process production. The experimental slices are as Figure 8 and Figure 9 .

[0049] Use the parameters in Table 1-1 to conduct positive and negative pulse electroplating experiments for Test Example 1, Test Example 2, Test Example 3, Test Example 4, and Test Example 5 respectively.

[0050]

[0051]

[0052] The measurement samples that have completed positive and negative pulse electroplating using the parameters in Table 1-1 are respectively sectioned and the cross-sections of the copper surfaces of the sectioned samples of the measurement samples are observed using a metallurgical microscope. The copper plating thicknesses at points A, B, C, D, E, and F in the measurement samples are shown in detail in Table 1-2. Among them, the specific positions of points A, B, C, D, E, and F are shown in detail in Figure 10 .

[0053] As can be seen from 1-1 and Table 1-2, when the forward and reverse pulse currents are used, with the forward pulse time being 0-100 milliseconds and the reverse pulse time being 0-10 milliseconds (Experimental Example 4), the copper plating thicknesses at points C and D are closest to the average value, minimum value, and maximum value among the six points A, B, C, D, E, and F. This indicates that in the forward and reverse pulse electroplating of the present invention under these pulse parameters, the thickness differences of the copper-plated circuit board at each point are small, the plating holes are more uniform, and it can effectively avoid the situations of thin copper plating layer inside the through holes, thick copper plating layer at the hole openings, reduced hole diameters at the hole openings, copper plating protrusions at the hole rings, and copper plating film clamping, which is convenient for the production of subsequent processes, reduces quality scrap, and enhances the reliability of the circuit board.

[0054] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A printed circuit board plating hole process, characterized in that, Including: Perform film laminating treatment on the circuit board after immersion flash plating, and wait for it to be exposed and developed; Place the exposed and developed circuit board in the electroplated copper solution, so that the area of the anode covers the circuit board and the anode is parallel to the circuit board; Plating holes by means of copper-iron system pulse electroplating.

2. The plating process for holes in a circuit board according to claim 1, characterized in that, During the positive and negative pulse electroplating process, the pulse voltage is 0.8 - 12V, and the positive current density is 5 - 35 ASF.

3. A circuit board plating hole process according to claim 2, characterized in that, The pulse current is a positive and negative pulse current, and the time of the pulse current is composed of continuous pulse current cycles T.

4. The electroplating process for holes of a circuit board according to claim 3, characterized in that During the positive and negative pulse electroplating process, the amplitude ratio of the positive pulse current to the negative pulse current is 50:200 - 50:

500.

5. A circuit board plating hole process according to claim 3, characterized in that, The pulse current cycle T includes a positive pulse time T1, a negative pulse time T2, a positive pulse time T3, a pulse stop time T4, and a negative pulse time T5.

6. A circuit board plating hole process according to claim 5, characterized in that, During the positive and negative pulse electroplating process, the positive pulse time T1 is 0 - 100 milliseconds, the negative pulse time T2 is not more than 50 milliseconds, the positive pulse time T3 is not more than 100 milliseconds, the pulse stop time T4 is not more than 4 milliseconds, and the negative pulse time T5 is not more than 8 milliseconds.

7. A circuit board plating hole process according to claim 6, characterized in that, During the positive and negative pulse electroplating process, the positive pulse time T1 is 100 milliseconds, and the negative pulse time T2 is 10 milliseconds.

8. A circuit board plating hole process according to claim 7, characterized in that, At 100 ms (positive current time), the circuit board exists as the cathode and the titanium mesh exists as the anode; at 10 ms (negative current time), the circuit board exists as the anode and the titanium mesh exists as the cathode.

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