Aliasing chip testing method and testing device

Abstract

The present invention belongs to the field of integrated circuit testing technology, and in particular relates to a method and device for testing aliased chips. The method comprises: generating a chip device defect and failure model classification matrix by constructing a chip internal component model; and burning test vectors into a chip testing device; performing functional and performance parameter testing on 2.5D / 3D aliased chips based on the relevant information of the chip device defect and failure model classification matrix and the firmware program of the test vectors; and improving the yield of multi-layer aliased chips by constructing a mass production failure warning model. The testing method implements functional and electrical performance parameter testing of multi-layer aliased chips. This method not only verifies the chip's functions and parameters, but also detects interconnection faults between internal components of the chip, and provides feedback to engineers based on mass production data, thereby improving the chip yield.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit testing technology, and in particular relates to a 2.5D / 3D aliasing chip testing method and testing device based on integrated navigation, control and computing information processing, which is suitable for functional verification, electrical performance testing and mass production yield optimization based on such aliasing chips. Background Art

[0002] With the development of integrated circuit testing, 3D-SiP technology can no longer meet current application requirements. For example, patent application number CN201910024235.7 discloses a multi-layer stacked 3D-SIP chip testing method. This method obtains a custom table of fault codes and loads a test program into a chip testing device. The custom table of fault codes is then combined with the test program to perform functional testing on the multi-layer integrated circuit chip. However, the above technical solution has at least the following problems when used: the technical process is simple, the internal stacked chips are simple, and it can only analyze simple SIP circuits. It cannot perform functional and parameter testing on 2.5D / 3D mixed chips or internal chips.

[0003] Chips based on 2.5D / 3D hybrid technology and integrated information processing for navigation, control, and computation have emerged. These highly complex integrated chips increase testing time and costs. Furthermore, new processes present numerous performance uncertainties, further increasing testing difficulty.

[0004] Therefore, how to provide a 2.5D / 3D aliasing chip testing method based on integrated information processing of navigation, control and computing has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] The present invention aims to provide a 2.5D / 3D aliasing chip testing method and device based on integrated navigation, control, and computing information processing. This testing method enables functional and electrical performance parameter testing of multi-layer aliasing chips. This method not only verifies chip functions and parameters but also detects interconnection faults between internal chip components. Furthermore, it provides feedback to engineers based on mass production data, thereby improving chip yield. This makes the present invention more widely applicable.

[0006] To solve the above technical problems, the present invention provides a 2.5D / 3D aliasing chip testing method based on integrated navigation, control and computing information processing, comprising:

[0007] By building a chip internal component model, a chip device defect and failure model classification matrix is ​​generated; and test vectors are burned into the chip test device;

[0008] Functional and performance parameter testing of 2.5D / 3D aliasing chips is performed based on information related to the chip device defect and failure model classification matrix and test vector firmware. Specifically, binary classification information of the chip failure model classification matrix is ​​obtained through the FPGA port of the 2.5D / 3D aliasing chip to determine whether there are functional and performance parameter issues with 2.5D / 3D aliasing.

[0009] By building a mass production failure warning model, the yield rate of multi-layer aliasing chips can be improved.

[0010] Preferably, the construction of the chip internal component model is to construct a chip internal model consisting of an FPGA component, a DSP component, a CIB core module and an AI module; wherein the FPGA component is integrated with FPGA, FLASH and DDR3; and the DSP component is integrated with DSP, NorFLASH and DDR3.

[0011] Preferably, the burning of the test vectors into the chip test device, i.e. starting the ARM and FPGA projects into the test device for detecting chip defects, includes: FPGA test program preloading, DSP test program preloading, CIB test program preloading and AI test program preloading, so as to realize parallel initialization of multi-core test resources.

[0012] Preferably, the functional and electrical performance parameter testing of the 2.5D / 3D hybrid chip includes:

[0013] FPGA component functional testing, including FLASH self-test, DDR3 1333 / 1600Mbps dual-rate verification, and GTH high-speed self-test;

[0014] FPGA component performance test, i.e. output port drive voltage test;

[0015] CIB functional test, namely SRIO / SPI / NAND FLASH / PCIe interface functional test;

[0016] AI functional testing, i.e. computing power testing;

[0017] DSP component functional testing, including floating-point testing, EMIF testing, and GMAC testing;

[0018] Internal component interconnection and communication testing, including DSP and CIB communication, FPGA and CIB communication, and FPGA and DSP communication testing.

[0019] Preferably, the construction of a mass production failure warning model includes:

[0020] The chip data to be tested is transmitted to the host computer to obtain the current failure data, and compared with the standard data to determine whether the parameters of the current chip to be tested deviate from the normal range;

[0021] According to the chip device defect and failure model classification matrix, the corresponding failure number F[i] is recorded, and then a mass production failure warning model is built on the host computer;

[0022] If the ratio of failure number F[i] / current test total number F is greater than 5%, the host computer will start to perform early warning operations according to the national standard 548C / 2021; all current failure numbers F[i] are counted, and if the ratio of other failure numbers F[i] / current failure number F[i] is greater than 95%, it will also be displayed on the host computer;

[0023] When the host computer is in the warning state, the current failure number F[i] will be displayed on the LED display board of the ARM board. The chip test device is in a power-off state when it is not operated for a long time. After the engineer confirms the warning state, the total number of tests F is passively cleared. At the same time, all failure comparison information stored in the failure number F[i] is discarded after the chip test device is powered on, and thus converted into a new mass production failure warning model to meet the needs of subsequent test failure analysis.

[0024] Preferably, the fault state definition of each test in the chip device defect and failure model classification matrix starts from 10000001 and ends at 10010011, 11111111 means the test is passed; 0XXXXXX means testing in progress, where X represents an uncertain state, X is 1 or 0.

[0025] The present invention also provides a 2.5D / 3D aliasing chip testing device based on navigation, control and computing integrated information processing, which performs the above-mentioned 2.5D / 3D aliasing chip testing method based on navigation, control and computing integrated information processing, including:

[0026] Host computer;

[0027] A multifunctional integrated processing device connected to the host computer;

[0028] Power adapter;

[0029] Clock adapter;

[0030] A test board for the chip to be tested is respectively communicatively connected to the power adapter, the clock adapter and the multifunctional integrated processing device; wherein the test board for the chip to be tested is used to fix the chip to be tested and power on the chip to be tested, and the test board for the chip to be tested is composed of a variety of circuit design hardware, and can complete the test of the chip to be tested under the instructions of the host computer, and display the test results in real time on the multifunctional integrated processing device.

[0031] Preferably, before the test program is imported, the test device needs to be set up, that is: during the test, the power adapter has multiple built-in voltage regulator chips. After power-on, the host computer sends a startup instruction to the multifunctional integrated processing device. The multifunctional integrated processing device processes the relevant information of the chip device defect and failure model classification matrix in sequence, and performs functional and performance parameter tests on the aliasing chip. Finally, the information corresponding to the chip device defect and failure model classification matrix is ​​fed back to the host computer to determine whether the chip is normal. After that, the power adapter is powered off and the test ends.

[0032] Preferably, the multifunctional integrated processing device comprises: an LED display board, an electronic load, an FPGA hardware board, a CPU hardware board, and an ARM hardware board; the ARM hardware board monitors the test of the FPGA hardware board and the CPU hardware board according to the test sequence, and feeds back the port status to the LED display board for displaying chip device defect and failure model classification matrix information;

[0033] The FPGA hardware board is connected to the circuit board of the chip under test through the FPGA interface, and is used for the FPGA component function and performance test, DSP component function test and internal component interconnection communication test of the aliasing chip;

[0034] The CPU hardware board is connected to the circuit board of the chip under test through the CPU interface and is used for CIB and AI function testing of the aliasing chip;

[0035] The ARM hardware board is connected to the circuit board of the chip under test through the ARM interface and is used for functional testing of the DSP component of the aliasing chip;

[0036] The power adapter has a built-in voltage regulator chip and is connected to the circuit board of the chip under test, and is used to power on and off the chip;

[0037] The clock adapter has multiple active clocks built in and is connected to the circuit board of the chip under test to provide a reference clock signal;

[0038] The FPGA hardware board includes an FPGA processor; the CPU hardware board includes a CPU processor; and the ARM hardware board includes an ARM processor.

[0039] Preferably, the loading of the test program on the multifunctional integrated processing device includes:

[0040] Loading FPGA functional test program into multifunctional integrated processing device; including:

[0041] Power on the circuit, apply VIVADO software, select compile and debug, generate BIT files and device burning steps to complete program burning;

[0042] Re-power the circuit, apply CCS software, import the project, build the project, connect the debugger, and execute the run debug step to complete the programming;

[0043] Loading the FPGA performance test program into the chip test device; including:

[0044] Re-power the circuit, use VIVADO software, select the bit file for performance test, and execute the device burning steps to complete the program burning;

[0045] Loading the CIB test program into the chip test device; including:

[0046] Re-power on the circuit, apply KEIL software, select the corresponding .c project file, connect the debugger, and update the internal program of the chip. After the update is completed, power off the chip.

[0047] Power on the circuit, apply VIVADO software, select compile and debug, generate BIT file, device burning steps, and complete program burning;

[0048] Loading the AI ​​test program into the chip test device; including:

[0049] Re-power the circuit, connect the PCIE interface, and use the Pytorch software in the Linux environment to select the corresponding Py file and perform matrix calculations to implement computing power testing;

[0050] Loading the DSP test program into the chip test device; including:

[0051] Re-power the circuit, apply CCS software, import the project, build the project, connect the debugger, and execute the run debug step to complete the programming;

[0052] Power on the circuit, apply VIVADO software, select compile and debug, generate BIT file, and device burning steps to complete program burning.

[0053] Compared with the prior art, the present invention has the following beneficial effects:

[0054] The 2.5D / 3D aliasing chip testing method for integrated navigation, control, and computing information processing provided by the present invention enables functional and electrical performance parameter testing of multi-layer aliasing chips. This method not only verifies the chip's functions and parameters, but also detects interconnection faults between internal chip components and improves chip yield based on feedback from mass production data to engineers. These advantages demonstrate that the present invention has wider applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1The present invention provides a flow chart of a 2.5D / 3D aliasing chip testing method based on integrated information processing of navigation, control and calculation.

[0056] Figure 2 This is a schematic structural diagram of the chip testing device provided by the present invention. DETAILED DESCRIPTION

[0057] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0058] like Figure 1 As shown, an embodiment of the present invention specifically provides an aliasing chip testing method, including:

[0059] S110, chip internal component model analysis;

[0060] S120, generating a chip device defect and failure model classification matrix;

[0061] S130, burning the test vector to the chip defect detection test platform;

[0062] S140, FPGA component functional testing;

[0063] S150, FPGA component performance test;

[0064] S160, CIB functional test;

[0065] S170, AI functional test;

[0066] S180, DSP component functional testing;

[0067] S190, internal component interconnection communication test;

[0068] S200, feeding back the chip defect detection test platform based on the chip device defect and failure model classification matrix and the test results;

[0069] S210, mass production failure warning to improve yield.

[0070] The tests include: FPGA component functional test (FLASH self-test, DDR3 1333 / 1600Mbps dual-rate verification, GTH high-speed self-test), FPGA component performance test (output port drive voltage test), CIB functional test (SRIO / SPI / NAND FLASH / PCIe interface function), AI functional test (computing power test), DSP component functional test (floating point test, EMIF test, GMAC test), internal component interconnection communication test (DSP and CIB communication, FPGA and CIB communication, FPGA and DSP communication).

[0071] The testing of the aliasing chip in sequence according to the chip device defect and failure model classification matrix and combined with the test program includes: FPGA component function test (FLASH self-test, DDR3 1333 / 1600Mbps dual-rate verification, GTH high-speed self-test), FPGA component performance test (output port drive voltage test), CIB function test (SRIO / SPI / NANDFLASH / PCIe interface function), AI function test (computing power test), DSP component function test (floating point test, EMIF test, GMAC test), internal component interconnection communication test (DSP and CIB communication, FPGA and CIB communication, FPGA and DSP communication).

[0072] The chip device defect and failure model classification matrix defines internal FLASH self-test, internal DDR3 1333 mbps self-test functional test, internal DDR3 1600 mbps self-test, and internal GTH high-speed self-test as FPGA component functional tests.

[0073] Preferably, the output port drive voltage test is defined as an FPGA component performance test based on the chip device defect and failure model classification matrix.

[0074] Preferably, the SRIO interface test, SPI interface test, MBIST test, CMU test, NAND FLASH interface function, DDR interface function, and PCIE interface function are defined as CIB function test according to the chip device defect and failure model classification matrix.

[0075] Preferably, the computing power test defined according to the chip device defect and failure model classification matrix is ​​an FPGA component performance test.

[0076] Preferably, the floating point test, EMIF test and GMAC test are defined as DSP component functional tests according to the chip device defect and failure model classification matrix.

[0077] Preferably, the internal DSP and CIB communication test, the internal FPGA and CIB communication test, and the internal FPGA and DSP communication test are defined as internal component interconnection communication tests according to the chip device defect and failure model classification matrix.

[0078] The 2.5D / 3D hybrid chip testing method for navigation, control, and computing integrated information processing provided by the present invention enables functional and electrical performance parameter testing of multi-layer hybrid chips. This method not only verifies the chip's functions and parameters, but also detects interconnection faults between internal chip components and provides feedback to engineers based on mass production data, thereby improving chip yield.

[0079] It is worth noting that before the test program is imported, the test device must be built. Figure 2 As shown, during testing, power adapter 410 has multiple built-in voltage regulator chips 400. After powering on, host computer 10 sends a startup command to multifunctional integrated processing device 15. Multifunctional integrated processing device 15 processes the chips in sequence according to the chip component defect and failure model classification matrix information, performs functional and performance tests on aliasing chip 220, and ultimately feeds back information corresponding to the chip component defect and failure model classification matrix to host computer 10, thereby determining whether the chip is functioning properly. Power adapter 410 is then powered off, and the test ends.

[0080] Specifically, such as Figure 2 As shown, the multifunctional integrated processing device 15 is provided with an ARM hardware board 190, which is connected to the circuit board 210 of the chip under test through the ARM interface 170, and is used for functional testing of the DSP components of the aliasing chip.

[0081] Specifically, such as Figure 2 As shown, the multifunctional integrated processing device 15 is provided with an LED display board 180, and the FPGA hardware board 100, the CPU hardware board 120 and the ARM hardware board 190 are interconnected through ports and feedback test information. The ARM hardware board 190 monitors the test feedback port status of the FPGA hardware board and the CPU hardware board according to the test sequence, and feeds back to the LED display board 180 for displaying chip device defect and failure model classification matrix information.

[0082] Specifically, such as Figure 2 As shown, the multifunctional integrated processing device 15 is also provided with a CPU hardware board 120, which is connected to the circuit board 210 of the chip under test through the CPU interface 150, and is used for CIB and AI function testing of the aliasing chip.

[0083] Specifically, such as Figure 2As shown, the multifunctional integrated processing device 15 is further provided with an FPGA hardware board 100, which is connected to the circuit board 210 of the chip under test via an FPGA interface 130, and is used for FPGA component function and performance testing of the aliasing chip, DSP component function testing, and internal component interconnection and communication testing.

[0084] Specifically, such as Figure 2 As shown, the multifunctional integrated processing device 15 is provided with an LED display board 180, an electronic load 115, an FPGA hardware board 100, a CPU hardware board 120 and an ARM hardware board 190, which are interconnected through ports and feed back test information. The ARM hardware board 190 monitors the test feedback port status of the FPGA hardware board and the CPU hardware board according to the test sequence and feeds it back to the LED display board 180 for displaying chip device defects and failure model classification matrix information.

[0085] Specifically, such as Figure 2 As shown, the aliasing chip 220 is internally composed of multiple components and chips, specifically an FPGA component 240 , a DSP component 260 , a CIB (core particle) module 200 , and an AI module 280 .

[0086] Specifically, such as Figure 2 As shown, the power adapter 410 has a built-in voltage regulator chip 400 and is connected to the circuit board 210 of the chip under test for powering on and off the chip.

[0087] Specifically, such as Figure 2 As shown, the clock adapter 300 has multiple active clocks built in and is connected to the circuit board 210 of the chip under test to provide a reference clock signal.

[0088] The FPGA hardware board 100 includes an FPGA processor 110 , the CPU hardware board 120 includes a CPU processor 140 , and the ARM hardware board 190 includes an ARM processor 160 .

[0089] The ARM interface 170 includes a JTAG debug bus, a UART serial port (extendable to RS-485) and a general signal direct connection channel. The CPU interface 150 provides a JTAG and UART dual debug interface and a PCIe high-speed channel interface. The FPGA interface 130 integrates a PCIE high-speed interface, a JTAG bus, and a programmable signal direct connection channel interface.

[0090] The central area of ​​the circuit board 210 of the chip under test is concave in design, and is used to fix the aliased chip under test 220. The PCB is a multi-layer board design.

[0091] Specifically, loading a test program onto the multifunctional integrated processing device includes:

[0092] Loading FPGA functional test program into the multifunctional integrated processing device;

[0093] Specifically, power on the circuit, apply VIVADO software, select compile and debug, generate BIT files, burn devices and other steps to complete program burning;

[0094] Specifically, re-power the circuit, apply CCS software, import the project, build the project, connect the debugger, and execute run debug and other steps to complete the burning;

[0095] Loading FPGA performance test program to chip test device;

[0096] Specifically, re-power the circuit, apply VIVADO software, select the bit file for performance test, and execute steps such as device burning to complete program burning;

[0097] Load the CIB test program into the chip test device;

[0098] Specifically, the circuit is powered on again, KEIL software is applied, the corresponding .c project file is selected, the debugger is connected, and the internal program of the chip is updated. After the update is completed, the chip is powered off;

[0099] Specifically, power on the circuit, apply VIVADO software, select compile and debug, generate BIT files, burn devices and other steps to complete program burning;

[0100] Load the AI ​​test program into the chip test device;

[0101] Specifically, the circuit is powered on again, the PCIE interface is connected, and the corresponding Py file is selected through the Pytorch software in the Linux environment, and matrix calculations are performed to implement computing power testing;

[0102] Load the DSP test program into the chip test device;

[0103] Specifically, repower the circuit, apply CCS software, import the project, build the project, connect the debugger, and execute run debug and other steps to complete the programming;

[0104] Specifically, power on the circuit, apply VIVADO software, select compile and debug, generate BIT files, burn devices and other steps to complete program burning;

[0105] Preferably, each test in the chip device defect and failure model classification matrix starts from 10000001 and ends at 10010011, and 11111111 indicates a passed test. 0XXXXXX indicates a test in progress, where X represents uncertainty and can be either 1 or 0.

[0106] Preferably, during the mass production test process, the data of the chip under test is transmitted to the host computer, and the current failure data is compared with the standard data to determine whether the parameters of the chip under test exceed the normal range. If the chip parameters are abnormal, the failure of the chip will be recorded as the corresponding failure number F[i] according to the chip device defect and failure model classification matrix, and a mass production failure warning model will be constructed on the host computer. When the ratio of the number of occurrences of a certain failure number F[i] to the current total number of tests F exceeds 5%, according to the national standard 548C / 2021, the system will issue a warning for the failure defect corresponding to the failure number F[i] in the host computer and display the warning information on the LED display of the ARM board. All current failure numbers F[i] are counted, and if the ratio of other failure numbers F[i] / current failure number F[i] is greater than 95%, it will also be displayed on the host computer. Once the host computer enters the warning state, the chip defect detection test platform will be in a power-off state if it is not operated for a long time. The total number of tests F will be cleared only after the engineer confirms the warning state. At the same time, all recorded failure numbers F[i] and their corresponding failure comparison information will be cleared after the chip defect detection test platform is powered on again, thereby generating a new mass production failure warning model to meet the subsequent test failure analysis needs.

[0107] Table 1 below shows the chip device defect and failure model classification matrix information;

[0108]

[0109] It should be noted that failure of the internal FLASH self-test, internal DDR3 1333mbps self-test function test, and internal DDR3 1600mbps self-test is identified as a FLASH defect; failure of the internal GTH high-speed self-test and output port drive voltage test is identified as an FPGA defect; failure of the SRIO interface test, SPI interface test, MBIST test, CMU test, NANDFLASH interface function, DDR interface function, and PCIE interface function is identified as a CIB defect; failure of the computing power test is identified as an AI defect; failure of the floating-point test, EMIF test, and GMAC test is identified as a DSP defect; failure of the internal DSP and CIB communication test, the internal FPGA and CIB communication test, and the internal FPGA and DSP communication test is identified as a packaging defect.

[0110] The test of the chip device defect and failure model classification matrix provided by the present invention is described in detail below in conjunction with the above Table 1.

[0111] If the test is normal, the ARM LED display panel will show 11111111;

[0112] During the test, the ARM LED display panel shows 0XXXXXX;

[0113] If there is a problem with the chip test, other status will be displayed;

[0114] 1. Internal FLASH self-test

[0115] Use FPGA to perform functional testing on FLASH through internal interconnection signals, mainly involving full address reading and writing of 55AA, AA55, 0000, 1111, and compare with the data pre-stored in FPGA. If the data is consistent, FLASH is normal, otherwise the internal FLASH self-test fails. FPGA sends the port signal to ARM processor 160. ARM detects the port change and feeds back 10000001 to the host computer, and displays the result on the LED display board.

[0116] 2. Internal DDR3 1333mbps self-test

[0117] Use FPGA to perform functional testing on FLASH through internal interconnection signals. The IP core uses DDR 1333 rate, mainly involving full address reading and writing of 55AA, AA55, 0000, and 1111, and compares it with the data pre-stored in FPGA. If the data is consistent, it indicates that the FLASH is normal, otherwise the internal FLASH self-test fails. The FPGA sends the port signal to the ARM processor. The ARM detects the port change and feeds back 10000010 to the host computer, and the result is displayed on the LED display board.

[0118] 3. Internal DDR3 1600mbps self-test

[0119] Use FPGA to perform functional testing on DDR3 through internal interconnection signals. The IP core uses DDR 1600 rate, mainly involving full address reading and writing of 55AA, AA55, 0000, and 1111, and compares it with the data pre-stored in FPGA. If the data is consistent, DDR3 is normal, otherwise the internal FLASH self-test fails. FPGA sends the port signal to the ARM processor. ARM detects the port change and feeds back 10000011 to the host computer, while displaying the result on the LED display board.

[0120] 4. Internal GTH high-speed self-test

[0121] The high-speed interface test program runs on the FPGA inside the device. The reference clock provides a clock signal, and through signal multiplication, the FPGA loop sends and reads data packets and counts them. If the total count is correct, the test passes. Otherwise, the test fails, and the internal GTH high-speed self-test fails. The FPGA sends a port signal to the ARM processor. The ARM detects the port change and feeds 10000100 back to the host computer, while also displaying the result on the LED display board.

[0122] 5. Output port drive voltage test

[0123] The device's internal FPGA runs the output port drive voltage test program, applying a drive current to the output port of the chip under test through an electronic load. This signal is then sent to the FPGA ADC port on the FPGA hardware board, which then feeds back the signal to the host computer. If the value is ≥1.4, the test passes. Otherwise, the test fails, and the output port drive voltage test fails. The ARM processor feeds 10000101 back to the host computer, while the result is displayed on the LED display.

[0124] 6. SRIO interface test

[0125] Configure the CIB's SRIO interface to 5.0Gbps Lane x2 mode. Run the SRIO data write request command in the ARM processor and send a write data packet request to the CIB's SRIO interface. After the CIB chip receives the write request command, it performs data packet exchange and returns a write response packet to the FPGA. Use the FPGA's logic analyzer to capture the SRIO port's write command and response packets. Count the write / read event delay time series, and take the maximum value of the two series as the final delay time. If the final delay data is ≤30μs, the test passes. Otherwise, the test fails, the SRIO interface fails, and the ARM processor sends a signal of 10000110 to the host computer, while displaying the result on the LED display.

[0126] 7. SPI interface test

[0127] Configure the SPI interface mode of the CIB, send instructions to the fixed-position registers of the chip and configure them. The FPGA is responsible for monitoring the SPI interface. If the data is normal, the test passes. Otherwise, the test fails and the SPI interface becomes invalid. The ARM processor feeds back 10000111 to the host computer and displays the result on the LED display board.

[0128] 8. NAND FLASH interface function

[0129] Run the test program to perform a full-address test on the Nand Flash through the CIB chip and count the capacity of all Nand Flash storage units. If the total Nand Flash capacity is ≥16Gb, the test passes. Otherwise, the test fails, the SPI interface becomes invalid, the ARM processor feeds back 10001000 to the host computer, and the result is displayed on the LED display board.

[0130] 9. PCIE interface function

[0131] Configure the PCIE interface rate of CIB to 5.0Gbps Lane x2 mode as the EP end; run the PCIE interface test program in the accompanying CPU core board, configure the accompanying CPU as the RC end, and the CPU core board uses the PCIE interface to cyclically write and read data packets to the EP end device, and complete the verification of sending and receiving data packets in the CPU core board. If the data packet transmission verification is correct, the test passes, otherwise the test fails, the PCIE interface fails, and the ARM processor feeds back 10001001 to the host computer, and displays the result on the LED display board.

[0132] 10. Computing power test

[0133] The AI ​​floating-point computing peak performance test program generates two floating-point matrices of [m:n] and [n:h] dimensions, with each matrix element defined as a floating-point number. The program multiplies these two matrices, resulting in a single computational effort of m*n*h*2. The program loops through e matrix multiplications, resulting in a total computational effort of MAI = e*m*n*h*2. The program uses a timer to obtain the total time T consumed by these matrix multiplications. The peak computing power of a single AI floating-point chip, PAI, is calculated as MAI / T = e*m*n*h*2 / T, measured in TFLOPS. If the peak computing power test result is ≥2.0 TFLOPS, the test passes. Otherwise, the test fails, and the computing power test fails. The ARM processor sends a signal of 10001010 to the host computer, while also displaying the result on the LED display.

[0134] 11. Floating point test

[0135] The floating-point peak performance test program loops and executes floating-point operations on all eight DSP cores. The loop count is c, and each loop contains d floating-point operations. The floating-point computations per DSP core are calculated as MCORE = c * d. The DSP timer is used to measure the program execution time, tREG. The timer frequency is 1 / 6 of the DSP operating frequency, resulting in a total loop time of T = tREG * 6ns. The peak floating-point computing power of a single DSP, PDSP, is calculated as 8 (cores) * MCORE / T = 8 * c * d / (tREG * 6 * 1000), expressed in TFLOPS. If the peak computing power test result is correct, the test passes. Otherwise, the floating-point test fails, and the ARM processor sends the value 10001011 to the host computer, while also displaying the result on the LED display.

[0136] 12. EMIF test

[0137] The EMIF interface test program is executed in the DSP chip inside the device. The EMIF operation data bit width is configured to be 32 bits (including all data lines). The memory on the EMIF interface is accessed and multi-address (including the transformation of all address lines) read and write operations are performed on the memory. First, 0x55AA55AA is written to each address, the written data is read, and the read and write data are compared for consistency. Then 0xAA55AA55 is written to each address, and the read and write data are compared. If the two are consistent, the test passes. Otherwise, the EMIF test fails and the ARM processor feeds back 10001100 to the host computer. The result is displayed on the LED display board.

[0138] 13. GMAC test

[0139] Connect the Ethernet interface of the DSP to the network port of the PC via a network cable, run the Ethernet test program in the DSP, configure the GMAC interface of the DSP to work in 1000Mbps mode, and at the same time, the test program in the DSP sends the data received by the GMAC port back through the port. Run the Ethernet test software on the PC. The software sends data packets to the GMAC interface of the DSP and receives data returned from the DSP GMAC port, and compares and verifies the sent and received data. If the data transmission is correct, the test passes. Otherwise, the test fails, the GMAC test fails, the ARM processor feeds back 10001101 to the host computer, and displays the result on the LED display board.

[0140] 14. Internal DSP and CIB communication test

[0141] After the DSP and CIB are loaded, the DSP is interconnected with the CIB through the EMIF interface, the EMIF operation data width is configured to 8 bits, and the CIB on the EMIF interface is accessed. If the access is successful, the test passes, otherwise it fails, the internal DSP and CIB communication test fails, and the ARM processor feeds back 10001110 to the host computer and displays the result on the LED display board.

[0142] 15. Internal FPGA and CIB communication test

[0143] After the FPGA and CIB are loaded, the FPGA is interconnected with the CIB through the IOB. The CIB feeds back all high and all low signals according to the corresponding ports. If the FPGA can detect the relevant signals, the test passes. Otherwise, the internal FPGA and CIB communication test fails. The ARM processor feeds back 10001111 to the host computer and displays the result on the LED display board.

[0144] 16. Internal FPGA and DSP communication test

[0145] After the FPGA and DSP are loaded, the FPGA is interconnected with the DSP through the IOB. The DSP sends data to the FPGA according to the EMIF interface. The FPGA stores and verifies the data, and the test passes. Otherwise, the internal FPGA and DSP communication test fails. The ARM processor feeds back 10010000 to the host computer and displays the result on the LED display board.

[0146] In summary, the present invention provides a 2.5D / 3D hybrid chip testing method based on integrated navigation, control, and computing information processing. This method not only verifies the performance and parameters of the chip, but also detects interconnection failures between internal components of the chip, and improves chip yields based on feedback from mass production data to engineers.

[0147] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A 2.5D / 3D aliasing chip testing method based on navigation, control and computing integrated information processing, characterized in that: include: By building a chip internal component model, a chip device defect and failure model classification matrix is ​​generated; and burning test vectors into chip test devices; Perform functional and performance parameter testing on 2.5D / 3D aliasing chips based on information about the chip device defect and failure model classification matrix and test vector firmware; That is, the binary classification information of the chip device defect and failure model classification matrix is ​​obtained through the FPGA port of the 2.5D / 3D aliasing chip, thereby determining whether the 2.5D / 3D aliasing chip has functional and performance parameter problems; By building a mass production failure warning model, the yield rate of multi-layer aliasing chips can be improved; The chip internal component model is constructed, that is, the chip internal model is constructed by the FPGA component, the DSP component, the CIB core module and the AI ​​module; wherein the FPGA component is integrated with FPGA, FLASH and DDR3; the DSP component is integrated with DSP, NorFLASH and DDR3; The construction of the mass production failure warning model includes: The chip data to be tested is transmitted to the host computer to obtain the current failure data, and compared with the standard data to determine whether the parameters of the current chip to be tested deviate from the normal range; According to the chip device defect and failure model classification matrix, the corresponding failure number F[i] is recorded, and then a mass production failure warning model is built on the host computer; If the ratio of the occurrence of failure number F[i] to the total number of current tests F is greater than 5%, the host computer starts to perform early warning operations; the occurrence of all current failure numbers F[i] is counted, and if the ratio of the occurrence of other failure numbers F[i] to the occurrence of the current failure number F[i] is greater than 95%, it will also be displayed on the host computer; When the host computer is in the warning state, the current failure number F[i] will be displayed on the LED display board of the ARM board. The chip test device is in a power-off state when it is not operated for a long time. After the warning state is confirmed, the total number of tests F is passively cleared. At the same time, all failure comparison information stored in the failure number F[i] is discarded after the chip test device is powered on, and thus converted into a new mass production failure warning model to meet the needs of subsequent test failure analysis; The fault state definition of each test in the chip device defect and failure model classification matrix starts from 10000001 and ends at 10010011, 11111111 means the test is passed; 0XXXXXX means testing in progress, where X represents an uncertain state, X is 1 or 0.

2. A 2.5D / 3D aliasing chip testing method based on navigation, control and computing integrated information processing according to claim 1, characterized in that: The burning of the test vectors into the chip test device is to start the ARM and FPGA projects into the test device for detecting chip defects; it includes: FPGA test program preloading, DSP test program preloading, CIB test program preloading and AI test program preloading to achieve parallel initialization of multi-core test resources.

3. The 2.5D / 3D aliasing chip testing method based on navigation, control and computing integrated information processing according to claim 1, characterized in that: The functional and electrical performance parameter testing of the 2.5D / 3D hybrid chip includes: FPGA component functional testing, including FLASH self-test, DDR3 1333 / 1600Mbps dual-rate verification, and GTH high-speed self-test; FPGA component performance test, i.e. output port drive voltage test; CIB functional test, namely SRIO / SPI / NAND FLASH / PCIe interface functional test; AI functional testing, i.e. computing power testing; DSP component functional testing, including floating-point testing, EMIF testing, and GMAC testing; Internal component interconnection and communication testing, including DSP and CIB communication, FPGA and CIB communication, and FPGA and DSP communication testing.

4. A 2.5D / 3D aliasing chip testing device based on navigation, control and computing integrated information processing, executing a 2.5D / 3D aliasing chip testing method based on navigation, control and computing integrated information processing according to any one of claims 1 to 3, characterized in that: include: Host computer; A multifunctional integrated processing device connected to the host computer; Power adapter; Clock adapter; The circuit board of the chip under test is communicatively connected to the power adapter, the clock adapter and the multifunctional integrated processing device respectively; The circuit board of the chip under test is used to fix the chip under test and power on the chip under test. The circuit board of the chip under test is composed of a variety of circuit design hardware, which can complete the test of the chip under test under the instructions of the host computer and display the test results in real time on the multifunctional integrated processing device.

5. The 2.5D / 3D aliasing chip testing device based on navigation, control and computing integrated information processing according to claim 4, characterized in that: Before the test program is imported, the test device needs to be built, that is: during the test, the power adapter has multiple built-in voltage regulator chips. After power-on, the host computer sends a startup instruction to the multi-functional integrated processing device. The multi-functional integrated processing device processes the relevant information of the chip device defect and failure model classification matrix in sequence, and performs functional and performance parameter tests on the aliasing chip. Finally, the information corresponding to the chip device defect and failure model classification matrix is ​​fed back to the host computer to determine whether the chip is normal. After that, the power adapter is powered off and the test ends.

6. The 2.5D / 3D aliasing chip testing device based on navigation, control and computing integrated information processing according to claim 4, characterized in that: The multifunctional integrated processing device includes: an LED display board, an electronic load, an FPGA hardware board, a CPU hardware board, and an ARM hardware board; the ARM hardware board monitors the test of the FPGA hardware board and the CPU hardware board according to the test sequence, and feeds back the port status to the LED display board for displaying chip device defect and failure model classification matrix information; The FPGA hardware board is connected to the circuit board of the chip under test through the FPGA interface, and is used for the FPGA component function and performance test of the aliasing chip, the DSP component function test and the internal component interconnection and communication test; The CPU hardware board is connected to the circuit board of the chip under test through the CPU interface and is used for CIB and AI function testing of the aliasing chip; The ARM hardware board is connected to the circuit board of the chip under test through the ARM interface and is used for functional testing of the DSP component of the aliasing chip; The power adapter has a built-in voltage regulator chip and is connected to the circuit board of the chip under test, and is used to power on and off the chip; The clock adapter has multiple active clocks built in and is connected to the circuit board of the chip under test to provide a reference clock signal; The FPGA hardware board includes an FPGA processor; the CPU hardware board includes a CPU processor; and the ARM hardware board includes an ARM processor.

7. The 2.5D / 3D aliasing chip testing device based on navigation, control and computing integrated information processing according to claim 4, characterized in that: The multifunctional integrated processing device loads a test program including: Loading FPGA functional test program into multifunctional integrated processing device; including: Power on the circuit, apply VIVADO software, select compile and debug, generate BIT files and device burning steps to complete program burning; Re-power the circuit, apply CCS software, import the project, build the project, connect the debugger, and execute the run debug step to complete the programming; Loading the FPGA performance test program into the chip test device; including: Re-power the circuit, use VIVADO software, select the bit file for performance test, and execute the device burning steps to complete the program burning; Loading the CIB test program into the chip test device; including: Re-power on the circuit, apply KEIL software, select the corresponding .c project file, connect the debugger, and update the internal program of the chip. After the update is completed, power off the chip. Power on the circuit, apply VIVADO software, select compile and debug, generate BIT file, device burning steps, and complete program burning; Loading the AI ​​test program into the chip test device; including: Re-power the circuit, connect the PCIE interface, and use the Pytorch software in the Linux environment to select the corresponding Py file and perform matrix calculations to implement computing power testing; Loading the DSP test program into the chip test device; including: Re-power the circuit, apply CCS software, import the project, compile the project, connect the debugger, and execute the run and debug steps to complete the programming; Power on the circuit, apply VIVADO software, select compile and debug, generate BIT file, and device burning steps to complete program burning.

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