Satellite-borne heterogeneous multi-core processor initialization method and system

Abstract

The invention provides a satellite-borne heterogeneous multi-core processor initialization method and system, and the method comprises the steps: S1, resetting all components to be in an initial state after the system is powered on or a main reset signal is triggered; s2, enabling the DSP core in each cluster to start executing a bootstrap program from the 0x0 position of the ROM; s3, querying a value of a loading state register; s4, waiting for a transmission request by querying the flag bit, and starting DMA transmission when an effective flag bit is detected; s5, generating a corresponding flag bit after DMA transmission is completed; and S6, finally executing a jump instruction, and enabling the program to jump to the DSP initial address to continue to be executed. According to the initialization method provided by the invention, a complex architecture and an interconnection structure of the heterogeneous multi-core processor are considered, and data exchange and cooperative calculation can be efficiently carried out between cores by configuring and optimizing a cache consistency protocol, a memory management unit, a bus controller and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of spaceborne computers, and in particular, to a method and system for initializing a spaceborne heterogeneous multi-core processor. Background Art

[0002] In a spaceborne system, the reliability and stability of a processor are one of the key factors to ensure the normal operation and task execution of a satellite. Heterogeneous multi-core processors have become the first choice for spaceborne systems due to their highly flexible architecture, low power consumption, and high performance. However, compared with traditional single-core processors, the initialization process of heterogeneous multi-core processors is more complex, mainly due to their multi-core structure and the need for startup sequence and parameter configuration between different cores.

[0003] Patent document CN112965755A discloses a method, device, electronic device, and storage medium for initializing a multi-core processor, which realizes the self-enumeration of each CPU core for core initialization information in the firmware stage through the method of inter-core interruption. Patent document CN118034936A discloses an application reconstruction method and system based on a spaceborne heterogeneous multi-core processor, which realizes the judgment of whether there is an application CPU program wake-up instruction by calculating the head address of the MultiBoot register value. Patent document CN116841620A discloses an embedded spaceborne heterogeneous multi-core intelligent computing system and method, which improves the neural network computing frame rate and energy efficiency for spaceborne applications through the neural network model inference acceleration of the master control CPU + multiple NPUs based on data flow parallelism. Patent document CN114398054A discloses a spaceborne processor management system supporting software reconstruction, which realizes the software reconstruction and management functions of on-orbit payloads through the spaceborne processor management system. Patent document CN117724724A discloses a compilation processing method, device, equipment, and medium for a multi-core heterogeneous processor, which reduces the waste of computing resources and storage resources of a computer system through virtualization parsing processing.

[0004] The initialization of a heterogeneous multi-core processor needs to consider the startup sequence and initialization process of multiple cores simultaneously. Since different cores may have different functions and uses, it is necessary to ensure that they are initialized in the correct order to ensure the stability and consistency of the entire system. This may involve precise adjustment and configuration of the startup sequence to meet the requirements of specific applications and tasks.

[0005] The initialization of a heterogeneous multi-core processor also involves parameter configuration and tuning for each core. Different cores may have different performance characteristics and power consumption requirements. Therefore, during the initialization process, appropriate parameter configuration is needed to balance the relationship between performance and power consumption. This may involve adjusting and optimizing aspects such as clock frequency, voltage, and power management strategies to ensure that the system can operate stably under various workloads.

[0006] In addition, since heterogeneous multi-core processors usually adopt complex architectures and interconnection structures, communication and collaborative work among various cores also need to be considered during the initialization process. This may involve configuring and tuning aspects such as cache coherence protocols, memory management units, and bus controllers to ensure that cores can efficiently exchange data and perform collaborative computing. Summary of the Invention

[0007] Aiming at the defects in the prior art, the purpose of the present invention is to provide a method and system for initializing an on-board heterogeneous multi-core processor.

[0008] According to a method for initializing an on-board heterogeneous multi-core processor provided by the present invention, it includes:

[0009] Step S1: After the system is powered on or the main reset signal is triggered, reset all components to the initial state;

[0010] Step S2: Make the DSP cores in each cluster start to execute the boot program from the 0x0 of the ROM;

[0011] Step S3: Query the value of the load status register. If the value is "1", jump to step S6; otherwise, continue to wait for data transmission;

[0012] Step S4: Wait for the transmission request by querying the flag bit. When a valid flag bit is detected, start the DMA transmission and transfer the program data packet in the FLASH to the local main program memory;

[0013] Step S5: After the DMA transmission is completed, generate a corresponding flag bit, and make the DSP core repeatedly query this flag bit. When it is confirmed that the transmission is completed, set the value of the load status register to "1";

[0014] Step S6: Finally, execute a jump instruction to make the program jump to the DSP starting address and continue to execute.

[0015] Preferably, step S1 includes designing a core start sequence control logic, and each core executes a self-check program by the BIOS after startup.

[0016] Preferably, the starting address of each DSP core in step S2 is set to the starting address of the ROM; the bootloader is stored in the firmware burned during chip manufacturing and is used to initialize the processor and load the main program.

[0017] Preferably, the load status register in step S3 is a register in the system, and its value includes two states. "1" indicates that the loading has been completed and the program directly jumps to the last step for execution; "0" indicates that the loading has not been completed and the program continues to execute downward, waiting for data transmission; when reset, the value is also "0".

[0018] Preferably, after the DMA transfer in step S4 is completed, a hardware flag bit is set to notify the software.

[0019] Preferably, the DSP core continues to poll the hardware flag bit. If it detects that the transfer is completed, the load status register is updated.

[0020] Preferably, when the load status register is set to "1", the bootloader will execute a jump instruction to transfer the control right to the main program in the DSP, representing the end of the bootloader and the startup of the operating system or application program.

[0021] Preferably, an external interrupt request is processed by storing a jump instruction; this instruction directly transfers the control right to a specific address of the interrupt handler; the specific address includes the address pointed to when the bootloader executes its last jump instruction.

[0022] An on - board heterogeneous multi - core processor initialization system provided by the present invention includes:

[0023] Module M1: After the system is powered on or the main reset signal is triggered, reset all components to the initial state;

[0024] Module M2: Make the DSP cores in each cluster start to execute the bootloader from 0x0 of the ROM;

[0025] Module M3: Query the value of the load status register. If the value is "1", jump to module M6; otherwise, continue to wait for data transmission;

[0026] Module M4: Wait for the transfer request by querying the flag bit. When a valid flag bit is detected, start the DMA transfer to transfer the program data packet in the FLASH to the local main program memory;

[0027] Module M5: Generate a corresponding flag bit after the DMA transfer is completed, make the DSP core repeatedly query this flag bit, and when it is confirmed that the transfer is completed, set the value of the load status register to "1";

[0028] Module M6: Finally, execute a jump instruction to make the program jump to the starting address of the DSP and continue execution.

[0029] Preferably, the module M1 includes a design core startup sequence control logic, and after each core starts, the BIOS executes a self-check program.

[0030] Preferably, the startup address of each DSP core in the module M2 is set to the starting address of the ROM; the bootloader is stored in the firmware burned during chip manufacturing and is used to initialize the processor and load the main program.

[0031] Preferably, the load status register in the module M3 is a register in the system, and its value includes two states. "1" indicates that the loading has been completed, and the program directly jumps to the last step for execution; "0" indicates that the loading has not been completed, and the program continues to execute downward, waiting for data transmission; when reset, the value is also "0".

[0032] Preferably, after the DMA transfer is completed in the module M4, a hardware flag bit is set to notify the software.

[0033] Preferably, the DSP core continues to poll the hardware flag bit. If it detects that the transfer is completed, the load status register is updated.

[0034] Preferably, when the load status register is set to "1", the bootloader will execute a jump instruction to transfer the control right to the main program in the DSP, representing the end of the bootloader and the startup of the operating system or application program.

[0035] Preferably, a jump instruction is stored to handle external interrupt requests; this instruction directly transfers the control right to a specific address of the interrupt handler; the specific address includes the address pointed to when the bootloader executes its last jump instruction.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. The initialization of a heterogeneous multi-core processor should consider the startup sequence and initialization process of multiple cores simultaneously. The initialization method provided by the present invention can ensure the reliability and stability of the on-board heterogeneous multi-core processor, and ensure that the satellite can operate and execute tasks normally.

[0038] 2. The present invention considers that different cores may have different performance characteristics and power consumption requirements. By configuring and optimizing the parameters of each core during the initialization process, the relationship between performance and power consumption is balanced.

[0039] 3. The initialization method provided by the present invention takes into account the complex architecture and interconnection structure of heterogeneous multi-core processors. By configuring and optimizing aspects such as cache coherence protocols, memory management units, and bus controllers, it ensures efficient data exchange and collaborative computing between cores.

[0040] Other beneficial effects of the present invention will be elaborated in the specific implementation manners through the introduction of specific technical features and technical solutions. Those skilled in the art should be able to understand the beneficial technical effects brought by the said technical features and technical solutions through these introductions. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] By reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, other features, objectives, and advantages of the present invention will become more apparent:

[0042] Figure 1 It is a flowchart of an initialization method for a spaceborne heterogeneous multi-core processor of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The present invention will be described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that those of ordinary skill in the art can make several changes and improvements without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0044] Referring to Figure 1 as shown, an initialization method for a spaceborne heterogeneous multi-core processor includes:

[0045] Step S1: After the system is powered on or the main reset signal is triggered, all components will be reset to the initial state. The power management system ensures stable power supply, preparing for subsequent hardware and software initialization.

[0046] Design the core startup sequence control logic to ensure that critical cores start first. After each core starts, the BIOS executes a self-check program to ensure the integrity of hardware and software.

[0047] Step S2: The DSP cores in each cluster start to execute the boot program from 0x0 of the ROM. The startup address of each DSP core is set to the starting address of the ROM, which is 0x0. The boot program is usually included in the firmware burned during chip manufacturing and is used to initialize the processor and load the main program.

[0048] Step S3: Query the value of the load status register. A value of "1" indicates that the loading has been completed, and the program jumps directly to the last step for execution; a value of "0" indicates that the loading has not been completed, and the program continues to execute downward, waiting for data transmission (the load status register is a register in the system, and its reset value is "0").

[0049] Step S4: Wait for the transmission request in a polling manner. The bootloader repeatedly polls the flag bit. When a valid flag bit is detected, the DSP configures the DMA-related registers to start the DMA transmission, and transfers the program data packet from the FLASH to the local main program memory. After the DMA transmission is completed, a hardware flag bit is set to notify the software. The DSP core continues to poll this flag bit. Once it detects that the transmission is completed, it updates the load status register to ensure that the system knows that the bootloader has been loaded.

[0050] Step S5: After the transmission is completed, a corresponding flag bit is generated. The DSP core repeatedly polls this flag bit. When a valid flag bit is detected, it is determined that the loading is completed, and the value of the load status register is set to "1". Once the load status register is set to "1", the bootloader executes a jump instruction to transfer the control right to the main program in the DSP, representing the end of the bootloader and the start of the operating system or application program.

[0051] Step S6: The bootloader finally executes a jump instruction, and the program jumps to the starting point of the DSP to continue execution.

[0052] Specifically, for the handling of external interrupt requests, a jump instruction is stored. The function of this instruction is to directly transfer the control right to a specific address of the interrupt handler. And this address is actually the address pointed to when the bootloader executes its last jump instruction.

[0053] The initialization of the heterogeneous multi-core processor should consider the startup sequence and initialization process of multiple cores simultaneously. The initialization method provided by the present invention can ensure the reliability and stability of the on-board heterogeneous multi-core processor, and ensure that the satellite can operate and execute tasks normally.

[0054] The present invention also provides an on-board heterogeneous multi-core processor initialization system. The on-board heterogeneous multi-core processor initialization system can be implemented by executing the process steps of the on-board heterogeneous multi-core processor initialization method, that is, those skilled in the art can understand the on-board heterogeneous multi-core processor initialization method as the preferred implementation manner of the on-board heterogeneous multi-core processor initialization system.

[0055] An on-board heterogeneous multi-core processor initialization system includes:

[0056] Module M1: After the system is powered on or the main reset signal is triggered, reset all components to the initial state;

[0057] Module M2: Cause the DSP cores in each cluster to start executing the boot program from the 0x0 of the ROM;

[0058] Module M3: Query the value of the load status register. If the value is "1", jump to Module M6; otherwise, continue to wait for data transmission;

[0059] Module M4: Wait for a transmission request by querying the flag bit. When a valid flag bit is detected, start a DMA transmission to transfer the program data packet in the FLASH to the local main program memory;

[0060] Module M5: Generate a corresponding flag bit after the DMA transmission is completed, cause the DSP core to repeatedly query this flag bit, and when it is confirmed that the transmission is completed, set the value of the load status register to "1";

[0061] Module M6: Finally execute a jump instruction to cause the program to jump to the DSP starting address and continue execution.

[0062] The Module M1 includes a design core startup sequence control logic, and each core executes a self-check program by the BIOS after startup.

[0063] The startup address of each DSP core in the Module M2 is set to the starting address of the ROM; the boot program is stored in the firmware burned during chip manufacturing and is used to initialize the processor and load the main program.

[0064] The load status register in the Module M3 is a register in the system, and its value includes two states. "1" indicates that the loading has been completed and the program directly jumps to the last step for execution; "0" indicates that the loading has not been completed and the program continues to execute downward, waiting for data transmission; when reset, the value is also "0".

[0065] After the DMA transmission in the Module M4 is completed, set a hardware flag bit to notify the software.

[0066] Cause the DSP core to continue polling the hardware flag bit. If it detects that the transmission is completed, update the load status register.

[0067] When the load status register is set to "1", the boot program will execute a jump instruction to transfer the control right to the main program in the DSP, representing the end of the boot program and the startup of the operating system or application program.

[0068] Handle external interrupt requests by storing a jump instruction; this instruction directly transfers the control right to a specific address of the interrupt handler; the specific address includes the address pointed to when the boot program executes its last jump instruction.

[0069] Those skilled in the art know that, in addition to implementing the system and its various devices, modules, and units provided by the present invention in the form of pure computer-readable program code, the method steps can be logically programmed to enable the system and its various devices, modules, and units provided by the present invention to be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. to achieve the same functions. Therefore, the system and its various devices, modules, and units provided by the present invention can be regarded as a kind of hardware component, and the devices, modules, and units included therein for implementing various functions can also be regarded as the structures within the hardware component; the devices, modules, and units for implementing various functions can also be regarded as either software modules for implementing the method or structures within the hardware component.

[0070] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Without conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A method for initializing a spaceborne heterogeneous multi-core processor, characterized in that, including: Step S1: After the system powers on or the main reset signal is triggered, reset all components to their initial states; Step S2: Cause the DSP cores in each cluster to start executing the boot program from the 0x0 of the ROM; Step S3: Query the value of the load status register. If the value is "1", jump to Step S6; otherwise, continue to wait for data transmission; Step S4: Wait for a transmission request by querying the flag bit. When a valid flag bit is detected, start a DMA transfer to transfer the program data packet in the FLASH to the local main program memory; Step S5: Generate a corresponding flag bit after the DMA transfer is completed, cause the DSP core to repeatedly query this flag bit. When it is confirmed that the transfer is completed, set the value of the load status register to "1"; Step S6: Finally execute a jump instruction to make the program jump to the DSP starting address and continue execution.

2. The method for initializing a spaceborne heterogeneous multi-core processor according to claim 1, wherein The said Step S1 includes designing a core startup sequence control logic, and after each core starts, the BIOS executes a self-check program.

3. The on-board heterogeneous multi-core processor initialization method according to claim 1, wherein In the said Step S2, the startup address of each DSP core is set to the starting address of the ROM; the boot program is stored in the firmware burned during chip manufacturing and is used to initialize the processor and load the main program.

4. The on-board heterogeneous multi-core processor initialization method according to claim 1, characterized in that In the said Step S3, the load status register is a register in the system, and its value includes two states. "1" indicates that the loading has been completed and the program directly jumps to the last step for execution; "0" indicates that it has not been loaded and the program continues to execute downward, waiting for data transmission; when reset, the value is also "0".

5. The on-board heterogeneous multi-core processor initialization method according to claim 1, characterized in that, In the said Step S4, after the DMA transfer is completed, set a hardware flag bit to notify the software.

6. The on-orbit heterogeneous multi-core processor initialization method according to claim 5, characterized in that Cause the DSP core to continue polling the hardware flag bit. If it detects that the transfer is completed, update the load status register.

7. The method for initializing a spaceborne heterogeneous multi-core processor according to claim 1, characterized in that, When the load status register is set to "1", the boot program will execute a jump instruction to transfer the control right to the main program in the DSP, representing the end of the boot program and the startup of the operating system or application program.

8. The method for initializing a spaceborne heterogeneous multi-core processor according to claim 1, characterized in that, Handle external interrupt requests by storing a jump instruction; this instruction directly transfers the control right to a specific address of the interrupt handler; the said specific address includes the address pointed to when the boot program executes its last jump instruction.

9. A spaceborne heterogeneous multi-core processor initialization system, characterized in that including: Module M1: After the system powers on or the main reset signal is triggered, reset all components to their initial states; Module M2: Cause the DSP cores in each cluster to start executing the boot program from the 0x0 of the ROM; Module M3: Query the value of the load status register. If the value is "1", jump to Module M6; otherwise, continue to wait for data transmission; Module M4: Wait for a transmission request by querying the flag bit. When a valid flag bit is detected, start a DMA transfer to transfer the program data packet in the FLASH to the local main program memory; Module M5: Generate a corresponding flag bit after the DMA transfer is completed, cause the DSP core to repeatedly query this flag bit. When it is confirmed that the transfer is completed, set the value of the load status register to "1"; Module M6: Finally execute a jump instruction to make the program jump to the DSP starting address and continue execution.

10. The on-board heterogeneous multi-core processor initialization system according to claim 9, characterized in that, The said Module M1 includes designing a core startup sequence control logic, and after each core starts, the BIOS executes a self-check program.

Images