Signal direction identification circuit and method

Abstract

The present invention discloses a signal direction identification circuit and method, relating to the field of integrated circuit technology. The circuit comprises a first signal terminal, a second signal terminal, and a signal identification circuit. The signal identification circuit includes multiple switching transistors. When the first signal terminal is at a first level signal, the circuit identifies the action signals of the multiple switching transistors and determines the signal transmission direction based on the action signals of the multiple switching transistors. Thus, the signal direction identification circuit can solve the problems of the prior art in accurately locating the source of a deadlock and isolating a deadlocked device from the bus, resulting in the overall failure of the bus architecture's management function, thereby achieving the technical effect of accurately identifying signal direction.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a signal direction identification circuit and method. Background Art

[0002] Integrated circuits (ICs) play a vital role in modern electronic systems. As electronic devices continue to grow in complexity, multi-chip interconnect architectures are widely used in a variety of high-performance computing, communications, and embedded systems. These systems typically consist of multiple chips with distinct functions, interacting and working together through complex signal networks. To ensure efficient system operation, the reliability, accuracy, and fault tolerance of signal transmission become key design considerations.

[0003] In related technologies, in multi-chip interconnect circuit designs, signal transmission typically relies on changes in the electrical level between pins to transfer information. Specifically, the pins of different chips are interconnected using a wired-AND connection. When any chip pulls the signal low, the other chips can read the low-level state. However, when a deadlock occurs, this circuit design cannot accurately locate the source of the deadlock, nor can it isolate the dead device from the bus, resulting in the overall failure of the bus architecture's management function, which urgently needs to be addressed. Summary of the Invention

[0004] The present invention provides a signal direction identification circuit and method to at least solve the problem that the existing technology cannot accurately locate the source of the hang and cannot isolate the hung device from the bus, resulting in the overall failure of the management function of the bus architecture, and achieve the technical effect of accurately identifying the signal direction.

[0005] The present invention provides a signal direction identification circuit, comprising: a first signal terminal, a second signal terminal and a signal identification circuit, wherein:

[0006] The signal identification circuit includes multiple switching tubes. When the first signal end is at a first level signal, the signal identification circuit identifies the action signals of the multiple switching tubes and determines the signal transmission direction based on the action signals of the multiple switching tubes.

[0007] The present invention provides a signal direction identification method, which uses the above-mentioned signal direction identification circuit, wherein the method includes the following steps:

[0008] When the first signal end is at a first level signal, identifying the action signals of the plurality of switch tubes;

[0009] The signal transmission direction is determined according to the action signals of the multiple switch tubes.

[0010] The present invention, when the first signal terminal is at a first level, can identify the action signals of multiple switch transistors in the signal identification circuit and determine the signal transmission direction based on the action signals of the multiple switch transistors. Thus, this signal direction identification circuit can solve the problems of the prior art in being unable to accurately locate the source of a deadlock and isolating a deadlocked device from the bus, resulting in the overall failure of the bus architecture's management function, thereby achieving the technical effect of accurately identifying signal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 A schematic structural diagram of a signal direction identification circuit provided by an embodiment of the present invention;

[0013] Figure 2 A schematic diagram of a “wired-AND” connection method between different chips in the related art;

[0014] Figure 3 A schematic diagram of a bus deadlock determination circuit provided by an embodiment of the present invention;

[0015] Figure 4 A schematic diagram of a signal transmission process provided by an embodiment of the present invention;

[0016] Figure 5 A schematic diagram of another signal transmission process provided by an embodiment of the present invention;

[0017] Figure 6 This is a flowchart of a signal direction identification method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0019] It should be noted that, in the description of the present invention, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. The terms "first," "second," etc., in the present invention are used to distinguish similar objects, and are not used to describe a particular order or precedence.

[0020] In order to enable those skilled in the art to better understand the solutions of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0021] An embodiment of the present invention provides a signal direction identification circuit. The circuit is described in detail in conjunction with the structure of the signal direction identification circuit.

[0022] Figure 1 It is a structural diagram of a signal direction identification circuit according to an embodiment of the present invention.

[0023] Before introducing the signal direction identification circuit according to the embodiment of the present invention, the relevant technical background is first introduced.

[0024] In complex electronic circuit designs, multiple chips are used because a single chip often cannot perform all functions. Each chip has many pins, and the pins of different chips can be interconnected. Communication between chips is achieved through changes in the electrical levels on these pins. For example, when a chip pin changes from a low state to a high state, this may indicate a "start" signal; while changing from a high state to a low state may indicate an "end" signal.

[0025] In the related art, the connection between the communication pins can be simplified as follows: Figure 2 As shown in the figure, the pins of multiple chips (IC_0 through IC_3) are connected together using a wired-AND circuit. When any chip pulls the signal low, the other chips can only read the low-level signal. (In other words, the wired-AND circuit connection method refers to multiple pins sharing the same signal line. If one pin pulls the signal low, the signal on the entire line will become low.) The pull-up resistor (R_up) is used to maintain the high level when the signal line is silent and enhance the driving capability of the GPIO (General Purpose Input / Output). The string resistor (R_string1 through R_string3) can be used to optimize signal quality. Its resistance value usually ranges from 0 ohms to tens of ohms.

[0026] However, a common problem in bus systems using wired-AND connectivity is that if any chip in the system fails and causes the bus to drop to a low level, the entire bus system becomes hung, and other chips on the bus are unable to communicate effectively (because the low bus level prevents any data transmission). As a result, management functions based on the bus become completely ineffective, seriously affecting the normal operation of the entire system.

[0027] Furthermore, when troubleshooting bus hangs, a common diagnostic approach is to disconnect each chip on the bus one by one to see if the bus voltage returns to a normal high level. However, in some cases, when two connected chips are disconnected, they can each resume normal operation, making it difficult to determine the source of the problem.

[0028] Precisely to address the aforementioned issues, embodiments of the present invention propose a signal direction identification circuit. When a first signal terminal is at a first level, the circuit can identify the actuation signals of multiple switching transistors within the circuit and determine the signal transmission direction based on the actuation signals of the multiple switching transistors. This circuit thus addresses the existing issues of being unable to accurately locate the source of a deadlock and isolating a deadlocked device from the bus, resulting in the overall failure of the bus architecture's management functions. This circuit achieves the technical effect of accurately identifying signal direction.

[0029] For example, Figure 1 As shown, the signal direction identification circuit 10 includes: a first signal terminal 100, a second signal terminal 200 and a signal identification circuit, wherein the signal identification circuit includes multiple switching tubes. When the first signal terminal 100 is in a first level signal, the action signals of the multiple switching tubes are identified, and the signal transmission direction is determined based on the action signals of the multiple switching tubes.

[0030] Specifically, if Figure 1 As shown, the signal direction identification circuit 10 of the embodiment of the present invention mainly includes a first signal terminal 100, a second signal terminal 200 and a signal identification circuit. Figure 1 IC1_PIN) is an input terminal of the signal direction identification circuit 10, which is usually connected to a pin of a chip (such as IC1) for receiving or sending signals; the second signal terminal 200 (such as Figure 1 IC2_PIN (shown) is another input terminal of signal direction identification circuit 10. It is typically connected to a pin of another chip (such as IC2) and is also used to receive or transmit signals. The signal identification circuit, as the core of signal direction identification circuit 10, contains multiple switches to control the direction of signal transmission.

[0031] In the embodiments of the present invention, the first-level signal may be a low level (Low). That is, the signal direction identification circuit 10 is primarily used to determine the transmission direction of the low-level signal. Specifically, when the first signal terminal 100 is in a low-level state, the signal identification circuit can identify and analyze the signal transmission path based on the states of multiple switching transistors, thereby determining the signal transmission direction. Specifically, it determines whether the signal is transmitted from the first signal terminal 100 to the second signal terminal 200, or from the second signal terminal 200 to the first signal terminal 100.

[0032] Optionally, the signal recognition circuit further includes: a first resistor R1, a second resistor R2, a first display element LED1, and a second display element LED2, wherein one end of the first resistor R1 is connected to the power access node; a plurality of switch tubes including first to fourth switch tubes Q1 to Q4, wherein the source (S) of the first switch tube Q1 is electrically connected to the first signal terminal 100 and the drain (D) of the third switch tube Q3, respectively, and the drain (D) of the first switch tube Q1 is electrically connected to the other end of the first resistor R1, one end of the first display element LED1, The gate electrode (G) of the third switch tube Q3 is electrically connected to the other end of the second indicator element LED2; the gate electrode (G) of the second switch tube Q2 is electrically connected to the other end of the first indicator element LED1, one end of the second indicator element LED2, the source electrode (S) of the third switch tube Q3, one end of the second resistor R2, and the drain electrode (D) of the fourth switch tube Q4; the drain electrode (D) of the second switch tube Q2 is electrically connected to the second signal terminal 200 and the source electrode (S) of the fourth switch tube Q4; the other end of the second resistor R2 is connected to the power access node.

[0033] Specifically, if Figure 1 As shown, multiple switching transistors are composed of first to fourth switching transistors Q1-Q4. These switching transistors are core components of the signal transmission path and are used to control the flow of signals. By controlling the conduction and shutdown of these switching transistors, the signal can be transmitted from one signal terminal to another. Resistors play a role in current limiting and voltage dividing in circuits. In this embodiment of the present invention, the first resistor R1 and the second resistor R2 can limit the current of the first indicator LED1 and the second indicator LED2 to prevent damage due to excessive current. In some cases, the voltage divider can also ensure the correctness of the signal transmission path. The first indicator LED1 and the second indicator LED2 are used to indicate the direction and status of signal transmission.

[0034] Therefore, through the combination of the switch tube and the display, the circuit can clearly indicate the signal transmission direction, which is very helpful for debugging and troubleshooting. Resistors R1 and R2 play the role of current limiting and voltage dividing in the circuit. By properly selecting the resistance value, it can ensure that the display is not damaged by excessive current during normal operation. At the same time, it can also optimize the voltage distribution of the signal transmission path and ensure stable signal transmission.

[0035] Optionally, in some embodiments, the first display element LED1 and the second display element LED2 are both light emitting diodes.

[0036] That is, in the embodiments of the present invention, LEDs can be used as display elements, and the state changes of the first display element LED1 and the second display element LED2 can intuitively indicate the direction of signal transmission and the location of the fault. For example, when a signal is transmitted from the first signal terminal 100 to the second signal terminal 200, the second display element LED2 may light up, indicating that the signal is being transmitted to the second signal terminal 200; when a signal is transmitted from the second signal terminal 200 to the first signal terminal 100, the first display element LED1 may light up, indicating that the signal is being transmitted to the first signal terminal 100. If the bus is hung and the second display element LED2 is lit, it means that the first signal terminal 100 may remain in a low-level state for a long time, causing the bus to hang, that is, the first signal terminal 100 is the source of the fault; similarly, if the bus is hung and the first display element LED1 is lit, it means that the second signal terminal 200 may remain in a low-level state for a long time, causing the bus to hang, that is, the second signal terminal 200 is the source of the fault. If both the first indicator LED1 and the second indicator LED2 are off, it means that the signal transmission path is not activated. This can be caused by the following two situations: (1) Both signal terminals are not in a low-level signal state. In this case, the bus may be in a normal state, and the deadlock problem may be caused by other reasons (such as power supply problems, connection problems, etc.); (2) Both signal terminals are faulty, resulting in the inability to transmit signals normally, which may also cause the bus to be deadlocked. In this case, further check whether the power supply and connection are normal.

[0037] It should be noted that theoretically, the situation where both the first indicator LED1 and the second indicator LED2 are illuminated will not occur. This is because signal transmission is unidirectional and the first and second indicator LED1 and LED2 will not illuminate simultaneously. If this situation occurs, it may be due to a circuit failure or signal conflict. In this case, further inspection should be carried out to ensure that the circuit connection is correct and there is no short circuit or misconnection. You can also check the signal terminal voltage level to confirm whether there is any abnormal signal.

[0038] Therefore, in the event of a bus hang (a certain signal terminal (such as the first signal terminal 100 or the second signal terminal 200) remains in a low level state for a long time), the source of the fault can be quickly located by observing the status of the LED without having to disconnect devices one by one for investigation, which greatly saves time and effort.

[0039] Optionally, in some embodiments, the first to fourth switch transistors Q1 - Q4 are all NMOS (N-Metal-Oxide-Semiconductor Field-Effect Transistor) transistors.

[0040] That is, the first through fourth switching transistors Q1-Q4, serving as control elements in the signal transmission path, can be NMOS transistors. The on and off states of the NMOS transistors are controlled by their gate voltage. When the difference between the gate voltage and the source voltage is greater than a threshold voltage, the NMOS transistor is on; otherwise, the NMOS transistor is off. Thus, by employing a unidirectional NMOS circuit design, signals from different sources can be effectively distinguished, thereby ensuring the correct direction of signal transmission.

[0041] Optionally, in some embodiments, the signal direction identification circuit 10 further includes: a third resistor R3, wherein the third resistor R3 is arranged between the drain (D) of the first switch tube Q1 and the first connection node, wherein the first connection node is a connection node formed when the drain (D) of the first switch tube Q1, the other end of the first resistor R1, one end of the first indicator LED1, the gate (G) of the third switch tube Q3, the other end of the second indicator LED2 and the source (S) of the second switch tube Q2 are electrically connected.

[0042] Specifically, if Figure 1 As shown, the signal direction identification circuit 10 further includes a third resistor R3, which is arranged between the drain (D) of the first switch tube Q1 and the first connection node (such as Figure 1 The first connection node is connected to the first signal terminal 100 (point M shown in the figure), forming a voltage divider network with the first resistor R1 to prevent signal transmission problems caused by excessively high or low voltages. The presence of the third resistor R3 also limits the current, ensuring stable signal transmission. When transmitting a signal from the first signal terminal 100 to the second signal terminal 200, the first switch Q1 is turned on, and the low-level signal can be transmitted to the first connection node through the first switch Q1.

[0043] It can be seen that the introduction of the third resistor R3 can optimize the signal transmission path, prevent signal conflicts, protect circuit components, and improve the stability and reliability of the circuit.

[0044] Optionally, in some embodiments, the signal direction identification circuit 10 further includes: a fourth resistor R4, wherein the fourth resistor R4 is arranged between the drain (D) of the fourth switch tube Q4 and the second connection node, wherein the second connection node is a connection node formed when the gate (G) of the second switch tube Q2, the other end of the first indicator LED1, one end of the second indicator LED2, the source (S) of the third switch tube Q3, one end of the second resistor R2 and the drain (D) of the fourth switch tube Q4 are electrically connected.

[0045] Specifically, if Figure 1 As shown, the signal direction identification circuit 10 further includes a fourth resistor R4, which is arranged between the drain (D) of the fourth switch tube Q4 and the second connection node (such as Figure 1 Similar to the third resistor R3, the fourth resistor R4 is also introduced to optimize circuit performance. It forms a voltage divider network with the second resistor R2 to prevent signal transmission issues caused by excessively high or low voltages. The presence of the fourth resistor R4 also limits current, ensuring stable signal transmission. When transmitting a signal from the second signal terminal 200 to the first signal terminal 100, the fourth switch Q4 is turned on, allowing the low-level signal to be transmitted to the second connection node through the fourth switch Q4.

[0046] It can be seen that the introduction of the fourth resistor R4 can also optimize the signal transmission path, prevent signal conflicts, protect circuit components, and improve the stability and reliability of the circuit.

[0047] Optionally, in some embodiments, the signal direction identification circuit 10 further includes: a hang judgment circuit, which is used to send a first isolation signal when the first signal terminal 100 is a bus hang source terminal, so as to isolate the first signal terminal 100 through the first isolation signal; or, when the second signal terminal 200 is a bus hang source terminal, send a second isolation signal to isolate the second signal terminal 200 through the second isolation signal.

[0048] Specifically, to detect whether a bus is hung and identify the source of the bus hang (i.e., the source of the fault), the hang detection circuit is a key component of the signal direction identification circuit 10. In this embodiment of the present invention, the hang detection circuit can determine whether the bus hang is caused by the first signal terminal 100 or the second signal terminal 200 and take appropriate isolation measures. Specifically, the hang detection circuit can determine whether a bus hang has occurred by monitoring the level and duration of the signal terminals. For example, if a signal terminal remains in a low level state for a long period of time (exceeding a preset threshold), the signal terminal is considered the source of the bus hang. When the first signal terminal 100 is detected as the source of the bus hang, the hang detection circuit can issue a first isolation signal, which isolates the first signal terminal 100 from the bus and prevents it from further affecting the bus status. Similarly, when the second signal terminal 200 is detected as the source of the bus hang, the hang detection circuit can issue a second isolation signal, which isolates the second signal terminal 200 from the bus and prevents it from further affecting the bus status.

[0049] The deadlock detection circuit can thus quickly identify the signal end causing the bus deadlock, eliminating the need to disconnect each device individually for troubleshooting, significantly saving time and effort. Furthermore, by isolating the faulty signal end, the faulty device can be prevented from affecting the normal operation of the entire bus, avoiding bus paralysis and improving system reliability and stability.

[0050] Optionally, in some embodiments, the bus hang-up judgment circuit includes: a first judgment unit and a second judgment unit, wherein the first judgment unit is connected to the source (S) of the first switch tube Q1, and is used to send a first isolation signal when the first signal terminal 100 is a bus hang-up source terminal, so as to isolate the first signal terminal 100 through the first isolation signal; the second judgment unit is connected to the source (S) of the fourth switch tube Q4, and is used to send a second isolation signal when the second signal terminal 200 is a bus hang-up source terminal, so as to isolate the second signal terminal 200 through the second isolation signal.

[0051] It will be appreciated that both the first and second isolation signals can isolate the faulty signal terminal from the bus by controlling the on / off state of at least one of the multiple switches. For example, if the first signal terminal 100 is a bus deadlock source, the first isolation signal can shut down the switch associated with the first signal terminal 100 (e.g., the first switch Q1), thereby severing its connection to the bus. Similarly, if the second signal terminal 200 is a bus deadlock source, the second isolation signal can shut down the switch associated with the second signal terminal 200 (e.g., the fourth switch Q4), thereby severing its connection to the bus.

[0052] Therefore, by isolating the fault source, even if a signal end fails, the system can still continue to operate normally, and the failure of a single device will not cause the entire system to fail, thereby enhancing the system's fault tolerance.

[0053] Optionally, in some embodiments, the first judgment unit includes: a first OR gate circuit and a first watchdog unit circuit, wherein the first input end of the first OR gate circuit is electrically connected to the first signal end 100, and the output end of the first OR gate circuit is connected to the gate (G) of the first switch tube Q1; the input end of the first watchdog unit circuit is electrically connected to the first signal end 100, and the output end of the first watchdog unit circuit is electrically connected to the second input end of the first OR gate circuit.

[0054] It should be noted that the deadlock detection circuit (including the first and second detection units) in this embodiment of the present invention primarily implements a low-level timeout disconnection function (i.e., isolating the fault source) through a watchdog circuit and a logical OR gate circuit. The watchdog timer (WDT) chip implements this function through a timer. Under normal circumstances, the user program needs to periodically send a signal (called "feeding the watchdog") to the watchdog chip input pin through level changes (high-low switching) to reset the timer. If the system fails to "feed the watchdog" on time for some reason, the timer will time out, and the watchdog chip will trigger a preset action (such as outputting a low-level signal or restarting the system).

[0055] That is, the watchdog chip input pin "feeds the dog" by periodically changing the level (high and low level switching) so that its output pin can maintain a high level state. However, when the watchdog chip input pin does not receive a level change for a long time, the watchdog chip output pin will become a low level state, thereby triggering a system reset or other exception handling operations.

[0056] A logic OR gate is a multi-input, single-output logic gate. Its output is high only when at least one input is high. If all inputs are low, the output is low. The input pins of a logic OR gate are the ports through which the logic gate receives signals and transmits input data. An OR gate typically has two or more input pins. The output pin of a logic OR gate is the port through which the logic gate outputs the processed signal. In an OR gate, the state of the output pin depends on the logical state of the input pins.

[0057] Specifically, if Figure 3As shown in (a), the first judgment unit includes a first OR gate circuit and a first watchdog unit circuit. The first input terminal of the first OR gate circuit is electrically connected to the first signal terminal 100 and can receive the signal from the first signal terminal 100. The second input terminal of the first OR gate circuit is electrically connected to the output terminal of the first watchdog unit circuit and can receive the output signal of the first watchdog unit circuit. The output terminal of the first OR gate circuit is connected to the gate (G) of the first switch tube Q1 and can control the conduction and shutdown of the first switch tube Q1 by controlling the gate (G) voltage of the first switch tube Q1. The input terminal of the first watchdog unit circuit is electrically connected to the first signal terminal 100 and can monitor the level status of the first signal terminal 100 (whether it remains at a low level for a long time, that is, whether it is hung). The output terminal of the first watchdog unit circuit is electrically connected to the second input terminal of the first OR gate circuit and can provide a status signal to the first OR gate circuit.

[0058] For example, if the first signal terminal 100 normally sends a low-level signal, the first input terminal of the first OR gate circuit can receive the low-level signal. At this time, the first watchdog unit circuit will not detect the deadlock state (because the low-level signal of the first signal terminal 100 is normal and short-lived). Then the first watchdog unit circuit can output a high-level signal to the second input terminal of the first OR gate circuit. The output terminal of the first OR gate circuit can be high, so that the first switch tube Q1 is turned on, and the signal can be transmitted from the first signal terminal 100 to the subsequent circuit.

[0059] If the first signal terminal 100 remains low for a long time (a "hang-up state"), the first watchdog unit circuit detects this abnormal hang-up state and outputs a low-level signal to the second input terminal of the first OR gate circuit. Because both input terminals of the first OR gate circuit are low, its output terminal is also low, causing the first switch Q1 to turn off, isolating the first signal terminal 100 from affecting the bus state and preventing a bus hang-up.

[0060] If the first signal terminal 100 is restored to a high level, the first signal terminal 100 can be reconnected to the bus by turning on the first switch tube Q1.

[0061] Therefore, by cooperating with the first OR gate circuit, the first watchdog unit circuit can trigger an isolation mechanism, thereby preventing a faulty device from affecting the normal operation of the entire bus, thereby improving the reliability and stability of the system.

[0062] Optionally, in some other embodiments, the second judgment unit includes: a second OR gate circuit and a second watchdog unit circuit, wherein the first input end of the second OR gate circuit is electrically connected to the second signal end 200, and the output end of the second OR gate circuit is connected to the gate (G) of the fourth switch tube Q4; the input end of the second watchdog unit circuit is electrically connected to the second signal end 200, and the output end of the second watchdog unit circuit is electrically connected to the second input end of the second OR gate circuit.

[0063] Specifically, if Figure 3 As shown in (b), the second judgment unit includes a second OR gate circuit and a second watchdog unit circuit. The first input terminal of the second OR gate circuit is electrically connected to the second signal terminal 200 and can receive the signal from the second signal terminal 200. The second input terminal of the second OR gate circuit is electrically connected to the output terminal of the second watchdog unit circuit and can receive the output signal of the second watchdog unit circuit. The output terminal of the second OR gate circuit is connected to the gate (G) of the fourth switch tube Q4 and can control the conduction and shutdown of the fourth switch tube Q4 by controlling the gate (G) voltage of the fourth switch tube Q4. The input terminal of the second watchdog unit circuit is electrically connected to the second signal terminal 200 and can monitor the level status of the second signal terminal 200 (whether it remains at a low level for a long time, that is, whether it is hung). The output terminal of the second watchdog unit circuit is electrically connected to the second input terminal of the second OR gate circuit and can provide a status signal to the second OR gate circuit.

[0064] For example, if the second signal terminal 200 normally sends a low-level signal, the first input terminal of the second OR gate circuit can receive the low-level signal. At this time, the second watchdog unit circuit will not detect the deadlock state (because the low-level signal of the second signal terminal 200 is normal and short-lived). Then the second watchdog unit circuit can output a high-level signal to the second input terminal of the second OR gate circuit. The output terminal of the second OR gate circuit can be high, so that the fourth switch tube Q4 is turned on, and the signal can be transmitted from the second signal terminal 200 to the subsequent circuit.

[0065] If the second signal terminal 200 remains low for a long period (a "hang-up state"), the second watchdog circuit detects this abnormal hang-up state and outputs a low-level signal to the second input terminal of the second OR gate circuit. Because both input terminals of the second OR gate circuit are low, its output terminal is also low, turning off the fourth switch Q4. This isolates the second signal terminal 200 from affecting the bus state and prevents a bus hang-up.

[0066] If the second signal terminal 200 returns to a high level, the second signal terminal 200 can be reconnected to the bus by turning on the fourth switch Q4.

[0067] Therefore, by cooperating with the second OR gate circuit, the second watchdog unit circuit can trigger the isolation mechanism, thereby preventing the faulty device from affecting the normal operation of the entire bus, thereby improving the reliability and stability of the system.

[0068] Optionally, in some embodiments, the first signal terminal 100, the second signal terminal 200, the control terminals of the plurality of switch tubes, the first connection node and the second connection node are all second level signals, wherein the second level signal is an opposite signal to the first level signal.

[0069] Optionally, in some embodiments, the level of the first level signal is lower than the level of the second level signal.

[0070] In the embodiments of the present invention, the second-level signal is the opposite of the first-level signal and is a high level. When the signal direction identification circuit 10 is in the "idle" state, key nodes within the circuit, such as the first signal terminal 100, the second signal terminal 200, the control terminals of the multiple switching transistors, and the first and second connection nodes, all display the second-level signal (i.e., a high level). At this point, the first through fourth switching transistors Q1-Q4 are all in the off state.

[0071] It should be noted that the condition for the switch tube to turn on is that the voltage difference between its gate (G) and source (S) is greater than a certain threshold voltage. That is to say, the switch tube will only turn on when this voltage difference is large enough.

[0072] Therefore, by using a high level as the default state, the circuit can be ensured to be in a stable state when idle, avoiding unnecessary signal interference; and turning off all switching tubes in the idle state can prevent fault signals from propagating between different paths, thereby improving the reliability of the circuit.

[0073] To facilitate those skilled in the art to further understand the working process of the signal direction identification circuit of the embodiment of the present application, the following is a Figure 4 and Figure 5 For further explanation.

[0074] like Figure 4 As shown, when the signal direction identification circuit is in a non-working (idle) state, the first signal terminal (IC1_PIN), the second signal terminal (IC2_PIN), the control terminals (PIN1, PIN2) of the multiple switch tubes, the first connection node (M) and the second connection node (N) are all high levels, and the first to fourth switch tubes Q1~Q4 are all in the off state.

[0075] When IC1 initiates communication, it will actively pull its own signal terminal (the first signal terminal (IC1_PIN)) from a high level to a low level.

[0076] If the low level at the first signal terminal (IC1_PIN) does not exceed a specific duration (no fault), the source (S) of the first switch Q1 connected to the first signal terminal (IC1_PIN) will also be low due to the low level at the first signal terminal (IC1_PIN). At this time, the gate (G) level of the first switch Q1 is determined by other control signals. If the gate (G) level is high enough so that the voltage difference between the gate (G) and the source (S) is greater than the threshold voltage, the first switch Q1 will be turned on.

[0077] After the first switch tube Q1 is turned on, the low-level signal is transmitted to the first connection node M through the first switch tube Q1. At this time, the level of the first connection node (M) becomes a low level.

[0078] Since the level of the first connection node (M) becomes low, the gate (G) level of the third switch tube Q3 connected to the first connection node (M) becomes low. For the switch tube, the low-level gate (G) voltage is not sufficient to turn on the third switch tube Q3, so the third switch tube Q3 remains in the off state.

[0079] When the third switch Q3 turns off, the voltage level at one end of the second indicator LED2, connected to the first connection node (M), becomes low, causing the second indicator LED2 to turn on and illuminate. This indicates that the signal is being transmitted from the first signal terminal (IC1_PIN) to the second signal terminal (IC2_PIN). At the same time, the gate (G) voltage level of the second switch Q2 is determined by other control signals. If the gate (G) voltage level is high enough, the second switch Q2 turns on, and the low-level signal is transmitted through the second switch Q2 to the second signal terminal (IC2_PIN).

[0080] The low-level signal is transmitted to the second signal terminal (IC2_PIN) through the second switch tube Q2, thereby completing the signal transmission from the first signal terminal (IC1_PIN) to the second signal terminal (IC2_PIN).

[0081] When the low level of the first signal terminal (IC1_PIN) lasts longer than a specific time, the deadlock detection circuit detects this and determines that the first signal terminal (IC1_PIN) is in the deadlock state. At this time, the deadlock detection circuit can send an isolation signal to set the switch control terminal (PIN1) related to the first signal terminal (IC1_PIN) to a low level. At this time, the gate (G) level of the first switch tube Q1 becomes a low level, so that the first switch tube Q1 remains in the off state.

[0082] Because the first switch Q1 is turned off, the first signal terminal (IC1_PIN) can no longer transmit signals to the first connection node (M) through the first switch Q1 (the first connection node (M) remains high, and the second signal terminal (IC2_PIN) is also high). Therefore, it can no longer affect the bus state. This isolates the first signal terminal (IC1_PIN), preventing it from being in a low state for a long time and causing a bus hang.

[0083] It should be noted that during signal transmission from the first signal terminal (IC1_PIN) to the second signal terminal (IC2_PIN), when the second signal terminal (IC2_PIN) reaches a low level, the fourth switch Q4 turns on. Theoretically, this causes the second connection node (N) to reach a low level, thereby turning off the second switch Q2 and disconnecting the transmission path from the first signal terminal (IC1_PIN) to the second signal terminal (IC2_PIN). However, the first signal terminal (IC1_PIN) pulls down the second connection node (N) via the first switch Q1 + third resistor R3 + second switch Q2 + fourth switch Q4, resulting in a weak driving capability. By adding the fourth resistor R4, the voltage distribution at the second connection node (N) can be maintained, allowing the second connection node (N) to still achieve a high level through voltage division. Therefore, the presence of the fourth resistor R4 allows the second signal terminal (IC2_PIN) to directly drive the second connection node (N) to a low level, but the first signal terminal (IC1_PIN) cannot drive the second connection node (N) to a low level. This is because the fourth resistor R4 limits the current through the fourth switch Q4, preventing the voltage of the second connection node (N) from being pulled down by the low level of the first signal terminal (IC1_PIN).

[0084] Similarly, the third resistor R3 is also provided to ensure the voltage distribution of the first connection node (M) to achieve the same effect.

[0085] like Figure 5 As shown, when the signal direction identification circuit is in a non-working (idle) state, the first signal terminal (IC1_PIN), the second signal terminal (IC2_PIN), the control terminals (PIN1, PIN2) of the multiple switch tubes, the first connection node (M) and the second connection node (N) are all high levels, and the first to fourth switch tubes Q1~Q4 are all in the off state.

[0086] When IC2 initiates communication, it will actively pull its own signal end (the second signal end (IC2_PIN)) from a high level to a low level.

[0087] If the low level at the second signal terminal (IC2_PIN) does not exceed a specified duration (no fault), the source (S) of the fourth switch Q4 connected to the second signal terminal (IC2_PIN) will also be low due to the low level at the second signal terminal (IC2_PIN). At this time, the gate (G) level of the fourth switch Q4 is determined by other control signals. If the gate (G) level is high enough so that the voltage difference between the gate (G) and the source (S) is greater than the threshold voltage, the fourth switch Q4 will be turned on.

[0088] After the fourth switch tube Q4 is turned on, the low-level signal is transmitted to the second connection node N through the fourth switch tube Q4. At this time, the level of the second connection node (N) becomes a low level.

[0089] Since the level of the second connection node (N) becomes low, the gate (G) level of the second switch tube Q2 connected to the second connection node (N) becomes low. For the switch tube, the low-level gate (G) voltage is not sufficient to turn on the second switch tube Q2, so the second switch tube Q2 remains in the off state.

[0090] When the second switch Q2 turns off, the voltage level at one end of the first indicator LED1 connected to the second connection node (N) goes low, causing the first indicator LED1 to turn on and illuminate. This indicates that the signal is being transmitted from the second signal terminal (IC2_PIN) to the first signal terminal (IC1_PIN). Simultaneously, the gate (G) voltage level of the third switch Q3 is determined by other control signals. If the gate (G) voltage level is high enough, the third switch Q3 turns on, and the low-level signal is transmitted through the third switch Q3 to the first signal terminal (IC1_PIN).

[0091] The low-level signal is transmitted to the first signal terminal (IC1_PIN) through the third switch tube Q3, thereby completing the signal transmission from the second signal terminal (IC2_PIN) to the first signal terminal (IC1_PIN).

[0092] If the low level of the second signal terminal (IC2_PIN) lasts longer than a specific time, the deadlock detection circuit will detect this and determine that the second signal terminal (IC2_PIN) is in the deadlock state. At this time, the deadlock detection circuit can send an isolation signal to set the switch control terminal (PIN2) associated with the second signal terminal (IC2_PIN) to a low level. At this time, the gate (G) level of the fourth switch tube Q4 becomes a low level, so that the fourth switch tube Q4 remains in the off state.

[0093] Because the fourth switch Q4 is off, the second signal terminal (IC2_PIN) can no longer transmit signals to the second connection node (N) through the fourth switch Q4 (the second connection node (N) remains high, and the first signal terminal (IC1_PIN) is also high). Therefore, it can no longer affect the bus state. This isolates the second signal terminal (IC2_PIN), preventing it from being in a low state for a long time and causing a bus hang.

[0094] The signal direction identification circuit proposed in an embodiment of the present invention can identify the action signals of multiple switch transistors in the signal identification circuit when the first signal terminal is at a first level signal, and determine the signal transmission direction based on the action signals of the multiple switch transistors. Therefore, this signal direction identification circuit can solve the problems of the existing technology that cannot accurately locate the source of the deadlock and cannot isolate the deadlocked device from the bus, resulting in the overall failure of the bus architecture's management function, and achieve the technical effect of accurately identifying signal direction.

[0095] Through the description of the above implementation methods, those skilled in the art can clearly understand that the circuit according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0096] The embodiments of the present application also provide a signal direction identification method.

[0097] Figure 6 This is a flowchart of a signal direction identification method according to an embodiment of the present application.

[0098] like Figure 6 As shown, the signal direction recognition method adopts Figure 1 The signal direction identification circuit of the embodiment, wherein the method comprises the following steps:

[0099] In step 601, when a first signal terminal is at a first level signal, action signals of a plurality of switch tubes are identified.

[0100] In step 602, the signal transmission direction is determined according to the action signals of the plurality of switch tubes.

[0101] Specifically, when the first signal terminal is at a first level (low), the signal transmission path can be determined by identifying the action signals of multiple switches (i.e., the on and off states of the switches). For example, the signal starts from the first signal terminal, passes through the on switches, and finally reaches the second signal terminal.

[0102] Optionally, in some embodiments, the signal transmission direction is determined based on the action signals of multiple switching tubes, including: identifying the switching tubes in the on state among the multiple switching tubes; taking the first signal end as the starting point and the second signal end as the end point, and taking the path formed by the switching tubes in the on state as the signal transmission direction.

[0103] That is, during signal transmission, the gate (G) and source (S) voltages of each switch are detected to determine whether it is conducting. For example, with the first signal terminal as the starting point and the second signal terminal as the end point, the signal can be traced from the starting point to the end point by following the path formed by the conducting switches.

[0104] Optionally, in some embodiments, the above-mentioned signal direction identification method further includes: obtaining the duration of time that the first signal end is in the first level signal; when the duration is greater than a preset duration, sending a first isolation signal through the deadlock judgment circuit to isolate the first signal end.

[0105] Specifically, by recording the duration of a first signal terminal maintaining a first level signal, if the first signal terminal maintains a low level for longer than a preset duration, the deadlock detection circuit will determine that the signal terminal is in a deadlock state. Subsequently, the deadlock detection circuit will issue an isolation signal (e.g., a first isolation signal) to isolate the first signal terminal from the bus, thereby preventing the bus from being deadlocked.

[0106] The signal direction identification method proposed in an embodiment of the present invention, through a signal direction identification circuit, can solve the problem that the existing technology is unable to accurately locate the source of the hang and is unable to isolate the hung device from the bus, resulting in the overall failure of the management function of the bus architecture, thereby achieving the technical effect of accurately identifying the signal direction.

[0107] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0108] The above is a detailed introduction to a signal direction identification circuit provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only intended to help understand the method and core concept of the present invention. It should be noted that, for those skilled in the art, various improvements and modifications may be made to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A signal direction identification circuit, characterized in that: include: A first signal terminal, a second signal terminal, a signal recognition circuit, first to fourth resistors and first to second display elements, wherein: The signal identification circuit includes a plurality of switch tubes, and when the first signal end is at a first level signal, identifies the action signals of the plurality of switch tubes, and determines the signal transmission direction based on the action signals of the plurality of switch tubes; One end of the first resistor is connected to a power access node, and the multiple switching transistors include first to fourth switching transistors, wherein the source of the first switching transistor is electrically connected to the first signal terminal and the drain of the third switching transistor, respectively; the drain of the first switching transistor is electrically connected to the other end of the first resistor, one end of the first display element, the gate of the third switching transistor, and the other end of the second display element, respectively; the gate of the second switching transistor is electrically connected to the other end of the first display element, one end of the second display element, the source of the third switching transistor, one end of the second resistor, and the drain of the fourth switching transistor, respectively; the drain of the second switching transistor is electrically connected to the second signal terminal and the source of the fourth switching transistor, respectively; and the other end of the second resistor is connected to the power access node; The third resistor is provided between the drain of the first switching transistor and a first connection node, wherein the first connection node is a connection node formed when the drain of the first switching transistor, the other end of the first resistor, one end of the first indicator, the gate of the third switching transistor, the other end of the second indicator, and the source of the second switching transistor are electrically connected; The fourth resistor is arranged between the drain of the fourth switching tube and a second connection node, wherein the second connection node is a connection node formed when the gate of the second switching tube, the other end of the first display element, one end of the second display element, the source of the third switching tube, one end of the second resistor and the drain of the fourth switching tube are electrically connected.

2. The signal direction identification circuit according to claim 1, characterized in that: The first to fourth switch tubes are all NMOS tubes.

3. The signal direction identification circuit according to claim 1, characterized in that: The first display element and the second display element are both light emitting diodes.

4. The signal direction identification circuit according to claim 1, characterized in that: Also includes: The bus hang judgment circuit is used to send a first isolation signal to isolate the first signal end through the first isolation signal when the first signal end is a bus hang source end; or to send a second isolation signal to isolate the second signal end through the second isolation signal when the second signal end is a bus hang source end.

5. The signal direction identification circuit according to claim 4, characterized in that: The deadlock determination circuit includes: a first determining unit connected to the source of the first switch tube, configured to send a first isolation signal when the first signal terminal is a bus-hang source terminal, so as to isolate the first signal terminal through the first isolation signal; The second judgment unit is connected to the source of the fourth switch tube and is used to send a second isolation signal when the second signal end is a bus-hanging source end, so as to isolate the second signal end through the second isolation signal.

6. The signal direction identification circuit according to claim 5, characterized in that: The first judgment unit includes: a first OR gate circuit, wherein a first input terminal of the first OR gate circuit is electrically connected to the first signal terminal, and an output terminal of the first OR gate circuit is connected to the gate of the first switch tube; A first watchdog unit circuit, wherein the input end of the first watchdog unit circuit is electrically connected to the first signal end, and the output end of the first watchdog unit circuit is electrically connected to the second input end of the first OR gate circuit.

7. The signal direction identification circuit according to claim 5, characterized in that: The second judgment unit includes: a second OR gate circuit, wherein a first input terminal of the second OR gate circuit is electrically connected to the second signal terminal, and an output terminal of the second OR gate circuit is connected to the gate of the fourth switch tube; A second watchdog unit circuit, wherein the input end of the second watchdog unit circuit is electrically connected to the second signal end, and the output end of the second watchdog unit circuit is electrically connected to the second input end of the second OR gate circuit.

8. The signal direction identification circuit according to any one of claims 1 to 7, characterized in that: The first signal end, the second signal end, the control ends of the multiple switch tubes, the first connection node and the second connection node are all second level signals, wherein the second level signal is an opposite signal to the first level signal. 9 . The signal direction identification circuit according to claim 8 , wherein a level of the first-level signal is lower than a level of the second-level signal.

10. A signal direction identification method, characterized in that: The method adopts the signal direction identification circuit according to any one of claims 1 to 9, wherein the method comprises the following steps: When the first signal end is at a first level signal, identifying the action signals of the plurality of switch tubes; The signal transmission direction is determined according to the action signals of the multiple switch tubes.

11. The signal direction identification method according to claim 10, characterized in that: The determining of the signal transmission direction according to the action signals of the plurality of switching tubes includes: Identifying a switch tube that is in an on state among the plurality of switch tubes; The signal transmission direction is defined as follows: a path formed by the switch tube in the on state and taking the first signal end as the starting point and the second signal end as the end point.

12. The signal direction identification method according to claim 11, characterized in that: Also includes: Obtaining a duration during which the first signal end is at the first level signal; When the duration is longer than a preset duration, a first isolation signal is sent out through the deadlock determination circuit to isolate the first signal end.

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