Method of forming electrode structure and electron beam steering apparatus

Abstract

A method of forming an electrode structure includes forming a first cavity and a second cavity in a first hard mask layer, filling the first cavity and the second cavity with a conductive material to form a first conductive pillar and a second conductive pillar. And planarizing exposed surfaces of the first conductive pillar and the second conductive pillar. Thereafter, a second hard mask layer is disposed on the first hard mask layer, a third cavity is formed through the second hard mask layer, and a second electroplating and planarization process is performed, the third cavity is filled with a conductive material to form a third conductive pillar contacting the second conductive pillar. The first electrode includes a first conductive pillar, and the second electrode includes a combination of a second conductive pillar and a third conductive pillar.

Description

Technical Field

[0001] The invention relates to a method for forming an electrode structure and an electron beam steering device. Background Art

[0002] The following relates to semiconductor devices, semiconductor electrode structures and methods for forming the same, microelectromechanical systems (MEMS) devices, and multi-electron beam controller components. Summary of the Invention

[0003] An embodiment of the present invention provides a method for forming an electrode structure for an electron beam control device, the method comprising: providing a first hard mask layer on a driving circuit including a patterned metallization layer; forming a first cavity and a second cavity in the first hard mask layer, the first cavity passing through the first hard mask layer to the patterned metallization layer, and the second cavity passing through the first hard mask layer to the patterned metallization layer; filling the first cavity and the second cavity with a conductive material to form a first conductive column and a second conductive column; performing a first planarization process on the exposed surface of the first conductive column and the exposed surface of the second conductive column; and performing the first planarization process on the exposed surface of the first conductive column and the exposed surface of the second conductive column. Thereafter, a second hard mask layer is disposed on the first hard mask layer, the second hard mask layer covering the planarized exposed surface of the first conductive pillar and the planarized exposed surface of the second conductive pillar; a third cavity is formed in the second hard mask layer, passing through the second hard mask layer to the second conductive pillar; the third cavity is filled with a conductive material to form a third conductive pillar contacting the second conductive pillar; a second planarization process is performed on the exposed surface of the third conductive pillar; and the first and second hard mask layers are removed to expose the first, second, and third conductive pillars, wherein the first electrode includes the first conductive pillar and the second electrode includes a combination of the second and third conductive pillars.

[0004] An embodiment of the present invention provides a method for forming an electrode structure for an electron beam control device, the method comprising: providing a driving circuit including an electron beam channel array, a driving transistor, and a patterned metallization layer; and disposing a first hard mask layer on the driving circuit; forming a first cavity array and a second cavity array through the first hard mask layer, wherein each of a plurality of electron beam channels is located between one of the first cavities and one of the second cavities; filling the first cavity with a conductive material through electroplating to form a first conductive pillar array and the second cavity to form a second conductive pillar array; and planarizing the first cavity. The method comprises the steps of: forming a first electrode array formed of the first conductive pillars and the second conductive pillars; disposing a second hard mask layer on the first hard mask layer and over the planarized exposed surfaces of the first and second conductive pillars; forming a third cavity array through the second hard mask layer, wherein the third cavity array is aligned with the second conductive pillar array; filling the third cavity array with a conductive material by electroplating to extend the height of the second conductive pillars; planarizing the exposed surfaces of the extended height second conductive pillars; and removing the first hard mask layer and the second hard mask layer to expose a first electrode array composed of the first conductive pillar array and a second electrode array composed of the extended height second conductive pillar array.

[0005] An embodiment of the present invention provides an electron beam steering device, comprising: a driving circuit, which includes an electron beam channel, a driving transistor and a patterned metallization layer; a first electrode and a second electrode, wherein: the height of the second electrode is higher than the first electrode, each electron beam channel has the first electrode and the second electrode on both sides of the electron beam channel, the second electrode has a first cross-sectional width at the lower part close to the driving circuit, and has a second cross-sectional width smaller than the first cross-sectional width at the upper part away from the driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1A to 1C An example method of forming an electrode structure is shown for comparison with an example method of forming an electrode structure according to an example embodiment of the present disclosure.

[0008] Figure 2 The operation of an electrode structure for electron beam control according to an example embodiment of the present disclosure is illustrated.

[0009] Figure 3 An example electrode structure formed by a method using multiple patternable hard mask layers according to an example embodiment of the present disclosure is shown.

[0010] Figures 4A to 4GVarious stages in the formation of an electrode structure according to an embodiment of the present disclosure are shown.

[0011] Figure 5 is a detailed diagram of an electrode structure according to an example embodiment of the present disclosure.

[0012] Figure 6 is another detailed diagram of an electrode structure according to an example embodiment of the present disclosure.

[0013] 7A to 7D A hard mask layer stacking method for forming an electrode structure according to an example embodiment of the present disclosure.

[0014] Figure 8 is a flow chart of a method of forming an electrode structure according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the description below may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature. The first and second features, so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and similar terms may be used herein to describe the relationship of one device or feature relative to another device or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0017] The term "layer" as used herein may include a single layer or multiple layers.

[0018] As used herein, the term “intermetal dielectric” (IMD) film or layer refers to a dielectric / insulating material layer between two metallization layers.

[0019] As used herein, the term “interlayer dielectric” (ILD) layer refers to an insulating structure of material placed between two conductive layers.

[0020] The term "hybrid" as used herein refers to an electrode height configuration (hybrid electrode height) which refers to more than one electrode, where the electrodes have pillars of different lengths and / or heights, or where one electrode is taller than the others.

[0021] As used herein, the term "TME" refers to a metallization layer and / or a top metallization layer.

[0022] As used herein, the term “TSV” refers to a through-silicon via or a through-hole through another material (eg, a dielectric material or layer, such as SiO 2 ).

[0023] The term "MEMS" as used herein refers to microelectromechanical systems and devices, which include systems and devices that combine electronic components and moving parts, or systems and devices that include electronic and mechanical devices and / or structures (such as electrode structures) without moving parts.

[0024] As used herein, the term "layered" or "multi-layered" structure refers to a structure comprising multiple levels or layers, wherein each successive level or layer is narrower in width than the previous level or layer.

[0025] As used herein, the term "metal plating" refers to the electroplating of metal or other conductive materials.

[0026] Electrodes and electrode structures are used in a variety of devices, including electron beam (e-beam) steering devices, such as those used in e-beam or multi-beam writing tools for semiconductor mask and wafer writing, and in e-beam inspection tools. For example, an electrode structure comprising conductive pillars (i.e., electrodes) of varying lengths is formed on a drive circuit (e.g., a silicon chip having a CMOS device) to serve as an e-beam controller component or an electron multi-beam deflection plate for electron mask exposure. The integration of the electrode structure and the drive circuit, i.e., a CMOS device or structure, is sometimes referred to in this disclosure as a mask writer MEMS device or an electrode MEMS device.

[0027] As will be further described herein, in the case of electron beam steering, the function of the electrodes is to electrostatically deflect or control (i.e., effectively shut down) an electron beam (or sub-beam) passing through the electron beam path of an electron beam control device through an electric field applied by an electrical bias electrode and a reference electrode.

[0028] The present disclosure and the example embodiments described herein provide an electrode structure and method for forming the same, as well as a MEMS structure including the electrode structure and a drive circuit, for use as a beamlet control board for an electron beam mask writer, an electron beam lithography tool, and the like. However, it should be understood that the electrode structure and method disclosed herein are not limited to these applications. Other applications of the disclosed electrode structure and method include electron beam inspection tools and the like.

[0029] As disclosed herein, an electrode structure includes a pair of electrodes of different lengths. The different lengths of the electrodes provide for the use of an electrode structure that suppresses or eliminates interference between controlled electron beams, wherein one electrode is used for grounding and the other electrode acts as a switch for electron beam control.

[0030] One method of forming a mixed height electrode structure includes using multiple photoresist patterning and metal plating processes to form the electrode structure on the drive circuit. The drive circuit is suitably formed as a wafer or tube die, which includes, in part, CMOS transistors, a dielectric layer and a top patterned metallization layer (TME), which includes electrical contacts for electrically bonding the electrode structure during PR (photoresist) patterning, and a metal plating process. As will be referenced below Figures 1A to 1C As further described, the PR patterning and metal plating process includes a series of steps, including: 1) performing a coating process to apply a PR coating to the surface of the driving circuit including the TME; 2) performing an exposure process to expose the PR coating to form a PR pattern for subsequent development; 3) developing the patterned and exposed PR coating to remove the patterned PR and expose the top surface area of the CMOS device for subsequent metal plating; 4) electroplating the first metallization layer on the two electrodes to form an electrode structure. The process steps 1)-4) are repeated to manufacture the electrode, wherein each cycle of the coating, exposure, development and metal plating process steps extends the height of the electrode. After the electrode is manufactured to the design reference height, the PR is removed to expose the electrode.

[0031] The PR resolution achieved through PR lithography may limit the aspect ratio that can be achieved in electrode formation. In addition, due to the multiple PR patterning and metal plating processes, the PR patterning and metal plating processes produce jagged and uneven electrode sidewall profiles. In other words, the standard deviation of the width of the pillar / electrode can be relatively high. The jagged or uneven sidewalls will produce significant non-uniformity in the electrostatic field generated between the bias pillar electrode and the ground pillar electrode, which in turn will adversely affect the controllability of the electron beam steering. In addition, the multiple PR patterning and metal plating processes of MEMS devices with high aspect ratio electroplated metal electrodes may cause the metal material on the top (mushroom) of the electrode to be over-plated or under-plated (humps or pits) due to the loading effect. This mushroom shape or insufficient plating will also have an adverse effect on the uniformity of the manipulation electrostatic field and may cause interference between the manipulation of adjacent electron beams.

[0032] Provided and described herein is another mixed height electrode structure and method for forming the same, which includes metal plating of multiple layers, stacks, or layers of conductive pillars to form an electrode structure, wherein the width of the top portion of the conductive pillar comprising the taller electrode is narrower than the width of the bottom portion of the conductive pillar below the top conductive pillar portion. The disclosed method is similar to a dual damascene process and advantageously facilitates the fabrication of high aspect ratio electrodes with different heights (e.g., a taller ground electrode and a shorter bias electrode) and straight sidewalls. A hard mask layer is formed to the height of the electrode (or a portion thereof) and patterned to form cavities for the short electrode and the tall electrode, followed by a metal plating process and chemical mechanical polishing (CMP) or other planarization process to fill the cavities to form the electrode pillars. The hard mask is then removed, for example, by an appropriate etch, to expose the high aspect ratio (pillar) electrodes. The result is a mixed height electrode structure having electrodes with uniform pillar widths across the entire pillar portion, and with a flat top surface. In other words, the patternable hard mask and metal plating process includes a patternable hard mask layer process to define the pattern, which then follows a dual damascene-like process to form metal electrodes of varying heights with a profile that includes non-jagged sides / profiles. The hard mask stack and deposition / coating / bonding process provides better control over the pillar / electrode profile compared to patterned PR and metal plating structures and methods.

[0033] refer to Figures 1A to 1C , described herein is an electrode structure and method of forming the same, which uses a cyclic photoresist patterning and metal plating process to form two sets of electrodes used as electron beam steering devices. The first set of electrodes includes electrodes 14 and 15, and the second set of electrodes includes electrodes 24 and 25 ( Figure 1B ).

[0034] like Figure 1A As shown, initially, the PR hybrid height electrode formation process performs an initial PR coating, exposure, and development PR process to form an initial patterned PR layer 17 on the driving circuit 8 including the CMOS devices 10 and 20, the IMD / ILD layers 11 and 21, the top patterned metallization layers 12 and 22, and the optional passivation layers 16 and 26. For an electron beam steering device or a multi-beam deflection plate, the driving circuit 8 is suitably formed as a two-dimensional (2D) array of the CMOS devices 10, 20 and the associated electron beam channels 13. Figure 1A 、 1B An illustrative portion of such an arrangement comprising one electron beam channel 13 and two CMOS devices 10 , 20 is shown in FIGS. 1 and 1C .

[0035] It is worth noting that the photoresist layer 17 is relatively thin, and in particular, not as thick as the desired final height of the pillar electrodes. The maximum thickness of the photoresist may be limited by the relative softness of the photoresist. Attempting to make the photoresist layer 17 too thick and then pattern it may result in photoresist collapse, in which the patterned features are distorted or partially filled. This is particularly likely for densely packed, high-aspect ratio features with small lateral critical dimensions.

[0036] Next, if Figure 1B As shown, the PR mixed height electrode formation process includes performing a metal plating process to plate a first metallization layer of electrode pillars 14, 15, 24, and 25. This results in the height of the conductive pillars being significantly shorter than the desired final electrode height. Therefore, in order to obtain the desired high aspect ratio pillar electrodes, the PR patterning process is repeated multiple times to gradually increase the height of the pillars to form the final electrodes 14, 15, 24, and 25 having multiple patterned PR layers 18 and plated metallization layers, resulting in Figure 1B If the patterned openings of successive photoresist layers are not precisely aligned, this can result in jagged sidewalls of the electrodes 14, 15, 24, and 25, as it requires multiple cycles of photoresist layer deposition, patterning, and electroplating steps.

[0037] Next, if Figure 1C As shown, the PR material is removed using a PR material removal process suitable for the PR layer material. The resulting hybrid electrode height structure is Figure 1C It is shown in Figure 1B A replica of the structure shown in , except that the patterned PR layer is removed from the structure. Figure 1C As shown in the electrode pillar top surface (EPTS) marked in FIG, the top surface of electrode pillar 15 includes an unfilled / pitted / rough / serrated electrode surface, and the top surface of electrode 25 includes an overfilled / mushroom-shaped electrode pillar surface. Figure 1C The electrode pillar sidewalls (EPSS) have a jagged sidewall profile, i.e., a relatively high standard deviation of the electrode width. In other words, the patterned PR metal plating process results in an electrode structure with an uneven and inconsistent metal plating surface.

[0038] refer to Figure 2 , although the reference numerals used are the same as Figures 1A to 1C The present invention is related to the electrode structure formed by patterning PR, but the operation of the electrode structure used as the electron beam control device is also applicable to the disclosed electrode structure formed by multiple continuous electroplating.

[0039] like Figure 2As shown, the electron beam steering device structure includes a drive circuit 8 (e.g., including transistors 10 and patterned metallization layers 12, 22 as described above) for driving electrodes 14, 15, 24, 25, 34, and 35. Generally speaking, through appropriate biasing of electrodes 14, 15, 24, 25, 34, and 35, the electron beam (at Figure 2 The electron beam (schematically indicated by the arrow labeled "e-") can be directed within the electron beam channel 13, or completely deflected outside the electron beam channel 13 (e.g., to turn the electron beam on or off, which may be suitable for some applications).

[0040] refer to Figure 3 and compare with reference Figure 1C , now offers patterned PR and electroplated mixed height electrode structures ( Figure 1C ) profile with hard mask (HM) patterning / layering and electroplating hybrid height electrode structure profile ( Figure 3 ) comparison.

[0041] As previously referenced Figures 1A to 1C As described above, the electrode structure obtained by patterning PR and metal plating process includes electrodes 14, 15, 24 and 25. The electrode column end surface and the electrode column, such as Figure 1C The EPTS region has a jagged sidewall profile, i.e., a relatively high standard deviation of the electrode width. In other words, the patterned PR metal plating process results in an electrode structure with an uneven and inconsistent metal plating surface.

[0042] and Figure 1C on the contrary, Figure 3A mixed height electrode structure that is hard mask (HM) patterned / layered and electroplated as disclosed herein is shown, including electrodes 150, 160 (including sub-pillars 160A and 160B), 250, and 260 (including sub-pillars 260A and 260B). By using a two-step HM patterning and metal plating process, the higher electrodes 160 and 260 each include two layers of pillars. Electrode 160 includes electrode sub-pillars 160A and 160B, wherein the width of electrode sub-pillar 160A is W1 and the width of electrode sub-pillar 160B is W2, wherein W2 is less than W1, thereby providing a layered electrode structure. Similarly, electrode 260 includes electrode sub-pillars 260A and 260B, wherein the width of electrode sub-pillar 260A is W1 and the width of electrode sub-pillar 260B is W2, wherein W2 is less than W1, thereby providing a layered electrode structure. By using post-plating planarization, the resulting electrode structure includes a flat electrode pillar top surface EPTS without mushrooms / pits / unfilled areas, and by using a thick hard mask (or two thick hard masks), the electrode pillar has a relatively smooth and consistent width / cross-sectional profile over the length of the electrode pillar (except for the designed junctions between the lower sub-pillars 160A and 260A and the upper sub-pillars 160B and 260B of the taller electrode pillars 160 and 260) relative to patterned PR and metal plating processes. In other words, straight metal electrodes are formed to define high aspect ratio patterns by using a patternable hard mask layer. The CMP process (applied to the top surface of the HM layer and the electrode top surface before removing the HM layer) flattens the electrode top surface to achieve a more uniform electrode height (H1+H2) and an overall more consistent electrode shape profile.

[0043] Similar to the electrode drive circuit described previously, Figure 3 Each electrode structure group is controlled by a driver circuit 118, which includes transistors 110 and 210 electrically connected to the CMOS device, IMD / IML layers 120 and 220, patterned metallization layers 130 and 230, optional passivation layers 121 and 221, and electron beam channels / TSVs 140 for the electron beam or beams to pass between electrodes 160 and 250. During the HM patterning and removal process, isolation structures 171A, 171B, 171C, and 171D are provided to electrically isolate electrodes 150 and 160, and to electrically isolate electrodes 250 and 260.

[0044] refer to Figures 4A to 4G , showing an example of an electron beam steering device according to an exemplary embodiment of the present disclosure. Figure 3 The electrode structure of the electrode structure is formed at various stages.

[0045] refer to Figure 4AThe electrode fabrication process begins by providing a driver circuit 118, for example, including exemplary transistors 110 and 210 (e.g., CMOS transistors), IMD / IML layers 120 and 220, patterned metallization layers 130 and 230 made of copper or other conductive materials, passivation layers 121 and 221, and vias / TSVs 140. The base material for the driver circuit 118 can be silicon, or a dielectric material such as, but not limited to, silicon dioxide, or other materials or combinations of materials suitable as substrates for active transistors and mechanically supporting the deposition of the IMD / IML layers 120 and 220. The driver circuit 118 can be fabricated using CMOS integrated circuit (IC) fabrication techniques, etc., to form the CMOS devices 110 and 210 in a silicon wafer or substrate, and using back-end-of-line (BEOL) processing to form the IMD / IML layers 120 and 220 and one or more metallization layers including the top metallization (TME) layer 130.

[0046] refer to Figure 4B , a first hard mask layer 181 is deposited on the driving circuit 118, such as the top metallization layers 130 and 230, the passivation layers 121 and 221, and the adhesion layer and metal plating contact seed layer 171. In an embodiment, the thickness or height of the first hard mask layer 181 is H1, the HM layer material is silicon, a dielectric or a polymer material, and the HM material deposition or covering process may include a deposition film, and / or a three-dimensional (3D) printing process. It is worth noting that the first hard mask layer 181 includes a material that is harder than the photoresist. Therefore, the first hard mask layer 181 can be made (and subsequently successfully patterned) to have a higher hardness than the photoresist. Figures 1A to 1C The process cycle of the embodiment can be used to increase the thickness of the photoresist layer 17. Specifically, the height H1 of the first hard mask layer 181 can be equal to the final height of the bias electrodes 150 and 250 (or H1 can be slightly higher to accommodate subsequent CMP planarization), so that the formation of the bias electrodes 150 and 250 and the lower sub-pillars 160A and 260A of the upper ground electrodes 160 and 260 can be manufactured in a single non-cyclic process sequence.

[0047] For example, first cavities 150-Cav and 250-Cav and second cavities 160A-Cav and 260A-Cav are formed in the first hard mask layer 181 through an appropriate photolithography-controlled etching process. A dry etching process can be used to etch cavities 150-Cav, 250-Cav, 160A-cav, and 260A-Cav having a width W1 in the first hard mask layer 181 at locations where the cavities are filled with a conductive material during a subsequent metal plating process to form electrode pillars 150, 160A, 250, and 260A. According to an exemplary embodiment, the dry etching process used depends on the HM material, wherein different plasma dry etching gases are used to remove the hard mask layer 181. For example, if the HM layer 181 material is silicon, SF6 etching gas is used; if the HM layer 181 material is a dielectric material, CF4 etching gas is used; and if the HM layer 181 material is a polymer material, O2 gas is used as the etching gas. The first cavities 150-Cav and 250-Cav pass through the first hard mask layer 181 to reach the patterned metallization layer 130. Similarly, the second cavities 160A-Cav and 260A-Cav pass through the first hard mask layer 181 to reach the patterned metallization layer. The first cavities 150-Cav and 250-Cav will be filled by electroplating to form the first electrodes 150 and 250, and the second cavities 160A-Cav and 260A-Cav will be filled by electroplating to form the lower sub-pillars 160A and 260A of the second electrodes 160 and 260, respectively (see FIG. Figure 4D and related descriptions). Therefore, the cross-sectional dimensions and shape of the cavity will determine the cross-sectional dimensions and shape of the corresponding electrode or lower electrode portion. Typically, the cross-section of the cavity and the corresponding electrode or lower electrode portion is circular; however, other cross-sectional shapes are also contemplated, such as square, rectangular, hexagonal, and more generally polygonal.

[0048] Optionally, before depositing the first hard mask layer 181 (eg Figure 4B Before the copper electroplating is performed, the process first covers the top surface of the electrode semiconductor drive circuit 118 with an optional adhesion layer or protective layer (not shown) and a metal electroplating contact seed layer 171. The optional adhesion layer or protective layer can protect the walls of the through-hole opening, for example, during the copper electroplating process. A thin layer of protective material such as tantalum (Ta), tantalum nitride (TaN), silicon nitride (SiN), silicon carbide (SiC), etc. can be optionally applied to the walls of the through-hole opening before performing copper electroplating. The seed layer 171 is typically a thin layer of the same material to be electroplated (e.g., a copper seed layer for electroplating copper), wherein the seed layer is formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like.

[0049] The metallization contact seed layer 171 is patterned to provide isolation structures 171A, 171B, 171C, and 171D, which are provided to electrically isolate electrodes 150 and 160 and to electrically isolate electrodes 250 and 260. In addition, passivation openings are formed to subsequently connect electrodes 150 and 250 to metallization layers 130 and 230 for controlling the bias of the shorter electrodes (150 and 250) through semiconductor control circuit transistors 110 and 210.

[0050] Reference Figure 4D , using metal plating to 1) fill cavities 150-Cav and 160A-Cav with conductive material ( Figure 4C ) to form the lower portions 160A of the first and second electrodes 150 and 160, respectively, and 2) filling the cavities 250A-Cav and 260A-Cav (as shown in FIG. 1 ) with a conductive material. Figure 4C ) to form the lower portions 260A of the first and second electrodes 250 and 260, respectively. According to example embodiments, the conductive material used to form the electrode pillars 150, 160A, 250, and 260A may include a metal (Cu, Ag, Au, Al) or a metal compound. For example, the conductive material may be copper (Cu), and thus copper electroplating is used. The electroplating fills the cavities 150-Cav, 250-Cav, 160A-Cav, and 260A-Cav, but typically also extends beyond the upper ends of the cavities.

[0051] Therefore, at this stage of the manufacturing process, the top end surfaces of the electrode posts 150, 160A, 250, and 260A may have an unacceptable surface profile and may include, for example, Figure 4D The unfilled HM cavity regions EPTS and / or the electrode columns 150 and 160A shown are Figure 4D The overfill metal region EPTS of the electrode column 250 shown, and / or Figure 4D The electrode 260A is shown with an overfill metal region EPTS.

[0052] Next, if Figure 4E As shown, after the metal plating process of the first HM layer 181 is completed, a CMP process is used to planarize the top surfaces of the HM layer 181 and the electrode pillars 150, 160A, 250 and 260A, thereby removing or eliminating the unfilled HM cavity region EPTS and the overfill metal region EPTS, as shown in FIG. Figure 4D shown.

[0053] Reference Figure 4F , showing the subsequent steps of forming electrode pillars 160B and 260B. This process is similar to that of reference Figures 4B to 4EThe process described above is performed, and a patternable hard mask process is performed to bond, deposit, and photo-pattern a second hard mask layer 182 on the first hard mask layer 181 and the top surfaces of the electrode pillars of the electrodes 150, 160A, 250, and 260A. Alternatively, the patternable hard mask process uses a deposition or coating process to form the hard mask. The second hard mask layer 182 is deposited / coated or bonded to the first hard mask layer 181. If a bonding process is used, it may include a bonding adhesive layer 172. If the bonding adhesive layer 172 acts as an etch stop layer, the etch stop layer material may be a metal (Ti, Cu, Al...), a diffusion barrier material (TaN, TiN...), and / or a dielectric material (silicon dioxide, silicon nitride...).

[0054] According to the example embodiment shown, the thickness or height of the second hard mask layer 182 is H2. Again, a dry etching process is used to etch cavities corresponding to the final upper portions 160B and 260B of the second electrodes 160 and 260. The cavities have a width W2 in the second hard mask layer 182 and are formed to align at the locations of the corresponding lower portions 160A and 260A. A subsequent metal plating process fills the cavities in the second hard mask layer 182 with a conductive material to form the electrode pillars 160B and 260B. Typically (although not necessarily) a metal plating process is used in this second plating step. Figure 4D The same conductive material as used in the electroplating step. Figure 4F As shown, the width W2 of electrode pillar 160B is less than the width W1 of electrode pillar 160A, and the width W2 of electrode pillar 260B is less than the width W1 of electrode pillar 260A. Similarly, electrode pillars 160B and 260B are typically formed with a circular cross-section, but may also have a square, hexagonal, or other cross-section. Subsequent CMP or other planarization is performed after electroplating to planarize the exposed ends of the plated upper portions 160B and 260B.

[0055] According to example embodiments, the bonding layer 172 material may be a polymer, such as a thermoset or photopolymer, including benzocyclobutene (BCB), or a dielectric, such as silicon dioxide.

[0056] refer to Figure 4G , using a HM material removal process suitable for the HM layer material to remove the hard mask layers 181 and 182. The resulting hybrid electrode height structure is Figure 4G It is shown in Figure 4F , except that the patterned HM layers 181 and 182 are removed from the structure. As shown in the region EPTS of the figure, the top surface of the electrode pillar includes a flat electrode end surface profile, and as shown in FIG. Figure 4G The regional EPSS is shown to have a smooth and non-serrated sidewall profile, i.e., a relatively low standard deviation of the electrode width.

[0057] Reference Figure 5 shows another view of the electrode structure shown in Figure 4G with dimension lines and the following dimension labels added:

[0058] (A): Length / height of electrode posts 160B and 260B

[0059] (B): Length / height of electrode posts 160A and 260A

[0060] (C): Width of electrode posts 150, 160A, 250, and 250A

[0061] (D): Width of electrode posts 160B and 260B

[0062] (E): Distance from the edge of the metal posts connecting electrodes 150 and 250 to the passivation layer openings, respectively.

[0063] (F): Inner corner angle of the top surfaces of electrode posts 160B and 260B

[0064] (G): Inner corner angle of the top surfaces of electrode posts 150 and 250

[0065] (H): Minimum electrode post spacing between electrode posts 150 and 160A and between electrode posts 250 and 250A

[0066] According to an embodiment of the present disclosure:

[0067] A > 0;

[0068] 0 < B, or 0 < B <= 5 μm;

[0069] 0 < C, or 0 < C < 0.2 μm;

[0070] 0 < D, or 0 < D < 0.2 μm;

[0071] E > 0;

[0072] F = 90 + / - 5 degrees;

[0073] G = 90 + / - 5 degrees;

[0074] H < 5 μm;

[0075] The maximum value of (A + B) of the electrode post top surface - the minimum value of (A + B) <= 5 μm;

[0076] The ratio of A / D > 4 μm / μm; the ratio of B / C > 10 μm / μm; and

[0077] C and D sigma (standard deviation of column width) < 0.2 μm.

[0078] Furthermore, it should be noted that, in a variant embodiment, the lower portions 160A and 260A and the upper portions 160B and 260B of the upper electrodes 160 and 260 may have the same cross-sectional dimensions or diameters. As another contemplated variant, if the electrodes 150 and 250 and the electrodes 160 and 260 both have the same height, then the second hard mask layer 182 deposition / patterning and the second electroplating step may be omitted.

[0079] In the illustrative examples described so far, the metallization layer includes only the top metallization layer (TME). However, the metallization layer may include multiple metallization layers interconnected through vias. Such a metallization stack is typically formed during the back-end of line (BEOL) processing of the IC workflow. Figure 6 , shows a detailed view of an example wiring of the metallization layer 130 through the IMD / ILD layer 120 and the passivation layer 121 to electrically connect the electrode CMOS driver semiconductor circuit 101 (fabricated on silicon) to the electrode 150. Figure 2 As shown, the second electrode, upper electrode 160A, is isolated from the electrode CMOS driver circuitry and is grounded when operating as an electron beam steering plate. Figure 6 Also shown in FIG. 1 is a more detailed view of the passivation layer 121 , including the via openings on the top surface of the metallization layer 130 described previously. Figure 6 The metallization layers of the metallization stack may be used to interconnect other electronic devices (not shown), such as circuits for receiving electrical signals for controlling the bias voltage applied to the bias electrode 150 .

[0080] The aforementioned example provides a reference electrode 160, 260 having two sections: lower sections 160A and 260A, and upper sections 160B and 260B, wherein the lower sections have a smaller diameter than the upper sections. This configuration, along with a reference electrode that is taller (i.e., taller) than the bias electrode, provides beneficial shielding to reduce interference in a multi-beam e-beam writer or maskless lithography apparatus. This can be expanded to the illustrative three sections or more.

[0081] refer to 7A to 7D , shows additional detail views of a multi-layer HM stack structure and its formation method to manufacture a series of electrode columns or other functional columns according to the present disclosure using the previously described multi-layer and HM processes. Specifically, Figure 7A Shown is a graph with a height H n Hard mask layer HM n , as Figure 7D The height H n , which means Figure 7A and 7C The hard mask layer HM1-HM shown in n Any one of . Figure 7AThe multilayer electrode columns 150, 160A and 160B, 161A and 161B and 161C are shown using a series of patterned HM layers (HM1, HM2, HM3, ..., HM n ) 181, 182 and 183 and the metal plating process are formed as follows: Figures 4A to 4G It is further shown that each conductive pillar is interconnected to a separate and different patterned metallization layer contact, namely M1, M2, M3...M n The result is a series of pillars with different heights (H1, H1+H2, H1+H2+H3, H1+H2+H3) and widths (W1, W2, W3, etc.) that can be used as electrodes for semiconductor-type devices that require high aspect ratio electrodes. n =0~100μm, and W n+1 <=Wn, 0-100 μm. This precise tailoring of the width as a function of the height profile can advantageously enable a precise tailoring of the electrostatic field formed by the electrodes.

[0082] refer to Figure 8 , which shows a flow chart of an example method of forming an electrode structure for an electron beam steering device according to the present disclosure.

[0083] In step S1 , the method provides a first hard mask layer on a driving circuit including a patterned metallization layer.

[0084] In step S2 , the method forms a first cavity and a second cavity in the first hard mask layer, the first cavity passing through the first hard mask layer to the patterned metallization layer, and the second cavity passing through the first hard mask layer to the patterned metallization layer.

[0085] In step S3 , the method performs a first electroplating process to fill the first cavity with a conductive material to form a first conductive pillar, and fill the second cavity with a conductive material to form a second conductive pillar.

[0086] At step S4 , the method performs chemical mechanical polishing (CMP) to planarize the exposed surface of the first conductive pillar and the exposed surface of the second conductive pillar.

[0087] In step S5 , after performing CMP, the method provides a second hard mask layer on the first hard mask layer, the second hard mask layer covering the planarized exposed surface of the first conductive pillar and the planarized exposed surface of the second conductive pillar.

[0088] In step S6 , the method forms a third cavity in the second hard mask layer that penetrates the second hard mask layer and reaches the second conductive pillar.

[0089] In step S7 , the method performs a second electroplating process to fill the third cavity with a conductive material to form a third conductive pillar contacting the second conductive pillar.

[0090] In step S8 , the method performs CMP to planarize the exposed surface of the third conductive pillar.

[0091] In step S9 , the method removes the first hard mask layer and the second hard mask layer to expose the first, second, and third conductive pillars.

[0092] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, and not all embodiments require a particular advantage. One advantage is that the electrode structure and the multiple hard mask layers and electroplating methods used to form the electrode structure provide improved control of the post / electrode profile, which improves the performance of the electrode structure, such as steering performance when used with an electron beam device.

[0093] Some further embodiments are described below.

[0094] In a non-limiting illustrative embodiment, a method for forming an electrode structure for an electron beam control device includes: providing a first hard mask layer on a driving circuit including a patterned metallization layer; forming a first cavity and a second cavity in the first hard mask layer, the first cavity passing through the first hard mask layer to the patterned metallization layer, and the second cavity passing through the first hard mask layer to the patterned metallization layer; filling the first cavity and the second cavity with a conductive material to form a first conductive pillar and a second conductive pillar; performing a first planarization process on the exposed surface of the first conductive pillar and the exposed surface of the second conductive pillar; and performing the first planarization process on the exposed surface of the first conductive pillar and the exposed surface of the second conductive pillar. After the process, a second hard mask layer is disposed on the first hard mask layer, the second hard mask layer covering the planarized exposed surface of the first conductive pillar and the planarized exposed surface of the second conductive pillar; a third cavity is formed in the second hard mask layer through the second hard mask layer to the second conductive pillar; the third cavity is filled with a conductive material to form a third conductive pillar contacting the second conductive pillar; a second planarization process is performed on the exposed surface of the third conductive pillar; the first hard mask layer and the second hard mask layer are removed to expose the first, second and third conductive pillars, wherein the first electrode includes the first conductive pillar and the second electrode includes a combination of the second and third conductive pillars.

[0095] In some embodiments, the third cavity has a smaller cross-sectional width than the second cavity, and the third conductive pillar has a smaller cross-sectional width than the second conductive pillar.

[0096] In some embodiments, the driving circuit includes a silicon substrate, and the method further includes: forming an electron beam channel including a through-silicon via passing through the silicon substrate, wherein the first electrode includes two first electrodes, the second electrode includes two second electrodes, and the electron beam channel is arranged between the two first electrodes and between the two second electrodes.

[0097] In some embodiments, the driving circuit includes a transistor, and the transistor is electrically connected to the first electrode through the patterned metallization layer of the driving circuit.

[0098] In some embodiments, the first hard mask layer and the second hard mask layer include silicon, a dielectric material, and / or a polymer; and the conductive material is copper, silver, aluminum, or a metal compound.

[0099] In some embodiments, the steps of disposing the second hard mask layer, patterning the second hard mask layer, filling the third cavity with the conductive material, and performing the second planarization process are repeated for multiple stacked second hard mask layers to form the third conductive pillar.

[0100] In some embodiments, the standard deviation of the first cross-sectional width of the first conductive pillar and the second conductive pillar is less than 0.2 μm; the angle between the horizontal axis of the exposed end surface of the first electrode and the longitudinal axis of the first electrode is 85 to 95 degrees; and the standard deviation of the second cross-sectional width of the third conductive pillar is less than 0.2 μm.

[0101] In some embodiments, the first longitudinal length of the first conductive pillar and the second conductive pillar is 1 μm to 100 μm; the first cross-sectional width of the first conductive pillar and the second conductive pillar is 1 μm to 100 μm; the second longitudinal length of the third conductive pillar is 1 μm to 100 μm; the second cross-sectional width of the third conductive pillar is 1 μm to 100 μm; the minimum spacing between the first conductive pillar and the second conductive pillar is less than 5 μm; and the aspect ratio is 1 to 30, and the aspect ratio is defined as (the first longitudinal length + the second longitudinal length) / the first cross-sectional width.

[0102] In another non-limiting illustrative embodiment, a method of forming an electrode structure for an electron beam control device includes: providing a driving circuit including an array of electron beam channels, a driving transistor, and a patterned metallization layer; and disposing a first hard mask layer on the driving circuit; forming a first array of cavities through the first hard mask layer and a second array of cavities through the first hard mask layer, wherein each of a plurality of electron beam channels is located between one of the first cavities and one of the second cavities; and filling the first cavities with a conductive material by electroplating to form a first array of conductive pillars and the second cavities to form a second array of conductive pillars. ; planarizing the exposed surfaces of the first and second conductive pillars; disposing a second hard mask layer on the first hard mask layer and over the planarized exposed surfaces of the first and second conductive pillars; forming a third cavity array through the second hard mask layer, wherein the third cavity array is aligned with the second conductive pillar array; filling the third cavity with a conductive material through electroplating to extend the height of the second conductive pillars; planarizing the exposed surfaces of the extended height second conductive pillars; removing the first hard mask layer and the second hard mask layer to expose a first electrode array composed of the first conductive pillar array and a second electrode array composed of the extended height second conductive pillar array.

[0103] In some embodiments, a cross-sectional width of the third cavity is smaller than a cross-sectional width of the second cavity, and a cross-sectional width of the third conductive pillar is smaller than a cross-sectional width of the second conductive pillar.

[0104] In some embodiments, the driving circuit includes a silicon substrate, and the method further includes: forming an electron beam channel, the electron beam channel including a through silicon via passing through the silicon substrate; wherein the electron beam channel is disposed between the first electrode and the second electrode.

[0105] In some embodiments, the driving transistor is electrically connected to the first electrode through the patterned metallization layer.

[0106] In some embodiments, the first hard mask layer and the second hard mask layer include silicon, a dielectric material and / or a polymer; and the conductive material is copper, silver, aluminum or a metal compound.

[0107] In some embodiments, the steps of providing the second hard mask layer, performing the electroplating process to fill the third cavity, and performing the planarization process are repeated for multiple stacked second hard mask layers to extend the height of the second conductive pillar.

[0108] In some embodiments, a standard deviation of the first cross-sectional width of the first conductive pillar and the second cross-sectional width of the second conductive pillar is less than 0.2 μm; and an angle between the horizontal axis of the exposed end surface of the first electrode and the longitudinal axis of the first electrode is 85 to 95 degrees.

[0109] In some embodiments, the first longitudinal length of the first conductive pillar and the second conductive pillar is 1 μm to 100 μm; the first cross-sectional width of the first conductive pillar and the second conductive pillar is 1 μm to 100 μm; the second longitudinal length of the third conductive pillar is 1 μm to 100 μm; the second cross-sectional width of the third conductive pillar is 1 μm to 100 μm; the minimum spacing between the first conductive pillar and the second conductive pillar is less than 5 μm; and the aspect ratio is 1 to 30, and the aspect ratio is defined as (the first longitudinal length + the second longitudinal length) / the first cross-sectional width.

[0110] In another non-limiting illustrative embodiment, an electron beam steering device includes: a driving circuit, which includes an electron beam channel, a driving transistor and a patterned metallization layer; a first electrode and a second electrode, wherein: the height of the second electrode is higher than the first electrode, each electron beam channel has the first electrode and the second electrode on both sides of the electron beam channel, and the second electrode has a first cross-sectional width at a lower portion close to the driving circuit and a second cross-sectional width at an upper portion away from the driving circuit that is smaller than the first cross-sectional width.

[0111] In some embodiments, the standard deviation of the cross-sectional width of the first electrode is less than 0.2 μm; the angle between the horizontal axis of the exposed end surface of the first electrode and the longitudinal axis of the first electrode is 85 to 95 degrees; and the standard deviation of the first cross-sectional width of the second electrode and the second cross-sectional width of the second electrode is less than 0.2 μm.

[0112] In some embodiments, selective electrical biasing of the first electrode deflects the electron beam passing between the first electrode and the second electrode.

[0113] In some embodiments, the first longitudinal length of the first electrode and the second electrode is 1 μm to 100 μm; the first cross-sectional width of the first electrode is 1 μm to 100 μm; the first cross-sectional width and the second cross-sectional width of the second electrode are 1 μm to 100 μm; the minimum spacing between the first electrode and the second electrode is less than 5 μm; and the aspect ratio is 1 to 30, and the aspect ratio is defined as (the first longitudinal length + the second longitudinal length) / the first cross-sectional width.

[0114] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications to them herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming an electrode structure, characterized in that: include: providing a first hard mask layer on the driving circuit including the patterned metallization layer; forming a first cavity and a second cavity in the first hard mask layer, the first cavity passing through the first hard mask layer to the patterned metallization layer, and the second cavity passing through the first hard mask layer to the patterned metallization layer; filling the first cavity and the second cavity with a conductive material to form a first conductive pillar and a second conductive pillar; performing a first planarization process on the exposed surface of the first conductive pillar and the exposed surface of the second conductive pillar; After performing the first planarization process, disposing a second hard mask layer on the first hard mask layer, wherein the second hard mask layer covers the planarized exposed surface of the first conductive pillar and the planarized exposed surface of the second conductive pillar; forming a third cavity in the second hard mask layer, passing through the second hard mask layer to the second conductive pillar; filling the third cavity with the conductive material to form a third conductive pillar contacting the second conductive pillar; performing a second planarization process on the exposed surface of the third conductive pillar; as well as removing the first hard mask layer and the second hard mask layer to expose the first, second and third conductive pillars, The first electrode includes the first conductive column, and the second electrode includes a combination of the second conductive column and the third conductive column.

2. The method according to claim 1, characterized in that The third cavity has a smaller cross-sectional width than the second cavity, and the third conductive pillar has a smaller cross-sectional width than the second conductive pillar.

3. The method according to claim 1, characterized in that The driving circuit includes a silicon substrate, and the method further includes: forming an electron beam channel including a through-silicon via (TSV) passing through the silicon substrate, The first electrode includes two first electrodes, the second electrode includes two second electrodes, and the electron beam channel is arranged between the two first electrodes and between the two second electrodes.

4. The method according to claim 1, wherein The standard deviation of the first cross-sectional widths of the first conductive pillar and the second conductive pillar is less than 0.2 μm; The angle between the horizontal axis of the exposed end surface of the first electrode and the longitudinal axis of the first electrode is 85 to 95 degrees; and A standard deviation of the second cross-sectional width of the third conductive pillar is less than 0.2 μm.

5. The method according to claim 1, wherein The first longitudinal length of the first conductive pillar and the second conductive pillar is 1 μm to 100 μm; The first cross-sectional width of the first conductive pillar and the second conductive pillar is 1 μm to 100 μm; The second longitudinal length of the third conductive column is 1 μm to 100 μm; The second cross-sectional width of the third conductive pillar is 1 μm to 100 μm; The minimum distance between the first conductive pillar and the second conductive pillar is less than 5 μm; as well as The aspect ratio is 1 to 30, and the aspect ratio is defined as (the first longitudinal length+the second longitudinal length) / the first cross-sectional width.

6. A method for forming an electrode structure, characterized in that: include: providing a drive circuit comprising an array of electron beam channels, a drive transistor, and a patterned metallization layer; providing a first hard mask layer on the driving circuit; forming an array of first cavities through the first hard mask layer and an array of second cavities through the first hard mask layer, wherein each of the plurality of electron beam channels is located between one of the first cavities and one of the second cavities; performing an electroplating process to fill the first cavity with a conductive material to form an array of first conductive pillars, and to fill the second cavity with a conductive material to form an array of second conductive pillars; performing a planarization process on exposed surfaces of the first and second conductive pillars; disposing a second hard mask layer on the first hard mask layer and over the planarized exposed surfaces of the first and second conductive pillars; forming an array of third cavities through the second hard mask layer, wherein the array of third cavities is aligned with the array of second conductive posts; performing the electroplating process to fill the third cavity with the conductive material to extend the height of the second conductive pillar; performing the planarization process on the exposed surface of the second conductive pillar of the extended height; as well as The first hard mask layer and the second hard mask layer are removed to expose a first electrode array consisting of the array of the first conductive pillars and a second electrode array consisting of the array of the second conductive pillars of the extended height.

7. The method according to claim 6, characterized in that The driving circuit includes a silicon substrate, and the method further includes: forming an electron beam channel, wherein the electron beam channel comprises a through silicon via (TSV) passing through the silicon substrate; The electron beam channel is arranged between the first electrode and the second electrode.

8. The method according to claim 6, characterized in that The driving transistor is electrically connected to the first electrode through the patterned metallization layer.

9. An electron beam steering device, characterized in that: include: a drive circuit including an electron beam channel, a drive transistor, and a patterned metallization layer; a first electrode and a second electrode, wherein: The second electrode is higher than the first electrode. Each of the electron beam paths has the first electrode and the second electrode located on opposite sides of the electron beam path, and The second electrode has a lower portion close to the driving circuit and having a first cross-sectional width, and an upper portion far from the driving circuit and having a second cross-sectional width smaller than the first cross-sectional width.

10. The electron beam steering device according to claim 9, characterized in that: Selective electrical biasing of the first electrode deflects the electron beam passing between the first electrode and the second electrode.

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