dynamic comparator

Abstract

The application relates to a dynamic comparator, which comprises a dynamic differential amplification module and a latch module. The power supply end of the dynamic differential amplification module is connected with a power supply, and two signal input ends are connected with first and second input signals, so that the module is locked when the dynamic comparator is in a reset stage and outputs first and second amplification signals when the dynamic comparator is in a comparison stage. The power supply end of the latch module is connected with the power supply, two signal input ends are connected with two signal output ends of the dynamic differential amplification module, and a clamping signal is further connected, and a control end is connected with a clock signal, so that the latch module is locked under the action of the clamping signal and the clock signal in the reset stage, and outputs a comparison result signal based on the two amplification signals in the comparison stage. The dynamic comparator can simultaneously meet the requirements of high speed, high precision and low power consumption.

Description

Technical Field

[0001] The present application relates to the technical field of comparators, and in particular to a dynamic comparator. Background Art

[0002] In most IoT applications, analog-to-digital converters (ADCs) serve as a bridge between the digital and physical worlds, and comparators are the core working unit of ADCs. The faster and higher the comparison speed of a comparator, the more energy it consumes.

[0003] In order to reduce power consumption, strong arm dynamic comparators that do not consume static current have replaced traditional static comparators and are widely used.

[0004] However, the currently commonly used dynamic comparator with Strong Arm structure has the problem of not being able to meet the requirements of high speed, high precision and low power consumption at the same time. Summary of the Invention

[0005] Based on this, it is necessary to provide a dynamic comparator.

[0006] The present application provides a dynamic comparator, comprising:

[0007] A dynamic differential amplifier module, wherein the power supply terminal of the dynamic differential amplifier module is used to connect to a power supply, the first signal input terminal of the dynamic differential amplifier module is used to receive a first input signal, and the second signal input terminal of the dynamic differential amplifier module is used to receive a second input signal, so that the dynamic differential amplifier module is in a locked state when the dynamic comparator is in a reset phase, and outputs a first amplified signal and a second amplified signal when the dynamic comparator is in a comparison phase;

[0008] A latch module, wherein the power supply end of the latch module is used to connect to a power supply, the first signal input end of the latch module is connected to the first signal output end of the dynamic differential amplifier module, the second signal input end of the latch module is connected to the second signal output end of the dynamic differential amplifier module, the first signal input end and the second signal input end of the latch module are also used to access a clamping signal, and the controlled end of the latch module is used to access a clock signal, so that when the dynamic comparator is in a reset stage, the latch module is in a locked state under the action of the clamping signal and the clock signal, and when the dynamic comparator is in a comparison stage, a comparison result signal is output based on the first amplified signal and the second amplified signal.

[0009] In one embodiment, a dynamic differential amplification module includes: an energy storage unit, an input amplification unit, a first controlled switch unit, and a second controlled switch unit;

[0010] The power supply terminal of the energy storage unit is connected to the power supply through the first controlled switch unit, the power supply terminal of the energy storage unit is connected to the power supply terminal of the input amplification unit, the first signal output terminal of the input amplification unit is connected to the first signal input terminal of the latch module, the second signal output terminal of the input amplification unit is connected to the second signal input terminal of the latch module, and the first signal input terminal and the second signal input terminal of the latch module are further connected to the clamping signal through the second controlled switch unit;

[0011] When the dynamic comparator is in a reset phase, the first controlled switch unit and the second controlled switch unit are both in an on state;

[0012] When the dynamic comparator is in the comparison stage, the first controlled switch unit and the second controlled switch unit are both in the disconnected state.

[0013] In one embodiment, the energy storage unit includes a tail capacitor C tail1 and tail capacitor C tail2 , the first controlled switch unit includes a controlled switch S1 and a controlled switch S2, and the second controlled switch unit includes a controlled switch S3 and a controlled switch S4;

[0014] Among them, the tail capacitor C tail1 The positive plate is connected to the positive electrode of the power supply through the controlled switch S1, and the tail capacitor C tail1 The negative plate is connected to the positive power supply terminal of the input amplifier unit; the tail capacitor C tail2 The positive plate is connected to the negative electrode of the power supply through the controlled switch S2, and the tail capacitor C tail2 The negative plate is connected to the negative power supply terminal of the input amplifier unit, the first signal input terminal of the latch module is connected to the clamping signal through the controlled switch S3, and the second signal input terminal of the latch module is connected to the clamping signal through the controlled switch S4;

[0015] When the dynamic comparator is in the reset phase, the controlled switch S1, the controlled switch S2, the controlled switch S3 and the controlled switch S4 are all in the on state;

[0016] When the dynamic comparator is in the comparison stage, the controlled switch S1 and the controlled switch S2 are in the off state, and the controlled switch S3 and the controlled switch S4 are both in the off state.

[0017] In one embodiment, the dynamic differential amplification module includes: an energy storage unit, an input amplification unit, a third controlled switch unit, a fourth controlled switch unit, and a fifth controlled switch unit;

[0018] The power supply terminal of the energy storage unit is connected to the power supply through the third controlled switch unit, the power supply terminal of the input amplification unit is connected to the power supply terminal of the energy storage unit through the fourth controlled switch unit, the first signal output terminal of the input amplification unit is connected to the first signal input terminal of the latch module, the second signal output terminal of the input amplification unit is connected to the second signal input terminal of the latch module, and the first signal input terminal and the second signal input terminal of the latch module are further connected to the clamping signal through the fifth controlled switch unit;

[0019] When the dynamic comparator is in the reset phase, the third controlled switch unit and the fifth controlled switch unit are both in the on state, and the fourth controlled switch unit is in the off state;

[0020] When the dynamic comparator is in the comparison stage, the third controlled switch unit and the fifth controlled switch unit are both in the off state, and the fourth controlled switch unit is in the on state.

[0021] In one embodiment, the energy storage unit includes an energy storage capacitor C RES , the third controlled switch unit includes a controlled switch S11 and a controlled switch S12, the fourth controlled switch unit includes a controlled switch S21 and a controlled switch S22, and the fifth controlled switch unit includes a controlled switch S31 and a controlled switch S32;

[0022] Among them, the energy storage capacitor C RES The positive plate is connected to the positive electrode of the power supply through the controlled switch S11, and the energy storage capacitor C RES The negative plate is connected to the negative electrode of the power supply through the controlled switch S12, and the energy storage capacitor C RES The positive plate is also connected to the positive power supply terminal of the input amplifier unit through the controlled switch S21, and the energy storage capacitor C RES The negative plate is also connected to the negative power supply terminal of the input amplifier unit through the controlled switch S22, the first signal input terminal of the latch module is connected to the clamping signal through the controlled switch S31, and the second signal input terminal of the latch module is connected to the clamping signal through the controlled switch S32;

[0023] When the dynamic comparator is in the reset phase, the controlled switches S11, S12, S31, and S32 are all in the on state, and the controlled switches S21 and S22 are in the off state;

[0024] When the dynamic comparator is in the comparison stage, the controlled switches S11 , S12 , S31 and S32 are all in the off state, and the controlled switches S21 and S22 are in the on state.

[0025] In one embodiment, a latch module includes an input pair unit and a latch unit;

[0026] The power supply terminal of the input pair unit is used to connect to the power supply, the first signal input terminal of the input pair unit is connected to the first signal output terminal of the dynamic differential amplifier module, the second signal input terminal of the input pair unit is connected to the second signal output terminal of the dynamic differential amplifier module, the first signal input terminal and the second signal input terminal of the input pair unit are also used to connect to the clamping signal, and the controlled terminal of the input pair unit is used to connect to the clock signal;

[0027] The first input end of the latch unit is connected to the first output end of the input pair unit, the second input end of the latch unit is connected to the second output end of the input pair unit, the controlled end of the latch unit is used to access the clock signal, and the signal output end of the latch unit is used to output the comparison result signal.

[0028] In one embodiment, the input pair unit includes: a switch tube M0, a switch tube M1, a switch tube M2, an auxiliary switch tube M11 and an auxiliary switch tube M22;

[0029] Among them, the source of the switch tube M0 is used to connect to the power supply, the gate of the switch tube M0 is used to connect to the clock signal, and the drain of the switch tube M0 is respectively connected to the source of the switch tube M1, the source of the switch tube M2, the source of the auxiliary switch tube M11, and the source of the auxiliary switch tube M22; the gate of the switch tube M1 is connected to the first signal output terminal of the dynamic differential amplifier module, and the gate of the switch tube M1 is also used to connect to the clamping signal. The drain of the switch tube M1 is respectively connected to the first input terminal of the latch unit and the drain of the auxiliary switch tube M11; the gate of the switch tube M2 is connected to the second signal output terminal of the dynamic differential amplifier module, and the gate of the switch tube M2 is also used to connect to the clamping signal. The drain of the switch tube M2 is respectively connected to the second input terminal of the latch unit and the drain of the auxiliary switch tube M22; the gates of the auxiliary switch tube M11 and the gates of the auxiliary switch tube M22 are both used to connect to the power supply;

[0030] When the dynamic comparator is in the reset stage, the switch tube M0 is in the off state; when the dynamic comparator is in the comparison stage, the switch tube M0 is in the on state.

[0031] In one embodiment, the latch unit is a dynamic latch.

[0032] In one embodiment, the input amplification unit includes: a first amplification unit and a second amplification unit;

[0033] The power supply terminal of the first amplifying unit is connected to the power supply terminal of the energy storage unit, and the signal input terminal of the first amplifying unit is used to receive the first input signal; the power supply terminal of the second amplifying unit is connected to the power supply terminal of the energy storage unit, and the signal input terminal of the second amplifying unit is used to receive the second input signal;

[0034] When the dynamic comparator is in a reset phase, the first amplifying unit and the second amplifying unit are both in a locked state;

[0035] When the dynamic comparator is in the comparison stage, the first amplifying unit outputs a first amplified signal based on the first input signal, and the second amplifying unit outputs a second amplified signal based on the second input signal.

[0036] In one embodiment, the first amplifying unit includes a switch tube MP1, a switch tube MN1 and a first integrating capacitor C X1 ;

[0037] The source of the switch tube MP1 is connected to the positive power supply terminal of the energy storage unit, and the drain of the switch tube MP1 is connected to the drain of the switch tube MN1, the first integral capacitor C X1 The positive plate of the switch tube MP1 and the first signal input terminal of the latch module are connected. The source of the switch tube MN1 is connected to the negative power supply terminal of the energy storage unit. The gate of the switch tube MP1 and the gate of the switch tube MN1 are both used to access the first input signal. The first integral capacitor C X1 The negative plate is grounded;

[0038] The second amplifier unit includes a switch tube MP2, a switch tube MN2 and a second integral capacitor C X2 ;

[0039] The source of the switch tube MP2 is connected to the positive power supply terminal of the energy storage unit, and the drain of the switch tube MP2 is connected to the drain of the switch tube MN2, the second integral capacitor C X2 The source of the switch tube MN2 is connected to the negative power supply terminal of the energy storage unit, and the gate of the switch tube MP1 and the gate of the switch tube MN1 are both used to access the second input signal. The second integral capacitor C X2 The negative plate is grounded.

[0040] The above dynamic comparator has at least the following beneficial effects:

[0041] By introducing a dynamic differential amplifier module to improve the gain and ensure comparison accuracy, the clamp signal and clock signal are used to control the working state to achieve zero-power reset, and the positive feedback mechanism of the latch module is combined to improve the comparison speed. These functions complement each other and effectively meet the strict requirements of high precision, high speed and low power consumption in scenarios such as high-speed data acquisition and analog-to-digital conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 is a schematic structural diagram of a traditional dynamic comparator in one embodiment;

[0044] Figure 2 is a structural diagram of a dynamic comparator in one embodiment;

[0045] Figure 3 is a schematic structural diagram of a dynamic comparator in another embodiment;

[0046] Figure 4 is a structural diagram of a dynamic comparator in yet another embodiment;

[0047] Figure 5 FIG. 4 is a signal timing diagram of a dynamic comparator in one embodiment. DETAILED DESCRIPTION

[0048] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0050] It will be understood that the terms "first," "second," and the like used herein may be used to describe various elements herein, but these elements are not limited by these terms. These terms are used solely to distinguish a first element from another element. For example, a first amplification unit may be referred to as a second amplification unit, and similarly, a second amplification unit may be referred to as a first amplification unit without departing from the scope of this application. The first amplification unit and the second amplification unit are both amplification units, but they are not the same amplification unit.

[0051] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0052] It is understood that “at least one” refers to one or more, “a plurality” refers to two or more, and “at least a portion of an element” refers to a portion or all of an element.

[0053] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0054] As described in the background technology, in most IoT application scenarios, the analog-to-digital converter plays the role of a bridge connecting the digital world and the physical world, and the comparator is the core working unit of the analog-to-digital converter. The faster and higher the comparison speed of the comparator, the more energy it consumes. In order to reduce power consumption, the strong arm type (Strong Arm) dynamic comparator that does not consume static current has replaced the traditional static comparator and has been widely used. Among them, the simple circuit structure of the Strong Arm type dynamic comparator is as follows Figure 1 As shown, CLK is an external high-speed clock signal. When CLK is low, switch M0 is turned off to avoid static current, switch M7 and switch M10 pull the drain of switch M1 and the drain of switch M2 to high level respectively, and switch M8 and switch M9 pull the output terminal V on and V op Pulled to high level, no current flows through the entire circuit, and the circuit is in the reset stage; when CLK is high, the switch tube M0 is turned on instantly, and V source Pulled low, the differential input pair and the latch structure start working in the comparison phase and output the comparison result.

[0055] However, the Strong Arm dynamic comparator still has some inherent disadvantages: Figure 1 As shown in the figure, since the switch tube M0 works in the linear region as a tail current source, the integrated current depends to a large extent on the input level, thus affecting the performance of the comparator, such as voltage offset, noise increase and speed reduction, that is, it is very sensitive to the input common mode voltage. Secondly, due to the inevitable gate-drain and gate-source overlap capacitance of the switch tube, V sourceInstantaneous changes in the voltage at the input terminals and the drains of switches M1 and M2 can cause voltage changes, affecting comparison accuracy. Simultaneously, the absorption and release of channel charge can also affect the differential input pair. As low-power products increasingly demand more energy efficiency, traditional Strong Arm dynamic comparators can no longer simultaneously meet the requirements for high speed, high precision, and low power consumption.

[0056] Specifically, such as Figure 1 The circuit diagram of the traditional Strong Arm dynamic comparator is given. In order to save energy, the dynamic comparator adopts a dynamic integration unit (such as the integration capacitor C x ) to replace the preamplifier of the static comparator. In low-noise applications, a larger integrating capacitor C is required. x To obtain good resolution. The working process of the dynamic comparator can be divided into two stages: comparison stage and reset stage. The on or off state of the switch tubes M7-M10 controlled by the CLK signal determines the stage of the comparator. In the comparison stage, the dynamic comparator acts as a dynamic integrator, continuously integrating the input signal to the capacitor C x When the output signal V on and V op Gradually pulled down to V th,p (i.e., the threshold voltage of switch tube M4 and switch tube M6) is below, the dynamic comparator enters the reset phase. For the Strong Arm type dynamic comparator of the transmission, the capacitor C x The integration behavior during the comparison phase determines the noise and power consumption of the dynamic comparator. Specifically, the capacitor C x The integration time is approximately expressed as:

[0057] ,

[0058] Among them, V th,n is the threshold voltage of switch tube M3 and switch tube M5, C x for Figure 1 Middle capacitor C x Rated capacitance value, I d is the drain current of switch tube M3 and switch tube M5. Integral gain A int Depends on the g of the input switch tube m (Transconductance) / I d (drain current) and V th,n , whose expression is:

[0059] ,

[0060] Generally speaking, the input switch tubes are biased in the strong inversion region. The input-referred noise of the dynamic comparator is mainly contributed by the dynamic integrator, and its input-referred noise can be expressed as:

[0061] ,

[0062] Among them, k, T and γ are all constants. From the above formula, we can see that by increasing g m / I d Or increase C x To reduce the input-referred noise of the dynamic comparator. Based on the noise contributed by the latch, the total noise of the Strong Arm dynamic comparator can be expressed as:

[0063] ,

[0064] in, The noise contributed by the latch is as follows: From the above formula, we can see that the high noise of the dynamic comparator is mainly due to the integral gain A int Too low.

[0065] from Figure 1 The circuit diagram and working process of the comparator in the figure show that the traditional Strong Arm comparator reduces power consumption and improves speed by eliminating the static working unit and adding positive feedback latch. However, the inventors found that the Strong Arm comparator still has the following obvious disadvantages: when the drain of the switch tube M1 and the switch tube M2 gradually decreases to VDD-V th,n When the switch tubes M3 and M5 are turned on, the comparison phase ends. This means that only in the initial discharge phase, the integral capacitor C x It has the effect of reducing noise. Generally speaking, the capacitor C x are relatively large, the capacitor C x A full discharge consumes a fixed amount of energy , which limits the energy efficiency of the Strong Arm comparator. In this way, the capacitor C x Full discharge will cause waste. Secondly, the integral gain is output common mode level V th,n The dynamic integral gain is limited to less than 10. In addition, the switch tube M0 generally works in the linear region as a tail current source. At this time, the input current Id is strongly related to the input voltage, which causes the performance of the comparator (such as noise, offset, speed) to be largely dependent on the common-mode input level V th,n .

[0066] Based on the above reasons, in an exemplary embodiment, Figure 2As shown, the present application provides a dynamic comparator, including a dynamic differential amplification module 2 and a latch module 4. The power supply end of the dynamic differential amplifier module 2 is used to connect to the power supply 100, the first signal input end of the dynamic differential amplifier module 2 is used to receive the first input signal, and the second signal input end of the dynamic differential amplifier module 2 is used to receive the second input signal, so that the dynamic differential amplifier module 2 is in a locked state when the dynamic comparator is in the reset stage, and outputs the first amplified signal and the second amplified signal when the dynamic comparator is in the comparison stage; the power supply end of the latch module 4 is used to connect to the power supply 100, the first signal input end of the latch module 4 is connected to the first signal output end of the dynamic differential amplifier module 2, and the second signal input end of the latch module 4 is connected to the second signal output end of the dynamic differential amplifier module 2. The first signal input end and the second signal input end of the latch module 4 are also used to receive the clamping signal, and the controlled end of the latch module 4 is used to receive the clock signal, so that when the dynamic comparator is in the reset stage, the latch module 4 is in a locked state under the action of the clamping signal and the clock signal, and outputs the comparison result signal based on the first amplified signal and the second amplified signal when the dynamic comparator is in the comparison stage.

[0067] The dynamic differential amplifier module 2 is a circuit module with differential amplification functionality. As the front-end signal processing unit of the dynamic comparator, it primarily performs differential amplification on two input signals (a first input signal and a second input signal). By amplifying the difference between the two input signals (i.e., the differential signal), it suppresses common-mode signals, thereby improving the signal-to-noise ratio and amplification accuracy. Higher gain means that even small differences in the input signals are amplified into more significant voltage differences, providing a clearer signal basis for subsequent fast comparisons by the latch module 4. As the decision-making unit of the dynamic comparator, the latch module 4 primarily compares the amplified signals output by the dynamic differential amplifier module 2 through a positive feedback mechanism and locks in the final comparison result. Upon receiving the differential amplified signal, the positive feedback rapidly amplifies the difference between the two signals, causing the output state to quickly converge to a logic high ("1") or low ("0"), avoiding delays in intermediate states. The "avalanche effect" of positive feedback enables extremely fast comparisons, significantly improving the overall response speed of the dynamic comparator.

[0068] For example, a dynamic differential amplifier module 2 is introduced, the power supply end of the dynamic differential amplifier module 2 is connected to the power supply 100, and the first signal input end and the second signal input end are connected to the first input signal and the second input signal respectively. Based on the differential amplification mechanism, by detecting the voltage difference between the two input signals, the common mode noise is suppressed and the effective differential signal is amplified. The high gain allows even small differences in the input signals to be amplified into significant voltage changes, for example, a 0.1mV input difference is amplified into a 10mV output difference, providing a more resolvable signal for the subsequent latch module 4, thereby greatly improving the sensitivity and accuracy of the comparator. In addition, in order to achieve zero power consumption in the reset phase, a clamping signal and a clock signal are introduced at the same time to accurately control the working state of the dynamic amplifier module and the latch module 4. The operation of the dynamic comparator is divided into a reset phase and a comparison phase, which are divided by the clock signal. For example, in the reset phase, the clock signal is high and the clamping signal is in an effective state. At this point, the dynamic differential amplifier module 2 can disconnect the current source by, for example, switching the current source, causing it to enter a locked state, not perform amplification, and achieve near-zero power consumption. Under the action of the clamping signal, the latch module 4 clamps the input node to a fixed level, while the clock signal shuts off its positive feedback path, placing it in a high-impedance state or reset state, also achieving zero power consumption. During the comparison phase, the clock signal becomes low, the clamping signal becomes invalid, and the two modules are activated, performing differential amplification and positive feedback latching functions, respectively. Based on the positive feedback function of the latch module 4, the comparison speed of the dynamic comparator is significantly improved. When the clock signal becomes low during the comparison phase, the latch module 4 is unlocked, and the amplified signal output by the dynamic differential amplifier module 2 is used as input. The positive feedback loop formed by the cross-coupled inverters rapidly amplifies the difference in the input signals, forming a stable logical state.

[0069] The above-mentioned dynamic comparator improves the gain to ensure comparison accuracy by introducing the dynamic differential amplifier module 2, uses the clamp signal and clock signal to control the working state to achieve zero-power reset, and combines the positive feedback mechanism of the latch module 4 to improve the comparison speed. The various functions complement each other and effectively meet the strict requirements of high precision, high speed and low power consumption in scenarios such as high-speed data acquisition and analog-to-digital conversion.

[0070] In an exemplary embodiment, Figure 3As shown, the dynamic differential amplifier module 2 includes an energy storage unit 21, an input amplifier unit 23, a first controlled switch unit 25, and a second controlled switch unit 27. The power supply terminal of the energy storage unit 21 is connected to the power supply 100 via the first controlled switch unit 25, the power supply terminal of the energy storage unit 21 is connected to the power supply terminal of the input amplifier unit 23, the first signal output terminal of the input amplifier unit 23 is connected to the first signal input terminal of the latch module 4, and the second signal output terminal of the input amplifier unit 23 is connected to the second signal input terminal of the latch module 4. The first signal input terminal and the second signal input terminal of the latch module 4 are also connected to the clamping signal via the second controlled switch unit 27. When the dynamic comparator is in the reset phase, the first controlled switch unit 25 and the second controlled switch unit 27 are both in the on state. When the dynamic comparator is in the comparison phase, the first controlled switch unit 25 and the second controlled switch unit 27 are both in the off state.

[0071] For example, during the reset phase, the first controlled switch unit 25 is in the on state, and the energy storage unit 21 is directly connected to the power supply 100 and the ground terminal, so that the energy storage unit 21 is in a short-circuit state, thereby being unable to power the input amplification unit 23. Secondly, when the second controlled switch unit 27 is in the on state, from the perspective of the circuit connection relationship, the clamping signal can act not only on the latch module 4, but also on the first signal output terminal and the second signal output terminal of the input amplification unit 23 to suppress the output of the input amplification unit 23, thereby further controlling the input amplification unit 23 in a locked state, ensuring that the dynamic comparator has no static energy consumption during the reset phase. In the comparison stage, the first controlled switch unit 25 is in the disconnected state, the energy storage unit 21 is not short-circuited, and can supply power to the input amplifier unit 23. The input amplifier unit 23 starts to work, and since the second controlled switch unit 27 is also in the disconnected state, the input amplifier unit 23 and the latch module 4 are not suppressed by the clamping signal. The input amplifier unit 23 performs differential amplification on the received first input signal and the second input signal, and outputs the first amplified signal and the second amplified signal to the latch module 4, so that the latch module 4 performs rapid comparison and latching, and outputs a comparison result signal.

[0072] In this embodiment, low-power consumption and high-efficiency control of the dynamic comparator are achieved by switching the states of the first controlled switch unit 25 and the second controlled switch unit 27 between the reset phase and the comparison phase. In the reset phase, the two switch units are turned on, short-circuiting the energy storage unit 21 and clamping the signal to suppress the input amplifier unit 23 and the latch module 4, ensuring no static energy consumption. In the comparison phase, the two switch units are turned off, allowing the energy storage unit 21 to power the input amplifier unit 23, and combining with the latch module 4 to achieve differential amplification, comparison, and latching of the signal, thereby precisely controlling the circuit operating state at different stages. This not only reduces static power consumption, but also ensures comparison speed and accuracy through dynamic power supply and signal processing, thereby improving overall energy efficiency.

[0073] In an exemplary embodiment, Figure 3 As shown, the energy storage unit 21 includes a tail capacitor C tail1 and tail capacitor C tail2 The first controlled switch unit 25 includes a controlled switch S1 and a controlled switch S2, and the second controlled switch unit 27 includes a controlled switch S3 and a controlled switch S4. tail1 The positive plate is connected to the positive electrode of the power supply 100 through the controlled switch S1, and the tail capacitor C tail1 The negative plate is connected to the positive power supply terminal of the input amplifier unit 23; the tail capacitor C tail2 The positive plate is connected to the negative electrode of the power supply 100 through the controlled switch S2, and the tail capacitor C tail2 The negative plate of the latch module 4 is connected to the negative power supply terminal of the input amplification unit 23, the first signal input terminal of the latch module 4 is connected to the clamping signal through the controlled switch S3, and the second signal input terminal of the latch module 4 is connected to the clamping signal through the controlled switch S4; when the dynamic comparator is in the reset stage, the controlled switch S1, the controlled switch S2, the controlled switch S3 and the controlled switch S4 are all in the on state; when the dynamic comparator is in the comparison stage, the controlled switch S1 and the controlled switch S2 are in the off state, and the controlled switch S3 and the controlled switch S4 are all in the off state.

[0074] For example, in the reset phase, the controlled switch S1 and the controlled switch S2 are closed, and the tail capacitor C tai11 Connected to the power supply 100, the tail capacitor C tai12 The voltage difference across the capacitor is zero; the controlled switch S3 and the controlled switch S4 are also closed, and the first signal output terminal and the second signal output terminal of the input amplifier unit 23, and the first signal input terminal and the second signal input terminal of the latch module 4 are connected to the clamping signal V cm In this way, the input amplifier unit 23 does not work due to the lack of effective power supply and clamping signal, thereby achieving no energy consumption in the reset phase. In the comparison phase, the controlled switch S1 and the controlled switch S2 are disconnected, and the tail capacitor C tai11 and tail capacitor Ctai12 As a power supply to support the input amplifier unit 23 to work, the tail capacitor C tai11 The voltage of the tail capacitor C tail2 The voltage of the gate is gradually raised, forming a conductive loop. Controlled switches S3 and S4 are also disconnected. Without the suppression effect of the clamp signal, the input amplifier unit 23 can receive the first and second input signals and perform differential amplification to obtain first and second amplified signals, which are then output to the first and second signal input terminals of the latch module 4. This allows the latch module 4 to quickly perform comparison and latching, and output a comparison result signal.

[0075] In this embodiment, the low power consumption and precise control of the dynamic comparator are achieved by switching the state of the controlled switch unit in the reset phase and the comparison phase. In the reset phase, the controlled switches S1, S2, S3, and S4 are all turned on, and the tail capacitor C tail1 and C tail2 Since the voltage difference is zero due to the direct connection between the power supply and the ground, the input amplifier unit 23 cannot be powered, and the signal V cm Controlled switches S3 and S4 act on input amplifier unit 23 and latch module 4, placing them in a locked state and ensuring no static energy consumption in the circuit. During the comparison phase, controlled switches S1, S2, S3, and S4 are all disconnected, and the tail capacitor acts as an independent power supply to power input amplifier unit 23, enabling it to differentially amplify the first and second input signals and output them to latch module 4. This eliminates the suppression of the clamping signal, allowing latch module 4 to quickly complete comparison and latching. By controlling the power on / off and signal path in stages, power consumption during the reset phase is significantly reduced, while signal processing speed and accuracy are guaranteed during the comparison phase, improving the overall energy efficiency and reliability of the dynamic comparator.

[0076] In an exemplary embodiment, Figure 4As shown, the dynamic differential amplification module 2 includes an energy storage unit 20 , an input amplification unit 23 , a third controlled switch unit 24 , a fourth controlled switch unit 26 and a fifth controlled switch unit 28 . Among them, the power supply end of the energy storage unit 20 is connected to the power supply 100 through the third controlled switch unit 24, the power supply end of the input amplification unit 23 is connected to the power supply end of the energy storage unit 20 through the fourth controlled switch unit 26, the first signal output end of the input amplification unit 23 is connected to the first signal input end of the latch module 4, and the second signal output end of the input amplification unit 23 is connected to the second signal input end of the latch module 4. The first signal input end and the second signal input end of the latch module 4 are also connected to the clamping signal through the fifth controlled switch unit 28; when the dynamic comparator is in the reset stage, the third controlled switch unit 24 and the fifth controlled switch unit 28 are both in the on state, and the fourth controlled switch unit 26 is in the off state; when the dynamic comparator is in the comparison stage, the third controlled switch unit 24 and the fifth controlled switch unit 28 are both in the off state, and the fourth controlled switch unit 26 is in the on state.

[0077] Illustratively, in the reset phase, the third controlled switch unit 24 is in the on state, and the power supply 100 charges the energy storage unit 20. However, since the fourth controlled switch unit 26 is in the off state, the energy storage unit 20 cannot supply power to the input amplification unit 23. At the same time, the fifth controlled switch unit 28 is in the on state. From the perspective of the circuit connection relationship, the clamping signal can not only act on the latch module 4, but also on the first signal output terminal and the second signal output terminal of the input amplification unit 23 to suppress the output of the input amplification unit 23, thereby further controlling the input amplification unit 23 in a locked state, ensuring that the dynamic comparator has no static energy consumption in the reset phase. During the comparison phase, the third controlled switch unit 24 is in the disconnected state, the power supply 100 stops charging the energy storage unit 20, and the fourth controlled switch unit 26 is in the on state, the energy storage unit 20 starts to power the input amplifier unit 23, and at the same time, the fifth controlled switch unit 28 is in the disconnected state, there is no input of the clamping signal, and neither the input amplifier unit 23 nor the latch module 4 suppresses the clamping signal. The input amplifier unit 23 performs differential amplification on the received first input signal and the second input signal, and outputs the first amplified signal and the second amplified signal to the latch module 4, so that the latch module 4 performs rapid comparison and latching, and outputs a comparison result signal.

[0078] In this embodiment, precise power consumption management and efficient signal processing of the dynamic comparator are achieved in different operating stages by controlling the on-off states of the switch units in stages. During the reset stage, the third controlled switch unit 24 is turned on to complete charging of the energy storage unit 20. At the same time, the fourth controlled switch unit 26 is disconnected to cut off the power supply connection between the energy storage unit 20 and the input amplifier unit 23. The fifth controlled switch unit 28 is turned on to introduce a clamping signal to lock the output of the input amplifier unit 23 and the latch module 4, ensuring that the circuit has no static current consumption. During the comparison stage, the third controlled switch unit 24 and the fifth controlled switch unit 28 are disconnected to stop charging and remove the clamping signal. The fourth controlled switch unit 26 is turned on to enable the energy storage unit 20 to power the input amplifier unit 23, supporting it to perform differential amplification of the input signal and drive the latch module 4 to quickly complete the comparison and latching. Through time-sharing control of power charging and power supply, combined with dynamic intervention and exit of the clamping signal, low power consumption characteristics are achieved in the reset stage, and the speed and accuracy of signal processing are guaranteed through independent power supply of the energy storage unit 20 in the comparison stage, effectively improving the energy efficiency and working reliability of the dynamic comparator.

[0079] In an exemplary embodiment, Figure 4 As shown, the energy storage unit 20 includes an energy storage capacitor C RES The third controlled switch unit 24 includes a controlled switch S11 and a controlled switch S12, the fourth controlled switch unit 26 includes a controlled switch S21 and a controlled switch S22, and the fifth controlled switch unit 28 includes a controlled switch S31 and a controlled switch S32. RES The positive plate is connected to the positive electrode of the power supply 100 through the controlled switch S11, and the energy storage capacitor C RES The negative plate is connected to the negative electrode of the power supply 100 through the controlled switch S12, and the energy storage capacitor C RES The positive plate is also connected to the positive power supply terminal of the input amplifier unit 23 through the controlled switch S21, and the energy storage capacitor C RES The negative plate is also connected to the negative power supply terminal of the input amplification unit 23 through the controlled switch S22. The first signal input terminal of the latch module 4 is connected to the clamping signal through the controlled switch S31, and the second signal input terminal of the latch module 4 is connected to the clamping signal through the controlled switch S32. When the dynamic comparator is in the reset stage, the controlled switches S11, S12, S31 and S32 are all in the on state, and the controlled switches S21 and S22 are in the off state. When the dynamic comparator is in the comparison stage, the controlled switches S11, S12, S31 and S32 are all in the off state, and the controlled switches S21 and S22 are in the on state.

[0080] For example, in the reset phase, the controlled switches S11 and S12 are closed, and the controlled switches S21 and S22 are opened. At this time, the energy storage capacitor C RES The positive plate is connected to the power supply 100 and the negative plate is grounded. The power supply 100 is the energy storage capacitor C RES At the same time, the controlled switches S31 and S32 are closed, and the first signal output terminal and the second signal output terminal of the input amplifier unit 23, and the first signal input terminal and the second signal input terminal of the latch module 4 are all connected to the clamping signal V cm In this way, the input amplifier unit 23 does not work due to the lack of effective power supply and clamping signal, thereby achieving no energy consumption in the reset phase. In the comparison phase, the controlled switches S11 and S12 are disconnected, the controlled switches S21 and S22 are closed, and the energy storage capacitor C RES The input amplifier unit 23 is powered as an independent power supply. At the same time, the controlled switches S31 and S32 are disconnected. Without the suppression effect of the clamp signal, the input amplifier unit 23 can receive the first input signal and the second input signal, and obtain the first amplified signal and the second amplified signal through differential amplification. The first amplified signal and the second amplified signal are then output to the first signal input terminal and the second signal input terminal of the latch module 4, so that the latch module 4 can quickly compare and latch and output the comparison result signal.

[0081] In this embodiment, the low power consumption operation and efficient signal processing of the dynamic comparator at different stages are achieved through the coordinated control of multiple groups of controlled switch units. In the reset stage, the controlled switches S11 and S12 are turned on to make the energy storage capacitor C RES The power supply 100 is charged and stored, and at the same time, the controlled switches S21 and S22 are disconnected to cut off the power supply connection with the input amplifier unit 23, and the controlled switches S31 and S32 are turned on to introduce the clamping signal V cm The output of the input amplifier unit 23 and the latch module 4 is locked to ensure that the circuit is only charged and not working, and there is no static energy consumption; in the comparison stage, the controlled switches S11, S12, S31, and S32 are disconnected to stop charging and remove the clamping signal, and the controlled switches S21 and S22 are turned on to make the energy storage capacitor C RES It serves as an independent power supply for the input amplifier unit 23, enabling it to differentially amplify the input signal and drive the latch module 4 to quickly complete comparison and latching. This design, through time-sharing multiplexing of power charging and power supply, and dynamic insertion and exit of the clamping signal, not only utilizes the energy storage capacitor to achieve efficient energy storage and release, but also significantly reduces power consumption during the reset phase through phased control. It also ensures the speed and accuracy of signal processing during the comparison phase, effectively improving the overall energy efficiency and reliability of the dynamic comparator.

[0082] In an exemplary embodiment, Figure 3 and Figure 4 As shown, the latch module 4 comprises an input pair unit 40 and a latch unit 42. The power supply end of the input pair unit 40 is used to access the power supply 100, the first signal input end of the input pair unit 40 is connected with the first signal output end of the dynamic differential amplification module 2, the second signal input end of the input pair unit 40 is connected with the second signal output end of the dynamic differential amplification module 2, the first signal input end and the second signal input end of the input pair unit 40 are also used to access the clamping signal, and the control end of the input pair unit 40 is used to access the clock signal. The first input end of the latch unit 42 is connected with the first output end of the input pair unit 40, the second input end of the latch unit 42 is connected with the second output end of the input pair unit 40, the control end of the latch unit 42 is used to access the clock signal, and the signal output end of the latch unit 42 is used to output the comparison result signal.

[0083] Exemplarily, in the reset phase, for example, the clock signal is high, at this time, the input pair unit 40 is controlled by the clock signal to cut off the power supply of the power supply 100, and at the same time, under the action of the clamping signal, the input pair unit 40 cannot receive and perform differential amplification processing on the input signal to output the amplified signal. Therefore, in the reset phase, the input pair unit 40 is also in a locked state without energy consumption, and the latch unit 42 is also in a locked state due to the action of the clock signal without energy consumption. In the comparison phase, for example, the clock signal is low, the input pair unit 40 is controlled by the clock signal to turn on the power supply link of the power supply 100, and at the same time, the input of the clamping signal is stopped. Since in the comparison phase, the dynamic differential amplification module 2 normally receives the first input signal and the second input signal for differential amplification and outputs the first amplified signal and the second amplified signal, therefore, in the comparison phase, the input pair unit 40 can receive the first amplified signal and the second amplified signal under the action of the power supply 100 without the clamping signal and input them to the latch unit 42 after processing. And the latch unit 42 starts to work under the control of the clock signal, receives the signal input by the input pair unit 40, and based on the positive feedback function of the latch unit 42, performs fast comparison and latching.

[0084] In this embodiment, the low power consumption and high efficiency switching of the latch module 4 in different stages are achieved through the coordinated control of the clock signal and the clamp signal. In the reset stage, the clock signal controls the input pair unit 40 to cut off the power supply 100, and locks its input port through the clamp signal, so that the input pair unit 40 and the latch unit 42 are both in a non-working state, completely eliminating static energy consumption; in the comparison stage, the clock signal turns on the power supply link of the input pair unit 40 and removes the clamp signal, so that it can receive the amplified signal output by the dynamic differential amplifier module 2 and perform differential processing, while triggering the latch unit 42 to quickly complete signal comparison and latching using a positive feedback mechanism. This design not only ensures the zero power consumption characteristics in the reset stage through precise control of the timing logic and signal path, but also significantly improves the latch speed and comparison accuracy through power activation and signal release in the comparison stage, achieving a balance between low power consumption and high performance of the dynamic comparator.

[0085] In an exemplary embodiment, Figure 3 and 4 As shown, the input pair unit 40 includes a switch tube M0, a switch tube M1, a switch tube M2, an auxiliary switch tube M11, and an auxiliary switch tube M22. Among them, the source of the switch tube M0 is used to connect to the power supply 100, the gate of the switch tube M0 is used to connect to the clock signal, and the drain of the switch tube M0 is respectively connected to the source of the switch tube M1, the source of the switch tube M2, the source of the auxiliary switch tube M11, and the source of the auxiliary switch tube M22; the gate of the switch tube M1 is connected to the first signal output terminal of the dynamic differential amplifier module 2, and the gate of the switch tube M1 is also used to connect to the clamping signal. The drain of the switch tube M1 is respectively connected to the first input terminal of the latch unit 42 and the drain of the auxiliary switch tube M11; The gate of the switch M2 is connected to the second signal output terminal of the dynamic differential amplifier module 2. The gate of the switch M2 is also used to receive the clamping signal. The drain of the switch M2 is respectively connected to the second input terminal of the latch unit 42 and the drain of the auxiliary switch M22. The gates of the auxiliary switch M11 and the auxiliary switch M22 are both used to receive the power supply 100. When the dynamic comparator is in the reset stage, the switch M0 is in the off state. When the dynamic comparator is in the comparison stage, the switch M0 is in the on state.

[0086] For example, during the reset phase, the clock signal is at a high level, switch M0 is in the off state, no current flows into switch M1, switch M2, auxiliary switch M11, and auxiliary switch M22, and the entire input pair unit 40 consumes no energy and outputs no signal. During the comparison phase, the clock signal is at a low level, switch M0 is in the on state, and the voltage of the power supply 100 is applied to the source of switch M1 and the source of switch M2. At this time, the clamp signal stops being output, and the dynamic differential amplifier module 2 operates normally to output the first amplified signal and the second amplified signal. The gate of switch M1 receives the first amplified signal, and the gate of switch M2 receives the second amplified signal. At this time, both switch M1 and switch M2 are turned on, thereby outputting the signal to the latch unit 42. The auxiliary switches M11 and M22 in the input pair unit 40 can eliminate the effects of voltage changes applied by the power supply 100 to the source electrodes of the switches M1 and M2 on the first amplified signal received by the gate of the switches M1 and M2, respectively, thereby further improving comparison accuracy. Specifically, the auxiliary switches M11 and M22 are structurally symmetrical and have matching parasitic capacitances with the switches M1 and M2, respectively. When the voltage changes applied by the power supply 100 to the source electrodes of the switches M1 and M2, the auxiliary switches M11 and M22 utilize the same parasitic capacitance coupling and synchronized channel charge release and absorption processes to generate interference signals of equal magnitude and opposite polarity to those of the main switches (switches M1 and M2). This cancels out the feedthrough effects of the main switches on the first and second input signals, thereby significantly improving the comparison accuracy of the comparator.

[0087] In this embodiment, an optimized balance between low power consumption and high precision is achieved for input pair unit 40 through a time-sharing power supply and parasitic effect compensation mechanism. During the reset phase, the clock signal controls the shutdown of switch M0, severing the power supply path and eliminating energy consumption in input pair unit 40. During the comparison phase, M0 switches on, simultaneously removing the clamp signal and allowing the differential amplified signal to be transmitted to latch unit 42 via switches M1 and M2. Specifically, the auxiliary switches M11 and M22 employ a symmetrical design with the main switches (M1 and M2). When the supply voltage fluctuates, the coupling interference generated by their parasitic capacitances cancels out the main switches. The synchronized channel charge changes further suppress feedthrough, ensuring the purity of the first and second amplified signals and significantly improving comparator accuracy. This design not only reduces static power consumption through time-sharing power supply but also eliminates parasitic interference through symmetrical compensation. It is particularly suitable for applications with stringent comparison accuracy requirements in high-speed, low-power scenarios.

[0088] In an exemplary embodiment, Figure 3 and Figure 4 As shown, the latch unit 42 is a dynamic latch.

[0089] Among them, the specific structure of the dynamic latch is as follows Figure 3 and Figure 4 As shown, the dynamic latch includes switch tubes M3, M4, M5, M6, M7, M8, M9, and M10. The source of switch tube M3 is connected to the drain of switch tube M1 and the drain of switch tube M7 respectively, the drain of switch tube M3 is connected to the drain of switch tube M4, the gate of switch tube M5, the gate of switch tube M6, and the drain of switch tube M8 respectively, the gate of switch tube M3 is connected to the gate of switch tube M4, the drain of switch tube M5, the drain of switch tube M6, and the drain of switch tube M9 respectively; the source of switch tube M4 is connected to the source of switch tube M6, the source of switch tube M7, and the source of switch tube M8 respectively. The source of the switch tube M9 is connected to the source of the switch tube M10, and the source of the switch tube M4 is also grounded; the source of the switch tube M5 is connected to the drain of the switch tube M2 and the switch tube M10 respectively; the gate of the switch tube M7, the gate of the switch tube M8, the gate of the switch tube M9 and the gate of the switch tube M10 are all used to receive the clock signal; the connection point between the drain of the switch tube M3 and the drain of the switch tube M4, and the connection point between the drain of the switch tube M5 and the drain of the switch tube M6 serve as the signal output terminal V of the dynamic latch. on and V op ; When the dynamic comparator is in the reset stage, the switch tubes M7, M8, M9 and M10 are all in the on state; when the dynamic comparator is in the comparison stage, the switch tubes M7, M8, M9 and M10 are all in the off state.

[0090] For example, in the reset phase, the clock signal is at a high level. Under the action of the clock signal, the switch tubes M7, M8, M9, and M10 are all turned on, so that the drain voltage of the switch tube M1 and the drain voltage of the switch tube M2 are pulled to zero level, and the output terminal V on and V op The voltages of the switches M7, M8, M9, and M10 are all turned off, so that the drain voltages of the switches M1 and M2 are determined by the working state of the dynamic latch. in , the second input signal is V ip , V in >V ipFor example, after being processed by the input amplifier unit 23, the first amplified signal V+ and the second amplified signal V- are output. At this time, V+<V-, the conduction capability of the switch tube M1 is stronger than the conduction capability of the switch tube M2. Therefore, the drain voltage of the switch tube M1 (and the source voltage of the switch tube M3) is pulled up faster than the drain voltage of the switch tube M2 (and the source voltage of the switch tube M5). In addition, because in the reset stage, the output terminal of the dynamic latch (V op and V on ) voltage (i.e., the gate voltage of the switch tube M3 and the switch tube M5) are both zero level. At the moment the comparison phase starts, the source voltage of the switch tube M3 is higher than the source voltage of the switch tube M5. Therefore, the overdrive voltage V gs -V th The larger the switch M3 is, the stronger the conduction capability is, making the drain of the switch tube M3 (that is, the output terminal V corresponding to the latch) on ) is quickly pulled high, the latch output V op It is quickly pulled down to zero level; at the same time, the latch structure formed by the switch tube M3, the switch tube M4 and the switch tube M6 provides positive feedback to quickly lock the output state.

[0091] In this embodiment, high-speed locking of the comparison result and low-power operation are achieved through the time-sharing control and positive feedback mechanism of the dynamic latch. In the reset phase, the clock signal controls the switch tubes M7-M10 to turn on, pulling the drain voltage of the input pair unit 40 and the latch output to zero level, while cutting off the power supply path to ensure that the latch has no static current consumption; in the comparison phase, the clock signal turns off M7-M10, and the latch is based on the differential signal of the input pair unit 40 (such as V in >V ip When V+<V-) triggers the positive feedback mechanism of the switch tubes M3-M6, which quickly amplifies the signal difference by overdriving the voltage difference, so that the output terminal V on Quickly pull up, V op Pulling the latch low and using positive feedback to quickly lock the state. The clock signal accurately switches the working state of the latch, eliminating power consumption during the reset phase. In the comparison phase, the dynamic current mirror and positive feedback structure are used to achieve nanosecond fast latching, significantly improving the speed and energy efficiency of the comparator.

[0092] In an exemplary embodiment, Figure 3 and Figure 4As shown, the input amplification unit 23 comprises a first amplification unit 231 and a second amplification unit 235. The power supply end of the first amplification unit 231 is connected to the power supply end of the energy storage unit 21 (20), and the signal input end of the first amplification unit 231 is used to access the first input signal; the power supply end of the second amplification unit 235 is connected to the power supply end of the energy storage unit 21 (20), and the signal input end of the second amplification unit 235 is used to access the second input signal; in the case that the dynamic comparator is in the reset phase, the first amplification unit 231 and the second amplification unit 235 are both in the locked state; in the case that the dynamic comparator is in the comparison phase, the first amplification unit 231 outputs the first amplified signal based on the first input signal, and the second amplification unit 235 outputs the second amplified signal based on the second input signal.

[0093] In some specific embodiments, as shown in FIG. 2, the first amplification unit 231 and the second amplification unit 235 are directly connected to the energy storage unit 21. Figure 3 As shown in FIG. 3, the first amplification unit 231 and the second amplification unit 235 can be connected to the energy storage unit 20 through the fourth controlled unit. Figure 4 As shown in FIG. 3, the first amplification unit 231 and the second amplification unit 235 can be connected to the energy storage unit 20 through the fourth controlled unit.

[0094] As shown in FIG. 3, the first amplification unit 231 and the second amplification unit 235 can be connected to the energy storage unit 20 through the fourth controlled unit.

[0095] In one exemplary embodiment, the first amplification unit 231 comprises a switch tube MP1, a switch tube MN1 and a first integral capacitor C X1 ; wherein the source of the switch tube MP1 is connected to the positive power supply end of the energy storage unit 21 (20), the drain of the switch tube MP1 is connected to the drain of the switch tube MN1, the positive plate of the first integral capacitor C X1 and the first signal input end of the latch module 4, the source of the switch tube MN1 is connected to the negative power supply end of the energy storage unit 21 (20), the gate of the switch tube MP1 and the gate of the switch tube MN1 are both used to access the first input signal, and the negative plate of the first integral capacitor C X1 The second amplification unit comprises a switch tube MP2, a switch tube MN2 and a second integral capacitor C X2The source of the switch tube MP2 is connected to the positive power supply terminal of the energy storage unit 21 (20), and the drain of the switch tube MP2 is connected to the drain of the switch tube MN2 and the second integral capacitor C X2 and the second signal input terminal of the latch module 4, the source of the switch tube MN2 is connected to the negative power supply terminal of the energy storage unit 21 (20), the gate of the switch tube MP1 and the gate of the switch tube MN1 are both used to access the second input signal, and the second integral capacitor C X2 The negative plate is grounded.

[0096] Among them, in some specific embodiments, such as Figure 3 As shown, the switch tube MP1, the switch tube MN1, the switch tube MP2 and the switch tube MN2 can be directly connected to the energy storage unit 21; in other specific embodiments, such as Figure 4 As shown, the switch tubes MP1 , MN1 , MP2 and MN2 can be connected to the energy storage unit 20 via the fourth controlled switch unit 26 .

[0097] For example, in a specific embodiment, Figure 3 As shown, for the case where the dynamic differential amplifier module 2 includes an energy storage unit 21, an input amplifier unit 23, a first controlled switch unit 25, and a second controlled switch unit 27, in the reset phase, the first controlled switch unit 25 is in the on state, and the energy storage unit 21 is directly connected to the power supply 100 and the ground terminal, so that the energy storage unit 21 is in a short-circuit state, thereby being unable to provide voltage to the source of the switch tube MP1 and the source of the switch tube MP2. Secondly, when the second controlled switch unit 27 is in the on state, the first integral capacitor C X1 The positive plate (ie, the drain of the switch tube MP1) and the second integral capacitor C X2 The positive plate (ie, the drain of the switch MP2) is connected to the clamping signal V cm , thereby turning off the switch transistors MP1, MN1, MP2, and MN2 without power supply and the clamp signal, thereby achieving no static energy consumption during the reset phase. In the comparison phase, the first controlled switch unit 25 is in the off state, the energy storage unit 21 is not short-circuited, and can provide voltage to the source of the switch transistor MP1 and the source of the switch transistor MP2. Since the second controlled switch unit 27 is also in the off state, the input amplifier unit 23 and the first integral capacitor C X1 The positive plate (ie, the drain of the switch tube MP1) and the second integral capacitor C X2 The positive plate (ie, the drain of the switch MP2) is not connected to the clamping signal V cm, so that the switch tubes MP1, MN1, MP2 and MN2 can be turned on, thereby outputting the first amplified signal and the second amplified signal to the latch module 4, so that the latch module 4 can quickly compare and latch and output the comparison result signal.

[0098] Under the above premise, the energy storage unit 21 includes the tail capacitor C tail1 and tail capacitor C tail2 , the first controlled switch unit 25 includes a controlled switch S1 and a controlled switch S2, and the second controlled switch unit 27 includes a controlled switch S3 and a controlled switch S4. In the reset phase, the controlled switch S1 and the controlled switch S2 are closed, and the tail capacitor C tail1 Connected to the power supply, the tail capacitor C tail2 Connected to the ground, the voltage difference across the capacitor is zero; the controlled switch S3 and the controlled switch S4 are closed, the first integrating capacitor C X1 The positive plate (ie, the drain of the switch tube MP1) and the second integral capacitor C X2 The positive plate (ie, the drain of the switch MP2) is connected to the clamping signal V cm At this time, the switch tubes MP1, MN1, MP2 and MN2 are all in the cut-off state, and there is no static energy consumption. In the comparison phase, the controlled switches S1 and S2 are disconnected, and the tail capacitor C tail1 and tail capacitor C tail2 As a power supply to support the first amplifying unit 231 and the second amplifying unit 235 to work, that is, at this time, the tail capacitor C tail1 The voltage through V SP is gradually pulled down, the tail capacitor C tail2 The voltage through V SN The voltage at the output terminal V+ of the first amplifier unit 231 and the voltage at the output terminal V- of the second amplifier unit 235 are determined by the conduction states of the switch tubes MP1, MN1, MP2, and MN2. At the same time, the voltage at the output terminal V+ of the first amplifier unit 231 is input to the gate of the switch tube M1, and the voltage at the output terminal V- of the second amplifier unit 235 is input to the gate of the switch tube M2, thereby controlling the conduction states of the switch tubes M1 and M2. tail1 and tail capacitor C tail2 The structure has the following advantages: On the one hand, taking the switch tube MN1 and the switch tube MN2 as NMOS tubes as an example, since in the comparison stage, the tail capacitor C tail2 The voltage across the line V SN is gradually raised, and the line V SN The voltage of the switch tube MN1 and the switch tube MN2 is also raised, and the gate-source voltage V gs In this process, as V SNThe voltage of the first integral capacitor C is gradually raised to the cut-off point, the switch tubes MN1 and MN2 are turned off, and the dynamic integration stops, avoiding the X1 and the second integrating capacitor C X2 On the other hand, in the comparison phase, as described above and in the background art, due to the gate-source voltage V gs Lowering the g of the switch tube m (Transconductance) / I d (drain current) increases, and due to the input reference noise of the input amplifier unit 23 and g m (Transconductance) / I d (drain current), so for the input amplifier unit 23 composed of the switch tube MP1, the switch tube MN1, the switch tube MP2 and the switch tube MN2, the g of the switch tube MP1 and the switch tube MP2 is inversely proportional. m (Transconductance) / I d When the (drain current) is increased, the input referred noise input to the latch module 4 is reduced.

[0099] In another specific embodiment, Figure 4 As shown, for the case where the dynamic differential amplifier module 2 includes an energy storage unit 20, an input amplifier unit 23, a third controlled switch unit 24, a fourth controlled switch unit 26, and a fifth controlled switch unit 28, in the reset phase, the third controlled switch unit 24 is in the on state, and the power supply 100 charges the energy storage unit 20. However, since the fourth controlled switch unit 26 is in the off state, the energy storage unit 20 cannot provide voltage to the source of the switch tube MP1 in the first amplifier unit 231 and the source of the switch tube MP2 in the second amplifier unit 235; at the same time, the fifth controlled switch unit 28 is in the on state. From the perspective of the circuit connection relationship, the clamping signal V cmThe current not only acts on the latch module 4, but also on the drains of the switch transistors MP1 and MN1 in the first amplifying unit 231, and the drains of the switch transistors MP2 and MN2 in the second amplifying unit 235. Therefore, in this case, the switch transistors MP1, MN1, MP2, and MN2 are all turned off, and no static energy is consumed. During the comparison phase, the third controlled switch unit 24 is in the off state, the power supply 100 stops charging the energy storage unit 20, and the fourth controlled switch unit 26 is in the on state. The energy storage unit 20 provides voltage to the source of the switch tube MP1 in the first amplifying unit 231 and the source of the switch tube MP2 in the second amplifying unit 235. At the same time, the fifth controlled switch unit 28 is in the off state. No clamping signal is input to the switch tubes MP1, MN1, MP2, and MN2. Under the action of the energy storage unit 20, the switch tubes MP1, MN1, MP2, and MN2 can be normally turned on, thereby performing differential amplification to output the first amplified signal and the second amplified signal to the latch module 4, so that the latch module 4 can quickly compare and latch and output a comparison result signal.

[0100] Under the above premise, the energy storage unit 20 includes the energy storage capacitor C RES , the third controlled switch unit 24 includes a controlled switch S11 and a controlled switch S12, the fourth controlled switch unit 26 includes a controlled switch S21 and a controlled switch S22, and the fifth controlled switch unit 28 includes a controlled switch S31 and a controlled switch S32. In the reset phase, the controlled switches S11 and S12 are closed, and the controlled switches S21 and S22 are opened. At this time, the energy storage capacitor C RES The positive plate is connected to the power supply 100, the energy storage capacitor C RES The negative plate is grounded, and the energy storage capacitor C RES The voltage at both ends is VDD; at the same time, the controlled switch S31 and the controlled switch S32 are closed, and the first integral capacitor C X1 The positive plate and the second integrating capacitor C X2 The positive plates of the switches MP1, MN1, MP2, and MN2 are all in the cut-off state, with no operating current and no static energy consumption. In the comparison phase, the controlled switches S11 and S12 are disconnected, and the controlled switches S21 and S22 are closed. At this time, the energy storage capacitor C RES The positive plate is connected to the source of the switch tube MP1 and the source of the switch tube MP2, and the energy storage capacitor C RES The negative plate is connected to the source of the switch tube MN1 and the source of the switch tube MN2, and the energy storage capacitor C RESThe voltage at both ends is used as an independent variable voltage source, and the transient initial voltage value is VDD; at the same time, the controlled switch S31 and the controlled switch S32 are disconnected, and the first integral capacitor C X1 The positive plate and the second integrating capacitor C X2 The positive plates of the switches MP1, MN1, MP2, and MN2 are not connected to the clamping signal, and the switch tubes MP1, MN1, MP2, and MN2 can be turned on normally, thereby performing differential amplification to output the first amplified signal and the second amplified signal to the latch module 4, so that the latch module 4 can quickly compare and latch and output the comparison result signal.

[0101] Among them, the energy storage unit 20 is composed of the energy storage capacitor C RES The structure also realizes the function of resisting the change of common mode voltage and process angle. Since the current flowing in and out of the same branch must be equal, that is, the current flowing through the switch tube MP1 is equal to the current flowing through the switch tube MN1, and the current flowing through the switch tube MP2 is equal to the current flowing through the switch tube MN2, then the current flowing from the common mode terminals V+ and V- to the first integrating capacitor C X1 and the second integrating capacitor C X2 The current must be 0, so a constant output common-mode voltage can be achieved without adding a common-mode feedback circuit.

[0102] For the case where the input common mode voltage changes, assuming that the common mode voltage = 600mV, the input amplifier unit 23 works in a balanced manner. If the common mode voltage drops from 600mV to 400mV, at the initial moment, due to the gate-source voltage V gs It must be greater than the gate-source voltage V of the switch tube MN1 and the switch tube MN2 gs , the conduction capability of the switch tube MP1 and the switch tube MP2 is stronger; but in order to ensure that the current flowing through the switch tube MP1 and the switch tube MP2, the switch tube MP1 and the switch tube MP2 are consistent, the energy storage capacitor C RES As an independent voltage source, it will automatically shift down 200mV to balance the overdrive voltage of the switch tubes MP1 and MP2, and the overdrive voltage of the switch tubes MP1 and MP2. The situation where the common-mode voltage increases is similar and will not be repeated here.

[0103] When the process angle changes, the threshold voltage V of the switch tube MP1 and the switch tube MP2 under the SF process angle is th Reduce the gate-source voltage V of the switch tube MN1 and the switch tube MN2 gs Initially, both V+ and V- are pulled low. This shift in independent power domains causes the conduction capabilities of switches MP1 and MP2, and switches MN1 and MN2, to change in the same direction, aligning the currents in the upper and lower paths to maintain proper operation. The FS process corner also operates similarly and will not be further elaborated here.

[0104] In order to describe the embodiments of the present application in more detail, Figures 2 to 5 Describe:

[0105] Figure 3 This is a schematic diagram of a specific circuit structure of a dynamic comparator in one embodiment of the present application, which includes a dynamic differential amplifier module 2 consisting of an energy storage unit 21, an input amplifier unit 23, a first controlled switch unit 25, and a second controlled switch unit 27, and a latch module 4 consisting of an input pair unit 40 and a latch unit 42. The energy storage unit 21 includes a tail capacitor C tail1 and tail capacitor C tail2 The first controlled switch unit 25 includes a controlled switch S1 and a controlled switch S2, and the second controlled switch unit 27 includes a controlled switch S3 and a controlled switch S4; the input amplifier unit 23 includes a first amplifier unit 231 and a second amplifier unit 235, and the first amplifier unit 231 includes a switch tube MP1, a switch tube MN1 and a first integral capacitor C X1 The second amplifier unit includes a switch tube MP2, a switch tube MN2 and a second integral capacitor C X2 The input pair unit 40 includes a switch tube M0, a switch tube M1, a switch tube M2, an auxiliary switch tube M11 and an auxiliary switch tube M22; the latch unit 42 is a dynamic latch, and the dynamic latch includes a switch tube M3, a switch tube M4, a switch tube M5, a switch tube M6, a switch tube M7, a switch tube M8, a switch tube M9 and a switch tube M10. The connection relationship between the various electronic components can be known by those skilled in the art with reference to the drawings, and will not be repeated here. Figure 5 As shown in the timing diagram, the controlled switches S1 , S2 , S3 and S4 change in phase and are controlled by the PhiA signal. The timing relationship between the clock signal CLK and the PhiA signal is in phase.

[0106] In the reset phase, the controlled switches S1 and S2 are closed, and the tail capacitor C tail1 Connected to the power supply, the tail capacitor C tail2 Connected to the ground, the voltage difference across the capacitor is zero; the controlled switch S3 and the controlled switch S4 are closed, the first integrating capacitor C X1 The positive plate (ie, the drain of the switch tube MP1) and the second integral capacitor C X2 The positive plate (ie, the drain of the switch MP2) is connected to the clamping signal V cmAt this time, the switches MP1, MN1, MP2, and MN2 are all in the off state, with no static energy consumption. Furthermore, because the clock signal is high during the reset phase, the switch M0 is in the off state, and no current flows into the switches M1, M2, auxiliary switches M11, and M22. The entire input pair unit 40 consumes no energy, and no signal is output. Under the action of the clock signal, the switches M7, M8, M9, and M10 in the dynamic latch are all turned on, causing the drain voltages of the switches M1 and M2 to be pulled to zero level, and the output terminal V on and V op The voltages of the switches M0 and M1 are pulled to zero level; at the same time, the switch tube M0 controlled by the clock signal is in the off state, no current flows through the dynamic latch, no signal is output, and the entire dynamic latch has no static energy consumption.

[0107] In the comparison phase, the controlled switches S1 and S2 are disconnected, and the tail capacitor C tail1 and tail capacitor C tail2 As a power supply to support the first amplifying unit 231 and the second amplifying unit 235 to work, that is, at this time, the tail capacitor C tail1 The voltage through V SP is gradually pulled down, the tail capacitor C tail2 The voltage through V SN The voltage at the output terminal V+ of the first amplifier unit 231 and the voltage at the output terminal V- of the second amplifier unit 235 are determined by the conduction states of the switch tubes MP1, MN1, MP2, and MN2. At the same time, the voltage at the output terminal V+ of the first amplifier unit 231 is input to the gate of the switch tube M1, and the voltage at the output terminal V- of the second amplifier unit 235 is input to the gate of the switch tube M2, thereby controlling the conduction states of the switch tubes M1 and M2. tail1 and tail capacitor C tail2 The structure has the following advantages: On the one hand, taking the switch tube MN1 and the switch tube MN2 as NMOS tubes as an example, since in the comparison stage, the tail capacitor C tail2 The voltage across the line V SN is gradually raised, and the line V SN The voltage of the switch tube MN1 and the switch tube MN2 is also raised, and the gate-source voltage V gs In this process, as V SN The voltage of the first integral capacitor C is gradually raised to the cut-off point, the switch tubes MN1 and MN2 are turned off, and the dynamic integration stops, avoiding the X1 and the second integrating capacitor C X2On the other hand, in the comparison phase, as described above and in the background art, due to the gate-source voltage V gs Lowering the g of the switch tube m (Transconductance) / I d (drain current) increases, and due to the input reference noise of the input amplifier unit 23 and g m (Transconductance) / I d (drain current), so for the input amplifier unit 23 composed of the switch tube MP1, the switch tube MN1, the switch tube MP2 and the switch tube MN2, the g of the switch tube MP1 and the switch tube MP2 is inversely proportional. m (Transconductance) / I d When the (drain current) is increased, the input referred noise input to the latch module 4 is reduced.

[0108] Furthermore, because the clock signal is at a low level during the comparison phase, switch M0 is in the on state, and the voltage of the power supply 100 is applied to the source of switch M1 and the source of switch M2. At this time, the clamp signal stops being output, and the dynamic differential amplifier module 2 operates normally, outputting the first amplified signal and the second amplified signal. The gate of switch M1 receives the first amplified signal, and the gate of switch M2 receives the second amplified signal. At this time, both switch M1 and switch M2 are turned on, thereby outputting the signal to the latch unit 42. The auxiliary switches M11 and M22 in the input pair unit 40 can eliminate the effects of voltage changes applied by the power supply 100 to the source of switch M1 and the source of switch M2 on the first amplified signal received by the gate of switch M1 and the second amplified signal received by the gate of switch M2, thereby further improving comparison accuracy. Specifically, the auxiliary switch tube M11 has a symmetrical structure with the switch tube M1 and has matching parasitic capacitances, and the auxiliary switch tube M22 has a symmetrical structure with matching parasitic capacitances. When the voltage applied by the power supply 100 to the source electrodes of the switch tubes M1 and M2 changes, the same parasitic capacitance coupling and synchronized channel charge release and absorption processes are utilized to generate interference signals of equal magnitude and opposite polarity to those of the main switch tubes (switch tubes M1 and M2), thereby offsetting the feedthrough effect of the main switch tubes on the first input signal and the second input signal, thereby significantly improving the comparison accuracy of the comparator.

[0109] At this time, the switch tubes M7, M8, M9 and M10 in the dynamic latch are all turned off, so that the drain voltage of the switch tube M1 and the drain voltage of the switch tube M2 are determined by the working state of the dynamic latch. in , the second input signal is V ip , V in >V ipFor example, after being processed by the input amplifier unit 23, the first amplified signal V+ and the second amplified signal V- are output. At this time, V+<V-, the conduction capability of the switch tube M1 is stronger than the conduction capability of the switch tube M2. Therefore, the drain voltage of the switch tube M1 (and the source voltage of the switch tube M3) is pulled up faster than the drain voltage of the switch tube M2 (and the source voltage of the switch tube M5). In addition, because in the reset stage, the output terminal (Vo p and V on ) voltage (i.e., the gate voltage of the switch tube M3 and the switch tube M5) are both zero level. At the moment the comparison phase starts, the source voltage of the switch tube M3 is higher than the source voltage of the switch tube M5. Therefore, the overdrive voltage V gs -V th The larger the switch M3 is, the stronger the conduction capability is, making the drain of the switch tube M3 (that is, the output terminal V corresponding to the latch) on ) is quickly pulled high, the latch output V op It is quickly pulled down to zero level; at the same time, the latch structure formed by the switch tube M3, the switch tube M4 and the switch tube M6 provides positive feedback to quickly lock the output state.

[0110] Figure 4 This is a schematic diagram of a specific circuit structure of a dynamic comparator in another embodiment of the present application, which includes a dynamic differential amplifier module 2 consisting of an energy storage unit 20, an input amplifier unit 23, a third controlled switch unit 24, a fourth controlled switch unit 26, and a fifth controlled switch unit 28, and a latch module 4 consisting of an input pair unit 40 and a latch unit 42. The energy storage unit 20 includes an energy storage capacitor C RES The third controlled switch unit 24 includes a controlled switch S11 and a controlled switch S12, the fourth controlled switch unit 26 includes a controlled switch S21 and a controlled switch S22, and the fifth controlled switch unit 28 includes a controlled switch S31 and a controlled switch S32; the input amplifier unit 23 includes a first amplifier unit 231 and a second amplifier unit 235, the first amplifier unit 231 includes a switch tube MP1, a switch tube MN1 and a first integral capacitor C X1 The second amplifier unit includes a switch tube MP2, a switch tube MN2 and a second integral capacitor C X2 The input pair unit 40 includes a switch tube M0, a switch tube M1, a switch tube M2, an auxiliary switch tube M11 and an auxiliary switch tube M22; the latch unit 42 is a dynamic latch, and the dynamic latch includes a switch tube M3, a switch tube M4, a switch tube M5, a switch tube M6, a switch tube M7, a switch tube M8, a switch tube M9 and a switch tube M10. The connection relationship between the various electronic components can be known by those skilled in the art with reference to the drawings, and will not be repeated here. Figure 5As shown in the timing diagram, the controlled switches S11, S12, S31 and S32 change in phase and are controlled by the PhiA signal; the controlled switches S21 and S22 change in phase and are controlled by the PhiB signal; the PhiA signal and the PhiB signal are in anti-phase in the time domain.

[0111] In the reset phase, the controlled switches S11 and S12 are closed, and the controlled switches S21 and S22 are disconnected. At this time, the energy storage capacitor C RES The positive plate is connected to the power supply 100, the energy storage capacitor C RES The negative plate is grounded, and the energy storage capacitor C RES The voltage at both ends is VDD; at the same time, the controlled switch S31 and the controlled switch S32 are closed, and the first integral capacitor C X1 The positive plate and the second integrating capacitor C X2 The positive plates of the switches MP1, MN1, MP2, and MN2 are all connected to the clamping signal. At this time, the switches MP1, MN1, MP2, and MN2 are all in the cut-off state, with no operating current and no static energy consumption. In the reset phase, the clock signal is at a high level, the switch M0 is in the off state, and no current flows into the switches M1, M2, the auxiliary switches M11, and M22. The input pair unit 40 as a whole has no energy consumption and no signal output. Under the action of the clock signal, the switches M7, M8, M9, and M10 in the dynamic latch are all turned on, causing the drain voltage of the switches M1 and M2 to be pulled to zero level, and the output terminal V on and V op The voltages of the switches M0 and M1 are pulled to zero level; at the same time, the switch tube M0 controlled by the clock signal is in the off state, no current flows through the dynamic latch, no signal is output, and the entire dynamic latch has no static energy consumption.

[0112] In the comparison phase, the controlled switches S11 and S12 are disconnected, and the controlled switches S21 and S22 are closed. At this time, the energy storage capacitor C RES The positive plate is connected to the source of the switch tube MP1 and the source of the switch tube MP2, and the energy storage capacitor C RES The negative plate is connected to the source of the switch tube MN1 and the source of the switch tube MN2, and the energy storage capacitor C RES The voltage at both ends is used as an independent variable voltage source, and the transient initial voltage value is VDD; at the same time, the controlled switch S31 and the controlled switch S32 are disconnected, and the first integral capacitor C X1 The positive plate and the second integrating capacitor C X2The positive plate of the battery is not connected to the clamping signal, and the switch tube MP1, the switch tube MN1, the switch tube MP2 and the switch tube MN2 can normally conduct, thereby performing differential amplification to output the first amplification signal and the second amplification signal to the latch module 4, so that the latch module 4 performs fast comparison and latching to output a comparison result signal.

[0113] In addition, in the comparison stage, the clock signal is at a low level, the switch tube M0 is in a conductive state, the voltage of the power supply 100 is applied to the source of the switch tube M1 and the source of the switch tube M2, and at this time, the clamping signal stops outputting, the dynamic differential amplification module 2 normally works to output the first amplification signal and the second amplification signal, the gate of the switch tube M1 receives the first amplification signal, and the gate of the switch tube M2 receives the second amplification signal, at this time, the switch tube M1 and the switch tube M2 are both conductive, thereby outputting the signal to the latch unit 42. Among them, the auxiliary switch tube M11 and the auxiliary switch tube M22 in the input pair unit 40 can eliminate the influence of the voltage change of the power supply 100 applied to the source of the switch tube M1 and the source of the switch tube M2 on the first amplification signal received by the gate of the switch tube M1 and the second amplification signal received by the gate of the switch tube M2, so as to further improve the comparison accuracy. Specifically, the auxiliary switch tube M11 is symmetrical with the switch tube M1 in structure and the parasitic capacitances are matched, the auxiliary switch tube M22 is symmetrical with the switch tube M2 in structure and the parasitic capacitances are matched, when the voltage change of the power supply 100 applied to the source of the switch tube M1 and the source of the switch tube M2 changes, by using the same parasitic capacitance coupling and synchronous channel charge release and absorption process, an interference signal equal in size and opposite in polarity to the main switch tube (the switch tube M1 and the switch tube M2) is generated, which offsets the feedthrough influence of the main switch tube on the first input signal and the second input signal, thereby significantly improving the comparison accuracy of the comparator.

[0114] At this time, the switch tube M7, the switch tube M8, the switch tube M9 and the switch tube M10 in the dynamic latch are all closed, so that the drain voltage of the switch tube M1 and the drain voltage of the switch tube M2 are determined by the working state of the dynamic latch. Taking the first input signal as V in , the second input signal as V ip , and V in >V ip , for example, after the processing of the input amplification unit 23, the first amplification signal V+ and the second amplification signal V- are output, at this time, V+<V-, the conduction ability of the switch tube M1 is stronger than that of the switch tube M2, therefore, the speed of pulling up the drain voltage of the switch tube M1 (and the source voltage of the switch tube M3) is faster than that of pulling up the drain voltage of the switch tube M2 (and the source voltage of the switch tube M5). In addition, in the reset stage, the output end (V op and V on) voltage (i.e., the gate voltage of the switch tube M3 and the switch tube M5) are both zero level, then at the moment the comparison phase starts, the source voltage of the switch tube M3 is higher than the source voltage of the switch tube M5, so the overdrive voltage Vg of the switch tube M3 is s -V th The larger the switch M3 is, the stronger the conduction capability is, making the drain of the switch tube M3 (that is, the output terminal V corresponding to the latch) on ) is quickly pulled high, the latch output V op It is quickly pulled down to zero level; at the same time, the latch structure formed by the switch tube M3, the switch tube M4 and the switch tube M6 provides positive feedback to quickly lock the output state.

[0115] Among them, the energy storage unit 20 is composed of the energy storage capacitor C RES The structure also realizes the function of resisting the change of common mode voltage and process angle. Since the current flowing in and out of the same branch must be equal, that is, the current flowing through the switch tube MP1 is equal to the current flowing through the switch tube MN1, and the current flowing through the switch tube MP2 is equal to the current flowing through the switch tube MN2, then the current flowing from the common mode terminals V+ and V- to the first integrating capacitor C X1 and the second integrating capacitor C X2 The current must be 0, so a constant output common-mode voltage can be achieved without adding a common-mode feedback circuit.

[0116] For the case where the input common mode voltage changes, assuming that the common mode voltage is 600mV, the input amplifier unit 23 works in a balanced manner. If the common mode voltage drops from 600mV to 400mV, at the initial moment, due to the gate-source voltage V gs It must be greater than the gate-source voltage V of the switch tube MN1 and the switch tube MN2 gs , the conduction capability of the switch tube MP1 and the switch tube MP2 is stronger; but in order to ensure that the current flowing through the switch tube MP1 and the switch tube MP2, the switch tube MP1 and the switch tube MP2 are consistent, the energy storage capacitor C RES As an independent voltage source, it will automatically shift down 200mV to balance the overdrive voltage of the switch tubes MP1 and MP2, and the overdrive voltage of the switch tubes MP1 and MP2. The situation where the common-mode voltage increases is similar and will not be repeated here.

[0117] When the process angle changes, the threshold voltage V of the switch tube MP1 and the switch tube MP2 under the SF process angle is th Reduce the gate-source voltage V of the switch tube MN1 and the switch tube MN2 gsInitially, both V+ and V- are pulled low. This shift in independent power domains causes the conduction capabilities of switches MP1 and MP2, and switches MN1 and MN2, to change in the same direction, aligning the currents in the upper and lower paths to maintain proper operation. The FS process corner also operates similarly and will not be further elaborated here.

[0118] In the description of this specification, reference to the terms "some embodiments" or "other embodiments" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0119] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0120] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A dynamic comparator, characterized in that: include: a dynamic differential amplification module, wherein the power supply terminal of the dynamic differential amplification module is used to connect to a power supply, the first signal input terminal of the dynamic differential amplification module is used to receive a first input signal, and the second signal input terminal of the dynamic differential amplification module is used to receive a second input signal, so that the dynamic differential amplification module is in a locked state when the dynamic comparator is in a reset phase, and outputs a first amplified signal and a second amplified signal when the dynamic comparator is in a comparison phase; A latch module, wherein the power supply end of the latch module is used to connect to the power supply, the first signal input end of the latch module is connected to the first signal output end of the dynamic differential amplifier module, the second signal input end of the latch module is connected to the second signal output end of the dynamic differential amplifier module, the first signal input end and the second signal input end of the latch module are also used to access the clamping signal, and the controlled end of the latch module is used to access the clock signal, so that when the dynamic comparator is in the reset stage, the latch module is in a locked state under the action of the clamping signal and the clock signal, and when the dynamic comparator is in the comparison stage, the comparison result signal is output based on the first amplified signal and the second amplified signal.

2. The dynamic comparator according to claim 1, wherein: The dynamic differential amplification module includes: an energy storage unit, an input amplification unit, a first controlled switch unit and a second controlled switch unit; The power supply terminal of the energy storage unit is connected to the power supply through the first controlled switch unit, the power supply terminal of the energy storage unit is connected to the power supply terminal of the input amplification unit, the first signal output terminal of the input amplification unit is connected to the first signal input terminal of the latch module, the second signal output terminal of the input amplification unit is connected to the second signal input terminal of the latch module, and the first signal input terminal and the second signal input terminal of the latch module are further connected to the clamping signal through the second controlled switch unit; When the dynamic comparator is in a reset phase, the first controlled switch unit and the second controlled switch unit are both in an on state; When the dynamic comparator is in the comparison stage, both the first controlled switch unit and the second controlled switch unit are in an off state.

3. The dynamic comparator according to claim 2, characterized in that The energy storage unit includes a tail capacitor C tail1 and tail capacitor C tail2 , the first controlled switch unit includes a controlled switch S1 and a controlled switch S2, and the second controlled switch unit includes a controlled switch S3 and a controlled switch S4; Among them, the tail capacitor C tail1 The positive plate is connected to the positive electrode of the power supply through the controlled switch S1, and the tail capacitor C tail1 The negative plate is connected to the positive power supply terminal of the input amplifier unit; the tail capacitor C tail2 The positive plate is connected to the negative electrode of the power supply through the controlled switch S2, and the tail capacitor C tail2 The negative plate of the latch module is connected to the negative power supply terminal of the input amplification unit, the first signal input terminal of the latch module is connected to the clamping signal through the controlled switch S3, and the second signal input terminal of the latch module is connected to the clamping signal through the controlled switch S4; When the dynamic comparator is in the reset stage, the controlled switch S1, the controlled switch S2, the controlled switch S3 and the controlled switch S4 are all in the on state; When the dynamic comparator is in the comparison stage, the controlled switch S1 , the controlled switch S2 , the controlled switch S3 , and the controlled switch S4 are all in an off state.

4. The dynamic comparator according to claim 1, wherein: The dynamic differential amplification module includes: an energy storage unit, an input amplification unit, a third controlled switch unit, a fourth controlled switch unit and a fifth controlled switch unit; The power supply terminal of the energy storage unit is connected to the power supply through the third controlled switch unit, the power supply terminal of the input amplifying unit is connected to the power supply terminal of the energy storage unit through the fourth controlled switch unit, the first signal output terminal of the input amplifying unit is connected to the first signal input terminal of the latch module, the second signal output terminal of the input amplifying unit is connected to the second signal input terminal of the latch module, and the first signal input terminal and the second signal input terminal of the latch module are further connected to the clamping signal through the fifth controlled switch unit; When the dynamic comparator is in a reset phase, the third controlled switch unit and the fifth controlled switch unit are both in an on state, and the fourth controlled switch unit is in an off state; When the dynamic comparator is in the comparison stage, the third controlled switch unit and the fifth controlled switch unit are both in an off state, and the fourth controlled switch unit is in an on state.

5. The dynamic comparator according to claim 4, characterized in that: The energy storage unit includes an energy storage capacitor C RES , the third controlled switch unit includes a controlled switch S11 and a controlled switch S12, the fourth controlled switch unit includes a controlled switch S21 and a controlled switch S22, and the fifth controlled switch unit includes a controlled switch S31 and a controlled switch S32; Wherein, the energy storage capacitor C RES The positive plate is connected to the positive electrode of the power supply through the controlled switch S11, and the energy storage capacitor C RES The negative plate is connected to the negative electrode of the power supply through the controlled switch S12, and the energy storage capacitor C RES The positive plate is also connected to the positive power supply terminal of the input amplifier unit through the controlled switch S21, and the energy storage capacitor C RES The negative plate is also connected to the negative power supply terminal of the input amplification unit through the controlled switch S22, the first signal input terminal of the latch module is connected to the clamping signal through the controlled switch S31, and the second signal input terminal of the latch module is connected to the clamping signal through the controlled switch S32; When the dynamic comparator is in the reset phase, the controlled switch S11, the controlled switch S12, the controlled switch S31, and the controlled switch S32 are all in the on state, and the controlled switch S21 and the controlled switch S22 are in the off state; When the dynamic comparator is in the comparison stage, the controlled switches S11 , S12 , S31 and S32 are all in the off state, and the controlled switches S21 and S22 are in the on state.

6. The dynamic comparator according to any one of claims 1 to 5, characterized in that: The latch module includes an input pair unit and a latch unit; The power supply terminal of the input pair unit is used to connect to the power supply, the first signal input terminal of the input pair unit is connected to the first signal output terminal of the dynamic differential amplification module, the second signal input terminal of the input pair unit is connected to the second signal output terminal of the dynamic differential amplification module, the first signal input terminal and the second signal input terminal of the input pair unit are also used to connect to the clamping signal, and the controlled terminal of the input pair unit is used to connect to the clock signal; The first input end of the latch unit is connected to the first output end of the input pair unit, the second input end of the latch unit is connected to the second output end of the input pair unit, the controlled end of the latch unit is used to access the clock signal, and the signal output end of the latch unit is used to output the comparison result signal.

7. The dynamic comparator according to claim 6, characterized in that: The input pair unit includes: a switch tube M0, a switch tube M1, a switch tube M2, an auxiliary switch tube M11 and an auxiliary switch tube M22; The source of the switch M0 is connected to the power supply, the gate of the switch M0 is connected to the clock signal, and the drain of the switch M0 is connected to the source of the switch M1, the source of the switch M2, the auxiliary switch M11, and the source of the auxiliary switch M22 respectively. The gate of the switch M1 is connected to the first signal output terminal of the dynamic differential amplifier module, and the gate of the switch M1 is also connected to the clamping signal. The drain of the switch M1 is respectively connected to the first input terminal of the latch unit and the drain of the auxiliary switch M11. The gate of the switch M2 is connected to the second signal output terminal of the dynamic differential amplifier module, and the gate of the switch M2 is also connected to the clamping signal. The drain of the switch M2 is respectively connected to the second input terminal of the latch unit and the drain of the auxiliary switch M22. The gates of the auxiliary switch M11 and the auxiliary switch M22 are both connected to the power supply. When the dynamic comparator is in the reset stage, the switch tube M0 is in the off state; when the dynamic comparator is in the comparison stage, the switch tube M0 is in the on state.

8. The dynamic comparator according to claim 7, characterized in that: The latch unit is a dynamic latch.

9. The dynamic comparator according to any one of claims 2 to 5, characterized in that: The input amplifying unit includes: a first amplifying unit and a second amplifying unit; The power supply terminal of the first amplifying unit is connected to the power supply terminal of the energy storage unit, and the signal input terminal of the first amplifying unit is used to receive the first input signal; the power supply terminal of the second amplifying unit is connected to the power supply terminal of the energy storage unit, and the signal input terminal of the second amplifying unit is used to receive the second input signal; When the dynamic comparator is in a reset phase, the first amplifying unit and the second amplifying unit are both in a locked state; When the dynamic comparator is in a comparison phase, the first amplifying unit outputs the first amplified signal based on the first input signal, and the second amplifying unit outputs the second amplified signal based on the second input signal.

10. The dynamic comparator according to claim 9, characterized in that: The first amplifying unit includes a switch tube MP1, a switch tube MN1 and a first integral capacitor C X1 ; The source of the switch tube MP1 is connected to the positive power supply terminal of the energy storage unit, and the drain of the switch tube MP1 is connected to the drain of the switch tube MN1, the first integral capacitor C X1 The positive plate of the latch module and the first signal input terminal of the latch module, the source of the switch tube MN1 is connected to the negative power supply terminal of the energy storage unit, the gate of the switch tube MP1 and the gate of the switch tube MN1 are both used to access the first input signal, the first integrating capacitor C X1 The negative plate is grounded; The second amplifying unit includes a switch tube MP2, a switch tube MN2 and a second integral capacitor CX2; The source of the switch tube MP2 is connected to the positive power supply terminal of the energy storage unit, the drain of the switch tube MP2 is respectively connected to the drain of the switch tube MN2, the second integral capacitor CX2, and the second signal input terminal of the latch module, the source of the switch tube MN2 is connected to the negative power supply terminal of the energy storage unit, the gates of the switch tubes MP1 and MN1 are both used to receive the second input signal, and the negative plate of the second integral capacitor CX2 is grounded.

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