A method and device for evaluating the number of defects between oxide and silicon carbide in SiC MOSFET

Abstract

A method and apparatus for evaluating the number of defects between oxide and silicon carbide in a SiC MOSFET belongs to the field of semiconductor device detection technology. The method comprises the following steps: obtaining dynamic characteristic data and static characteristic data of the silicon carbide MOSFET in the same state; the same state being the same drain-source voltage and the same channel current; the dynamic characteristic data and static characteristic data including the gate-source voltage and the drain-source voltage and channel current at the same moment; obtaining the gate-source voltage difference in the same state based on the dynamic characteristic data and the static characteristic data, and calculating the estimated number of defects between oxide and silicon carbide; and obtaining the final number of defects based on the estimated number of defects. This application calculates the number of defects at the gate oxide and silicon carbide interface by taking advantage of the difference in the dynamic and static characteristics of the SiC MOSFET caused by the defect response time delay, thereby reducing the cost of defect evaluation.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor device detection, and in particular relates to a method and device for evaluating the number of defects between oxide and silicon carbide in SiC MOSFET. Background Art

[0002] Compared with silicon MOSFET, silicon carbide MOSFET has broad application prospects due to its low on-resistance, low capacitance characteristics and excellent high temperature, high frequency and high voltage performance.

[0003] However, device reliability issues caused by a large number of defects at the interface between low-quality gate silicon oxide and silicon carbide have hindered the further development of silicon carbide MOSFETs.

[0004] To evaluate the interface between silicon oxide and silicon carbide, a series of material analyses are typically required, along with the use of test structures to indirectly reflect the quality of the manufacturing process. For example, during the tape-out process, in addition to the product, the wafer may also include test structures such as MOS capacitors or lateral long-channel MOSFETs. The test structures undergo the same gate manufacturing process as the product, reducing the need to modify process parameters or omit processes in certain steps, thereby eliminating the impact of unnecessary processes. By evaluating the interface defect density of the test structures, the interface defect density of the silicon carbide MOSFET product can be indirectly reflected.

[0005] Currently, high-frequency capacitance-voltage testing and charge pump testing are commonly used to evaluate the interface between silicon oxide and silicon carbide.

[0006] High-frequency capacitance-voltage testing has the following defects: the currently widely used gate oxide process of high-temperature annealing in a nitrogen-containing environment results in a defect response time of nanoseconds, requiring a frequency exceeding 100MHz to fully reflect the characteristics of the defect. Therefore, the required equipment is expensive, costing millions of yuan, and requires the use of a test structure, which cannot directly reflect the characteristics of the SiC MOSFET gate oxide and SiC interface.

[0007] Charge pump testing has the following defects: it is difficult to quantitatively reflect the characteristics of defects, requires a lot of physical deduction and analysis, and also requires the use of test structures, and cannot directly reflect the characteristics of the SiC MOSFET gate oxide and SiC interface.

[0008] Therefore, it is urgent to develop a method for evaluating the number of defects between oxide and silicon carbide in SiC MOSFET to solve the problems in the existing technology. Summary of the Invention

[0009] The present invention aims to provide a method for evaluating the number of defects between oxide and silicon carbide in SiC MOSFETs. The method utilizes the difference between the dynamic and static characteristics of silicon carbide MOSFETs caused by the defect response time delay to calculate the number of gate oxide and silicon carbide interface defects in silicon carbide MOSFET products, thereby solving the problem of high cost of silicon oxide and silicon carbide interface defect detection raised in the above background technology.

[0010] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0011] A method for evaluating the number of defects between oxide and silicon carbide in SiC MOSFETs comprises the following steps:

[0012] Obtaining dynamic characteristic data and static characteristic data of the silicon carbide MOSFET in the same state; wherein the same state refers to the same drain-source voltage and the same channel current; the static characteristic data is test data when all responsive defects are responsive, and the dynamic characteristic data is test data when all defects are unresponsive; the dynamic characteristic data and static characteristic data include the gate-source voltage and the drain-source voltage and channel current at the same moment;

[0013] Based on the dynamic characteristic data and the static characteristic data, the gate-source voltage difference under the same state is obtained, and the estimated number of defects between the oxide and the silicon carbide is calculated;

[0014] Based on the estimated number of defects, the final number of defects is obtained.

[0015] Furthermore, the calculation formula for estimating the number of defects includes the following:

[0016] ;

[0017] Where q is the charge carried by the electron, N traps is the number of unresponsive defects during dynamic testing, C OX is the gate capacitance of SiC MOSFET, V GS3 is the static gate-source voltage, V GS1 is the gate-source voltage.

[0018] Furthermore, the final defect count is a percentage of the maximum value in the estimated defect count.

[0019] Furthermore, the dynamic characteristic data is obtained through dynamic testing, which includes the following steps:

[0020] Acquire first characteristic data and second characteristic data; wherein the first characteristic data and the second characteristic data are various measurement data of the silicon carbide MOSFET when it is fast switched at different drain-source voltages;

[0021] The channel current at the same time as the gate-source voltage is obtained according to the first characteristic data and the second characteristic data to obtain dynamic characteristic data.

[0022] Furthermore, the channel current at the same moment is calculated by the following equations:

[0023] ;

[0024] ;

[0025] Among them, I D1 、dV GD1 / dt and V DS1 are the power loop current, gate-drain voltage change rate and drain-source voltage in the first characteristic data, I CH1 is the current flowing through the channel at the corresponding moment, C GD1 is the gate-drain capacitance at the corresponding moment;

[0026] I D2 、dV GD2 / dt and V DS2 are the power loop current, gate-drain voltage change rate and drain-source voltage in the second characteristic data, I CH2 is the current flowing through the channel at the corresponding moment, C GD2 is the gate-drain capacitance at the corresponding moment.

[0027] Furthermore, the static characteristic data is obtained through static testing, which includes the following steps:

[0028] Applying a static test voltage waveform between the drain and power source of the silicon carbide MOSFET;

[0029] After the static test voltage waveform stabilizes, a defect balance voltage waveform is applied between the gate and the Kelvin source of the silicon carbide MOSFET, and third characteristic data is obtained, wherein the third characteristic data includes the drain-source voltage, the gate-source voltage, and the drain loop current at the same time;

[0030] According to the drain-source voltage, the gate-source voltage and the channel current flowing at the same moment are extracted, wherein the channel current flowing at the same moment is equal to the drain loop current at the same moment.

[0031] Furthermore, the defect balance voltage waveform is a gradient-down waveform.

[0032] Furthermore, before static testing and dynamic testing, it also includes:

[0033] Balance the defects of SiC MOSFETs;

[0034] The defects of the silicon carbide MOSFET are balanced by the following steps:

[0035] After the drain and power source of the SiC MOSFET are shorted, a defect-balancing voltage waveform is applied between the gate and the Kelvin source.

[0036] A computer device comprises a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method.

[0037] A computer program product comprises a computer program, which implements the steps of the method when executed by a processor.

[0038] The present invention has the following advantages:

[0039] (1) This application uses the difference between the dynamic and static characteristics of SiC MOSFET caused by the defect response time delay to calculate the number of gate oxide and SiC interface defects in SiC MOSFET products. It can be directly applied to SiC MOSFET products with high reliability.

[0040] (2) This application does not require a high-frequency sine wave generator or low-temperature equipment close to absolute zero, and is low-cost. The equipment used is general-purpose equipment such as power supply, probe, oscilloscope, etc., and no additional expenses are required.

[0041] Other features and advantages of the present invention will be disclosed in detail in the following specific embodiments and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 a circuit diagram of the test circuit for this application;

[0043] Figure 2 Schematic diagram of the defect balance voltage waveform of this application;

[0044] Figure 3 A schematic diagram of the dynamic test voltage waveform of this application;

[0045] Figure 4 A schematic diagram of the static test voltage waveform of this application;

[0046] Figure 5 V obtained for dynamic and static testing of this application GS -I CH Curve comparison chart;

[0047] Figure 6 A graph showing the relationship between the number of defects and gate-source voltage in response to this application. DETAILED DESCRIPTION

[0048] In order to better understand the purpose, structure and function of the present invention, the present invention is further described in detail below with reference to the accompanying drawings.

[0049] A method for evaluating the number of defects between oxide and silicon carbide in SiC MOSFETs comprises the following steps:

[0050] Obtaining dynamic characteristic data and static characteristic data of the silicon carbide MOSFET in the same state; wherein the same state refers to the same drain-source voltage and the same channel current; the static characteristic data is test data when all responsive defects are responsive, and the dynamic characteristic data is test data when all defects are unresponsive; the dynamic characteristic data and static characteristic data include the gate-source voltage and the drain-source voltage and channel current at the same moment;

[0051] Based on the dynamic characteristic data and the static characteristic data, the gate-source voltage difference under the same state is obtained, and the estimated number of defects between the oxide and the silicon carbide is calculated;

[0052] Based on the estimated number of defects, the final number of defects is obtained.

[0053] The calculation formula for the estimated number of defects includes the following:

[0054] ;

[0055] Where q is the charge carried by the electron, N traps The number of unresponsive defects during the dynamic test, in cm -2 , C OX is the gate capacitance of the SiC MOSFET, in F, V GS3 is the static gate-source voltage in V, V GS1 is the gate-source voltage in V.

[0056] In this embodiment, the final defect quantity is the maximum value among the estimated defect quantities.

[0057] Optionally, the final defect count may also be limited to a percentage of the maximum value in the estimated defect count, such as 90%, 95%, etc. of the maximum value.

[0058] Specifically, in this embodiment, the drain-source voltage is the voltage between the drain and the power source, and the gate-source voltage is the voltage between the gate and the Kelvin source.

[0059] The dynamic characteristic data and the static characteristic data are obtained by connecting a test circuit to the silicon carbide MOSFET to be tested and performing dynamic testing and static testing.

[0060] like Figure 1 As shown, the test circuit includes a low voltage source V S and gate drive circuit, the low voltage source V SConnected to the drain and power source of the silicon carbide MOSFET to be tested, the gate drive circuit is connected to the gate and Kelvin source of the silicon carbide MOSFET to be tested. In this embodiment, the low voltage source and the gate drive circuit are used to provide voltage. Real-time detection of drain-source voltage V DS , the power loop current I flowing into the drain and out of the power source D , gate-source voltage V GS , Gate drive circuit current I flowing into the gate and out of the Kelvin source G .

[0061] It is also possible to bring the defects of SiC MOSFETs into equilibrium before dynamic and static testing.

[0062] In this embodiment, the defects of the silicon carbide MOSFET are balanced by the following steps:

[0063] V S The voltage is set to 0, the drain of the SiC MOSFET and the power source are shorted, and a defect balance voltage waveform is applied between the gate and the Kelvin source through the gate drive circuit. Figure 2 As shown, the defect-balancing voltage waveform is a gradient-decreasing waveform, with the voltage decreasing stepwise to zero over time to maintain a balanced defect state in the silicon carbide MOSFET, i.e., a dynamic equilibrium between the charge trapped by the defects and the charge released. In this embodiment, the defect-balancing voltage waveform begins to decrease after 100ms, with a decreasing interval of 10ms, and each decreasing voltage level is 0.1V. The specific decreasing time, decreasing interval, and decreasing voltage level are determined based on achieving a dynamic equilibrium between the charge trapped by the defects and the charge released, and can be set as needed.

[0064] The maximum gate-source voltage V applied to the defect balance voltage waveform is GS，max Determined by the SiC MOSFET gate oxide thickness and the gate operating voltage recommended in the datasheet.

[0065] In this embodiment, the drain-source voltage V DS and gate-source voltage V GS The gate-source voltage V GS At the same time, the channel current I CH Calculated after two dynamic tests.

[0066] Specifically, the two dynamic tests include the following steps:

[0067] A first dynamic test voltage waveform is applied between the drain and the power source of the silicon carbide MOSFET, and a fast switch is performed after the first dynamic test voltage waveform is stabilized to obtain first characteristic data of the first dynamic test; the first characteristic data includes the gate-source voltage V GS1 and the gate-source voltage V GS1 At the same time, the drain-source voltage V DS1 The fast switch will quickly increase the gate-source voltage to the maximum gate-source voltage V GS，max .

[0068] A second dynamic test voltage waveform is applied between the drain and the power source of the silicon carbide MOSFET, and a fast switch is performed after the second dynamic test voltage waveform stabilizes to obtain the second characteristic data of the second dynamic test. The second characteristic data includes the gate-source voltage V GS2 and the gate-source voltage V GS2 At the same time, the drain-source voltage V DS2 Among them, V DS1 With V DS2 Different sizes, maximum gate-source voltage V GS，max Same size.

[0069] According to the first characteristic data and the second characteristic data, the gate-source voltage V GS1 At the same time, the channel current I CH1 , to obtain dynamic characteristic data. In this embodiment, the statically measured drain-source voltage and V DS1 The same, so the first characteristic data and the corresponding channel current I CH1 For dynamic characteristic data, if the statically measured drain-source voltage is DS2 If the second characteristic data and the corresponding channel current I are the same, CH2 It is dynamic characteristic data.

[0070] In this embodiment, the first dynamic test voltage waveform or the second dynamic test voltage waveform is as follows Figure 3 As shown, set the voltage conversion time to more than 10s, at V S After stabilization, fast switching is performed, and the switching time is generally less than 100ns.

[0071] In this embodiment, when calculating the channel current at the same time as the gate-source voltage, in order to exclude C GD The effect of current, the method used in this embodiment is to S =V S1 and V S =V S2 Measurements are performed at two very small voltages to obtain various measurement data of the two tests, including first characteristic data and second characteristic data, and calculated according to the equation group.

[0072] In the low drain-to-source voltage variation range, the capacitance C between the gate and drain of the SiC MOSFET GD The on-resistance has nothing to do with the drain-power source, but only with the voltage between the gate and the Kelvin source. S During the dynamic switching process, I D The channel current I CH and flows through C GD current, this application at V S =V S1 and V S =V S2 The two dynamic tests have the following equations:

[0073] ;

[0074] Due to the applied V S1 and V S2 Very small, the C of SiC MOSFET GD The on-resistance is only related to the gate-source voltage. The on-resistance is the drain-source voltage divided by the current flowing through the channel. GS1 =V GS2 When , there exists a second set of equations:

[0075] ;

[0076] Among them, I D1 、dV GD1 / dt and V DS1 are the power loop current, gate-drain voltage change rate and drain-source voltage in the first characteristic data, I CH1 is the current flowing through the channel at the corresponding moment, C GD1 is the gate-drain capacitance at the corresponding moment;

[0077] I D2 、dV GD2 / dt and V DS2 are the power loop current, gate-drain voltage change rate and drain-source voltage in the second characteristic data, I CH2 is the current flowing through the channel at the corresponding moment, C GD2 is the gate-drain capacitance at the corresponding moment.

[0078] According to the first and second equations, we can get I CH1 and I CH2 .

[0079] The first characteristic data and the second characteristic data include power loop current, gate-drain voltage change rate and drain-source voltage, the gate-drain voltage change rate dV GD / dt can be calculated by measuring the gate-drain voltage d(V GS -V DS ) / dt is obtained, which is a prior art and will not be described in detail in this application.

[0080] In this embodiment, the low drain-power source voltage variation range is as small as possible, and the C GD The on-resistance is only related to the gate-source voltage. In this embodiment, the voltage range is related to the device limit that the hardware can detect. If the hardware can meet the accuracy of all measurement data of 1% under the condition of 0.01V, then it is 0.01V.

[0081] The static characteristic data is obtained through a static test, and the static test includes the following steps:

[0082] Apply a static test voltage waveform between the drain and power source of the SiC MOSFET; Figure 4 As shown, in this embodiment, the static test voltage waveform is a stable voltage;

[0083] After the static test voltage waveform is stable, a defect balance voltage waveform is applied between the gate and the Kelvin source of the silicon carbide MOSFET, and third characteristic data is obtained, wherein the third characteristic data includes the drain-source voltage V DS3 , gate-source voltage V GS3 And the drain loop current I D3 ;

[0084] According to the drain-source voltage, the gate-source voltage and the channel current flowing at the same moment are extracted, wherein the channel current flowing at the same moment is equal to the drain loop current at the same moment; the drain-source voltage V in the static characteristic data GS3 With V GS1 Same size.

[0085] In this embodiment, the static characteristic data includes the gate-source voltage V GS3 and the gate-source voltage V GS3 At the same time, the drain-source voltage V DS3 and the channel current I CH3 .

[0086] In this embodiment, the defect balance voltage waveform is a gradient-down shape, from the maximum gate-source voltage V GS，max The gradient drops to 0. Figure 4 As shown, during the static test process, V GS After each change, the data is maintained for 10ms, and the data is read 5ms after the change, so the measured I D3 Flow through C GD Current compared to I CH3Ignore it and it can be considered that I D3 =I CH3 Therefore, during the static test, the V GS3 、V DS3 , I CH3 Can be obtained directly.

[0087] Defects are the direct cause of the difference between the dynamic and static characteristics of SiC MOSFET products. The static characteristics of SiC MOSFET are the characteristics in the equilibrium state, that is, the characteristics of the device when all defects that can respond are responded. When the switching speed is fast enough, the dynamic characteristics at this time are considered to be the characteristics of the device when all defects do not respond. By comparing the static characteristics and fast dynamic characteristics of SiC MOSFET, the impact of the number of defects can be obtained. Defects affect the characteristics by affecting the equivalent threshold voltage of SiC MOSFET. At a fixed V DS and I CH conditions, dynamic and static applied V GS The difference is the impact of the defect.

[0088] To verify the accuracy of the proposed method, the number of defects was set to 1.4×1012 cm in the TCAD simulation. -2 The calculated I of SiC MOSFET under static and dynamic test conditions CH -V GS Curves such as Figure 5 As shown in Figure 2, the dynamic test sets all defects to be non-responsive, while the static test sets the defect responses to be in a balanced state at all times. Figure 6 As shown in the figure, the defect number change diagram in response to the gate-source voltage change during the static test is calculated using the method of the present application. The horizontal axis is the drain-source voltage during the static test. The maximum defect number calculated is about 1.524×1012 cm -2 , with an accuracy rate of over 90%.

[0089] A computer device comprises a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method.

[0090] A computer program product comprises a computer program, which implements the steps of the method when executed by a processor.

[0091] A computer-readable storage medium stores a computer program, which implements the steps of the method when executed by a processor.

[0092] It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be protected by the present invention.

[0093] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A method for evaluating the number of defects between oxide and silicon carbide in SiC MOSFET, characterized in that: The steps include: Obtaining dynamic characteristic data and static characteristic data of the silicon carbide MOSFET in the same state; wherein the same state refers to the same drain-source voltage and the same channel current; the static characteristic data is test data when all responsive defects are responsive, and the dynamic characteristic data is test data when all defects are unresponsive; the dynamic characteristic data and static characteristic data include the gate-source voltage and the drain-source voltage and channel current at the same moment; Based on the dynamic characteristic data and the static characteristic data, the gate-source voltage difference under the same state is obtained, and the estimated number of defects between the oxide and the silicon carbide is calculated; Based on the estimated defect count, the final defect count is obtained; The calculation formula for the estimated number of defects includes the following: ； Where q is the charge carried by the electron, N traps is the number of unresponsive defects during dynamic testing, C OX is the gate capacitance of SiC MOSFET, V GS3 is the static gate-source voltage, V GS1 is the gate-source voltage during dynamic test.

2. The method for evaluating the number of defects between oxide and silicon carbide in SiC MOSFET according to claim 1, wherein: The final defect count is a percentage of the maximum value among the estimated defect counts.

3. The method for evaluating the number of defects between oxide and silicon carbide in SiC MOSFET according to claim 1 or 2, wherein: The dynamic characteristic data is obtained through dynamic testing, which includes the following steps: Acquire first characteristic data and second characteristic data; wherein the first characteristic data and the second characteristic data are various measurement data of the silicon carbide MOSFET when it is fast switched at different drain-source voltages; According to the first characteristic data and the second characteristic data, the current flowing through the channel at the same time as the gate-source voltage is obtained to obtain dynamic characteristic data.

4. The method for evaluating the number of defects between oxide and silicon carbide in SiC MOSFET according to claim 3, wherein: The calculation equations for the channel current at the same moment include the following: ； ； Among them, I D1 、dV GD1 / dt and V DS1 are the power loop current, gate-drain voltage change rate and drain-source voltage in the first characteristic data, I CH1 is the current flowing through the channel at the corresponding moment, C GD1 is the gate-drain capacitance at the corresponding moment; I D2 、dV GD2 / dt and V DS2 are the power loop current, gate-drain voltage change rate and drain-source voltage in the second characteristic data, I CH2 is the current flowing through the channel at the corresponding moment, C GD2 is the gate-drain capacitance at the corresponding moment.

5. The method for evaluating the number of defects between oxide and silicon carbide in SiC MOSFET according to claim 4, wherein: The static characteristic data is obtained through static testing, which includes the following steps: Applying a static test voltage waveform between the drain and source of the silicon carbide MOSFET; After the static test voltage waveform stabilizes, a defect balance voltage waveform is applied between the gate and the Kelvin source of the silicon carbide MOSFET, and third characteristic data is obtained, wherein the third characteristic data includes the drain-source voltage, the gate-source voltage, and the drain loop current at the same time; According to the drain-source voltage, the gate-source voltage and the channel current flowing at the same moment are extracted to obtain the static gate-source voltage and the drain-source voltage and channel current flowing at the same moment as the static gate-source voltage, wherein the channel current flowing at the same moment is equal to the drain loop current at the same moment.

6. The method for evaluating the number of defects between oxide and silicon carbide in SiC MOSFET according to claim 5, wherein: The defect balance voltage waveform is a gradient-downward shape.

7. The method for evaluating the number of defects between oxide and silicon carbide in SiC MOSFET according to claim 6, wherein: Before static and dynamic testing, it also includes: Balance the defects of SiC MOSFETs; The defects of the silicon carbide MOSFET are balanced by the following steps: After the drain and power source of the SiC MOSFET are shorted, a defect-balancing voltage waveform is applied between the gate and the Kelvin source.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory, wherein: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 7.

9. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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