Microsystem interconnection test method based on core particles

Abstract

The invention discloses an interconnection testing method based on a chip particle microsystem, and belongs to the technical field of chip testing. Wherein the chip particle microsystem structure is analyzed, the number of chip particle microsystem interconnection networks is determined, the interconnection networks are classified, and the method mainly comprises the steps of boundary scanning chip interconnection networks and hybrid interconnection networks, automatically generating test vectors based on the boundary scanning technology, loading and running the test vectors through ATE, and classifying the interconnection networks. And designing a real installation test system to test the hybrid internet, if the hybrid internet is judged to have a fault, triggering a boundary scan test program, and diagnosing the fault type through a boundary scan test method. By combining the boundary scanning test with the real installation test technology, on the premise that the hardware cost is not increased, the real installation test and the boundary scanning test are fused in a cross-platform mode, the high coverage rate test of the core particle microsystem interconnection network is achieved, and the application quality of the core particle microsystem is guaranteed.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testing, and in particular to a chiplet-based microsystem interconnection testing method. Background Art

[0002] In the field of microsystems, chiplet microsystems are emerging as an emerging technology architecture. Chiplet microsystems integrate multiple chips into a single package, achieving advantages such as high density, miniaturization, and high performance. However, the connections between the chips in a chiplet microsystem are extremely complex.

[0003] However, in the construction of chiplet microsystems, wiring is crucial, and the stability and maturity of the packaging process are key factors affecting the quality of the wiring, which in turn affects the performance of the entire chiplet microsystem. Therefore, conducting comprehensive and in-depth interconnect testing of chiplet microsystems is particularly important and critical. It is imperative to ensure that the testing covers all possible fault scenarios that may occur in chiplet connections, such as open circuits, short circuits, and bridges, in order to ensure the stable operation and performance of the chiplet microsystem in practical applications.

[0004] Currently, existing interconnection testing methods have the following defects and shortcomings:

[0005] 1. Single test strategy and insufficient coverage: Existing methods lack a classification test strategy for hybrid interconnect networks containing both boundary scan and non-boundary scan chips, resulting in failure coverage that cannot reach the ideal level.

[0006] 2. Ambiguous positioning: Installation testing solves the problem of overall interconnect testing. If an interconnect test problem occurs during installation testing, the installation can only locate the problem on a group of interconnects, but cannot pinpoint the specific faulty line. Boundary scan technology, however, is limited by the chip's support characteristics and has difficulty effectively covering the interconnect network of non-scanning chips, resulting in a relatively coarse fault diagnosis granularity.

[0007] 3. Low test efficiency: Traditional boundary scan testing methods rely on dedicated test equipment and are extremely cumbersome and complex in terms of test vector generation and loading processes. This makes it difficult to adapt to the efficient production pace pursued by automatic test equipment (ATE), thus seriously affecting overall test efficiency.

[0008] 4. Cost and compatibility issues: Existing interconnect testing methods often require additional configuration of dedicated hardware equipment and supporting software, which undoubtedly increases testing costs. Moreover, such methods are difficult to be compatible with diverse chip microsystem architectures, greatly limiting their application scope and flexibility.

[0009] Existing technical solutions have yet to provide effective solutions to these issues. For example, relying solely on boundary scan testing can overlook interconnect defects in non-scanned chips, while accurate fault location cannot be achieved through assembly testing alone. Furthermore, traditional interconnect testing methods fail to fully consider optimization and improvements for the testability design of chip microsystems, resulting in poor versatility in test solutions. This makes it difficult to meet the stringent quality control requirements of mass production, especially in high-density packaging scenarios. Summary of the Invention

[0010] In order to address the deficiencies in the above-mentioned prior art, the present application provides a chiplet microsystem interconnection testing method, which achieves high coverage testing of the chiplet microsystem interconnection network without increasing hardware costs.

[0011] The technical solution is as follows:

[0012] A chiplet-based microsystem interconnection testing method is provided, comprising:

[0013] Step S1, analyzing the chiplet microsystem structure and classifying the chiplet microsystem interconnection network into a boundary scan chip interconnection network and a hybrid interconnection network;

[0014] Step S2, generating test vectors based on boundary scan technology, loading and running the test vectors through automatic test equipment (ATE) to cover boundary scan chip interconnect network faults;

[0015] Step S3: Designing a real-world test system to test the hybrid interconnection network. If the hybrid interconnection network is determined to have a fault, triggering a boundary scan test program to diagnose the fault type using a boundary scan test method.

[0016] Step S4: combining the test results of step S2 and step S3, outputting the global fault coverage of the chiplet microsystem interconnection network.

[0017] Furthermore, the interconnection network of the chiplet microsystem is classified according to whether the chip supports boundary scan technology, including:

[0018] Boundary scan chip interconnect network: The chips connected at both ends of the interconnect network support boundary scan technology;

[0019] Hybrid interconnection network: One end of the interconnection network is connected to the boundary scan chip, and the other end is connected to the non-boundary scan chip.

[0020] Furthermore, the boundary scan chip interconnection network includes an interconnection network of DSP microcomponents and FPGA microcomponents.

[0021] Furthermore, the hybrid interconnection network includes at least an interconnection network between NAND FLASH and CIB, an interconnection network between DSP microcomponents and CIB, an interconnection network between FPGA microcomponents and CIB, an interconnection network between NOR FLASH chip and FPGA chip, an interconnection network between DDR chip and FPGA chip, and an interconnection network between NOR FLASH chip and DSP chip.

[0022] Furthermore, the actual installation test system includes: a DC regulated power supply, a DC / DC converter, a programmable device, a host computer, a CPU core board, a crystal oscillator, a memory, an FPGA core board, and a microsystem chip. The DC regulator is connected to the DC / DC converter, the DC / DC converter is connected to the microsystem chip, the programmable device is respectively connected to the DC / DC converter and the host computer, the host computer is respectively connected to the programmable device and the microsystem chip, and the microsystem chip is respectively connected to the CPU core board, crystal oscillator, memory, and FPGA core board; at the same time, the actual installation system is integrated with the boundary scan system, the host computer is connected to the boundary scan test system, the boundary scan test system is connected to the microsystem chip, the power-on timing and reset signal are controlled by the programmable device, and the functional test program is run to perform full-address read and write verification and interface protocol testing on the non-boundary scan chip interconnection network.

[0023] Furthermore, the full address read and write verification includes:

[0024] Verification of interconnection between DSP and NOR FLASH: Perform full-address erase and read / write test on NOR FLASH through SPI interface of DSP, and compare the read / write data consistency. If they are consistent, it is determined that there is no fault in the interconnection network between DSP and NOR FLASH.

[0025] FPGA and DDR interconnection verification: Initialize the DDR and perform full-address read and write tests by loading the FPGA test program, and compare the read and write data consistency. If they are consistent, it is determined that the FPGA and DDR interconnection network is fault-free;

[0026] DSP and DDR interconnection verification: Initialize the DDR and perform full-address read and write tests by loading the DSP test program, and compare the read and write data consistency. If they are consistent, it is determined that the DSP and DDR interconnection network is fault-free;

[0027] CIB and NAND Flash interconnection verification: Connect the CIB chip to the emulator and run the test program to perform full-address read and write tests on the NAND Flash. Compare the read and write data consistency. If they are consistent, it is determined that the CIB and NAND Flash interconnection network is fault-free.

[0028] Furthermore, the interface protocol test includes:

[0029] SRIO write operation verification: Run the SRIO data write request instruction in the FPGA or DSP, send a write data packet request to the SRIO interface of the CIB, and the CIB chip performs the data packet exchange operation after receiving the write request and returns a write response packet to the FPGA or DSP after the operation is completed.

[0030] SRIO read operation verification: Run the SRIO data read request instruction in the FPGA or DSP and send a read data packet request to the SRIO interface of the CIB. After receiving the read request, the CIB chip performs the data packet exchange operation and returns a read response packet to the FPGA or DSP after the operation is completed.

[0031] If both the write response packet and the read response packet comply with the protocol specifications and the data is complete, it is determined that the SRIO interconnection network between the CIB chip and the FPGA / DSP chip is fault-free.

[0032] Furthermore, the method is applicable to a core microsystem comprising the following components:

[0033] At least one CIB chip, FPGA micro-component, DSP micro-component, NAND Flash micro-component;

[0034] The FPGA micro-component and the DSP micro-component are interconnected via the SRIO X4 interface and the EMIF interface, and the CIB chip is connected to the FPGA micro-component and the DSP micro-component respectively via the SRIO X4 interface.

[0035] The technical solution includes at least the following technical effects:

[0036] Analyze the structure of the chip microsystem, determine the number of chip microsystem interconnection networks, and classify the interconnection networks, which mainly include boundary scan chip interconnection networks and hybrid interconnection networks (boundary scan chip and non-boundary scan chip interconnection networks). Automatically generate test vectors based on boundary scan technology, load and run test vectors through ATE to cover boundary scan chip interconnection network faults. At the same time, combine the actual installation test technology and design an actual installation system to cover the hybrid interconnection network faults. By combining boundary scan testing with actual installation test technology, high coverage testing of the chip microsystem interconnection network is achieved without increasing hardware costs (the target coverage rate reaches 100%), ensuring the application quality of the chip microsystem.

[0037] It should be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0039] Figure 1 A flowchart of a chiplet-based microsystem interconnection testing method provided in one embodiment of the present application;

[0040] Figure 2 A schematic diagram of the core particle microsystem structure provided in one embodiment of the present application;

[0041] Figure 3 A flow chart for boundary scan chip interconnect network testing provided in one embodiment of the present application;

[0042] Figure 4 This is a schematic diagram of the structure of the installation and boundary scan test system provided in one embodiment of the present application. DETAILED DESCRIPTION

[0043] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0044] As attached Figure 1 As shown, the present application provides a chiplet-based microsystem interconnection testing method, which aims to solve the problem of interconnection line testing between chips and perform high-coverage testing of microsystem interconnection without increasing the cost of existing microsystem testing; the method includes the following steps:

[0045] Step S1, analyzing the chiplet microsystem structure and classifying the chiplet microsystem interconnection network into a boundary scan chip interconnection network and a hybrid interconnection network (a boundary scan chip and a non-boundary scan chip interconnection network);

[0046] Step S2, generating test vectors based on boundary scan technology, loading and running the test vectors through automatic test equipment to cover boundary scan chip interconnect network faults;

[0047] Step S3: Designing a test system to test the hybrid interconnection network. If the hybrid interconnection network is determined to have a fault, triggering a boundary scan test program to diagnose the fault type through a boundary scan test method to cover the hybrid interconnection network fault.

[0048] Step S4: combining the test results of step S2 and step S3, outputting the global fault coverage of the chiplet microsystem interconnection network.

[0049] By combining boundary scan testing with actual installation testing technology, high coverage testing of the chiplet microsystem's interconnection network can be achieved without increasing hardware costs, with the target coverage reaching 100%, thereby effectively ensuring the application quality of the chiplet microsystem.

[0050] It should be noted that the boundary scan test is not only for boundary scan chip interconnection networks, but can also test hybrid interconnection networks. For boundary scan chip interconnection networks, the priority use of boundary scan testing improves test efficiency. For hybrid interconnection networks, the use of actual installation test systems has high test efficiency. Therefore, for hybrid networks, the actual installation test system is preferred to test faults. When the actual installation test system tests a problem (that is, it tests that there is a fault in the interconnection network), the boundary scan test is started to specifically locate whether it is an open circuit fault or a short circuit fault. The actual installation test system solves the problem of overall interconnection line testing. If an interconnection line test problem occurs during the actual installation test, the actual installation test can only locate a group of interconnection lines with a problem, and cannot locate which specific line has a problem. The boundary scan test can specifically locate the location of the failed line, which can make up for the shortcomings of the actual installation test.

[0051] The actual installation test system used in the prior art is used for functional testing of modules, while the actual installation test system used in this application is used for interconnection testing between modules. Internet faults are discovered through the actual installation test system test, and the boundary scan test program is triggered, and then the faulty interconnection line is located through boundary scan testing. The actual installation test system used in this application is used to test interconnection lines. Unlike the functional test actual installation solution, the actual installation test system used in this application for testing interconnection lines is more inclined to the coverage of interconnection lines, not just the functional test of a certain functional module. In addition, unlike the prior art, the prior art actual installation test and boundary scan test belong to distributed test platforms. This application integrates actual installation test and boundary scan test across platforms, which not only improves test efficiency but also improves fault location accuracy.

[0052] In one embodiment, if Figure 2 As shown in the figure, the chiplet microsystem architecture primarily consists of a Chiplet Interconnect Bus (CIB), two FPGA microcomponents, two DSP microcomponents, and one Nand Flash microcomponent. The FPGA microcomponent includes the Nor Flash, FPGA, and DDR microcomponents, while the DSP microcomponent includes the DSP, Nor Flash, and DDR microcomponents. The CIB connects to the FPGA and DSP microcomponents via the SRIO X4 interface, and to the Nand Flash microcomponent via the Nand interface. The FPGA and DSP microcomponents are connected via the SRIO X4 and EMIF interfaces.

[0053] Determine the number of interconnection networks of the core microsystem and classify the interconnection networks. First, perform testability design of the microsystem, and then classify the interconnection networks according to the specific product situation.

[0054] In one embodiment, chiplet microsystem interconnect networks are categorized based on whether the chips support boundary scan technology. A network where both chips support boundary scan technology is categorized as a boundary scan chip interconnect network. A network where one end of the network is connected to a boundary scan chip and the other end is connected to a non-boundary scan chip is categorized as a hybrid interconnect network (a network where both boundary scan chips and non-boundary scan chips are interconnected).

[0055] In this embodiment, the chiplet microsystem interconnection network mainly includes a boundary scan chip interconnection network and a hybrid interconnection network, as shown in Table 1.

[0056] Table 1 Classification of interconnection networks

[0057]

[0058]

[0059] Automatically generate test vectors based on boundary scan technology, load and run test vectors through ATE, and cover boundary scan chip interconnection network faults. Configure the state of the core microsystem according to the type and model of the integrated circuit, parse the DSP's EXTEST instruction through the DSP's boundary scan file BSDL, and parse the FPGA's EXTEST instruction through the FPGA's boundary scan file BSDL; after the core microsystem is configured, generate test vectors that adapt to the ATE equipment according to the EXTEST instruction, and compare the test vectors with the actual response vectors. If they are consistent, it is determined that the interconnection network has no faults and the chip under test is normal; if they are inconsistent, it is determined that the chip under test is faulty and there is a fault in the interconnection network. Specifically, Figure 3 shown.

[0060] DSPs are digital signal processing chips. They employ a Harvard architecture with separate program and data registers, feature dedicated hardware multipliers, extensive pipeline operations, and provide specialized DSP instructions for rapidly implementing various digital signal processing algorithms. FPGAs are a further development of programmable devices like PALs and GALs. They emerged as a semi-custom circuit within the application-specific integrated circuit (ASIC) field, addressing both the limitations of custom circuits and the limited gate count of existing programmable devices. A BSDL file is a spreadsheet describing an IC's IEEE 1149.1 or JTAG design. The EXTEST instruction places the IC in external boundary scan test mode, effectively affecting normal chip operation. This instruction is used for external chip testing. Output pins in test mode are driven by a BSC update latch. The BSCscan latch captures input data for shifting operations. Test stimulus can be input through TDI and the test response observed through TDO. After the shift operation, the new test stimulus is stored in the BSC's update latch.

[0061] like Figure 4 As shown, a design implementation system is used to test the hybrid interconnection network. If the hybrid interconnection network is determined to have a fault, the fault type is diagnosed through the boundary scan test method to cover the hybrid interconnection network fault. The implementation system mainly includes a DC regulated power supply, a DC / DC converter, a programmable device, a host computer, a CPU core board, a crystal oscillator, a memory, an FPGA core board, a microsystem chip, etc. The DC regulator is connected to the DC / DC converter, the DC / DC converter is connected to the microsystem chip, the programmable device is connected to the DC / DC converter and the host computer respectively, the host computer is connected to the programmable device and the microsystem chip respectively, and at the same time, the microsystem chip is connected to the CPU core board, crystal oscillator, memory, and FPGA core board respectively. At the same time, the implementation system is integrated with the boundary scan system, the host computer is connected to the boundary scan test system, and the boundary scan test system is connected to the microsystem chip. The power-on timing and reset signal are controlled by the programmable device, and the functional test program is run to perform full-address read and write verification and interface protocol testing on the non-boundary scan chip interconnection network.

[0062] The installed system uses a series of test steps, such as FPGA program burning, DSP SPI interface test, DDR initialization and read / write test, NAND Flash full address test, SRIO interface test, etc., to detect whether there is a fault in the interconnection network between the chips in the chip microsystem. If it is determined that the hybrid interconnection network has a fault, the boundary scan test program is triggered to diagnose the fault type through the boundary scan test method. The specific steps are as follows:

[0063] The voltage regulator provides the microsystem chip with the necessary voltage for operation via a DC / DC converter. The circuit's power-on sequence and reset signal are controlled by the onboard programmable device. The host computer inputs commands to the onboard programmable device to control its operation. A crystal oscillator provides the microsystem with a clock signal.

[0064] If the FPGA program can be burned into the internal NOR FLASH normally and the FPGA is successfully booted, it means that there is no fault in the interconnection network between the FPGA chip and the NOR FLASH chip.

[0065] DSP erases the built-in NOR FLASH through the SPI interface, traverses all address read and write tests, and compares whether the read and written data are consistent. If they are consistent, the test passes, indicating that there is no fault in the interconnection network between the DSP chip and the NOR FLASH chip.

[0066] The FPGA chip loads the test program from the NOR FLASH and initializes the DDR. After initialization, the test program reads and writes all addresses of the DDR and compares whether the read and write data are consistent. If they are consistent, the test passes, indicating that there is no fault in the interconnection network between the FPGA chip and the DDR chip.

[0067] The DSP chip loads the test program from the NOR FLASH and initializes the DDR. After initialization, the test program reads and writes all addresses of the DDR and compares whether the read and write data are consistent. If they are consistent, the test passes, indicating that there is no fault in the interconnection network between the DSP chip and the DDR chip.

[0068] Use the emulator to connect the CIB chip and run the test program to perform a full-address test on the NAND Flash. Compare the read and write data to see if they are consistent. If they are consistent, the test passes, indicating that there is no fault in the interconnection network between the CIB chip and the NAND Flash chip.

[0069] Configure the CIB's SRIO interface mode and execute the SRIO data write request instruction in the FPGA / DSP. This sends a write packet request to the CIB's SRIO interface. After the CIB chip receives the write request instruction, it performs a packet exchange operation and returns a write response packet to the FPGA / DSP. After the event is complete, execute the SRIO data read request instruction in the FPGA / DSP and send a read packet request to the CIB's SRIO interface. After the CIB chip receives the read request instruction, it performs a packet exchange operation and returns a read response packet to the FPGA / DSP. If this function is implemented, it indicates that the interconnection network between the CIB chip and the FPGA / DSP chip is healthy.

[0070] If the hybrid interconnect network is determined to have a fault, the boundary scan test program is triggered, and then the fault type is diagnosed through the boundary scan test method to specifically locate which line has a problem, whether it is an open circuit fault or a short circuit fault.

[0071] The boundary scan system is integrated with the mounting system, the host computer is connected with the boundary scan test system, and the boundary scan test system is connected with the microsystem chip.

[0072] Combining the test results of the above two test methods, the global fault coverage of the chiplet microsystem interconnection network is output.

[0073] This method achieves high coverage testing (target coverage of 100%) of the chiplet microsystem interconnection network without increasing hardware costs through the coordinated cooperation of chiplet microsystem interconnection network classification, boundary scan testing, and actual assembly testing. The specific logic is as follows:

[0074] First, the classification of interconnect networks serves as the basis for decision-making in test strategies. By analyzing the chip microsystem architecture, interconnect networks are divided into two categories: one is chip interconnects that support boundary scan technology on both ends (such as the EMIF interface between DSP and FPGA), and the other is hybrid interconnects with a boundary scan chip on one end and a non-boundary scan chip on the other (such as the SPI interface between FPGA and NOR Flash, and the interconnection between CIB and NAND Flash). This classification directly determines the allocation of test resources—boundary scan testing is preferred for boundary scan interconnect networks to reduce costs, while hybrid interconnect networks must rely on actual assembly testing to cover physical connections. This classification mechanism avoids the waste of resources caused by blindly selecting methods in traditional testing, such as avoiding ineffective testing caused by forcibly using boundary scan technology on non-scan chips.

[0075] Secondly, boundary scan testing and on-device testing complement each other in functionality. For boundary scan interconnect networks, the EXTEST instruction set is generated by parsing the BSDL files of chips like DSPs and FPGAs. Automatic test equipment (ATE) then loads the test vectors and compares the response data bit by bit, accurately locating the specific failing pin or circuit (e.g., a shorted data line on an EMIF interface). However, this method fails to cover interconnects with non-boundary scan chips (e.g., Flash, DDR, etc.). In this case, on-device testing is necessary: by building an on-device test system that includes programmable devices, clock modules, and multiple memory interfaces, full-address read and write verification (e.g., a DSP traversing the NOR Flash address space via the SPI interface) and protocol interaction testing (e.g., SRIO packet exchange between the FPGA and CIB) is performed to verify the physical connectivity and signal integrity of the hybrid interconnect network. However, on-device testing can only determine whether an interconnect group has an anomaly (e.g., "FPGA-DDR interconnect failure") and cannot pinpoint the specific failing circuit. Further boundary scan testing is required for root-cause diagnosis.

[0076] Ultimately, the dynamic collaboration of the three achieves global coverage. When the actual installation test detects an anomaly in a hybrid interconnect network (such as a failure in communication between CIB and NAND Flash), the system automatically triggers the boundary scan test, and scans the interconnection lines of the relevant boundary scan chip line by line (such as the SRIO interface connected to the CIB), and quickly locates the specific fault point (such as a broken SRIO data line). The classification mechanism ensures that no interconnection network is missed, the boundary scan test provides high-precision diagnosis, and the actual installation test covers the physical layer blind area. The two are combined to output a global fault coverage report. This collaborative mechanism not only reduces costs, but also solves the defect of traditional actual installation testing that "only finds problems but cannot locate them", and makes up for the limitation that a single boundary scan technology is ineffective for non-scanning devices, ultimately realizing a complete test closed loop for the microsystem interconnection network.

[0077] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0078] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A chiplet-based microsystem interconnection testing method, characterized in that: include: Step S1, analyzing the chiplet microsystem structure and classifying the chiplet microsystem interconnection network into a boundary scan chip interconnection network and a hybrid interconnection network; Step S2, generating test vectors based on boundary scan technology, loading and running the test vectors through automatic test equipment to cover boundary scan chip interconnect network faults; Step S3: Designing a real-world test system to test the hybrid interconnection network. If the hybrid interconnection network is determined to have a fault, triggering a boundary scan test program to diagnose the fault type using a boundary scan test method. Step S4: combining the test results of step S2 and step S3, outputting the global fault coverage of the chiplet microsystem interconnection network.

2. The chiplet-based microsystem interconnection testing method according to claim 1, characterized in that: The interconnection network of the chip microsystem is classified according to whether the chip supports boundary scan technology, including: Boundary scan chip interconnect network: The chips connected at both ends of the interconnect network support boundary scan technology; Hybrid interconnection network: One end of the interconnection network is connected to the boundary scan chip, and the other end is connected to the non-boundary scan chip.

3. The chiplet-based microsystem interconnection testing method according to claim 2, characterized in that: The boundary scan chip interconnection network includes an interconnection network of DSP microcomponents and FPGA microcomponents.

4. The chiplet-based microsystem interconnection testing method according to claim 2, characterized in that: The hybrid interconnection network includes at least an interconnection network between NAND FLASH and CIB, an interconnection network between DSP microcomponents and CIB, an interconnection network between FPGA microcomponents and CIB, an interconnection network between NOR FLASH single chip and FPGA single chip, an interconnection network between DDR single chip and FPGA single chip, and an interconnection network between NOR FLASH single chip and DSP single chip.

5. The chiplet-based microsystem interconnection testing method according to claim 2, characterized in that: The specific steps of automatically generating test vectors based on boundary scan technology and loading and running the test vectors through automatic test equipment include: Configure the state of the chiplet microsystem according to the type and model of the integrated circuit; Parse the DSP's EXTEST instruction through the DSP's boundary scan file BSDL; Parse the FPGA's EXTEST instruction through the FPGA's boundary scan file BSDL; After the core microsystem is configured, the test vectors adapted to the ATE equipment are generated according to the EXTEST instruction; The test vector is compared with the actual response vector. If they are consistent, it is determined that the interconnection network has no faults and the chip under test is normal.

6. The chiplet-based microsystem interconnection testing method according to claim 1, characterized in that: The actual installation test system includes: a DC regulated power supply, a DC / DC converter, a programmable device, a host computer, a CPU core board, a crystal oscillator, a memory, an FPGA core board and a microsystem chip. The DC regulator is connected to the DC / DC converter, the DC / DC converter is connected to the microsystem chip, the programmable device is respectively connected to the DC / DC converter and the host computer, the host computer is respectively connected to the programmable device and the microsystem chip, the microsystem chip is respectively connected to the CPU core board, crystal oscillator, memory and FPGA core board, the actual installation test system is integrated with the boundary scan system, the host computer is connected to the boundary scan test system, the boundary scan test system is connected to the microsystem chip, the power-on timing and reset signal are controlled by the programmable device, and the functional test program is run to perform full-address read and write verification and interface protocol testing on the non-boundary scan chip interconnection network.

7. The chiplet-based microsystem interconnection testing method according to claim 6, characterized in that: The full address read and write verification includes: Verification of interconnection between DSP and NOR FLASH: Perform full-address erase and read / write test on NOR FLASH through SPI interface of DSP, and compare the read / write data consistency. If they are consistent, it is determined that there is no fault in the interconnection network between DSP and NOR FLASH. FPGA and DDR interconnection verification: Initialize the DDR and perform full-address read and write tests by loading the FPGA test program, and compare the read and write data consistency. If they are consistent, it is determined that the FPGA and DDR interconnection network is fault-free; DSP and DDR interconnection verification: Initialize the DDR and perform full-address read and write tests by loading the DSP test program, and compare the read and write data consistency. If they are consistent, it is determined that the DSP and DDR interconnection network is fault-free; CIB and NAND Flash interconnection verification: Connect the CIB chip to the emulator and run the test program to perform full-address read and write tests on the NAND Flash. Compare the read and write data consistency. If they are consistent, it is determined that the CIB and NAND Flash interconnection network is fault-free.

8. The chiplet-based microsystem interconnection testing method according to claim 6, characterized in that: The interface protocol test includes: SRIO write operation verification: Run the SRIO data write request instruction in the FPGA or DSP, send a write data packet request to the SRIO interface of the CIB, and the CIB chip performs the data packet exchange operation after receiving the write request and returns a write response packet to the FPGA or DSP after the operation is completed. SRIO read operation verification: Run the SRIO data read request instruction in the FPGA or DSP and send a read data packet request to the SRIO interface of the CIB. After receiving the read request, the CIB chip performs the data packet exchange operation and returns a read response packet to the FPGA or DSP after the operation is completed. If both the write response packet and the read response packet comply with the protocol specifications and the data is complete, it is determined that the SRIO interconnection network between the CIB chip and the FPGA / DSP chip is fault-free.

9. The chiplet microsystem interconnection testing method according to claim 1, wherein: The method is applicable to a core microsystem comprising the following components: At least one CIB chip, FPGA micro-component, DSP micro-component, NAND Flash micro-component; The FPGA micro-component and the DSP micro-component are interconnected via the SRIO X4 interface and the EMIF interface, and the CIB chip is connected to the FPGA micro-component and the DSP micro-component respectively via the SRIO X4 interface.

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