Voltage stabilizing circuit, memory and memory system

Abstract

The invention provides a voltage stabilizing circuit, a memory and a memory system, and relates to the technical field of semiconductor chips. The voltage stabilizing circuit comprises a load pair transistor, an input pair transistor and a first transistor. The input pair transistor is coupled between the load pair transistor and the first transistor; the load pair transistor is coupled with a first voltage end, and the first transistor is coupled with a second voltage end; a transistor of the input pair transistor is in an on state when a voltage difference between a gate and a source is less than or equal to zero. The voltage stabilizing circuit aims to solve the problems that a voltage stabilizing circuit is poor in stability and cannot provide stable voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a voltage stabilizing circuit, a memory, and a storage system. Background Art

[0002] A low dropout regulator (LDO) is a circuit that converts a high input voltage into a low, stable output voltage. Widely used in storage devices, LDOs are characterized by their low voltage dropout. This means the voltage difference between the input and output voltages is very small. This allows LDOs to operate even when the input voltage is close to the output voltage, reducing energy waste and improving efficiency. Summary of the Invention

[0003] The embodiments disclosed herein provide a voltage stabilizing circuit, a memory, and a storage system. The embodiments disclosed herein employ the following technical solutions:

[0004] In a first aspect, a voltage stabilization circuit is provided, comprising: a load pair transistor, an input pair transistor, and a first transistor; the input pair transistor is coupled between the load pair transistor and the first transistor; the load pair transistor is coupled to a first voltage terminal, and the first transistor is coupled to a second voltage terminal; the transistor of the input pair transistor is in an on state when the voltage difference between the gate and the source is less than or equal to zero.

[0005] In some embodiments, the input pair transistor includes a second transistor and a third transistor, the first end of the second transistor is coupled to the load pair transistor, and the second end of the second transistor is coupled to the first end of the first transistor; the first end of the third transistor is coupled to the load pair transistor, the second end of the third transistor is coupled to the first end of the first transistor, and the control end of the third transistor is coupled to the third voltage end.

[0006] In some embodiments, the second transistor and the third transistor are N-channel depletion-type MOS transistors.

[0007] In some embodiments, the load pair transistor includes a fourth transistor and a fifth transistor; the first end of the fourth transistor is coupled to the first voltage end, the second end of the fourth transistor is coupled to the first end of the second transistor, and the control end of the fourth transistor is coupled to the second end of the fourth transistor; the first end of the fifth transistor is coupled to the first voltage end, the second end of the fifth transistor is coupled to the first end of the third transistor, and the control end of the fifth transistor is coupled to the second end of the fourth transistor.

[0008] In some embodiments, the load pair transistor is a P-channel MOS transistor, and the first transistor is an N-channel MOS transistor.

[0009] In some embodiments, the voltage stabilizing circuit further includes: a power control circuit and a voltage divider circuit; the first end of the power control circuit is coupled to the fourth voltage end, the second end of the power control circuit is coupled to the first end of the voltage divider circuit, the second end of the power control circuit is coupled to the output end of the voltage stabilizing circuit, and the third end of the power control circuit is coupled to the first end of the third transistor; the second end of the voltage divider circuit is coupled to the fifth voltage end, and the third end of the voltage divider circuit is coupled to the control end of the second transistor.

[0010] In some embodiments, the power control circuit includes a sixth transistor; the first end of the sixth transistor is coupled to the first end of the power control circuit, the second end of the sixth transistor is coupled to the second end of the power control circuit, and the control end of the sixth transistor is coupled to the third end of the power control circuit.

[0011] In some embodiments, the sixth transistor is a P-channel MOS transistor or an N-channel MOS transistor.

[0012] In a second aspect, a memory is provided, comprising a memory array and a peripheral circuit coupled to the memory array, the peripheral circuit comprising a voltage stabilizing circuit; the voltage stabilizing circuit is configured to provide voltage to the memory array; the voltage stabilizing circuit comprises a load pair transistor, an input pair transistor, and a first transistor; the input pair transistor is coupled between the load pair transistor and the first transistor; the load pair transistor is coupled to the first voltage terminal, and the first transistor is coupled to the second voltage terminal; the transistor of the input pair transistor is in an on state when the voltage difference between the gate and the source is less than or equal to zero.

[0013] According to a third aspect, a storage system is provided. The storage system includes a storage controller and the memory according to the second aspect, wherein the storage controller is configured to control the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A block diagram of an electronic device provided for an embodiment of the present disclosure;

[0015] Figure 2 A block diagram of a storage system provided in an embodiment of the present disclosure;

[0016] Figure 3 A block diagram of a memory provided for an embodiment of the present disclosure;

[0017] Figure 4 A block diagram of a peripheral circuit provided for an embodiment of the present disclosure;

[0018] Figure 5 A circuit diagram of a voltage stabilizing circuit provided in an embodiment of the present disclosure;

[0019] Figure 6 A circuit diagram of an operational amplifier circuit provided in an embodiment of the present disclosure;

[0020] Figure 7 A circuit diagram of another voltage stabilizing circuit provided in an embodiment of the present disclosure;

[0021] Figure 8 A schematic diagram of circuit stability simulation provided by an embodiment of the present disclosure;

[0022] Figure 9 Another circuit stability simulation schematic diagram provided by an embodiment of the present disclosure;

[0023] Figure 10 A schematic diagram of a Monte Carlo analysis of a circuit provided by an embodiment of the present disclosure;

[0024] Figure 11 Another circuit Monte Carlo analysis schematic diagram provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0026] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0027] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0028] When describing some embodiments, the term "coupled" and its derivatives may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. In this case, "coupled" can also be described as "connected." Furthermore, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

[0029] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0030] "A and / or B" includes the following three combinations: A only, B only, and the combination of A and B. The use of "suitable for" or "configured to" herein is intended to be open and inclusive, and does not exclude devices that are suitable for or configured to perform additional tasks or steps. Furthermore, the use of "based on" is intended to be open and inclusive, as a process, step, calculation, or other action "based on" one or more conditions or values may, in practice, be based on additional conditions or values beyond those specified.

[0031] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0032] The embodiments of the present disclosure provide an electronic device, which may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc. Figure 1 , Figure 1 A schematic diagram of an electronic device 10 provided in an embodiment of the present disclosure is shown, including a host 100 and a storage system 110. The host 100 is coupled to the storage system 110 to write data to the storage system 110 or read data stored in the storage system 110. The host is also called a master device, and the storage system is also called a slave device. In an electronic device, a slave device can be accessed by different master devices. For example, taking a mobile phone as an example, the central processing unit (CPU) and digital signal processing (DSP) of the mobile phone can all serve as hosts to access the storage system.

[0033] For example, see Figure 2 , Figure 2FIG2 shows a schematic diagram of a storage system 110 provided in an embodiment of the present disclosure. The storage system 110 includes a memory controller 111 and a memory 112. The memory controller 111 is coupled to the memory 112 to control the memory 112 to store data. The memory 112 can be a two-dimensional (2D) memory or a three-dimensional (3D) memory.

[0034] The storage system 110 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package). That is, the storage system 110 can be applied to and packaged in different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0035] In some embodiments, the storage system 110 includes a memory controller 111 and multiple memories 112. The storage system 110 may be integrated into a memory card. The memory card includes any one of a personal computer memory card international association (PCMCIA) card (abbreviated as PC card), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multi-media card (MMC), a secure digital memory card (SD), and a UFS.

[0036] Figure 3 1 shows a schematic diagram of a memory 112, which may include a peripheral circuit 200 and a memory array 300.

[0037] Figure 4 FIG. 3 shows a schematic structural diagram of a memory array 300 and a peripheral circuit 200 . Figure 4In the embodiment, the peripheral circuit 200 includes an I / O interface 210, a control logic unit 220, a row decoder 230, a voltage generator 240, a column decoder 260, a page buffer 250, a data bus 270 and a register 280. It should be understood that in some examples, the peripheral circuit 200 may also include Figure 4 Additional circuitry not shown.

[0038] The I / O interface 210 may be coupled to the control logic unit 220 and act as a control buffer to buffer data from a memory controller (eg, Figure 2 The I / O interface 210 receives control commands received from the memory controller 111 in the memory cell array 300 and relays them to the control logic unit 220, and buffers status information received from the control logic unit 220 and relays it to the host. The I / O interface 210 can also be coupled to the page buffer 250 via the data bus 270 and acts as a data I / O interface 210 and a data buffer to buffer data and relay it to or from the memory cell array 300.

[0039] The control logic unit 220 may be coupled to the voltage generator 240, the page buffer 250, the column decoder 260, the row decoder 230, and the I / O interface 210, and may be configured to control the operation of the various peripheral circuits. The control logic unit 220 may generate an operation signal to control the operation of the row decoder 230, the column decoder 260, the page buffer 250, and the voltage generator 240 in response to a command (CMD) or control signal from the memory controller 111; the command may be a program command, a read command, or the like.

[0040] The row decoder 230 may supply the word line voltage generated from the voltage generator 240 to the selected word lines and unselected word lines of the memory cell array 300 in response to the control of the control logic unit 220. As described in detail below, the row decoder 230 is configured to perform a program operation on the memory cells coupled to one or more selected word lines in the memory cell array 300.

[0041] The voltage generator 240 may generate various voltages for performing operations such as erasing, programming, reading, and verifying on the memory cell array 300 using an external power supply voltage or an internal power supply voltage.

[0042] The column decoder 260 may be controlled in response to the control logic unit 220 and select one or more memory cell strings 310 in the memory cell array 300 by applying a bit line voltage generated from the voltage generator 240 .

[0043] The page buffer 250 can read data from the memory cell array 300 and program (write) data to the memory cell array 300 according to the control signal from the control logic unit 220. In one example, the page buffer 250 can store the program data (write data) to be programmed into the memory cell array 300. In another example, the page buffer 250 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer 250 can also detect a low-power signal from the bit line representing the data bit stored in the memory cell and amplify the small voltage swing to a recognizable logic level during a read operation.

[0044] The register 280 may be coupled to the control logic unit 220 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.

[0045] Those skilled in the art will appreciate that the operations performed by the row decoder 230, the page buffer 250, the control logic unit 220, and the voltage generator 240 described in this disclosure may be performed by a processing circuit. The processing circuit may include, but is not limited to, hardware such as a logic circuit or a hardware / software combination such as a processor that executes software.

[0046] In a feasible implementation, the voltage generator 240 may include a voltage stabilizing circuit 2401 . When the voltage generator 240 provides voltage to the memory array, the voltage stabilizing circuit 2401 may convert a high voltage input into a stable low voltage output.

[0047] The following will be combined with the Figure 5 , for an explanation of the overall structure of the voltage stabilization circuit, see Figure 5 The voltage stabilization circuit can be divided into three sub-circuits as a whole, including the operational amplifier circuit, the power control circuit and the voltage divider circuit.

[0048] The operational amplifier circuit can be a multi-terminal device. A first terminal (S1A) of the operational amplifier circuit can be coupled to a first voltage terminal, which can be a VDD terminal. A second terminal (S1B) of the operational amplifier circuit can be coupled to a third terminal (S2C) of the power control circuit. A fourth terminal (S1D) of the operational amplifier circuit can be coupled to a second voltage terminal, which can be a GND terminal. The GND terminal is a ground reference voltage, typically 0V. A third terminal (S1C) of the operational amplifier circuit can be coupled to a third voltage terminal, which can be a Vref terminal. The voltage at the Vref terminal can be a reference voltage. The voltage value of the first voltage terminal is greater than the voltage value of the third voltage terminal. For example, VDD is a high voltage of 1.8V, and Vref is a low voltage of 0.6V.

[0049] The power control circuit can be a multi-terminal device, the first terminal (S2A) of the power control circuit can be coupled to the fourth voltage terminal, the fourth voltage terminal can be the VDD terminal, the second terminal (S2B) of the power control circuit can be coupled to the first terminal (S3A) of the voltage divider circuit, the second terminal (S2B) of the power control circuit can also be coupled to the output terminal of the voltage stabilizing circuit, the output terminal can be the Vout terminal, and the output terminal of the voltage stabilizing circuit is used to connect to the load terminal.

[0050] The voltage divider circuit can be a multi-terminal device, the second terminal (S3B) of the voltage divider circuit can be coupled to the fifth voltage terminal, the fifth voltage terminal can be the GND terminal, the GND terminal is the ground reference voltage, usually 0V, and the third terminal (S3C) of the voltage divider circuit can be coupled to the fifth terminal (S1E) of the operational amplifier circuit.

[0051] The first terminal of the power control circuit is used to input a relatively high voltage, and the third terminal of the power control circuit is used to input a control voltage provided by the operational amplifier circuit. The power control circuit can be configured to provide an output voltage to the load terminal based on the control voltage and the input voltage provided by the fourth voltage terminal. The voltage output by node S2B and the voltage input by node S2A have a small voltage difference. For example, the voltage input by the first terminal of the power control circuit can be 1.8V, while the voltage output by the second terminal of the power control circuit can be 1.7V. The voltage divider circuit can be used to collect the voltage output by the second terminal of the power control circuit and feed the collected voltage back to the operational amplifier circuit. The operational amplifier circuit can be used to compare the voltage fed back by the voltage divider circuit with a reference voltage and then adjust the control voltage provided to the power control circuit based on the comparison result. Through closed-loop voltage feedback control, the voltage output by the power control circuit has a high degree of stability.

[0052] For example, when the output end (Vout end) of the voltage stabilizing circuit causes the voltage to drop due to load changes or other reasons, the voltage across the voltage divider circuit will also drop, thereby causing the voltage at point M in the voltage divider circuit to drop. Furthermore, the voltage divider circuit feeds back the voltage information of point M to the operational amplifier circuit, and the operational amplifier circuit compares the potential of point M with the reference voltage of the third end (Vref) of the operational amplifier circuit. Then, the operational amplifier circuit reduces the control voltage output to the power control circuit, causing the potential of the third end (S2C) of the power control circuit to drop, and the current of the power control circuit will increase. The increase in the current of the power control circuit will cause the voltage of the output end (Vout end) of the voltage stabilizing circuit to rise, completing a feedback control, so that the output end (Vout end) of the voltage stabilizing circuit returns to the normal potential.

[0053] When the voltage at the output end (Vout end) of the voltage stabilizing circuit increases due to load changes or other reasons, the voltage at both ends of the voltage divider circuit will also increase, thereby causing the voltage at point M in the voltage divider circuit to increase. Furthermore, the operational amplifier circuit compares the potential at point M with the reference voltage at the third end (Vref end) of the operational amplifier circuit. The operational amplifier circuit will increase the control voltage output to the power control circuit, causing the potential of the third end (S2C) of the power control circuit to increase, and the current of the power control circuit will decrease. The decrease in current of the power control circuit will cause the voltage at the output end (Vout end) of the voltage stabilizing circuit to decrease, completing a feedback control, so that the voltage at the output end (Vout end) of the voltage stabilizing circuit returns to the normal potential.

[0054] It can be seen that the control voltage output by the operational amplifier circuit directly affects the voltage regulation capability of the voltage regulator circuit. That is, if the control voltage output by the operational amplifier circuit is stable, the voltage regulation capability of the voltage regulator circuit is also stable. Therefore, ensuring the stability and accuracy of the control voltage output by the operational amplifier circuit can ensure that the entire voltage regulator circuit has good voltage regulation capability.

[0055] The following will be combined with the Figure 6 , for a detailed description of the structure and working principle of the operational amplifier circuit, see Figure 6 The operational amplifier circuit includes a load pair transistor, an input pair transistor, and a first transistor. The input pair transistor is coupled between the load pair transistor and the first transistor; the load pair transistor is coupled to the first voltage terminal, and the first transistor is coupled to the second voltage terminal. The input terminal of the operational amplifier circuit can be the fifth terminal (S1E) of the operational amplifier circuit, the output terminal of the operational amplifier circuit can be the second terminal (S1B) of the operational amplifier circuit, the output terminal of the voltage divider circuit is used for feedback connection to the input terminal of the operational amplifier circuit, and the output terminal of the operational amplifier circuit is used to output a control voltage provided to the power control circuit.

[0056] In an operational amplifier circuit, the gates of the input pair transistors are used to input the voltage fed back by the voltage divider circuit and the reference voltage, respectively. Changes in the voltage fed back by the voltage divider circuit and the reference voltage will cause changes in the control voltage output by the operational amplifier circuit. Since the reference voltage is a fixed value, the control voltage output by the operational amplifier circuit depends on the voltage fed back by the voltage divider circuit. The load pair transistors form an active current mirror and, acting as the load of the operational amplifier circuit, transmit the voltage changes fed back by the voltage divider circuit to the output of the operational amplifier circuit, thereby causing changes in the control voltage.

[0057] The first transistor controls the tail current, which is the total current flowing through the operational amplifier circuit. Controlling the tail current can influence key circuit performance, such as gain and bias point. The primary purpose of tail current control is to adjust the circuit's operating point so that it operates within the desired current and voltage ranges.

[0058] When the input pair transistor is an N-channel enhancement-mode MOS transistor, since the N-channel enhancement-mode MOS transistor has the characteristic of being in the on state when the voltage difference between the gate and source is greater than or equal to the threshold voltage, a voltage difference will exist between the drain voltage of the first transistor and the gate of the input pair transistor, thereby causing the drain voltage (point P) of the first transistor to be lower than the voltage of the gate of the input pair transistor. If the voltage difference between the source and drain of the first transistor is smaller, the first transistor is more likely to enter the linear operating region, causing the entire voltage regulator circuit to be unstable. Therefore, it is necessary to increase the drain voltage of the first transistor so that the first transistor operates in the saturation region, thereby maintaining a stable operating state for the entire voltage regulator circuit.

[0059] In a feasible implementation, the load pair transistor may be a P-channel MOS transistor, and the first transistor may be an N-channel MOS transistor.

[0060] In one possible implementation, the transistor of the input pair transistor is in an on state when a voltage difference between a gate and a source is less than or equal to zero.

[0061] The input pair transistors can be replaced to increase the drain voltage of the first transistor. The input pair transistors having the characteristic of being in the on-state when the voltage difference between the gate and the source is greater than or equal to the threshold voltage are replaced with input pair transistors having the characteristic of being in the on-state when the voltage difference between the gate and the source is less than or equal to zero. Since the input pair transistors are in the on-state when the voltage difference between the gate and the source is less than or equal to zero, the drain (point P) voltage of the first transistor can be made equal to or greater than the voltage of the gate of the input pair transistor, and thus the voltage difference between the source and the drain of the first transistor is larger. By replacing the input pair transistors, the first transistor can be placed in the saturation region, thereby ensuring the stability of the output of the operational amplifier circuit.

[0062] Setting the transistor of the input pair transistor to be in the on state when the voltage difference between the gate and the source is less than or equal to zero, compared to setting the transistor of the input pair transistor to be in the on state when the voltage difference between the gate and the source is greater than or equal to the threshold voltage, can effectively increase the drain voltage of the transistor that controls the tail current, so that the transistor that controls the tail current can operate stably in the saturation region, thereby making the output voltage of the entire voltage stabilizing circuit have higher stability, and the voltage stabilizing circuit has good voltage following performance.

[0063] The following will be combined with the Figure 7 The structure and voltage transfer relationship between the input transistor pair and the load transistor pair are explained.

[0064] In one possible embodiment, the input pair transistors include a second transistor and a third transistor, wherein the source (Q2B) of the second transistor is coupled to the drain (Q1A) of the first transistor; the source (Q3B) of the third transistor is coupled to the drain (Q1A) of the first transistor; and the gate (Q3C) of the third transistor is coupled to the third voltage terminal. The load pair transistors include a fourth transistor and a fifth transistor, wherein the source (Q4A) of the fourth transistor is coupled to the first voltage terminal, the drain (Q4B) of the fourth transistor is coupled to the drain (Q2A) of the second transistor, and the gate (Q4C) of the fourth transistor is coupled to the drain (Q4B) of the fourth transistor. The source (Q5A) of the fifth transistor is coupled to the first voltage terminal, the drain (Q5B) of the fifth transistor is coupled to the drain (Q3A) of the third transistor, and the gate (Q5C) of the fifth transistor is coupled to the gate (Q4C) of the fourth transistor.

[0065] The transfer relationship between the input voltage of the operational amplifier circuit and the voltage at node N can be expressed as formula (1):

[0066]

[0067] In the above expression, V N Represents the voltage of node N, V in represents the voltage at the non-inverting input terminal of the operational amplifier circuit, that is, the voltage fed back by the voltage divider circuit, gm2 represents the transconductance of the second transistor, and the ratio of the slight change in drain current to the slight change in gate-source voltage that causes this change is called transconductance, which reflects the control ability of the gate-source voltage over the drain current. rO2 represents the output impedance of the second transistor, gm4 represents the transconductance of the fourth transistor, rO4 represents the output impedance of the fourth transistor, and / / represents a parallel relationship.

[0068] The relationship between the output voltage of the operational amplifier circuit and the voltage at node N can be expressed as follows:

[0069]

[0070] In the above expression, V N Represents the voltage of node N, V out represents the output voltage of the operational amplifier circuit, that is, the control voltage provided to the power control circuit, rO3 represents the output impedance of the third transistor, rO5 represents the output impedance of the fifth transistor, and gm5 represents the transconductance of the fifth transistor.

[0071] Based on the voltage transfer relationship shown in formula (1) and formula (2), the voltage transfer relationship between the output voltage of the operational amplifier circuit and the voltage at the non-inverting input terminal of the operational amplifier circuit can be determined. Since the transconductance values of the load to the transistor are the same, that is, gm4 = gm5, the voltage transfer relationship between the output voltage of the operational amplifier circuit and the voltage at the non-inverting input terminal of the operational amplifier circuit can be shown as formula (3):

[0072]

[0073] For example, when V in When it increases by 0.1V, V out The corresponding increase is 0.1gm2(rO3 / / rO5)V. When V in When V out It also correspondingly reduces 0.2gm2(rO3 / / rO5)V.

[0074] In a feasible implementation, the fourth transistor and the fifth transistor may be P-channel MOS transistors, the first transistor may be an N-channel MOS transistor, and the sixth transistor may be a P-channel MOS transistor or an N-channel MOS transistor.

[0075] In a feasible embodiment, in combination with the Figure 7 The detailed structure and principle of the power control circuit are described. The power control circuit includes a sixth transistor, which is a P-channel MOS transistor. The source (Q6A) of the sixth transistor is coupled to the first end (S2A) of the power control circuit, the drain (Q6B) of the sixth transistor is coupled to the second end (S2B) of the power control circuit, and the control end (Q6C) of the sixth transistor is coupled to the third end (S2C) of the power control circuit.

[0076] For example, the source (Q6A) of the sixth transistor is used to input a higher voltage, the control terminal (Q6C) of the sixth transistor is used to input the control voltage provided by the operational amplifier circuit, the sixth transistor can be configured to provide an output voltage to the load terminal based on the control voltage and the input voltage provided by the third voltage terminal, and the drain (Q6B) of the sixth transistor provides an output voltage to the load terminal.

[0077] In a feasible embodiment, in combination with the Figure 7 The detailed structure and principle of the voltage divider circuit are described. The voltage divider circuit can be implemented in the form of resistor voltage divider. The voltage divider circuit can include a first voltage divider resistor (R1) and a second voltage divider resistor (R2). The relationship between the output voltage of the power control circuit collected by the voltage divider circuit and the voltage fed back to the operational amplifier circuit can be shown as formula (4):

[0078]

[0079] In the above expression, VS2B Represents the output voltage of the power control circuit, V S3C It represents the voltage fed back to the operational amplifier circuit by the voltage divider circuit, that is, the voltage fed back to the operational amplifier circuit by the voltage divider circuit changes with the output voltage of the power control circuit.

[0080] The following will be combined with the Figure 8 and Figure 9 , the stability of the voltage stabilizing circuit using N-channel enhancement-type MOS transistors and N-channel depletion-type MOS transistors as input transistors is explained.

[0081] Figure 8 This is a schematic diagram of the stability simulation of the voltage stabilization circuit using an N-channel enhancement type MOS transistor as the input transistor. Figure 8 In the figure, the upper curve represents the schematic diagram of the change of the gain of the voltage stabilizing circuit with frequency, and the lower curve represents the schematic diagram of the change of the phase margin with frequency. The phase margin can be used to characterize the circuit stability of the voltage stabilizing circuit. The larger the phase margin value, the higher the circuit stability of the voltage stabilizing circuit.

[0082] It can be seen that when the gain of the voltage regulator circuit approaches zero, the phase margin of the voltage regulator circuit is 38 degrees. Figure 9 This is a schematic diagram of the stability simulation of the voltage regulator circuit using an N-channel depletion-type MOS transistor as the input transistor. Figure 9 In the figure, when the gain of the voltage regulator circuit approaches zero, the phase margin of the voltage regulator circuit is 66 degrees. It can be seen that the phase margin of the voltage regulator circuit using depletion-mode MOS transistors as input transistors is much greater than the phase margin of the voltage regulator circuit using enhancement-mode MOS transistors as input transistors. Therefore, the voltage regulator circuit using depletion-mode MOS transistors as input transistors has higher voltage stability.

[0083] Through Figure 8 and Figure 9 A comparative analysis shows that transistor voltage regulator circuits using depletion-mode MOS transistors as inputs perform better in terms of stability. Improved phase margin means better circuit stability, which is crucial for applications requiring high voltage accuracy and stability.

[0084] The following will be combined with the Figure 10 and Figure 11 , Monte Carlo analysis is performed on the voltage regulator circuit of the transistor using N-channel enhancement-type MOS transistors and N-channel depletion-type MOS transistors as input. Monte Carlo analysis is a statistical simulation method. Monte Carlo simulation is used to fit the process deviations introduced by the chip during the production process, and consider the impact of these random variables on circuit performance through multiple simulations.

[0085] Figure 10This is a Monte Carlo simulation diagram of a voltage regulator circuit using an enhancement mode MOS transistor as the input transistor. Figure 10 In the figure, the σ value of the transistor using an enhancement-mode MOS tube as the input is 4.06mV. Due to process limitations, there is a certain deviation between the ideal state and the actual state in the circuit, and the σ value reflects the deviation between the ideal state and the actual state. The smaller the σ value, the smaller the deviation between the ideal state and the actual state, and the more concentrated the normal distribution of the Monte Carlo simulation diagram.

[0086] For example, the standard value may be 10mv. For example, if the standard value is 10mv, the Monte Carlo simulation of the voltage stabilizing circuit meets the requirements if 3σ is less than or equal to 10mv. Figure 10 , 3σ=12.18mv>10mv, so it does not meet the requirements. Figure 11 This is a Monte Carlo simulation diagram of a depletion-type MOS transistor as an input transistor. Figure 11 In the example, a depletion-type MOS tube is used as the input transistor, and the σ value is 2.75mv. Figure 11 , 3σ=8.25mv<10mv, so it meets the requirements.

[0087] The voltage stabilizing circuit provided by the embodiment of the present disclosure can effectively increase the drain voltage of the transistor that controls the tail current by setting the transistor of the input pair transistor to be in the on state when the voltage difference between the gate and the source is less than or equal to zero, compared to setting the transistor of the input pair transistor to be in the on state when the voltage difference between the gate and the source is greater than or equal to the threshold voltage, so that the transistor that controls the tail current can operate stably in the saturation region, thereby making the output voltage of the entire voltage stabilizing circuit have higher stability, and the voltage stabilizing circuit has good voltage following performance.

[0088] The present disclosure also provides a memory, for example, the memory includes the voltage stabilizing circuit as in the above embodiment. Figure 3 The memory shown.

[0089] The present disclosure also provides a storage system. For example, the storage system includes the memory and the controller as described in the above embodiment, and the memory is coupled to the controller. Figure 2 The storage system shown.

[0090] The present disclosure also provides an electronic device, which includes a host and the aforementioned storage system, wherein the host and the storage system are connected. Figure 1 The electronic device shown.

[0091] Those skilled in the art will clearly understand that, for the convenience and brevity of description, in the above embodiments, the description of each embodiment has different emphases. For the parts that are not described in detail in a certain embodiment, reference can be made to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0092] It should be understood that the embodiments provided herein can be implemented in other ways. For example, the division of a module is merely a logical functional division, and in actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or ignoring or not implementing certain features.

[0093] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0094] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A voltage stabilizing circuit, characterized in that: include: a load pair transistor, an input pair transistor, and a first transistor; The input pair transistor is coupled between the load pair transistor and the first transistor; The load pair transistor is coupled to a first voltage terminal, and the first transistor is coupled to a second voltage terminal; The transistor of the input pair transistor is in an on state when a voltage difference between a gate and a source is less than or equal to zero.

2. The voltage stabilizing circuit according to claim 1, wherein: The input pair transistor includes a second transistor and a third transistor, a first terminal of the second transistor is coupled to the load pair transistor, and a second terminal of the second transistor is coupled to the first terminal of the first transistor; A first terminal of the third transistor is coupled to the load-pair transistor, a second terminal of the third transistor is coupled to the first terminal of the first transistor, and a control terminal of the third transistor is coupled to a third voltage terminal.

3. The voltage stabilizing circuit according to claim 2, wherein: The second transistor and the third transistor are N-channel depletion-type MOS transistors.

4. The voltage stabilizing circuit according to claim 2, wherein: The load pair transistors include a fourth transistor and a fifth transistor; A first terminal of the fourth transistor is coupled to the first voltage terminal, a second terminal of the fourth transistor is coupled to the first terminal of the second transistor, and a control terminal of the fourth transistor is coupled to the second terminal of the fourth transistor; A first terminal of the fifth transistor is coupled to the first voltage terminal, a second terminal of the fifth transistor is coupled to the first terminal of the third transistor, and a control terminal of the fifth transistor is coupled to the second terminal of the fourth transistor.

5. The voltage stabilizing circuit according to claim 1, wherein: The load pair transistor is a P-channel MOS transistor, and the first transistor is an N-channel MOS transistor.

6. The voltage stabilizing circuit according to claim 5, characterized in that: The voltage stabilizing circuit further includes: a power control circuit and a voltage dividing circuit; A first terminal of the power control circuit is coupled to the fourth voltage terminal, a second terminal of the power control circuit is coupled to the first terminal of the voltage divider circuit, a second terminal of the power control circuit is coupled to the output terminal of the voltage stabilization circuit, and a third terminal of the power control circuit is coupled to the first terminal of the third transistor; The second terminal of the voltage divider circuit is coupled to the fifth voltage terminal, and the third terminal of the voltage divider circuit is coupled to the control terminal of the second transistor.

7. The voltage stabilizing circuit according to claim 6, wherein: The power control circuit includes a sixth transistor; The first end of the sixth transistor is coupled to the first end of the power control circuit, the second end of the sixth transistor is coupled to the second end of the power control circuit, and the control end of the sixth transistor is coupled to the third end of the power control circuit.

8. The voltage stabilizing circuit according to claim 7, wherein: The sixth transistor is a P-channel MOS transistor or an N-channel MOS transistor.

9. A memory, characterized in that: The invention comprises a memory array and a peripheral circuit coupled to the memory array, wherein the peripheral circuit comprises a voltage stabilizing circuit; the voltage stabilizing circuit is configured to provide a voltage to the memory array; The voltage stabilizing circuit includes a load pair transistor, an input pair transistor and a first transistor; The input pair transistor is coupled between the load pair transistor and the first transistor; The load pair transistor is coupled to a first voltage terminal, and the first transistor is coupled to a second voltage terminal; The transistor of the input pair transistor is in an on state when a voltage difference between a gate and a source is less than or equal to zero.

10. A storage system, characterized in that: The invention comprises a memory controller and the memory according to claim 9, wherein the memory controller is configured to control the memory device.

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