Chip packaging structure and preparation method and application thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a chip packaging structure and a preparation method and application thereof. The chip packaging structure comprises a chip and a packaging component, wherein the chip and the packaging component are connected together through a copper connecting layer; and the copper connecting layer comprises a three-dimensional network structure formed by interweaving copper nanorods. According to the embodiment of the invention, the chip and the packaging component are attached together through the copper connecting layer, and the copper nanorod three-dimensional network structure in the copper connecting layer can improve the connection strength of the chip and the packaging component. A connecting layer between the chip and the packaging component is only copper, so that the electric conductivity and the heat conductivity are excellent, and the electric signal transmission and heat conduction performance of the chip can be improved; the copper connecting layer has a high melting point and is not easy to melt even if the chip packaging structure works at a high temperature, so that the reliability of the chip packaging structure can be improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a chip packaging structure and its preparation method and application. Background Art

[0002] With the rapid development of the semiconductor industry, electronic products are becoming increasingly miniaturized, and chip integration is increasing. This increased chip integration is enabling higher-power modules. Silicon carbide (SiC) boasts a wider bandgap than silicon (meaning it can block greater voltages and has a higher breakdown voltage) and lower thermal resistance (improving heat dissipation). Therefore, high-power modules are gradually transitioning from silicon-based IGBT (insulated gate bipolar transistor) chips to SiC-based chips.

[0003] For silicon-based chips, the packaging and manufacturing of their modules primarily utilizes a solder paste brazing process, which uses solder paste to connect the silicon chip to the substrate. Silicon-based modules using this process exhibit excellent thermal, electrical, and mechanical properties. However, when silicon carbide-based modules are packaged and manufactured using the same process, their excellent performance is significantly limited. This is primarily due to the high junction temperature (the actual operating temperature of semiconductors in electronic devices) of silicon carbide, while the tin connection layer produced by the solder paste brazing process has a low melting point. Under high operating temperatures, this connection layer easily melts and falls off. Therefore, the traditional solder paste brazing process can no longer meet the connection layer requirements of silicon carbide-based modules.

[0004] To this end, the industry has developed processes that use silver and copper pastes to replace tin paste. However, the high price of silver paste has limited its development. Moreover, whether it is tin paste, silver paste, or copper paste, they are all liquid solders containing solvents. The evaporation of solvents will cause high porosity in the connection layer between the chip and the substrate, affecting the connection strength between the chip and the substrate. Moreover, in high-density three-dimensional packaging, tin and silver are prone to migration under the influence of multiple fields such as thermal cycling, electromigration, oxidation, and pressure, growing a large number of whisker-like structures, which have a negative impact on the chip's electrical signal transmission and heat conduction, and may even cause electronic devices to short-circuit and fail. Summary of the Invention

[0005] The purpose of this application is to provide a chip packaging structure and its preparation method and application, aiming to solve the problems of insufficient connection strength between the chip and the packaging component, as well as poor electrical signal transmission and thermal conductivity of the connection layer between the chip and the packaging component, making it difficult to serve at high temperatures.

[0006] To achieve the above application objectives, the technical solutions adopted in this application are as follows:

[0007] In a first aspect, the present application provides a chip packaging structure, comprising a chip and a packaging component, wherein the chip and the packaging component are connected together via a copper connection layer; the copper connection layer comprises a three-dimensional mesh structure formed by interweaving copper nanorods.

[0008] The chip and the packaging component of the present application are connected together through a copper connection layer. The three-dimensional network structure of copper nanorods in the copper connection layer has a firm and stable structure, which can improve the connection strength between the chip and the packaging component.

[0009] Moreover, chips and packaging components used for chip packaging generally use copper for electrical signal transmission and heat conduction. The connection layer between the chip and the packaging component of the present application is only copper, which has excellent electrical and thermal conductivity, which is beneficial to improving the electrical signal transmission and thermal conductivity of the chip; the formed copper connection layer has a high melting point, and it is not easy to melt even if the chip packaging structure works at high temperature, thereby improving the reliability of the chip packaging structure and meeting the requirements of high-temperature service.

[0010] In some embodiments, the copper connection layer has a thickness of 0.5 to 2 μm, optionally 1 to 2 μm. A thin copper connection layer facilitates lightweight packaging. Even with such a thin copper connection layer, high connection strength can be achieved.

[0011] In some embodiments, the packaging component includes one or more of a ceramic substrate, a lead frame, a printed circuit board, and a strip;

[0012] And / or, the chip includes one or more of a silicon carbide-based chip, a silicon-based chip, and a gallium nitride-based chip.

[0013] Typically, the surfaces of these chips and packaging components are covered with copper.

[0014] The chip packaging structure of the present application is applicable to various chips and various packaging components and has a wide applicability. In particular, the chip packaging structure of the present application can be applied to the packaging structure of silicon carbide chips with high junction temperature characteristics, and is expected to be used in high-power module products.

[0015] In a second aspect, the present application provides a method for preparing a chip packaging structure, comprising:

[0016] Providing a chip and a packaging component each having a copper nanorod layer on its surface, and stacking the chip and the packaging component so that the copper nanorod layers of the two contact each other to obtain an intermediate component;

[0017] The intermediate piece is subjected to hot pressing sintering and annealing treatment.

[0018] This application utilizes the high surface activity of copper nanorods to deposit copper nanorod layers on the surfaces of the chip and packaging component. Once the two copper nanorod layers are in contact, the chip and packaging component can be bonded at low temperatures, reducing the copper-copper bonding temperature. Annealing after hot pressing promotes the diffusion of copper atoms in the copper nanorod layer, allowing the copper nanorod layers of the chip and packaging component to fuse together, forming a three-dimensional network structure. This creates a strong, stable copper connection layer between the chip and packaging component, improving the connection strength between the chip and packaging component.

[0019] Moreover, chips and packaging components used for chip packaging generally use copper for electrical signal transmission and heat conduction. The preparation method of the present application is a direct metal diffusion interconnection process without solder or adhesive. In the resulting chip packaging structure, the connection layer between the chip and the packaging component is only copper, which has excellent electrical and thermal conductivity, which is beneficial to improving the chip's electrical signal transmission and thermal conduction performance; the formed copper connection layer has a high melting point, and it is not easy to melt even if the chip packaging structure works at high temperature, thereby improving the reliability of the chip packaging structure and meeting the requirements of high-temperature service.

[0020] In addition, the preparation method of the present application does not require the deposition of a metal buffer layer on the surface, and does not require complex cleaning and photolithography processes to produce unique surface morphology. It has low requirements for the flatness of the surface of the chip and packaging components, greatly simplifies the chip packaging process, reduces costs, and is compatible with packaging components such as chips and ceramic substrates used in common power modules.

[0021] In some embodiments, the sizes of the copper nanorods contained in the copper nanorod layer on the chip surface and the packaging component surface are independently at least one of (1) to (3):

[0022] (1) The aspect ratio is (1.5-5):1, optionally (2-4):1;

[0023] (2) a diameter of 150 to 500 nm, optionally 200 to 400 nm;

[0024] (3) The length is 450 to 900 nm, optionally 600 to 800 nm.

[0025] Copper is arranged on the surface of the chip or packaging component in the form of nanorods of the above-mentioned size, showing high activity and low melting point, and can be melted and connected at low temperature. After hot pressing, sintering and annealing, a stable and strong three-dimensional network structure is formed.

[0026] In some embodiments, the thickness of the copper nanorod layer on the chip surface and the packaging component surface is independently 450-900 nm, optionally 550-650 nm.

[0027] In some embodiments, the method for preparing the copper nanorod layer includes magnetron sputtering deposition.

[0028] In some embodiments, the magnetron sputtering deposition method includes: controlling the angle between the normal line of the chip or packaging component and the normal line of the copper target to be an acute angle, performing sputtering deposition on the surface of the chip or packaging component to form a copper nanorod layer.

[0029] By controlling the angle between the normal line of the chip or packaging component and the normal line of the copper target to be an acute angle during the sputtering deposition process, that is, using inclined sputtering deposition, a copper nanorod layer can be formed by sputtering deposition on the surface of the chip or packaging component.

[0030] In some embodiments, the angle between the normal of the chip or package component and the normal of the copper target is 80° to 85°. The tilt angle is related to the morphology of the copper nanorods. In the embodiments of the present application, tilted sputtering deposition at an angle of 80° to 85° can produce copper nanorods of appropriate size, with short sputtering times and high efficiency.

[0031] In some embodiments, during the step of stacking the chip and the packaging component, the copper nanorods contained in the copper nanorod layers of the two components intersperse with each other. Specifically, the copper nanorods in the chip intersperse with the gaps between the copper nanorods in the packaging component, and simultaneously, the copper nanorods in the packaging component intersperse with the gaps between the copper nanorods in the chip. This interlacing facilitates the formation of an interwoven network structure, enhancing the connection strength between the chip and the packaging component.

[0032] In some embodiments, the temperature of the hot pressing sintering process is 250-280° C., optionally 270-280° C. This application can achieve copper-copper bonding at low temperature, reduce the process temperature of copper-copper bonding, help protect the structure of the chip and packaging components, and reduce costs.

[0033] In some embodiments, the pressure during the hot-pressing sintering process is 20-50 MPa, and optionally 30-50 MPa. Applying a pressure of 20-50 MPa to the intermediary can not only promote the smooth fusion of the copper nanorod layers of the chip and the packaging component to form a high-strength copper connection layer, but also maintain the structural stability of the chip and packaging component, thereby preventing damage to the chip and packaging component.

[0034] In some embodiments, the hot pressing sintering process lasts for 20 to 30 minutes, and optionally 25 to 30 minutes. A preliminary connection can be formed in a relatively short sintering time, which is highly efficient.

[0035] In some embodiments, the vacuum degree of the hot pressing sintering process is 600-800 Pa, optionally 650-750 Pa. Copper nanorods have high surface activity and are easily oxidized when exposed to oxygen, so hot pressing sintering under vacuum can well maintain the chemical stability of the copper nanorods.

[0036] In some embodiments, the annealing temperature is 400-500° C., optionally 450-500° C. Annealing the hot-pressed sintered connection structure at a higher annealing temperature can further promote the efficient diffusion of copper atoms in the copper nanorod layer, allowing them to occupy sites and form a stable connection layer network structure, thereby improving the connection strength between the chip and the packaging component and forming a chip packaging structure with a stable connection layer.

[0037] In some embodiments, the heating rate of the annealing treatment is 40-50°C / min, optionally 42-46°C / min. Heating to the desired annealing temperature at a rate of 40-50°C / min is beneficial for relieving stress in the copper connection layer, improving the strength of the copper connection layer, and having high efficiency.

[0038] In some embodiments, the annealing treatment time is 20 to 40 minutes, and optionally 25 to 35 minutes. After a relatively short period of heat preservation annealing, the connection can be completed to form a stable copper connection layer.

[0039] In a third aspect, the present application provides an electronic device comprising the above-mentioned chip packaging structure.

[0040] The electronic devices may include 3C products, home appliances, car appliances, lighting equipment, new energy vehicles, industrial equipment, etc.

[0041] In the chip packaging structure of the embodiment of the present application, the chip and the packaging component are bonded together via a high-strength and stable copper connection layer, so the electronic device including the chip packaging structure will have high structural stability.

[0042] At the same time, in the chip packaging structure, the chip and the packaging component are connected by copper, which has excellent electrical signal transmission performance and thermal conductivity. Therefore, applying this chip packaging structure to electronic devices is conducive to improving the electrical signal transmission performance and thermal conductivity of electronic devices. Moreover, the copper connection layer between the chip and the packaging component has a high melting point, and it is not easy to melt even when the chip packaging structure operates at high temperatures. The chip packaging structure has excellent reliability. Therefore, applying this chip packaging structure to electronic devices is conducive to increasing the operating temperature of electronic devices, meeting the requirements of high-temperature service, and broadening the use scenarios of electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] Figure 1 This is a flow chart for preparing the chip packaging structure in Example 1 of the present application;

[0045] Figure 2 This is a schematic diagram of placing the chip and substrate on the sample holder in Example 1 of the present application;

[0046] Figure 3 is a schematic diagram of the oblique deposition of nano-copper rods in Example 1 of the present application;

[0047] Figure 4 is a SEM image of the surface morphology of the substrate without sputtering-deposited copper nanorods in Example 1 of the present application;

[0048] Figure 5 1 is a SEM image of the surface morphology of the substrate after sputtering and depositing copper nanorods in Example 1 of the present application, wherein (a) is a top view of the surface and (b) is an oblique view of the cross section;

[0049] Figure 6 is a SEM image of the surface morphology of the chip without sputtering and depositing copper nanorods in Example 1 of the present application;

[0050] Figure 7 1 is a SEM image of the chip surface morphology after sputtering and depositing copper nanorods in Example 1 of the present application, wherein (a) is a top view of the surface and (b) is an oblique view of the cross section;

[0051] Figure 8 This is a schematic diagram of the stacked chip and substrate in Example 1 of the present application;

[0052] Figure 9 Surface morphology of the copper connection layer exposed after the chip is separated from the substrate of the chip packaging structure in Example 1 of the present application, where (a) and (b) are the morphologies of the copper connection layer remaining on the substrate surface; (c) is the copper connection layer remaining on the chip surface;

[0053] Figure 10 This is the morphology of the copper connection layer remaining on the substrate surface after the chip and substrate of the chip packaging structure in Comparative Example 1 are separated;

[0054] Figure 11 This is the morphology of the copper connection layer remaining on the chip surface after the chip and substrate of the chip packaging structure in Comparative Example 1 are separated.

[0055] Among them, the reference numerals in the figures are:

[0056] 10—chip, 11—copper nanorod layer on the chip surface, 20—substrate, 21—copper nanorod layer on the substrate surface, 30—sample holder, 40—copper target. DETAILED DESCRIPTION

[0057] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, the present application is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0058] In this application, the term "and / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0059] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, "at least one of a, b, or c", or "at least one of a, b and c" can all mean: a, b, c, ab (i.e., a and b), ac, bc, or abc, where a, b, c can be single or multiple.

[0060] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. Some or all of the steps can be executed in parallel or sequentially. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0061] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0062] The weights of the relevant components mentioned in the examples of this application may not only refer to the specific content of each component, but also represent the weight ratio between the components. Therefore, as long as the content of the relevant components is proportionally enlarged or reduced according to the examples of this application, it is within the scope disclosed in the examples of this application. Specifically, the mass described in the examples of this application may be a mass unit known in the chemical industry, such as μg, mg, g, kg, etc.

[0063] The terms "first" and "second" are used solely for descriptive purposes to distinguish objects, such as substances, from one another and should not be understood to indicate or imply relative importance or to implicitly specify the quantity of the technical features being referred to. For example, without departing from the scope of the embodiments of this application, a first XX may also be referred to as a second XX, and similarly, a second XX may also be referred to as a first XX. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more of such features.

[0064] A first aspect of an embodiment of the present application provides a chip packaging structure, including a chip and a packaging component, wherein the chip and the packaging component are connected together through a copper connection layer; the copper connection layer includes a three-dimensional network structure formed by interweaving copper nanorods.

[0065] A chip packaging structure refers to the structure formed by placing, bonding, fixing, or connecting a chip to a substrate, frame, or other component. It can also be called a chip mounting structure. In the embodiments of this application, a packaging component refers to the component used to package and connect the chip. A three-dimensional copper nanorod network structure refers to a three-dimensional network structure composed of copper nanorods.

[0066] The chip and the packaging component of the embodiment of the present application are connected together through a copper connection layer. The three-dimensional network structure of copper nanorods in the copper connection layer has a strong and stable structure, which can improve the connection strength between the chip and the packaging component.

[0067] Furthermore, chips and the packaging components used to package them generally utilize copper for electrical signal transmission and heat conduction. The connection layer between the chip and the packaging component in the embodiments of the present application consists solely of copper, which has excellent electrical and thermal conductivity, thereby improving the chip's electrical signal transmission and thermal conductivity. The resulting copper connection layer has a high melting point and is not easily melted even when the chip packaging structure operates at high temperatures, thereby improving the reliability of the chip packaging structure and meeting high-temperature service requirements. Furthermore, the connection layer between the chip and the packaging component does not contain metals such as tin and silver, thereby preventing the migration of these metals under electromigration and other factors, and exhibiting excellent electromigration resistance.

[0068] In some embodiments, the copper connection layer has a thickness of 0.5 to 2 μm, optionally 1 to 2 μm, such as any value among 0.5 μm, 1 μm, 1.3 μm, 1.5 μm, and 2 μm, or a range between any two values. A thin copper connection layer facilitates lightweighting of the package structure. Even with such a thin copper connection layer, high connection strength can be achieved.

[0069] In some embodiments, the packaging component includes one or more of a ceramic substrate, a lead frame, a printed circuit board, and a strip. Alternatively, the packaging component includes a ceramic substrate, such as one or more of an aluminum oxide substrate and an aluminum nitride substrate.

[0070] The chip includes one or more of a silicon carbide-based chip, a silicon-based chip, and a gallium nitride-based chip.

[0071] Typically, the surfaces of these chips and packaging components are covered with copper.

[0072] The chip packaging structure of the embodiment of the present application is applicable to various chips and various packaging components and has a wide applicability. In particular, the chip packaging structure of the embodiment of the present application can be applied to the packaging structure of silicon carbide chips with high junction temperature characteristics, and is expected to be used in high-power module products.

[0073] A second aspect of an embodiment of the present application provides a method for preparing a chip packaging structure, comprising:

[0074] Providing a chip and a packaging component each having a copper nanorod layer on its surface, and stacking the chip and the packaging component so that the copper nanorod layers of the two contact each other to obtain an intermediate component;

[0075] The intermediate piece is subjected to hot pressing sintering and annealing treatment.

[0076] The present embodiment utilizes the high surface activity of copper nanorods to deposit copper nanorod layers on the surfaces of the chip and packaging component. Once the two copper nanorod layers are in contact, the chip and packaging component can be bonded at low temperatures, reducing the copper-copper bonding temperature. Annealing after hot pressing promotes the diffusion of copper atoms in the copper nanorod layer, allowing the copper nanorod layers of the chip and packaging component to fuse together, forming a three-dimensional network structure. This creates a strong, stable copper connection layer between the chip and packaging component, enhancing the connection strength between the chip and packaging component.

[0077] Moreover, chips and the packaging components used to package them generally use copper for electrical signal transmission and heat conduction. The preparation method of the embodiments of the present application is a solder-free, adhesive-free direct metal diffusion interconnection process. In the resulting chip packaging structure, the connection layer between the chip and the packaging component is composed solely of copper, which has excellent electrical and thermal conductivity, thereby improving the chip's electrical signal transmission and thermal conductivity. The formed copper connection layer has a high melting point and is not easily melted even when the chip packaging structure operates at high temperatures. Therefore, the reliability of the chip packaging structure can be improved and meet the requirements of high-temperature service. In addition, the connection layer between the chip and the packaging component does not contain metals such as tin and silver, which can prevent the migration of metals such as tin and silver under the influence of electromigration and other factors, and has excellent anti-electromigration capabilities.

[0078] In addition, the preparation method of this embodiment does not require the deposition of a metal buffer layer on the surface, and does not require complex cleaning and photolithography processes to produce a unique surface morphology. It has low requirements for the flatness of the surface of the chip and packaging components, greatly simplifies the chip packaging process, reduces costs, and is compatible with packaging components such as chips and ceramic substrates used in common power modules.

[0079] In some embodiments, the sizes of the copper nanorods contained in the copper nanorod layer on the chip surface and the packaging component surface are independently at least one of (1) to (3):

[0080] (1) The aspect ratio is (1.5-5):1, optionally (2-4):1;

[0081] (2) a diameter of 150 to 500 nm, optionally 200 to 400 nm;

[0082] (3) The length is 450 to 900 nm, optionally 600 to 800 nm.

[0083] For example, the aspect ratio of the copper nanorods can be 1.5:1, 1.8:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, or a range between any two of these values. The diameter of the copper nanorods can be any of 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm, or a range between any two of these values. The length of the copper nanorods can be any of 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, or 900 nm, or a range between any two of these values.

[0084] Copper is arranged on the surface of the chip or packaging component in the form of nanorods of the above-mentioned size, showing high activity and low melting point, and can be melted and connected at low temperature. After hot pressing, sintering and annealing, a stable and strong three-dimensional network structure is formed.

[0085] In some embodiments, the thickness of the copper nanorod layer on the surface of the chip and the packaging component is independently 450 to 900 nm, optionally 550 to 650 nm, for example, any value among 450 nm, 500 nm, 550 nm, 570 nm, 600 nm, 640 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, or the range between any two values.

[0086] In some embodiments, the method for preparing the copper nanorod layer includes magnetron sputtering deposition.

[0087] In some embodiments, the magnetron sputtering deposition method includes: controlling the angle between the normal line of the chip or packaging component and the normal line of the copper target to be an acute angle, and performing sputtering deposition on the surface of the chip or packaging component.

[0088] The angle between the normal to the chip or package component and the normal to the copper target is typically the angle between the chip or package component and the copper target. By controlling the angle between the normal to the chip or package component and the normal to the copper target to be acute during sputtering deposition, i.e., employing tilted sputtering deposition, a copper nanorod layer can be sputter-deposited on the surface of the chip or package component.

[0089] In some embodiments, the angle between the normal of the chip or packaging component and the normal of the copper target is 80° to 85°, optionally 80° to 82°, for example, it can be any point value among 80°, 81°, 82°, 83°, 84°, 85° or the range between any two point values.

[0090] The tilt angle is related to the morphology of the copper nanorods. Furthermore, the tilt angle affects the size of the copper nanorods. Within a certain range, a larger tilt angle results in a smaller diameter and shorter length of the copper nanorods, which in turn requires a longer deposition time to achieve the desired thickness of the nanorod layer. The present embodiment employs tilted sputtering deposition at an angle of 80° to 85°, which can produce copper nanorods of appropriate size with shorter sputtering times and higher efficiency.

[0091] In some embodiments, before forming the copper nanorod layer on the surface of the chip or packaging component, the chip or packaging component is subjected to a surface activation treatment. This surface activation treatment includes ultrasonic cleaning or ion cleaning of the chip or packaging component. Surface activation improves the surface condition of the chip and packaging component, facilitating the secure bonding of the copper nanorod layer to the chip and packaging component surfaces.

[0092] In some embodiments, during the step of stacking the chip and the packaging component, the copper nanorods contained in the copper nanorod layers of the two components intersperse with each other. Specifically, the copper nanorods in the chip intersperse with the gaps between the copper nanorods in the packaging component, and simultaneously, the copper nanorods in the packaging component intersperse with the gaps between the copper nanorods in the chip. This interlacing facilitates the formation of an interwoven network structure, enhancing the connection strength between the chip and the packaging component.

[0093] Typically, in practice, the chip and package are placed together in a deposition chamber and sputtered at the same angle to deposit the copper nanorod layer. This results in the copper nanorods oriented in the same direction after sputtering. During the stacking step, simply rotate one of the chip and package so that their sputtered surfaces touch and overlap, allowing the copper nanorods on both sputtered surfaces to interpenetrate.

[0094] In some embodiments, the temperature of the hot pressing sintering process is 250-280°C, optionally 270-280°C, for example, any value among 250°C, 260°C, 270°C, and 280°C, or a range between any two values. Hot pressing sintering is a sintering method that simultaneously pressurizes and heats a processed component to achieve simultaneous forming and sintering. The embodiments of the present application can achieve copper-copper bonding at low temperatures, reducing the process temperature of copper-copper bonding and thus helping to reduce costs.

[0095] In some embodiments, the hot-pressing sintering process is performed at a pressure of 20 to 50 MPa, optionally 30 to 50 MPa, such as any value among 20 MPa, 30 MPa, 40 MPa, and 50 MPa, or a range between any two values. Applying a pressure of 20 to 50 MPa to the intermediary not only promotes smooth fusion of the copper nanorod layers of the chip and the packaging component, forming a high-strength copper connection layer, but also maintains the structural stability of the chip and packaging component, preventing damage to the chip and packaging component.

[0096] In some embodiments, the hot pressing sintering treatment time is 20 to 30 minutes, optionally 25 to 30 minutes, for example, any value among 20 minutes, 25 minutes, and 30 minutes, or a range between any two values. A preliminary connection can be formed after a short sintering time, which is highly efficient.

[0097] In some embodiments, the vacuum level during hot-pressing sintering is 600-800 Pa, optionally 650-750 Pa, for example, any value among 600 Pa, 650 Pa, 700 Pa, 750 Pa, and 800 Pa, or a range between any two values. Copper nanorods have high surface activity and are easily oxidized by oxygen. Therefore, hot-pressing sintering under vacuum can effectively maintain the chemical stability of the copper nanorods.

[0098] In some embodiments, the annealing temperature is 400°C to 500°C, optionally 450°C to 500°C, for example, any one of 400°C, 450°C, and 500°C, or a range between any two of these values. Annealing the hot-pressed sintered connection structure at a higher annealing temperature can further promote efficient diffusion of copper atoms in the copper nanorod layer, allowing them to occupy sites and form a stable connection layer network structure, thereby increasing the connection strength between the chip and the packaging component and forming a chip packaging structure with a stable connection layer.

[0099] In some embodiments, the heating rate in the annealing step is 40-50°C / min, optionally 42-46°C / min, for example, any of 40°C / min, 42°C / min, 46°C / min, 48°C / min, and 50°C / min, or a range between any two of these values. Heating to the desired annealing temperature at a rate of 40-50°C / min is beneficial for relieving stress in the copper interconnect layer, improving its strength, and achieving high efficiency.

[0100] In some embodiments, the annealing time is 20 to 40 minutes, optionally 25 to 35 minutes, for example, any of 20 minutes, 25 minutes, 30 minutes, 35 minutes, and 40 minutes, or a range between any two of these values. The annealing time refers to the holding time at the desired annealing temperature after reaching that temperature. A shorter holding time at the annealing temperature allows for a complete connection, forming a stable copper connection layer.

[0101] In some embodiments, the annealing treatment is a pressureless annealing treatment. Pressureless annealing means annealing is performed without applying external force. In actual operation, the annealing treatment can be performed under atmospheric pressure or vacuum conditions, and the vacuum degree can be set to 30 to 60 Pa, optionally 40 to 60 Pa, such as any point value among 30 Pa, 40 Pa, 50 Pa, 60 Pa or the range between any two point values. After the annealing is completed, the temperature can be rapidly cooled at a rate of 50 to 60 ° C / min, optionally at a rate of 55 to 60 ° C / min, such as any point value among 50 ° C / min, 55 ° C / min, 60 ° C / min or the range between any two point values. Cooling can be achieved by purging with a protective gas (such as nitrogen, helium, argon, etc.). Annealing under no pressure can effectively release the stress in the copper connection layer and improve the strength of the copper connection layer.

[0102] A third aspect of an embodiment of the present application provides an electronic device, which includes the above-mentioned chip packaging structure.

[0103] The electronic devices may include 3C products, home appliances, car appliances, lighting equipment, new energy vehicles, industrial equipment, etc.

[0104] In the chip packaging structure of the embodiment of the present application, the chip and the packaging component are connected via a high-strength and stable copper connection layer, so the electronic device including the chip packaging structure will have high structural stability.

[0105] At the same time, in the chip packaging structure, the chip and the packaging component are connected by copper, which has excellent electrical signal transmission performance and thermal conductivity. Therefore, applying this chip packaging structure to electronic devices is conducive to improving the electrical signal transmission performance and thermal conductivity of electronic devices. Moreover, the copper connection layer between the chip and the packaging component has a high melting point, and it is not easy to melt even when the chip packaging structure operates at high temperatures. The chip packaging structure has excellent reliability. Therefore, applying this chip packaging structure to electronic devices is conducive to increasing the operating temperature of electronic devices, meeting the requirements of high-temperature service, and broadening the use scenarios of electronic devices.

[0106] The following describes the details in conjunction with specific embodiments.

[0107] Example 1

[0108] A chip packaging structure, specifically a structure formed by interconnecting a silicon carbide chip and an alumina ceramic copper-clad substrate. The silicon carbide chip and the alumina ceramic copper-clad substrate are connected together through a copper connection layer. The preparation flow chart is as follows Figure 1 Shown, including:

[0109] 1. Cleaning: ultrasonically and plasma clean the substrate and chip in sequence;

[0110] 2. Oblique deposition: depositing copper nanorods on the substrate and chip surface;

[0111] 3. Hot pressing sintering: perform high-pressure pre-sintering and preliminary connection between substrate and chip;

[0112] 4. Pressureless annealing: Perform pressureless annealing on the sintered sample to complete the connection.

[0113] The specific steps include:

[0114] 1. Cleaning: First, use anhydrous ethanol as a cleaning agent to ultrasonically clean the substrate and chip. After ultrasonic cleaning, place them in an oven at 40°C for 5 minutes. Then, plasma clean the substrate and chip in an argon-hydrogen mixed atmosphere to activate their surfaces and facilitate the next step of deposition.

[0115] 2. Tilt deposition: Use magnetron sputtering to deposit copper nanorods. Place the cleaned substrate and chip horizontally on the sample holder. Figure 2 As shown, the chip 10 and the substrate 20 are arranged in parallel and placed horizontally on the sample holder 30. Figure 3 As shown, the normal line of the sample holder 30 and the normal line of the copper target 40 are kept at an angle of 80°, and the sputtering deposition of the copper layer is started. The sputtering time is 30 minutes, the sputtering power is 300W, the sputtering atmosphere is argon, and the sputtering partial pressure is 1Pa.

[0116] like Figure 4Shown is the SEM image of the surface morphology of the substrate without sputtering deposited copper nanorods. Figure 5 SEM images of the substrate surface morphology after sputtering and deposition of copper nanorods [(a) surface top view, (b) cross-sectional oblique view]. Figure 6 This is the SEM image of the chip surface morphology without sputtering deposited copper nanorods. Figure 7 The SEM images of the chip surface morphology after sputtering and deposition of copper nanorods [(a) surface top view, (b) cross-sectional oblique view]. Figures 4 to 7 The oblique deposition process ultimately resulted in a copper nanorod layer on both the chip and substrate surfaces, consisting of copper nanorods with diameters ranging from 200 to 400 nm, heights from 600 to 800 nm, and aspect ratios ranging from 2:1 to 4:1. A step profiler measured the thickness of the copper nanorod layer to be approximately 640 nm on the chip surface and 570 nm on the substrate surface. Within the copper nanorod layer, the copper nanorods were uniformly oriented, with gaps between them.

[0117] 3. Hot pressing sintering: Figure 8 As shown, the chip 10 and substrate 20 are placed face-to-face (with one of them flipped so that the copper nanorod layer 11 on the chip 10 surface and the copper nanorod layer 21 on the substrate 20 surface are oriented in the same direction). The stacked sample is then pressurized and sintered using a hot press to complete the initial connection. The hot pressing sintering temperature is 280°C, the heating rate is 80°C / min, the sintering pressure is 50 MPa, the sintering time is 25 minutes, and the vacuum level is 700 Pa. After the hot pressing is completed, the hot press is cooled using the water cooling mode for 5 minutes to obtain a sample (intermediate component) with a preliminary connection between the substrate and the chip.

[0118] 4. Pressureless Annealing: The hot-pressed intermediate components are subjected to pressureless annealing to complete the final connection. During the annealing process, the vacuum level in the furnace chamber is 50 Pa, the heating rate is set at 45°C / min, the annealing temperature is 450°C, and the holding time is 30 minutes. After the holding period, nitrogen is purged to rapidly cool the components at a rate of 55°C / min to obtain the final chip package structure.

[0119] Example 2

[0120] The difference between this embodiment and embodiment 1 is that the sintering pressure is adjusted from 50 MPa to 40 MPa.

[0121] A chip packaging structure is specifically formed by interconnecting a silicon carbide chip and an alumina ceramic copper-clad substrate. The silicon carbide chip and the alumina ceramic copper-clad substrate are connected together through a copper connection layer. The preparation of the chip packaging structure specifically includes the following steps:

[0122] 1. Cleaning: First, use anhydrous ethanol as a cleaning agent to ultrasonically clean the substrate and chip. After ultrasonic cleaning, place them in an oven at 40°C for 5 minutes. Then, plasma clean the substrate and chip in an argon-hydrogen mixed atmosphere to activate their surfaces and facilitate the next step of deposition.

[0123] 2. Tilt deposition: Use magnetron sputtering to deposit copper nanorods. Place the cleaned substrate and chip horizontally on the sample holder. Figure 2 As shown, the chip 10 and the substrate 20 are arranged in parallel and placed horizontally on the sample holder 30. Figure 3 As shown, the normal to the sample holder 30 was maintained at an 80° angle to the normal to the copper target 40, and sputtering deposition of the copper layer began. The sputtering time was 30 minutes, the sputtering power was 300 W, the sputtering atmosphere was argon, and the sputtering partial pressure was 1 Pa. Through oblique deposition, a copper nanorod layer consisting of copper nanorods with diameters ranging from 200 to 400 nm, heights ranging from 600 to 800 nm, and aspect ratios ranging from 2:1 to 4:1 was ultimately formed on both the chip and substrate surfaces. The copper nanorods were uniformly oriented, and there was a certain amount of space between the copper nanorods.

[0124] 3. Hot pressing sintering: Figure 8 As shown, the chip 10 and substrate 20 are placed face-to-face (the orientation of one of them is reversed so that the copper nanorod layer 11 on the chip 10 surface and the copper nanorod layer 21 on the substrate 20 surface are in the same direction). The stacked sample is then pressurized and sintered using a hot press to complete the initial connection. The hot pressing sintering temperature is 280°C, the heating rate is 80°C / min, the sintering pressure is 40MPa, the time is 25 minutes, and the vacuum level is 700Pa. After the hot pressing is completed, the hot press is cooled in water-cooling mode for 5 minutes to obtain a sample (intermediate component) with a preliminary connection between the substrate and the chip.

[0125] 4. Pressureless Annealing: The hot-pressed intermediate components are subjected to pressureless annealing to complete the final connection. During the annealing process, the vacuum level in the furnace chamber is 50 Pa, the heating rate is set at 45°C / min, the annealing temperature is 450°C, and the holding time is 30 minutes. After the holding period, nitrogen is purged to rapidly cool the components at a rate of 55°C / min to obtain the final chip package structure.

[0126] Example 3

[0127] The difference between this embodiment and embodiment 1 is that the sputtering time is adjusted from 30 minutes to 20 minutes.

[0128] A chip packaging structure is specifically formed by interconnecting a silicon carbide chip and an alumina ceramic copper-clad substrate. The silicon carbide chip and the alumina ceramic copper-clad substrate are connected together through a copper connection layer. The preparation of the chip packaging structure specifically includes the following steps:

[0129] 1. Cleaning: First, use anhydrous ethanol as a cleaning agent to ultrasonically clean the substrate and chip. After ultrasonic cleaning, place them in an oven at 40°C for 5 minutes. Then, plasma clean the substrate and chip in an argon-hydrogen mixed atmosphere to activate their surfaces and facilitate the next step of deposition.

[0130] 2. Tilt deposition: Use magnetron sputtering to deposit copper nanorods. Place the cleaned substrate and chip horizontally on the sample holder. Figure 2 As shown, the chip 10 and the substrate 20 are arranged in parallel and placed horizontally on the sample holder 30. Figure 3 As shown, the normal to the sample holder 30 was maintained at an 80° angle to the normal to the copper target 40, and sputtering deposition of the copper layer began. The sputtering time was 20 minutes, the sputtering power was 300 W, the sputtering atmosphere was argon, and the sputtering partial pressure was 1 Pa. Through oblique deposition, a copper nanorod layer consisting of copper nanorods with diameters ranging from 180 to 270 nm, heights ranging from 490 to 560 nm, and aspect ratios ranging from 1.8:1 to 3:1 was ultimately formed on both the chip and substrate surfaces. The copper nanorods were uniformly oriented, and there was a certain amount of space between the copper nanorods.

[0131] 3. Hot pressing sintering: Figure 8 As shown, the chip 10 and substrate 20 are placed face-to-face (the orientation of one of them is reversed so that the copper nanorod layer 11 on the chip 10 surface and the copper nanorod layer 21 on the substrate 20 surface are in the same direction). The stacked sample is then pressurized and sintered using a hot press to complete the initial connection. The hot pressing sintering temperature is 280°C, the heating rate is 80°C / min, the sintering pressure is 40MPa, the time is 25 minutes, and the vacuum level is 700Pa. After the hot pressing is completed, the hot press is cooled in water-cooling mode for 5 minutes to obtain a sample (intermediate component) with a preliminary connection between the substrate and the chip.

[0132] 4. Pressureless Annealing: The hot-pressed intermediate components are subjected to pressureless annealing to complete the final connection. During the annealing process, the vacuum level in the furnace chamber is 50 Pa, the heating rate is set at 45°C / min, the annealing temperature is 450°C, and the holding time is 30 minutes. After the holding period, nitrogen is purged to rapidly cool the components at a rate of 55°C / min to obtain the final chip package structure.

[0133] Comparative Example 1

[0134] The difference between this comparative example and Example 1 is that the pressureless annealing step is not performed, and the process ends with hot pressing sintering. The preparation method of the chip packaging structure of this comparative example includes the following steps:

[0135] 1. Cleaning: First, use anhydrous ethanol as a cleaning agent to ultrasonically clean the substrate and chip. After ultrasonic cleaning, place them in an oven at 40°C for 5 minutes. Then, plasma clean the substrate and chip in an argon-hydrogen mixed atmosphere to activate their surfaces and facilitate the next step of deposition.

[0136] 2. Tilt deposition: Use magnetron sputtering to deposit copper nanorods. Place the cleaned substrate and chip horizontally on the sample holder. Figure 2 As shown, the chip 10 and the substrate 20 are arranged in parallel and placed horizontally on the sample holder 30. Figure 3 As shown, the normal line of the sample holder 30 and the normal line of the copper target 40 are kept at an angle of 80°, and the sputtering deposition of the copper layer is started. The sputtering time is 30 minutes, the sputtering power is 300W, the sputtering atmosphere is argon, and the sputtering partial pressure is 1Pa.

[0137] 3. Hot pressing sintering: Figure 8 As shown, the chip 10 and substrate 20 were placed face-to-face (with one side facing the other, so that the copper nanorod layer 11 on the chip 10 surface and the copper nanorod layer 21 on the substrate 20 surface were oriented in the same direction). The stacked sample was then pressurized and sintered using a hot press to complete the initial connection. The hot press sintering temperature was 280°C, the heating rate was 80°C / min, the sintering pressure was 50 MPa, the sintering time was 25 minutes, and the vacuum level was 700 Pa. After the hot press sintering, the hot press was cooled using the water cooling mode for 5 minutes to obtain a sample with the substrate and chip connected.

[0138] The performance tests of the chip packaging structures of the comparative examples and embodiments are as follows.

[0139] (1) Shear strength

[0140] Test method: Use a push-pull force tester to push the chip to test the shear strength of the copper connection layer. The shear strength unit is MPa. The chip size is 5mm×6mm.

[0141] The test results are shown in Table 1.

[0142] [Table 1]

[0143] Implementation Cases Shear strength (MPa) Example 1 27.335 Example 2 20.016 Example 3 17.042 Comparative Example 1 4.315

[0144] The test results show:

[0145] 1) The chip packaging structures of Examples 1 to 3 have excellent shear strength. After the shear strength test, the chip is separated from the substrate, and the surface morphology of the exposed copper connection layer is observed. It can be seen that the copper connection layer between the chip and the substrate has a three-dimensional network structure formed by interweaving copper nanorods, such as Figure 9 As shown ( Figure 9 This is a topography of the connection layer of the chip packaging structure of Example 1. The total thickness of the copper connection layer remaining on the chip surface and the copper connection layer remaining on the substrate surface measured by a step profiler is approximately 1.3 μm, that is, the thickness of the copper connection layer between the chip and the substrate is approximately 1.3 μm).

[0146] In contrast, the shear strength of the chip packaging structure of Comparative Example 1 is only 4.315 MPa, which is only 16% to 25% of that of Examples 1 to 3, and the shear strength is significantly reduced. Observation of the surface of the copper connection layer exposed after the chip and substrate of Comparative Example 1 are separated reveals that the morphology of the copper connection layer is similar to the morphology of the copper nanorod layer on the surface of the chip and substrate before hot pressing, and no three-dimensional network structure is formed. Figure 10 After the chip of the chip package structure of Comparative Example 1 is separated from the substrate, the morphology of the copper connection layer remaining on the substrate surface can be observed to be different from the surface morphology of the substrate with copper nanorods sputtered before hot pressing sintering ( Figure 5 ) has almost no change in morphology, and no network structure has been formed; Figure 11 After the chip of the chip package structure of Comparative Example 1 is separated from the substrate, the morphology of the copper connection layer remaining on the chip surface can be observed to be different from the surface morphology of the chip with copper nanorods sputtered before hot pressing sintering ( Figure 7 ) has hardly changed in morphology and no network structure has been formed.

[0147] The comparison results show that the connection strength between the chip and the substrate can be significantly improved by forming a copper connection layer with a copper three-dimensional network structure between the chip and the substrate. At the same time, during the preparation process, after hot pressing and sintering, annealing treatment is required so that the copper nanorods on the surface of the chip and the substrate can be interwoven to form a three-dimensional network structure. This is due to the lack of a diffusion process at medium and high temperatures (such as 450°C), which makes it difficult for copper atoms to diffuse efficiently, occupy sites, and form a stable connection layer network, resulting in a significant decrease in shear strength. This also shows that the two-step process of hot pressing and annealing must cooperate with each other to promote the diffusion and growth of copper atoms and form a connection layer network. This can be used as a low-cost, stable metal diffusion bonding method to form a stable chip packaging structure.

[0148] 2) Analysis and comparison of Example 1, Example 2 and Example 3 show that, during the preparation process, by adjusting parameters such as sintering pressure and sputtering time, the shear strength of the chip packaging structure can be adjusted. The sintering pressure can be used as a driving force for the diffusion of copper atoms. Under this driving force, copper atoms migrate away from their original position and occupy new sites. Therefore, adjusting the sintering pressure can change the shear strength of the chip packaging structure. The length of the sputtering time affects the length of the copper nanorods formed (and thus the thickness of the copper connecting layer), the aspect ratio, etc., and thus affects the contact area after the chip and the substrate are stacked, which changes the rate of diffusion bonding of copper atoms. Therefore, by adjusting the sputtering time, the connection between the chip and the substrate can be adjusted, and under suitable sputtering time, the required shear strength can be obtained.

[0149] (2) Thermal conductivity

[0150] Because the copper connection layer between the chip and substrate in the chip package structure is very thin and the surface is uneven after the chip and substrate are peeled off, it is impossible to directly test the thermal conductivity of the copper connection layer between the chip and substrate. However, the copper connection layer is composed of a layer of copper nanorods sputtered on the surface of the chip and substrate. The thickness of the copper connection layer and the copper nanorod layer are very small, so the thermal conductivity of the copper nanorod layer can be used to represent the thermal conductivity of the copper connection layer.

[0151] The substrate with copper nanorods sputtered obliquely on its surface according to Example 1 (i.e., the substrate obtained in Step 2 of Example 1) was placed on a heating table (with the copper nanorods sputtered facing up) and the heating table temperature set to 70°C. A thermocouple (the first thermocouple) was placed on the surface area of the substrate sputtered with copper nanorods (the first area), and another thermocouple (the second thermocouple) was placed on the surface area of the substrate not sputtered with copper nanorods (the second area). Tests revealed that the temperatures of the first and second thermocouples were the same over the same period of time. That is, the temperature gradient between the bottom of the substrate and the first area was equal to the temperature gradient between the bottom of the substrate and the second area over the same period of time. Considering that the substrate is copper-clad, and the only heat transfer path between the first and second areas is the copper nanorod layer, it can be inferred that the thermal conductivity of this copper nanorod layer is consistent with that of pure copper (386.4 W / (mK)). Therefore, the thermal conductivity of the copper connection layer between the chip and the substrate in the chip packaging structure is also comparable to that of pure copper.

[0152] Since the thermal conductivity of solder paste is only 67W / (mK), the thermal conductivity of the copper connection layer between the chip and the substrate in this application is significantly higher than that of solder paste; and the thickness of the tin-containing connection layer made of traditional solder paste is about 100μm, while the thickness of the copper connection layer between the chip and the substrate in this application is only 1.3μm, which is significantly thinner than the tin-containing connection layer. Therefore, it can be determined that the copper connection layer of this application can better improve the thermal conductivity of the chip packaging structure than the traditional tin-containing connection layer.

[0153] At the same time, copper has better electrical conductivity than tin. Therefore, compared with the traditional tin-containing connection layer, the copper connection layer of the present application can better improve the electrical conductivity of the chip packaging structure.

[0154] In addition, the melting point of copper is 1083℃, and the melting point of solder paste is about 220℃, which also shows that the copper connection layer made of nano-copper rods can better meet the requirements of low-temperature sintering and high-temperature service.

[0155] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A chip packaging structure, characterized in that: The invention comprises a chip and a packaging component, wherein the chip and the packaging component are connected together through a copper connection layer; the copper connection layer comprises a three-dimensional network structure formed by interweaving copper nanorods.

2. The chip packaging structure according to claim 1, wherein: The thickness of the copper connection layer is 0.5 to 2 μm; and / or, the packaging component comprises one or more of a ceramic substrate, a lead frame, a printed circuit board, and a strip; And / or, the chip includes one or more of a silicon carbide-based chip, a silicon-based chip, and a gallium nitride-based chip.

3. The chip packaging structure according to claim 2, characterized in that: The thickness of the copper connection layer is 1-2 μm.

4. A method for preparing a chip packaging structure, characterized in that: include: Providing a chip and a packaging component, each having a copper nanorod layer on its surface, and stacking the chip and the packaging component so that the copper nanorod layers of the chip and the packaging component are in contact with each other, thereby obtaining an intermediate component; The intermediate piece is subjected to hot pressing sintering and annealing.

5. The method for preparing a chip packaging structure according to claim 4, characterized in that: The sizes of the copper nanorods contained in the copper nanorod layer on the chip surface and the packaging component surface are independently at least one of (1) to (3): (1) Aspect ratio (1.5-5):1; (2) Diameter of 150-500 nm; (3) Length is 450-900 nm; and / or, the thickness of the copper nanorod layer on the chip surface and the packaging component surface is independently 450 to 900 nm; and / or, the method for preparing the copper nanorod layer comprises a magnetron sputtering deposition method; And / or, in the step of stacking the chip and the packaging component, the copper nanorods contained in the copper nanorod layers of the two components are interlaced with each other.

6. The method for preparing the chip packaging structure according to claim 5, characterized in that: The sizes of the copper nanorods contained in the copper nanorod layer on the chip surface and the packaging component surface are independently at least one of (1) to (3): (1) Aspect ratio (2-4):1; (2) Diameter is 200-400 nm; (3) Length is 600-800 nm; and / or, the thickness of the copper nanorod layer on the chip surface and the packaging component surface is independently 550 to 650 nm; And / or, the magnetron sputtering deposition method includes: controlling the angle between the normal line of the chip or the packaging component and the normal line of the copper target to be an acute angle, and performing sputtering deposition on the surface of the chip or the packaging component.

7. The method for preparing a chip packaging structure according to claim 6, wherein: The angle between the normal line of the chip or the packaging component and the normal line of the copper target is 80° to 85°.

8. The method for preparing a chip packaging structure according to any one of claims 4 to 7, characterized in that: The temperature of the hot pressing sintering treatment is 250-280°C; And / or, the pressure of the hot pressing sintering process is 20 to 50 MPa; And / or, the hot pressing sintering treatment time is 20 to 30 minutes; And / or, the vacuum degree of the hot pressing sintering process is 600-800 Pa; And / or, the annealing temperature is 400-500°C; And / or, the heating rate of the annealing treatment is 40-50°C / min; And / or, the annealing treatment time is 20 to 40 minutes.

9. The method for preparing a chip packaging structure according to claim 8, wherein: The temperature of the hot pressing sintering treatment is 270-280°C; And / or, the pressure of the hot pressing sintering process is 30-50 MPa; And / or, the hot pressing sintering treatment time is 25 to 30 minutes; And / or, the vacuum degree of the hot pressing sintering process is 650-750 Pa; And / or, the annealing temperature is 450-500°C; And / or, the heating rate of the annealing treatment is 42-46°C / min; And / or, the annealing treatment time is 25 to 35 minutes.

10. An electronic device, characterized in that: The chip packaging structure comprises the chip packaging structure according to any one of claims 1 to 3.

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