A control system and control method for load power matching of power amplifier equipment based on FIR digital filter

Abstract

The present invention discloses a control system for load power matching of a power amplifier device based on an FIR digital filter and a control method thereof. The control system for load power matching of a power amplifier device based on an FIR digital filter comprises an MCU, a signal processing module, and a power unit. The MCU is used to receive and process relevant detection or communication signals and transmit them to the signal processing module, upload detection data of the power amplifier device, and calculate parameters. The signal processing module is used to receive and perform FIR digital filtering on the signal data, and the power unit performs power conversion on the detection or communication signal of the load. The present invention provides a control system for load power matching of a power amplifier device based on an FIR digital filter and a control method thereof. The control system can solve the problem that different load characteristics require specific matching networks and that the matching network cannot be replaced for specific underwater application scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to a control system and a control method for load power matching of a power amplifier device based on an FIR digital filter. Background Art

[0002] With the development of underwater exploration and communication technology, the application range of underwater equipment is becoming more and more extensive, and power amplifiers play a vital role. However, the underwater environment is complex and changeable, and the entire system consisting of water, power amplifiers, and loads is also complex and changeable.

[0003] Power amplifier applications often involve loads with varying characteristics, and the load's impedance varies across different frequency bands. This results in significant variations in the power conversion efficiency of the power amplifier, making it difficult to meet the requirements of applications such as detection and communication. This poses a significant challenge to the matching of the power amplifier and the load. Traditional power matching methods for power amplifiers struggle to accurately adapt to the dynamic changes of various loads, especially as loads exhibit varying characteristics in different application scenarios. When underwater acoustic signals propagate through water, they experience absorption, scattering, and multipath effects, resulting in severe signal attenuation. Efficient impedance matching is required to improve transmit power utilization.

[0004] For example, in underwater acoustic systems, energy transmission efficiency is crucial. In underwater communications systems, efficient energy transmission can extend communication distances; in sonar systems, it can improve detection sensitivity and range. By achieving impedance matching for underwater acoustic loads, energy loss during transmission can be reduced, allowing more electrical energy to be converted into acoustic energy and effectively radiated into the water.

[0005] Achieving load power matching is also crucial for efficient and stable operation of power amplifiers. A mismatched load power can lead to lower underwater acoustic power transmission efficiency, reduced device stability, and even damage to various components. Therefore, efficiently and effectively implementing a matching network to match the output impedance of the power amplifier to the load impedance is crucial for improving overall system performance. Summary of the Invention

[0006] In order to solve the problems in the above-mentioned background technology, the present invention provides a control system and a control method for load power matching of a power amplifier device based on an FIR digital filter, which can optimize the weight and volume of the matching network in the existing matching scheme, solve the complexity and singleness brought about by the need for specific matching networks for different load characteristics, and solve the problem that the matching network cannot be replaced for specific underwater application scenarios.

[0007] The present invention provides a control system for power matching of a power amplifier device and a load based on an FIR digital filter, comprising an MCU, a signal processing module, and a power unit. The MCU is used to receive and process detection or communication signals sent by a host computer and transmit the processed detection or communication signals to the signal processing module, as well as upload detection data of the power amplifier device to the host computer and calculate parameters. The signal processing module is used to receive and perform FIR digital filtering on the detection or communication signals sent by the MCU and drive the power unit to perform power conversion on the load.

[0008] The signal processing module uses FPGA as a hardware platform, and includes a data receiving and processing submodule, an FIR digital filter, a driving submodule, a PLL phase-locked loop submodule and a fault alarm submodule. The data receiving and processing submodule is used to receive and process the detection or communication signal sent by the MCU and transmit the processed detection or communication signal to the FIR digital filter. The FIR digital filter is used to perform digital filtering on the received detection or communication signal. The driving submodule is used to convert the detection or communication signal processed by the FIR digital filter into a driving signal required by the power unit of the power amplification device. The PLL phase-locked loop submodule is used to implement the relevant clock signals required by all processing logics. The fault alarm submodule is used to receive the abnormal data value and alarm flag uploaded by the data receiving and processing submodule and the FIR digital filter, perform alarm processing, and transmit the abnormal data value and the alarm flag to the MCU.

[0009] In a preferred embodiment of the control system for load power matching of power amplification equipment based on FIR digital filter provided by the present invention, the data receiving and processing submodule interacts with the MCU for detection or communication signal data through a parallel port communication protocol, and includes a data flow control unit, a sampling and restoration unit, a linear interpolation unit, a data amplitude conversion unit and a filter configuration parameter unit. The data flow control unit is used to realize the reception control of the detection or communication signal and the filter configuration parameters. The sampling and restoration unit, the linear interpolation unit and the data amplitude conversion unit are respectively used to perform sampling and restoration, linear interpolation and data amplitude conversion on the detection or communication signal data received by the data flow control unit, and then transmit the processed detection or communication signal data to the FIR digital filter after synchronization through the pipeline register. The filter configuration parameter unit is used to store and output the filter configuration parameters received by the data flow control unit.

[0010] In a preferred embodiment of the control system for load power matching of power amplifier equipment based on FIR digital filter provided by the present invention, the data receiving and processing submodule also interacts with the MCU through a serial communication protocol for sensor data transmission and related threshold parameters, including a threshold parameter configuration unit, an input and output monitoring signal upload unit, an ADC voltage and current sampling unit and an alarm data upload unit. The input and output monitoring signal upload unit is used to feed back the sensor data sampling signal of the back-end power matching to the MCU in real time, the ADC voltage and current sampling unit is used to receive external sensor data, and the alarm data upload unit is used to alarm abnormal data values ​​and transmit the abnormal data values ​​and alarm flags to the fault alarm submodule.

[0011] In a preferred embodiment of the control system for load power matching of a power amplifier device based on an FIR digital filter provided by the present invention, the FIR digital filter includes a BRAM1 signal data area, a first register, a filtering calculation unit and a second register, the BRAM1 signal data area is used to store the detection or communication signal data to be processed, the first register is used to perform local clock cache synchronization on the detection or communication signal data taken out from the BRAM1 signal data area, the filtering calculation unit is used to calculate the filtered detection or communication signal data, and the second register is used to output the filtered detection or communication signal data for local clock cache synchronization.

[0012] In a preferred embodiment of the control system for load power matching of a power amplifier device based on an FIR digital filter provided by the present invention, the filtering calculation unit includes a BRAM2 filtering data storage area, a shift register and an adder, and the BRAM2 filtering data storage area is used to store the matrix parameters required by the FIR digital filter.

[0013] In a preferred embodiment of the control system for load power matching of a power amplifier device based on an FIR digital filter provided by the present invention, the FIR digital filter also includes a data discrimination unit, which is used to perform real-time detection and corresponding actions when there is an abnormality in the detection or communication signal data output by the FIR digital filter.

[0014] In a preferred embodiment of the control system for load power matching of power amplifier equipment based on FIR digital filter provided by the present invention, the signal processing module adopts FPGA as the hardware platform.

[0015] The present invention also provides a control method for a control system of a power amplifier device load power matching based on an FIR digital filter, comprising the following steps:

[0016] Obtain the actual load impedance test data that has not been processed by the FIR digital filter and draw the actual impedance gain curve of the load;

[0017] Determine the gain range of each frequency band that needs to be adjusted according to the requirements, calculate the required gain ratio within the bandwidth, obtain the gain matrix parameters that need to be adjusted at the frequency point, and store them in the FIR digital filter;

[0018] Obtain the actual load impedance test data after being processed by the FIR digital filter and draw the actual impedance gain curve;

[0019] The actual load impedance gain curve processed by the FIR digital filter is compared with the load impedance gain curve not processed by the FIR digital filter, and the load impedance gain curve is calibrated in combination with the gain matrix parameters.

[0020] In a preferred embodiment of the control method of the control system for load power matching of a power amplifier device based on an FIR digital filter provided by the present invention, MATLAB is used to draw a gain curve and calculate gain matrix parameters.

[0021] In a preferred embodiment of the control method of the control system for load power matching of a power amplifier device based on an FIR digital filter provided by the present invention, actual load impedance test data of different types of loads that have not been processed by the FIR digital filter and actual load impedance test data that have been processed by the FIR digital filter are obtained respectively and corresponding actual impedance gain curves are drawn. The actual impedance gain curves of different types of loads that have not been processed by the FIR digital filter and the actual impedance gain curves that have been processed by the FIR digital filter are compared respectively, and the impedance gain curves of different types of loads are calibrated in combination with the gain matrix parameters of different types of loads to achieve power matching of different types of loads.

[0022] Compared with the prior art, the control system and control method for load power matching of power amplifier equipment based on FIR digital filter provided by the present invention have the following beneficial effects:

[0023] 1. The control system and control method for load power matching of power amplifier devices based on FIR digital filters provided by the present invention process detection or communication signals and compensate for signals of different frequency bands at the signal source level. In effect, this method adjusts the gain curve under different impedances, thereby achieving network matching at the output load end, improving power transmission efficiency, and reducing energy loss. The digital processor platform FPGA (Field Programmable Logic Device) allows for flexible design of FIR digital filter parameters and power matching algorithms to adapt to various complex application scenarios. Whether in shallow or deep waters, for sonar transducers or other underwater loads, efficient power matching can be achieved.

[0024] 2. The control system and control method for load power matching of a power amplifier device based on an FIR digital filter provided by the present invention perform gain processing on different types of detection or communication signals at the power amplifier device end without adding excessive hardware matching networks, thereby reducing the system weight and volume.

[0025] 3. The control system and control method for load power matching of power amplifier equipment based on FIR digital filter provided by the present invention can be calibrated according to the matching characteristics of the load. It has the advantages of strong adaptability to loads with different characteristics and the ability to change the matrix parameters of the FIR digital filter in different application scenarios for rapid application.

[0026] 4. The control system and control method for load power matching of power amplifier equipment based on FIR digital filter provided by the present invention can be remotely deployed and parameters can be iterated for different frequency bands, which reduces the hardware dependence on the matching network, improves the versatility of the power amplifier equipment, and reduces the cost of use. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0028] Figure 1 : The following are comparison diagrams of 1kHz~5kHz swept frequency signals and spectrum gain curves before and after filtering; (a) is the 1kHz~5kHz swept frequency signal diagram before filtering, (b) is the spectrum gain curve diagram corresponding to the 1kHz~5kHz swept frequency signal before filtering, (c) is the 1kHz~5kHz swept frequency signal diagram after FIR digital filter processing, and (d) is the spectrum gain curve diagram corresponding to the 1kHz~5kHz swept frequency signal after FIR digital filter processing;

[0029] Figure 2 This is a structural block diagram of a control system for load power matching of a power amplifier device based on an FIR digital filter provided by the present invention;

[0030] Figure 3 yes Figure 2 Schematic diagram of the processing flow of the data receiving and processing submodule shown;

[0031] Figure 4 for Figure 2 Schematic diagram of the processing flow of the FIR digital filter shown;

[0032] Figure 5 for Figure 4The RTL structure block diagram of the FIR digital filter is shown. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0034] FPGA (field programmable gate array) has the advantages of high integration, flexible compilation, and efficient parallel processing. From the hardware circuit design level, it can simplify the circuit complexity and remove redundant logic control circuit elements in the circuit, thereby reducing the development difficulty of circuit design and shortening the development cycle. In addition, FPGA has powerful digital signal processing IP cores (intellectual property cores) and memory IP cores, which have great advantages in designing digital filters. Therefore, using FPGA as the hardware platform for digital filter implementation can reconfigure parameters without changing the hardware environment, and it has the advantages of being cheap, flexible, and convenient.

[0035] FIR (finite impulse response) digital filters have the advantages of stability and good amplitude-frequency characteristics. They can be designed with a strictly linear phase, thus avoiding phase distortion of the processed signal. Therefore, they are widely used in digital signal processing systems.

[0036] The present application provides a control system for load power matching of a power amplifier device based on an FIR digital filter and a control method thereof, which consists of a FIR digital filter simulation model design on a MATLAB simulation platform and a FIR digital filter design based on a digital processor platform FPGA. MATLAB is responsible for complex signal analysis, filter parameter design, coefficient calculation, etc., while FPGA is responsible for building the filter structure at the hardware level, thereby realizing digital filtering on the hardware.

[0037] Among them, the MATLAB simulation platform FIR digital filter simulation model design includes:

[0038] 1. The design of an FIR digital filter is primarily based on its impulse response. Based on the equiripple optimal approximation design principle, Ys(a) represents the approximated amplitude characteristic function, and Y(a) represents the amplitude characteristic function of the actual designed filter. According to the design requirements of a linear-phase FIR digital filter, Ys(a) must satisfy the linear phase constraint. The weighted error function w(a) is defined as w(a) = X(a)[Ys(a) - Y(a)], where X(a) is the amplitude error weighting function used to control the amplitude approximation accuracy in different frequency bands. The coefficient vector h(n) that minimizes the maximum absolute amplitude error |w(a)| within the filter's passband and stopband is found. The spectral characteristic curve of an FIR digital filter using the equiripple optimal approximation method exhibits equiripple characteristics in both the passband and stopband. The equiripple optimal approximation method is essentially an optimization algorithm that effectively overcomes the various shortcomings of window function FIR digital filter design methods and frequency sampling-based FIR digital filter design methods, minimizing the algorithm's maximum error (peak ripple). The equiripple optimal approximation method is used to design digital FIR filters.

[0039] The unit impulse response h(k) of the FIR digital filter is finite in length. Let its length be N, and its transfer function is H(z)=h(0)z 0 +h(1)z -1 …+h(k)z -k , where h(k) is the unit impulse response of the filter, N is the filter order, and k ranges from 0 to N-1. The differential equation of this transfer function describes the relationship between the input signal m(z) and the output signal y(z): Y(n)=h(0)m(n)+h(1)m(n-1)+…+h(k)m(nk), where h(k) is the unit impulse response of the filter, N is the filter order, and k ranges from 0 to N-1. The output signal is obtained by convolving the input signal with the filter coefficients. In underwater environments, accurate signal processing is crucial for achieving precise power matching. FIR digital filters have linear phase characteristics and can filter signals without changing the signal phase, which ensures the accuracy of the load signal.

[0040] 2. Use the MATLAB simulation platform to design an FIR digital filter model and determine the type of model to use based on the load characteristics. The digital signal processing toolbox in the MATLAB simulation platform provides a number of filter functions that make FIR digital filter operations more convenient and faster. For example, write a MATLAB simulation program to generate the excitation signal U, set the parameters of MATLAB's firpm function, and design an FIR digital filter simulation model based on the required signal sampling frequency, signal frequency range, impedance gain, and other parameter requirements. This includes a series of matrix parameters such as the FIR digital filter order, frequency vector, amplitude vector, weight vector, passband and stopband cutoff frequencies, and simultaneously iteratively optimize the model based on actual measurement data. The firpm function provided by MATLAB is further designed, including the order N of the FIR digital filter, the frequency vector F = [f1, f2, …, f2n], the amplitude vector A = [A1, A2, …, A2n], and the weight vector W = [W1, W2, …, Wn]. N is set to 32, the frequency vector F is a vector of normalized frequency points, specified between 0 and 1, with the normalized frequency 1 corresponding to the Nyquist sampling frequency. The amplitude vector A is adjustable within the desired gain range, and the weight vector W specifies the passband and stopband contributions. The firpm function in MATLAB allows for convenient input of filter coefficients, and the chirp function in MATLAB is used to design the excitation signal. Taking a 1-5 kHz swept frequency signal as an example, the excitation signal U = chirp(T, F0, step, F1, 'linear', -90) is set to generate a swept frequency signal with a frequency range of 1 kHz to 5 kHz, a quantized amplitude of ±1, and a duration of 5 seconds. The sampling rate is Fs = 48000 Hz, F0 = 1000 Hz, F1 = 5000 Hz, step = 5, the modulation method is linear frequency modulation, and the initial phase P = -90°. Combining the chirp and firpm functions can create signal data at different frequencies. This signal data effectively simulates the impedance differences at different frequencies under real load conditions.

[0041] 3. Obtain the impedance test data of the load and obtain the gain curves of different loads. Determine the gain range of each frequency band that needs to be adjusted according to the requirements. Draw the curve of the test data on the MATLAB tool, calculate the required gain ratio within the bandwidth, and obtain the gain matrix parameters that need to be adjusted at the frequency point. Figure 1 As shown, Figure 1Figure 1 compares the 1kHz to 5kHz swept-frequency signal and its spectrum gain curves before and after filtering. (a) shows the 1kHz to 5kHz swept-frequency signal before filtering. After impedance adjustment through the FIR filter, the 1kHz to 5kHz swept-frequency signal exhibits varying gains at different frequencies. (b) shows the spectrum gain curve corresponding to the 1kHz to 5kHz swept-frequency signal before filtering. This gain curve also effectively reflects the actual power output matching at the load. Signals at 2, 3, and 4 kHz within the frequency band are selected for comparison. (c) shows the 1 kHz to 5 kHz swept-frequency signal after FIR digital filter processing. The corresponding frequency gains are -43.31 dB, -47.54 dB, and -40.89 dB, respectively. (d) shows the corresponding spectral gain curve of the 1 kHz to 5 kHz swept-frequency signal after FIR digital filter processing. The corresponding spectral amplitude gains of the 2, 3, and 4 kHz signals are -42.17 dB, -43.59 dB, and -42.44 dB, respectively. The spectral gain curves of the processed swept-frequency signal achieve nearly consistent spectral amplitudes after FIR digital filter compensation. This indicates that FIR digital filters can effectively address power matching issues caused by varying load impedance. This design essentially meets the requirements of FIR digital filter design. Specifically, under practical conditions, the gain curve can be further adjusted to fit the load impedance variation curve under different impedance conditions to achieve load power matching. The MATLAB simulation platform provides the FDA Tool (Filter Design & Analysis Tool) filter parameter tool, which can be used in conjunction with the digital processor platform FPGA. Based on this function, the next step is to implement the specific functions of the digital processor platform FPGA.

[0042] The design of FIR digital filter based on hardware platform FPGA includes:

[0043] 1. Based on the characteristics of the hardware platform FPGA, the FIR digital filter designed on the MATLAB simulation platform is imported into the FPGA for implementation. A modular and hierarchical design concept is adopted for the entire FPGA side, so as to have a more detailed understanding and division of labor design of the functions of each part, and use the Verilog hardware programming language to design the FIR digital filter. The core processing system is based on the MCU+FPGA platform. The MCU is responsible for receiving and processing related detection or communication signals and transmitting them to the signal processing module based on the hardware platform FPGA, uploading the detection data of the power amplifier equipment and calculating the relevant parameters. The signal processing module based on the hardware platform FPGA realizes the reception of signal data and FIR digital filtering processing, and drives the power unit inside the power amplifier equipment to perform power conversion on the load. Figure 2As shown, the signal processing module based on the hardware platform FPGA includes but is not limited to the following parts: data receiving and processing submodule, FIR digital filter, driving submodule, PLL phase-locked loop submodule, fault alarm submodule, etc.

[0044] Specifically:

[0045] 1. Data Receiving and Processing Submodule: This submodule processes detection or communication signals sent by the host computer. The submodule's timing clock frequency is determined based on the sampling frequency of the detection or communication signal. An internal frequency generator, such as the PLL (phase-locked loop) submodule, generates the corresponding clock signal for processing.

[0046] See 3, Figure 3 This is a schematic diagram of the processing flow of the data receiving and processing submodule.

[0047] Communication between the FPGA and the MCU primarily involves the parallel port communication protocol and the serial port (USART) communication protocol. The FPGA (programmable logic device) uses the parallel port communication protocol to exchange detection or communication signal data with the MCU, and the serial port (USART) communication protocol for other data exchange. The parallel port communication protocol also includes a data flow control unit and a series of signal groups. The data flow control unit controls the reception and reception of detection or communication signals and filter configuration parameters. The signal groups include data transmission start and stop signals, data error stop signals, data confirmation signals, and data feedback signals. The serial port (USART) communication protocol includes the transmission of sensor data such as voltage and current, as well as the reading and writing of relevant threshold parameters. Based on the sampling theorem Fs ≥ 2 • Fmax, where Fs is the sampling frequency and Fmax is the maximum signal frequency, the FPGA performs data processing on the detection or communication signal data received via the parallel port communication, including sampling and reduction, linear interpolation, and data amplitude conversion. The processed detection or communication signal data is synchronized through pipeline registers and transmitted to the next-stage FIR digital filter. The data reception and processing submodule is also responsible for collecting external sensor data, including but not limited to the interaction of signals from the input and output monitoring signal upload unit, the ADC voltage and current sampling unit, and the alarm data upload unit. The input and output monitoring signal upload unit feeds back the sensor data sampling signals for back-end power matching to the MCU in real time. This sensor data feedback facilitates the design of the FIR digital filter matrix parameters and enables iteration of the post-stage matching parameters. Subsequent updates to the FIR digital filter's impedance gain adjustment matrix parameters are also remotely transmitted from the MCU to the FPGA's BRAM2 filter data storage area via the data reception and processing submodule.

[0048] 2. FIR digital filter: This FIR digital filter is used to implement digital filtering of detection or communication signals. The FIR digital filter module is written in Verilog and uses shift registers and adders to implement convolution operations.

[0049] See also Figure 4 , Figure 4 The following is a schematic diagram of the FIR digital filter processing flow. The FIR digital filter input is the detection or communication signal data to be processed by the previous-level data reception and processing submodule, and the output is the detection or communication signal data after being filtered by the FIR digital filter. The data processing flow first stores the detection or communication signal data to be processed in the BRAM1 signal data area. The BRAM1 signal data area is a continuous storage space within the FPGA that is used to temporarily store the detection or communication signal data to be processed. The BRAM1 signal data area is the first-level data cache, which is used to prevent calculation timing violations between subsequent registers while ensuring that currently transmitted data is not lost.

[0050] The detection or communication signal data to be processed is taken out from the BRAM1 signal data area and sent to the first register for local clock cache synchronization. Register synchronization can not only reduce some problems introduced by cross-clock but also alleviate the impact of metastable states, optimize timing and facilitate convergence.

[0051] The detection or communication signal data to be processed after local clock synchronization is sent to the filter calculation unit, which contains BRAM2 filter data storage area, shift register, adder and other circuits, which can efficiently calculate the filtered data. Among them, the BRAM2 filter data storage area stores the matrix parameters required for the FIR digital filter. The filter configuration parameters calculated in the MATLAB simulation platform can be remotely exported and written to the BRAM2 filter data storage area through the MCU. The FIR digital filter coefficients designed by the MATLAB simulation platform are a series of floating-point numbers, and FPGA does not support floating-point operations. Therefore, the floating-point numbers need to be converted into fixed-point numbers, and the Q value quantization method is used to expand the coefficients by 2. 15 =32768 times, and then converted to a 16-bit binary number. Using a specific algorithm in the FPGA to convert the multiplication operation into a lookup table operation can effectively reduce the consumption of hardware resources and improve the execution speed of the circuit.

[0052] The filtered detection or communication signal data is sent to the second register for output local clock buffer synchronization. Similarly, after synchronization, the probability of glitch output errors in the register intermediate stage combinational logic is reduced, ensuring stable output of register data.

[0053] The FIR digital filter also includes a data detection unit, which verifies the detection or communication signal after it has been filtered by the IR digital filter. This unit is used to detect and respond to anomalies in the detection or communication signal output by the FIR digital filter in real time. Data anomalies primarily indicate abnormal data values ​​in the output, such as maximum or minimum values, or filtered data values ​​exceeding the defined data bit width. The detection time for an anomaly is the minimum local clock tick time, which is related to the system design clock. While issuing an alarm, the data detection unit transmits the abnormal data value and alarm flag to the fault alarm submodule. Furthermore, the unit shuts down the power output of the power amplifier's subsequent stages to protect downstream equipment.

[0054] See also Figure 5 , Figure 5 This is the RTL (Register Transfer Level) view of an FIR digital filter, including input-stage registers, filter modules, intermediate-stage registers, output-stage registers, multiplexers, and adders. Each register level also includes a unified clock source, reset signal, and clock enable signal. The data flow timing logic for the entire signal filtering process is controlled by the sampling frequency and other internal control logic. After filtering, the signal data is buffered in the output register and then passed to the next-level module for processing.

[0055] Based on the sensor data feedback collected by the data receiving and processing submodule, the actual impedance gain curve is obtained. The vector matrix parameters are improved in the MATLAB simulation program module, and the configuration parameters of the FIR digital filter are iteratively input into the BRAM2 filter data storage area of ​​the FIR digital filter of the FPGA. The actual power output before and after is compared to calibrate the impedance gain curve.

[0056] 3. Driver submodule: This module converts detection or communication signal data passing through the FIR digital filter into the drive signal required by the power unit of the power amplifier. This drive signal controls the amplitude and frequency of the output waveform by adjusting the pulse width. This module converts the input DC voltage into a high-frequency pulse signal and extracts the required AC signal through the subsequent power LC filter, thus achieving the subsequent power amplification function.

[0057] 4. PLL phase-locked loop submodule: The PLL phase-locked loop submodule is used to implement the relevant clock signals required for all processing logic. The PLL phase-locked loop submodule is actually an IP core integrated inside the FPGA. The IP core is a pre-designed and verified integrated circuit design module that can be embedded in the FPGA or other types of chips. Its purpose is to reduce design time, reduce costs, and improve system performance and reliability. The IP core of the PLL phase-locked loop submodule can perform system-level clock management and offset control on the clock network, achieving the effects of clock multiplication, division, phase offset and programmable duty cycle, which can conveniently provide the sampling frequency required by the signal and the drive signal reference frequency required by the subsequent driver submodule.

[0058] The FIR digital filter-based control system and method for load power matching in power amplifiers provided by this invention utilizes a collaborative hardware and software design to timely adjust the gain of detection or communication signals based on the actual impedance gain curve at the load end, rapidly correcting the optimal output parameters of the power amplifier and adjusting the power output level. This enables the power amplifier system to respond to dynamic changes in the underwater environment and load, meeting the requirements of underwater equipment in certain specific situations.

[0059] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A control system for load power matching of power amplifier equipment based on FIR digital filter, characterized in that: It includes an MCU, a signal processing module and a power unit. The MCU is used to receive and process the detection or communication signals sent by the host computer and transmit the processed detection or communication signals to the signal processing module, upload the detection data of the power amplifier device to the host computer, and calculate the parameters; the signal processing module is used to receive and perform FIR digital filtering on the detection or communication signals sent by the MCU, and drive the power unit to perform power conversion on the load; The signal processing module includes a data receiving and processing submodule, an FIR digital filter, a driving submodule, a PLL phase-locked loop submodule and a fault alarm submodule. The data receiving and processing submodule is used to receive and process the detection or communication signal sent by the MCU and transmit the processed detection or communication signal to the FIR digital filter. The FIR digital filter is used to perform digital filtering on the received detection or communication signal. The driving submodule is used to convert the detection or communication signal processed by the FIR digital filter into a driving signal required by the power unit of the power amplification device. The PLL phase-locked loop submodule is used to implement the relevant clock signals required by all processing logics. The fault alarm submodule is used to receive the abnormal data value and alarm flag uploaded by the data receiving and processing submodule and the FIR digital filter, perform alarm processing, and transmit the abnormal data value and the alarm flag to the MCU.

2. The control system for load power matching of power amplifier equipment based on FIR digital filter according to claim 1, characterized in that: The data receiving and processing submodule interacts with the MCU for detection or communication signal data through a parallel port communication protocol, and includes a data flow control unit, a sampling and restoration unit, a linear interpolation unit, a data amplitude conversion unit, and a filter configuration parameter unit. The data flow control unit is used to realize the reception control of the detection or communication signal and the filter configuration parameters. The sampling and restoration unit, the linear interpolation unit, and the data amplitude conversion unit are respectively used to perform sampling and restoration, linear interpolation, and data amplitude conversion on the detection or communication signal data received by the data flow control unit, and then transmit the processed detection or communication signal data to the FIR digital filter after synchronization through the pipeline register. The filter configuration parameter unit is used to store and output the filter configuration parameters received by the data flow control unit.

3. The control system for load power matching of power amplifier equipment based on FIR digital filter according to claim 2, characterized in that: The data receiving and processing submodule also interacts with the MCU through a serial communication protocol to transmit sensor data and related threshold parameters, including a threshold parameter configuration unit, an input and output monitoring signal upload unit, an ADC voltage and current sampling unit, and an alarm data upload unit. The input and output monitoring signal upload unit is used to feed back the back-end power matching sensor data sampling signal to the MCU in real time, the ADC voltage and current sampling unit is used to receive external sensor data, and the alarm data upload unit is used to alarm abnormal data values ​​and transmit the abnormal data values ​​and alarm flags to the fault alarm submodule.

4. The control system for load power matching of power amplifier equipment based on FIR digital filter according to claim 1, characterized in that: The FIR digital filter includes a BRAM1 signal data area, a first register, a filtering calculation unit and a second register. The BRAM1 signal data area is used to store the detection or communication signal data to be processed. The first register is used to synchronize the detection or communication signal data taken out from the BRAM1 signal data area with the local clock cache. The filtering calculation unit is used to calculate the filtered detection or communication signal data. The second register is used to output the filtered detection or communication signal data with the local clock cache synchronization.

5. The control system for load power matching of power amplifier equipment based on FIR digital filter according to claim 4, characterized in that: The filtering calculation unit includes a BRAM2 filtering data storage area, a shift register and an adder. The BRAM2 filtering data storage area is used to store matrix parameters required by the FIR digital filter.

6. The control system for load power matching of power amplifier equipment based on FIR digital filter according to claim 4, characterized in that: The FIR digital filter further includes a data discrimination unit, which is used to perform real-time detection and corresponding actions when abnormalities are found in the detection or communication signal data output by the FIR digital filter.

7. The control system for load power matching of power amplifier equipment based on FIR digital filter according to claim 1, characterized in that: The signal processing module uses FPGA as a hardware platform.

8. A control method for a control system for load power matching of a power amplifier device based on an FIR digital filter according to any one of claims 1 to 7, characterized in that: The following steps are involved: Obtain the actual load impedance test data that has not been processed by the FIR digital filter and draw the actual impedance gain curve of the load; Determine the gain range of each frequency band that needs to be adjusted according to the requirements, calculate the required gain ratio within the bandwidth, obtain the gain matrix parameters that need to be adjusted at the frequency point, and store them in the FIR digital filter; Obtain the actual load impedance test data after being processed by the FIR digital filter and draw the actual impedance gain curve; The actual load impedance gain curve after being processed by the FIR digital filter is compared with the load impedance gain curve not processed by the FIR digital filter, and the load impedance gain curve is calibrated in combination with the gain matrix parameters.

9. The control method of a control system for load power matching of a power amplifier device based on an FIR digital filter according to claim 8, characterized in that: MATLAB is used to draw the gain curve and calculate the gain matrix parameters.

10. The control method of a control system for load power matching of a power amplifier device based on an FIR digital filter according to claim 8, characterized in that: The actual impedance test data of different types of loads before and after FIR digital filter processing are obtained and the corresponding actual impedance gain curves are drawn. The actual impedance gain curves of different types of loads before and after FIR digital filter processing are compared respectively. The impedance gain curves of different types of loads are calibrated in combination with the gain matrix parameters of different types of loads to achieve power matching of different types of loads.

Images