Post-sample selectable gain in sample and hold analog-to-digital converter

Abstract

A system and method for a post-sample selectable gain circuit in a sample and hold (S / H) analog-to-digital converter (ADC). The method includes reducing or amplifying a reference voltage to generate a plurality of candidate voltages associated with a plurality of measurement accuracies of the sampler circuit, each of the plurality of candidate voltages being respectively associated with a respective one of the plurality of measurement accuracies. The method includes selecting, by a processing device and based on an input voltage of the sampler circuit, from the plurality of candidate voltages, a particular candidate voltage associated with an optimal measurement accuracy of the plurality of measurement accuracies. The method includes generating a sampler voltage associated with the optimal measurement accuracy by operating the sampler circuit based on the particular candidate voltage or an additional voltage associated with the particular candidate voltage.

Description

Technical Field

[0001] The present disclosure relates generally to the field of electronics, and more particularly to a post-sampling selectable gain circuit in a sample-and-hold (S / H) analog-to-digital converter (ADC). Background Art

[0002] An analog-to-digital converter (ADC) is a system that converts a continuous-time and continuous-amplitude analog signal into a discrete-time and discrete-amplitude digital signal. The ADC does not perform the conversion continuously, but rather periodically, sampling the input and limiting the permissible bandwidth of the input signal. An ADC can also provide isolated measurements, such as an electronic device that converts an analog input voltage or current into a digital number representing the magnitude of the voltage or current. The digital output can be a binary number proportional to the analog input, but there are several other possibilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like reference numerals indicate similar elements and in which:

[0004] Figure 1 A block diagram illustrating an example environment for using a post-sample selectable gain (PSSG) circuit in a S / H ADC according to some embodiments;

[0005] Figure 2 According to some embodiments Figure 1 Variations of the example environment in ;

[0006] Figure 3 According to some embodiments Figure 1 and Figure 2 A block diagram of an example reference generator and reference selector in FIG; and

[0007] Figure 4 is a flow chart of a process for improving the measurement accuracy of a S / H ADC using a PSSG circuit, according to some embodiments. DETAILED DESCRIPTION

[0008] The following description sets forth many specific details, such as examples of specific systems, components, methods, etc., to provide a better understanding of the various embodiments of the technology described herein, such as improving the measurement accuracy of the S / H ADC by using a post-sampling selectable gain circuit. However, it will be apparent to those skilled in the art that at least some embodiments may be practiced without these specific details. In other cases, well-known components, elements, or methods are not described in detail or presented in a simple block diagram format to avoid unnecessarily obscuring the technology described herein. Therefore, the specific details set forth below are merely exemplary. Specific embodiments may differ from these exemplary details and are still contemplated to be within the scope of the present invention.

[0009] The accuracy with which an ADC converts an analog input signal into a digital output signal depends, at least in part, on the amplitude of the analog input signal—that is, as the amplitude decreases, the ADC's ability to accurately perform the conversion also decreases. A conventional technique for improving ADC accuracy in converting an analog input signal into a digital output signal is to amplify the analog input signal before it is measured by the ADC in order to fully utilize the ADC's input voltage range. Signal amplification is performed via a dedicated operational amplifier (OpAmp) or a programmable gain amplifier (PGA). The output of this amplifier is then sampled at the ADC's sample-and-hold (S&H) stage, and conversion of the sampled voltage is subsequently performed after the sample-end (EOS) is reached.

[0010] However, the use of amplifiers in this conventional configuration has several limitations. First, if the ADC samples multiple signals simultaneously, each of these signals requires its own dedicated amplifier. Depending on whether the amplifier is on-chip or off-chip, it consumes silicon area, or PCB area and component cost. Second, in systems with low-latency EOS triggering requirements, the amplifier must always be enabled so that the EOS can occur promptly after receiving the corresponding trigger. Third, amplification occurs during the ADC's sampling time, so the amplification setting is frozen after the EOS. Fourth, when adjusting the amplifier's gain, the output requires a specific amount of time to settle to the new value. During this time frame, no meaningful EOS event occurs. Fifth, when the amplifier is shared among multiple ADC channels (for example, with multiplexed inputs to the amplifier), varying the amplifier's gain between channels can limit conversion speed. Sixth, the amplifier limits the signal's bandwidth, and the ADC's S&H stage will have a higher bandwidth limit. Seventh, each amplifier will have its own gain error, which means that if good gain error performance is desired, each amplifier must be calibrated.

[0011] An alternative conventional technique for amplifying small-amplitude input signals is to reduce the minimum voltage step (e.g., least significant bit (LSB) step size) of the ADC operation by implementing attenuation via capacitor scaling. In this design, the sampling capacitor is larger than the capacitive digital-to-analog converter (C-DAC) used for conversion, effectively giving the sampled signal a higher weight than the C-DAC output.

[0012] However, shrinking the minimum voltage step also presents several limitations. First, if the ADC samples multiple signals simultaneously, each of these signals requires its own sampling capacitor. These sampling capacitors consume a non-negligible amount of silicon area, as they must have capacitance values many times higher than the C-DAC's. Second, amplification occurs during the ADC's sampling time, so the amplification setting is frozen after the EOS (Electrode Time) period. Third, due to implementation complexity, the amplification settings used are limited to a coupling of predefined settings. Fourth, large sampling capacitors require long sampling times, which limits the maximum single-channel conversion throughput. Furthermore, each gain setting requires a separate sampling capacitor and, therefore, a separate sampling time, meaning that not all gain settings are equal or transparent to the end user. Fifth, the implementation requires at least partial discharge of the sampling capacitor during the conversion process, necessitating a large charge from the sensor at the start of sampling after conversion. Sixth, the reduced C-DAC LSB size also makes comparator decisions more difficult, which in turn requires a longer comparator decision time and limits the ADC's speed. Seventh, the architecture requires the sampling capacitor and C-DAC to be separate entities. This, combined with the discharge of the sampling capacitor during the conversion phase, leads to dielectric relaxation issues. This effect must then be addressed by, for example, relaxing or footnoting the specification limits, introducing dedicated calibration mechanisms, etc. Finally, since the sampling capacitor and C-DAC are separate entities, mismatches in the capacitor ratios from the desired values result in gain errors. This gain error must then be corrected for each sampling capacitor / C-DAC combination in use.

[0013] Aspects of the present disclosure address the above-mentioned and other deficiencies by disclosing a post-sample selectable gain (PSSG) circuit for improving the measurement accuracy of a S / H ADC.

[0014] In an exemplary embodiment, the outputs of a plurality of reference generators are coupled to a first set of inputs of a reference selector, the output of the reference selector being coupled to a sampler circuit. The plurality of reference generators are configured to receive a reference voltage and scale down or amplify the reference voltage to generate a plurality of candidate voltages associated with a plurality of measurement precisions of the sampler circuit. Each of the plurality of candidate voltages is associated with a respective measurement precision from the plurality of measurement precisions. Logic circuitry (e.g., one or more processors) is coupled to a second set of inputs of the reference selector. The logic circuitry is configured to use the reference selector and, based on an input voltage to the sampler circuit, select a particular candidate voltage associated with the best measurement precision from the plurality of candidate voltages. The sampler circuit is configured to generate a sampler voltage associated with the best measurement precision by operating the sampler circuit based on the particular candidate voltage or an additional voltage associated with the particular candidate voltage. For example, a DAC may generate an analog voltage (e.g., the additional voltage) based on the particular candidate voltage.

[0015] Compared to conventional architectures with per-sampler gain amplifiers, the disclosed embodiments offer several benefits. First, compared to conventional systems that use amplifiers on each channel, the disclosed embodiments take up less implementation area. While each sampler with a gain setting will require its own dedicated amplifier, in situations where multiple channels must be sampled simultaneously, the reference generator can be shared between channels.

[0016] Second, the bandwidth of the input signal of this embodiment is not limited by any amplifier; thus allowing for shorter sampling times, especially in the case of multiplexed input voltages.

[0017] Third, instead of having a gain error per amplifier, there is only a single gain error per reference generator. This is beneficial for pseudo-differential operation, where two single-ended samplers are sampled simultaneously, but converted by two different conversion sequences, and their results are then subtracted. Gain errors on these pseudo-differential conversions are common and are thus reduced or even eliminated.

[0018] Fourth, the gain setting is flexible, not fixed, and can be changed almost instantly, even after sampling has ended. Furthermore, changes to the gain setting do not require any special handling by the application software, such as initially extending the sampling time after the change.

[0019] Fifth, the present embodiment is robust against input voltage misconfiguration and voltage overshoot / undershoot. That is, voltages outside the per-gain reference voltage range (Vrefp / gain) will not affect the performance of the circuit (e.g., amplifier desaturation which would then require a longer sampling time to recover).

[0020] Finally, this embodiment also uses less power than conventional solutions.

[0021] Compared to conventional architectures with gain setting implemented via capacitive attenuation, embodiments of the present invention also offer several benefits. First, area is reduced, as the sampler's C-net can be sized as low as possible to meet matching and noise (kTC) requirements. In particular, the sampler capacitance does not need to be larger than the DAC (e.g., Csamp ~ G*Cdac in the case of capacitive attenuation).

[0022] Second, the present embodiment has a flexible gain setting (as opposed to a fixed one) that can be changed immediately, even after sampling is complete. The change in gain setting does not require any special handling by the application software (e.g., an initial extended sampling time after the change).

[0023] Third, the smaller sampling capacitor allows for shorter sampling times. Furthermore, it enables implementations where the capacitor is not discharged, so that only the delta voltage between the previous and current samples needs to be settled, which is conceptually impossible with the capacitive decay of conventional solutions. Furthermore, this means that the minimum possible sampling time is independent of the gain setting, as the sampling capacitor used is not proportional to the gain setting.

[0024] Fourth, this embodiment uses reduced input charge consumption. Since the sampler is not discharged during a conversion, only the delta charge for the previous sample should be provided by the sensor.

[0025] Fifth, there is the minimization of dielectric relaxation effects. The sampler and conversion C-net can be the same, and the sampling capacitor is not discharged during conversion. Therefore, the voltage "imprinted" on the capacitor (i.e., the memory effect) is always similar, which means that relaxation to the old voltage value introduces minimal error.

[0026] Sixth, gain error is reduced. That is, instead of having one gain error per sampler (e.g., due to mismatch between the sampler and the conversion C-net), there is only a single gain error per reference. As mentioned above, this is good for pseudo-differential operation.

[0027] Finally, this embodiment has a higher conversion speed. That is, the effective least significant bit (LSB) voltage difference on the comparator nodes is maximized, which means higher comparator speed and therefore higher conversion speed because the comparator decision time is inversely proportional to the resolution voltage difference on its inputs.

[0028] Figure 1A block diagram illustrates an example environment for using a post-sample selectable gain (PSSG) circuit in an S / H ADC, according to some embodiments. Environment 100 includes a PSSG circuit 101 and a sensor circuit 120. PSSG circuit 101 includes one or more reference generators 102 (e.g., reference generator 102a and reference generator 102b). PSSG circuit 101 includes a reference selector 104 (e.g., reference selector 104a, reference selector 104b). PSSG circuit 101 includes a DAC 106, logic circuit 130 (e.g., one or more processors), and a comparator 140. PSSG circuit 101 includes one or more sampler circuits 108. For example, PSSG circuit 101 includes sampler circuit 108a ("Sampler 1"), sampler circuit 108b ("Sampler 2"), and finally sampler circuit 108c ("Sampler X").

[0029] The output of reference generator 102 is coupled to a first set of inputs of reference selector 104, and the output of reference selector 104 is coupled to a first set of inputs of DAC 106. The output of DAC 106 is coupled to a first set of inputs of each sampler circuit 108, and the output of each sampler circuit 108 is coupled to an input of comparator 140. A first set of outputs of logic circuit 130 is coupled to a second set of inputs of reference generator 102; a second set of outputs of logic circuit 130 is coupled to a second set of inputs (sometimes referred to as select inputs) of reference selector 104; and a third set of outputs of logic circuit 130 is coupled to a second set of inputs of sampler circuit 108.

[0030] A dedicated output of sensor circuit 120 is coupled to an input of each sampler circuit. For example, Output 1 (Vin1) of sensor circuit 120 is coupled to the third input of sampler circuit 108a; Output 2 (Vin2) of sensor circuit 120 is coupled to the third input of sampler circuit 108b; and Output 3 (VinX) of sensor circuit 120 is coupled to the third input of sampler circuit 108c. Sensor circuit 120 can drive Output 1, Output 2, and Output 3 at the same voltage. For example, sensor circuit 120 can drive Output 1, Output 2, and Output 3 with a direct current (DC) voltage (e.g., 1V). Sensor circuit 120 can drive Output 1, Output 2, and Output 3 with different voltages. For example, sensor circuit 120 can drive Output 1 with 1V, Output 2 with 2V, or Output 3 with 3V. In some embodiments, sensor circuit 120 can be provided by a third party (e.g., a customer).

[0031] Reference generators 102 are each configured to have a specific gain level or setting. For example, reference generator 102a is configured to have a specific gain level (eg, 1) and reference generator 102b is configured to have a different gain level (eg, 2).

[0032] The reference generator 102 is configured to receive an input voltage range (referred to as a reference voltage) from a negative reference (vrefn) to a positive reference (vrefp). The reference generator 102 is configured to scale down the reference voltage to generate a plurality of candidate voltages associated with a plurality of measurement accuracies of the sampler circuit 108a based on different gain levels / settings; wherein each candidate voltage is associated with a respective measurement accuracy from the plurality of measurement accuracies.

[0033] For example, if a first candidate voltage generated from reference generator 102 a or a voltage derived from the candidate voltage (e.g., via a DAC) is provided to a first set of inputs of sampler circuit 108 a, sampler circuit 108 a may generate an output voltage having a first measurement accuracy based on the first candidate voltage and Vin 1. Alternatively, if a second candidate voltage generated from reference generator 102 b or a voltage derived from the candidate voltage (e.g., via one or more DACs) is provided to the first set of inputs of sampler circuit 108 a, sampler circuit 108 a may generate an output voltage having a second measurement accuracy based on the second candidate voltage and Vin 1.

[0034] The logic circuit 130 is configured to select a particular candidate voltage from among a plurality of candidate voltages and based on an input voltage (e.g., Vin) to the sampler circuit 108a that will cause the sampler circuit 108 to produce an output with the highest measurement accuracy. For example, the logic circuit 130 compares the plurality of candidate voltages with the input voltage (e.g., Vin) to generate a plurality of difference voltages. The logic circuit 130 can identify a particular difference voltage that is less than all other difference voltages in the plurality of difference voltages. The logic circuit 130 can then determine that the particular difference voltage corresponds to the particular candidate voltage. In response, the logic circuit 130 can then send an output signal to the select input of the reference selector 104 to cause the reference selector 104 to select the particular candidate voltage and allow the particular candidate voltage to pass to the first input of the DAC 106.

[0035] In some embodiments, the designer of PSSG circuit 101 already knows that PSSG circuit 101 will be coupled to a specific sensor circuit 120 providing a specific input voltage. Therefore, the designer can pre-configure PSSG circuit 101 to operate optimally with that specific input voltage by pre-selecting an appropriate gain setting based on the input voltage so that the reference voltage matches the voltage range. Thus, in this embodiment, PSSG circuit 101 is not required to select an appropriate gain setting because the designer has already pre-selected the appropriate gain setting to enable the ADC to operate with optimal measurement accuracy for its intended application.

[0036] The DAC 106 is configured to generate an analog voltage (eg, Vdac) based on a particular candidate voltage and a voltage input from the logic circuit 130. The DAC 106 provides the analog voltage to each sampler circuit 108.

[0037] Sampler circuit 108a generates an output voltage based on the analog voltage and Vin1. Sampler circuit 108b generates an output voltage based on the analog voltage and Vin2. Sampler circuit 108c generates an output voltage based on the analog voltage and VinX. By ensuring that the analog voltage matches or nearly matches the input voltage range of the sampler circuit, logic circuit 130 can maximize the measurement accuracy of sampler circuit 108.

[0038] Figure 2 According to some embodiments Figure 1 Environment 200 includes PSSG circuit 201 and sensor circuit 120. Although PSSG circuit 201 includes Figure 1 101 (e.g., reference generator 102, reference selector 104, logic circuit 130, and comparator 140), but there are significant differences in coupling. First, PSSG circuit 101 includes a single DAC 106 that drives its output into each sampler circuit 108, but PSSG circuit 201 moves the DAC into each sampler circuit 208. Specifically, sampler circuit 208a includes DAC 206a, sampler circuit 208b includes DAC 206b, and sampler circuit 208c includes DAC 206c.

[0039] According to an exemplary embodiment, in a first operation, the PSSG circuit 201 samples the input voltage by connecting all switches of the DAC 206 to their corresponding Vin and closing the common-mode switches. In a second operation, the PSSG circuit 201 stops sampling the input voltage by opening the common-mode switches 228 (e.g., 228a, 228b, and 228c), and then holds the sampled voltage until the sampler can convert. That is, the PSSG circuit 201 closes the common-mode switches 228 during sampling to define the voltage on one side of the sampling capacitor, while the DAC 206 defines the voltage on the other side. Alternatively, in some embodiments, the PSSG circuit 201 first opens the input switch pair on the input side of the sampler circuit 208 before opening the common-mode switches 228.

[0040] In the third operation, the sampler is in a hold state as long as its isolation switch is open. Thus, an example sequence includes: opening the common-mode switch 228 of the sampler circuit 208, opening the input switch pair 229 of the sampler circuit 208, closing the isolation switch 227 of the sampler circuit 208, and closing and restarting the sampler circuit 208 by opening the isolation switch 227 and closing the common-mode switch 228 and the input switch pair 229.

[0041] In the fourth operation, at the start of a conversion, the PSSG circuit 201 selects a gain setting, and therefore a reference voltage, using which the sampled voltage is converted via the reference selector 104. In some embodiments, the reference selector 104 can be a single analog multiplexer. In some embodiments, the PSSG circuit 201 can also switch the gain value implemented by the reference generator 102—however, this may come at the expense of a delay until the reference generator 102 stabilizes to the new reference voltage. In the fourth operation, the PSSG circuit 201 then performs an A / D conversion using the selected reference voltage.

[0042] Figure 3 According to some embodiments Figure 1 and Figure 2 . A block diagram of an example reference generator and reference selector is shown in FIG. Reference generator 102 includes reference buffers 302 (e.g., reference buffer 302a, reference buffer 302b, reference buffer 302c) and switches 105 (e.g., switches 105a, 105b, 105c, and 105d). Reference generator 102 also includes resistors 303. Specifically, reference generator 102 includes resistors 303a (8R), 303b (2R), 303c (R), and 303d (R). Each resistor 303 can be a fixed resistor or an adjustable resistor.

[0043] The reference generator 102 is configured to receive an input voltage range (referred to as reference voltages) from a negative reference (vrefn) to a positive reference (vrefp). The reference voltages (vn and vp) used in ADC operation are created by divider circuitry followed by a reference buffer, such as Figure 2 In an example embodiment, when using the Gain=1 setting, the reference can also be passed in an unbuffered manner.

[0044]

[0045] However, in other embodiments, the gain setting can be set to any value that produces the desired ADC measurement accuracy for a particular application. For example, the gain setting can be set to a value greater than 1 (e.g., 2, 3, 10, etc.), which will scale down the reference voltage. Alternatively, the gain setting can be set to a value less than 1 (e.g., 0.5), which will effectively amplify (increase) the reference voltage rather than scale it down.

[0046] Although it achieves minimal delay between gain selection and conversion start, it is not strictly required to have any reference generator fixed to only a single setting. Instead, in some embodiments, if the application constraints allow, the gain setting of any reference generator can be dynamic while maintaining or even further enhancing existing advantages, such as area and power consumption.

[0047] Figure 4 is a flow chart of a process for improving the measurement accuracy of a S / H ADC using a PSSG circuit according to some embodiments. Although for illustrative purposes, the operation Figure 4 400 is depicted as a single operation in a particular order, but in other embodiments, one or more operations or portions thereof are performed in a different order or overlapping in time, serially or in parallel, or are omitted, or one or more additional operations are added, or the method is changed in some combination. In some embodiments, process 400 may be performed by processing logic including hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), firmware, or a combination thereof. In some embodiments, some or all of the operations of process 400 may be performed by Figure 1 One or more components of the PSSG circuit 101 (e.g., reference generator 102, reference selector 104, DAC 106, sampler circuit 108, logic circuit 130, comparator 140) and / or Figure 2 The PSSG circuit 201 is implemented by one or more components of the PSSG circuit 201 (eg, the reference generator 102, the reference selector 104, the DAC 206, the sampler circuit 208, the logic circuit 130, the comparator 140).

[0048] will be relative to Figure 1 The process 400 is described with reference to the PSSG circuit 101 in FIG. 1 , but may be used Figure 2 Process 400 may be implemented using PSSG 201 in the example embodiment. At operation 402, in some embodiments, reference generator 102 receives a reference voltage. At operation 404, in some embodiments, reference generator 102 scales down or scales up the reference voltage to generate a plurality of candidate voltages associated with a plurality of measurement precisions of the sampler circuit. Each candidate voltage in the plurality of candidate voltages is associated with a respective measurement precision in the plurality of measurement precisions. Reference generator 102 may scale down or scale up the reference voltage to generate the plurality of candidate voltages by generating the plurality of candidate voltages based on a plurality of gain levels, wherein each candidate voltage is associated with a respective gain level in the plurality of gain levels.

[0049] At operation 406, in some embodiments, logic circuit 130 may compare a plurality of candidate voltages with the input voltage to generate a plurality of difference voltages. At operation 408, in some embodiments, logic circuit 130 may select a difference voltage from the plurality of difference voltages. At operation 410, in some embodiments, logic circuit 130 may compare the selected difference voltage with other difference voltages in the plurality of difference voltages. At operation 412, in some embodiments, logic circuit 130 may determine whether the selected difference voltage is less than the other difference voltages in the plurality of difference voltages. If not, logic circuit 130 proceeds to operation 414 to select the next difference voltage from the plurality of difference voltages, and then proceeds to operation 410 to repeat the operation using the next difference voltage.

[0050] However, if the logic circuit 130 determines that the selected difference voltage is less than the other difference voltages in the plurality of difference voltages, the logic circuit 130 proceeds to operation 416 to select a candidate voltage corresponding to the selected difference voltage. At operation 418, in some embodiments, the logic circuit 130 generates a sampler voltage associated with optimal measurement accuracy by operating one or more sampler circuits 108 based on the particular candidate voltage or additional voltages associated with the particular candidate voltage.

[0051] In the above description, some parts of the detailed description are presented in terms of algorithms and symbolic representations of the operations on analog signals and / or digital signals or data bits in non-transient storage media. These algorithmic descriptions and representations are means by which those skilled in the art of data processing use the essence of their work to be most effectively conveyed to those skilled in the art. Algorithms are here and generally envisioned as self-consistent sequences of steps leading to a desired result. The steps are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. It has been demonstrated that, primarily for general reasons, it is convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0052] References in the description to "an embodiment," "one embodiment," "example embodiment," "some embodiments," and "various embodiments" mean that a particular feature, structure, step, operation, or characteristic described in connection with one or more embodiments is included in at least one embodiment of the present disclosure. Furthermore, the appearances of the phrases "an embodiment," "one embodiment," "example embodiment," "some embodiments," and "various embodiments" in various places in the description are not necessarily all referring to the same embodiment.

[0053] The description includes references to the accompanying drawings that form a part of the detailed description. The accompanying drawings show diagrams according to exemplary embodiments. These embodiments (which may also be referred to herein as "examples") are described in sufficient detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to practice, make, and / or use the subject matter.

[0054] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise indicated, as will be apparent from the above discussion, it should be understood that throughout this specification, discussions utilizing terms such as "scaling," "selecting," "generating," "determining," "comparing," "providing," "adjusting," "detecting," and the like refer to actions and processes of an integrated circuit (IC) controller or similar electronic device that manipulate and transform data represented as physical (e.g., electronic) quantities within the controller's registers and memories into other data similarly represented as physical quantities within the controller's memories or registers or other such non-transitory storage media of information.

[0055] The words "example" or "exemplary" are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as an "example" or "exemplary" is not necessarily to be construed as being preferred or advantageous over other aspects or designs. On the contrary, the use of the words "example" or "exemplary" is intended to present concepts in a concrete way. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X includes A or B" is intended to mean any natural inclusive permutation. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied under any of the aforementioned instances. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be interpreted to mean "one or more" unless otherwise specified or clear from the context to point to a singular form. In addition, the use of the terms "embodiment" or "one embodiment" throughout the text is not intended to refer to the same embodiment unless so described.

[0056] The embodiments described herein may also relate to devices for performing the operations herein (e.g., such as AC-DC converters and / or ESD protection systems / circuits). The device may be specially constructed for the desired purpose, or it may include firmware or hardware logic that is selectively activated or reconfigured by the device. Such firmware may be stored in a non-transitory computer-readable storage medium, such as, but not limited to, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a flash memory, or any type of medium suitable for storing electronic instructions. The term "computer-readable storage medium" should be deemed to include a single medium or multiple media that stores one or more sets of instructions. The term "computer-readable medium" should also be deemed to include any medium that can store, encode, or carry a set of instructions for a machine to execute so that the machine executes any one or more of the methods of the present embodiment. Therefore, the term "computer-readable storage medium" should be deemed to include, but not limited to, solid-state memory, optical media, magnetic media, any medium that can store a set of instructions for a machine to execute so that the machine executes any one or more of the methods of the present embodiment.

[0057] The above description sets forth many specific details, such as examples of specific systems, components, methods, etc., in order to provide a good understanding of several embodiments of the present disclosure. It should be understood that the above description is intended to be illustrative and not restrictive. After reading and understanding the above description, many other embodiments will be apparent to those skilled in the art. Therefore, the scope of the present disclosure should be determined with reference to the appended claims and the full scope of equivalents to which such claims are entitled.

Claims

1. A method comprising: scaling down or scaling up the reference voltage to generate a plurality of candidate voltages associated with a plurality of measurement precisions of the sampler circuit, each candidate voltage in the plurality of candidate voltages being respectively associated with a corresponding measurement precision in the plurality of measurement precisions; selecting, by one or more processors and based on an input voltage to the sampler circuit, a particular candidate voltage associated with a best measurement accuracy among the plurality of measurement accuracies from the plurality of candidate voltages; as well as A sampler voltage associated with the best measurement accuracy is generated by operating the sampler circuit based on the particular candidate voltage or an additional voltage associated with the particular candidate voltage.

2. The method according to claim 1, wherein Scaling down or scaling up the reference voltage to generate the plurality of candidate voltages comprises: The plurality of candidate voltages are generated based on a plurality of gain levels, each candidate voltage being associated with a respective gain level of the plurality of gain levels.

3. The method of claim 1, further comprising: The input voltage of the sampler circuit is determined by reading a measurement value associated with the input voltage from a register location or a memory location.

4. The method of claim 1, further comprising: The input voltage of the sampler circuit is determined by sampling the input voltage.

5. The method according to claim 1, wherein Selecting the particular candidate voltage from the plurality of candidate voltages based on the input voltage of the sampler circuit includes: comparing the plurality of candidate voltages with the input voltage to generate a plurality of difference voltages; determining that a particular differential voltage in the plurality of differential voltages is less than all other differential voltages in the plurality of differential voltages; and The particular difference voltage is determined to be associated with the particular candidate voltage.

6. The method of claim 1, wherein Generating the sampler voltage by operating the sampler circuit based on the particular candidate voltage includes: providing the particular candidate voltage to the sampler circuit; generating a first digital-to-analog converter (DAC) voltage using a first DAC of the sampler circuit; and The sampler voltage is generated based on the first DAC voltage using the sampler circuit.

7. The method according to claim 6, further comprising: providing the particular candidate voltage to a second sampler circuit; generating a second DAC voltage using a second DAC of the second sampler circuit; as well as The sampler voltage is generated based on the second DAC voltage using the second sampler circuit.

8. The method of claim 1, wherein Generating the sampler voltage by operating the sampler circuit based on the additional voltage associated with the particular candidate voltage includes: generating the additional voltage based on the particular candidate voltage using a single digital-to-analog converter (DAC); providing the additional voltage to the sampler circuit; and The sampler voltage is adjusted based on the additional voltage using the sampler circuit.

9. The method according to claim 8, further comprising: providing the additional voltage to a second sampler circuit; as well as The sampler voltage is adjusted based on the additional voltage using the second sampler circuit.

10. The method according to claim 1, further comprising: After generating the sampler voltage, detecting that the input voltage of the sampler circuit changes to an updated input voltage; selecting, from the plurality of candidate voltages, a different candidate voltage associated with a different one of the plurality of measurement accuracies based on the updated input voltage; as well as Different sampler voltages associated with the different measurement accuracies are generated by operating the sampler circuit based on the different candidate voltages or different voltages associated with the different candidate voltages.

11. An integrated circuit comprising: multiple reference generators; a reference selector coupled to the plurality of reference generators; one or more processors coupled to the reference selector; as well as a sampler circuit coupled to the reference selector, Wherein, the plurality of reference generators are configured as follows: scaling down or scaling up the reference voltage to generate a plurality of candidate voltages associated with a plurality of measurement precisions of the sampler circuit, each candidate voltage in the plurality of candidate voltages being respectively associated with a corresponding measurement precision in the plurality of measurement precisions; The one or more processors are configured to: selecting, using the reference selector and based on an input voltage of the sampler circuit, a particular candidate voltage associated with a best measurement accuracy among the plurality of measurement accuracies from the plurality of candidate voltages; and Wherein, the sampler circuit is configured as follows: A sampler voltage associated with the best measurement accuracy is generated by operating the sampler circuit based on the particular candidate voltage or an additional voltage associated with the particular candidate voltage.

12. The integrated circuit according to claim 11, wherein: In order to reduce or amplify the reference voltage to generate the plurality of candidate voltages, the plurality of reference generators are further configured to: The plurality of candidate voltages are generated based on a plurality of gain levels, each candidate voltage being associated with a respective gain level of the plurality of gain levels.

13. The integrated circuit according to claim 11, wherein: The one or more processors are further configured to: The input voltage of the sampler circuit is determined by reading a measurement value associated with the input voltage from a register location or a memory location.

14. The integrated circuit according to claim 11, wherein: The one or more processors are further configured to: The input voltage of the sampler circuit is determined by sampling the input voltage.

15. The integrated circuit of claim 11, wherein: To select the specific candidate voltage from the plurality of candidate voltages, the one or more processors are further configured to: comparing the plurality of candidate voltages with the input voltage to generate a plurality of difference voltages; determining that a particular differential voltage in the plurality of differential voltages is less than all other differential voltages in the plurality of differential voltages; as well as The particular difference voltage is determined to be associated with the particular candidate voltage.

16. The integrated circuit of claim 11, wherein: The sampler circuit also includes a first digital-to-analog converter (DAC) configured to generate a first DAC voltage; and Wherein, the sampler circuit is further configured as: The sampler voltage is generated based on the first DAC voltage.

17. The integrated circuit of claim 16, further comprising a second sampler circuit coupled to the reference selector, the second sampler circuit further comprising a second DAC configured to generate a second DAC voltage; and in, The second sampler circuit is further configured to: The sampler voltage is generated based on the second DAC voltage.

18. The integrated circuit of claim 11, further comprising: a single digital-to-analog converter (DAC) configured to generate the additional voltage based on the particular candidate voltage; and Wherein, the sampler circuit is further configured as: The sampler voltage is adjusted based on the additional voltage.

19. The integrated circuit of claim 11, further comprising a second sampler circuit coupled to the reference selector, and in, The one or more processors are further configured to: After generating the sampler voltage, detecting that the input voltage of the sampler circuit changes to an updated input voltage; as well as selecting, using the reference selector and based on the updated input voltage, a different candidate voltage associated with a different one of the plurality of measurement accuracies from the plurality of candidate voltages; and Wherein, the second sampler circuit is configured as: Different sampler voltages associated with the different measurement accuracies are generated by operating the sampler circuit based on the different candidate voltages or different voltages associated with the different candidate voltages.

20. A method comprising: receiving a plurality of candidate voltages associated with a plurality of measurement precisions of a sampler circuit, each candidate voltage of the plurality of candidate voltages being respectively associated with a corresponding measurement precision of the plurality of measurement precisions; selecting, from the plurality of candidate voltages, a particular candidate voltage associated with a best measurement accuracy among the plurality of measurement accuracies; as well as The particular candidate voltage is forwarded to allow a sampler circuit to generate a sampler voltage associated with the best measurement accuracy based on the particular candidate voltage.

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