Method for automatically generating macro cell layout with standard cell structure

Abstract

The invention discloses an automatic generation method of a macro cell layout with a standard cell structure, belongs to the technical field of automatic generation methods of macro cell layouts, solves the problem that the prior art cannot adapt to automatic generation of layouts, avoids mismatch of symmetrical structures, and optimizes the area of the layouts. The method comprises the following steps of: generating an MOS (Metal Oxide Semiconductor) single-finger Pcell with the same channel size as a target macro cell layout, embedding a power track and a grounding track, reserving a metal shape for a grid electrode pin, a source electrode pin and a drain electrode pin which are arranged on a second metal layer to form an independent unit structure, and performing horizontal mirror image copying to form an independent unit structure; and reconstructing a second metal layer according to the macro-cell schematic diagram to connect the pins to obtain an overall unit structure, then arranging through holes at the pins to connect the different metal layers, arranging buffer structures at the two sides to form a final overall unit structure, and finally exporting a GDS file. The method is used for automatically generating the macro cell layout with the standard cell structure.

Description

Technical Field

[0001] The invention discloses an automatic generation method of a macro cell layout with a standard cell structure, which is used for automatically generating a macro cell layout with a standard cell structure and belongs to the technical field of automatic generation methods of macro cell layouts. Background Art

[0002] Traditional analog and analog mixed-signal (AMS) circuit layout often relies on manual design, resulting in long design cycles and low efficiency, and requiring a high level of expertise in high-performance analog circuit design. Furthermore, existing layout methods often struggle to adapt to the complex design rules of advanced process nodes, limiting design flexibility and reusability. In recent years, with the rapid development of digital circuit design, automatic placement and routing (PnR) technology for digital standard cells has gradually matured, but its design support for analog circuits remains insufficient. Therefore, a new cell structure is urgently needed to improve this situation.

[0003] Currently, parameterized cells (Pcells) play an important role in the field of integrated circuit design. They allow users to customize parameters when creating cells. This type of cell is programmable, and by defining different parameter values, various variants can be generated to suit different specifications or performance requirements. Pcells can be regarded as programmable cells that define their shape and function through parameter changes, allowing designers to adjust the behavior of the cell by adjusting parameters without modifying the underlying graphics. When implementing Pcells, it is necessary to define parameters, write code, and integrate the code into a library. Pcells can quickly generate different layout versions by changing parameters for iteration and optimization.

[0004] In modern integrated circuit design, MOS transistors (metal-oxide semiconductor field-effect transistors) are one of the core components of circuits. To improve design efficiency and flexibility, designers have adopted parameterized cell (Pcell) technology to automatically generate different MOS transistor layouts. For example, the MOS transistor layout structure with a standard cell structure and its usage method disclosed in 202410285287.0. When using parameterized cell technology to automatically generate MOS transistor layouts, a set of input parameters must first be defined. These input parameters describe the key characteristics of the MOS transistor, such as gate length, gate width, and source and drain region dimensions. Then, using a programming language (such as Verilog-A or Custom Script) provided by an EDA tool (such as Cadence Virtuoso or Synopsys CustomCompiler), a definition script for the parameterized cell is written. The definition script must include the logic for generating the layout based on the input parameters, such as how to arrange the source and drain regions, the gate position, and the layout of the metal connections. After running the parameterized cell definition script, the EDA tool automatically generates the corresponding MOS transistor layout based on the defined set of input parameters. The generated MOS transistor layout also needs to undergo DRC (Design Rule Checking) and LVS (Layout Versus Schematic) checks to ensure that it meets process specifications and is correctly connected. Some commonly used combined symmetrical parts (differential pairs, current mirrors, differential loads, cross-coupled pairs, etc.) can be constructed into macro units for reuse in subsequent circuit layout designs, thereby reducing design time, saving chip circuit layout area, and reducing layout mismatch effects.

[0005] In summary, the existing technology has the following technical problems:

[0006] 1. Current PCeIl tools often rely on fixed templates or limited parameter ranges, limiting their ability to support diverse design requirements. This makes them inflexible and inefficient when dealing with special design requirements. In particular, in complex layout structures, the generated PCels do not have a standard structure, and manual adjustments are still necessary. Therefore, when using parameterized cell technology to automatically generate MOS tube layouts, they do not have a standardized structure similar to digital standard cells, making them unsuitable for subsequent automated generation of the overall chip layout. Manual adjustments are also required, resulting in low layout efficiency.

[0007] 2. Existing technologies cannot automatically generate the overall chip layout;

[0008] 3. There is still a mismatch problem for symmetrical structures (such as differential pair structure, differential load structure, current mirror structure, cross-coupled pair structure, etc.). Summary of the Invention

[0009] In response to the above-mentioned research problems, the purpose of the present invention is to provide a method for automatically generating a macro cell layout with a standard cell structure, so as to solve the problem that when generating a macro cell layout in the prior art, the macro cell layout does not have a standardized structure similar to that of a digital standard cell, cannot adapt to the subsequent automatic layout generation, and requires manual adjustment, resulting in low layout efficiency. In addition, this solution reduces the overall layout area of the chip circuit and reduces the mismatch effect.

[0010] In order to achieve the above object, the present invention adopts the following technical solutions:

[0011] A method for automatically generating a macrocell layout having a standard cell structure comprises the following steps:

[0012] Step 1: Generate a single-finger parameterized cell with the same channel width and length as the target macrocell layout, defined as a MOS tube single-finger Pcell. Pcell is a parameterized cell provided in the PDK, which stands for Process Design Kit.

[0013] Step 2: Embed the power rail and ground rail in the same position as the power rail and ground rail of the digital standard cell in the PDK in the MOS tube single-finger Pcell, and reserve metal shapes for the gate pin, source pin, and drain pin set on the second metal layer Metal 2 to form an independent unit structure;

[0014] Step 3: Mirror and copy the independent unit structure horizontally until the number of independent unit structures is equal to the number of interpolation fingers of the target macro unit layout;

[0015] Step 4: Align all independent unit structures according to the gate width and arrange them horizontally. Use the second metal layer, Metal 2, to horizontally connect the gate pins, source pins, and drain pins of each independent unit structure to form a routing track to build the overall unit structure.

[0016] Step 5: Setting through holes at the gate pin, source pin, and drain pin of each independent unit structure of the overall unit structure to connect different metal layers, and setting a left buffer structure and a right buffer structure on both sides of the overall unit structure to form a final overall unit structure;

[0017] Step 6: Reconstruct the layout according to the final overall unit structure and the target macro unit schematic diagram and output the GDS file of the macro unit to obtain the target macro unit layout.

[0018] Furthermore, the number of interpolation fingers of the single interpolation finger parameterization unit in step 1 is 1.

[0019] Furthermore, the power rail and the ground rail in step 2 are implemented by copying the power rail and the ground rail of the standard inverter structure in the digital standard cell library of the target process.

[0020] Furthermore, the horizontal width of the independent unit structure in step 2 is an integer multiple of the CPP pitch, and the vertical height is an integer multiple of the PGP pitch, wherein CPP represents the center polysilicon pitch and PGP represents the power-ground pitch.

[0021] Furthermore, in the horizontal mirroring process in step 3, the subsequent horizontal mirroring is a horizontal mirroring of the independent unit structure obtained in the previous time, wherein the mirroring axis of the horizontal mirroring is the vertical center of the independent unit structure obtained in the previous time.

[0022] Furthermore, in step 5, the gate pin is connected to the second metal layer Metal 2 and the gate layer through a through hole, and the source pin and the drain pin are connected to the second metal layer Metal 2 and the active area layer through a through hole;

[0023] In step 5, the gate pin, drain pin and source pin are respectively marked with a gate pin mark, a drain pin mark and a source pin mark.

[0024] Further, in step 5:

[0025] The left buffer structure intercepts the left part of the PRBoundary of the target process standard inverter, extends it to the right by a CPP distance, and then copies it to the left side of the overall unit structure. The CPP distance represents the center polysilicon spacing, and the PRBoundary represents the layout and routing boundary.

[0026] The right buffer structure intercepts the right part of the PRBoundary of the target process standard inverter, extends it to the left by a CPP distance, and then copies it to the right side of the overall unit structure.

[0027] Furthermore, the reconstructed layout obtained in step 5 refers to generating port pins, metal traces, through holes, contact holes and pin annotations for the final overall unit structure according to the macro unit schematic.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] 1. After generating a single-finger Pcell of a MOS tube, the present invention adds a power rail, a ground rail, a gate pin, a source pin, and a drain pin to the single-finger Pcell of the MOS tube to form an independent unit structure. The independent unit structure can be regarded as a core similar to a Pcell of the same size, plus some peripheral structures. Each independent unit structure has a power rail and a ground rail. Such standardization ensures that all independent unit structures have a uniform height on the one hand, and maintains horizontal splicing on the other hand, and facilitates the formation of an overall unit structure by placing all independent unit structures on a row basis in the subsequent placement stage (horizontal mirroring). A left buffer structure and a right buffer structure are respectively added to the left and right sides of the overall unit structure, ensuring that when multiple macro unit layouts with standard unit structures are adjacent to each other on the left and right, the left buffer structure and the right buffer structure added to the adjacent overall unit structures leave sufficient spacing between adjacent macro unit layouts with standard unit structures. , thereby avoiding any gap or overlapping DRC errors. After the GDS file is generated, the digital automatic layout and routing tool (APR) can be used to realize automatic layout and routing between the macro cell layout and other circuit components, supporting seamless splicing of digital and analog mixed circuit layouts. No further manual adjustment is required during automatic layout, which greatly reduces the time and cost required for layout drawing. There is no need to solve complex DRC and LVS problems. The required macro cell (Macro) layout can be generated within a few seconds to ensure that the generated macro cell (Macro) layout meets the design specifications and can accurately meet the performance requirements of the macro cell (Macro), fully meeting the needs of macro cell (Macro) layout design. Therefore, after the macro cell (Macro) layout is automatically generated, no manual adjustment is required, the efficiency is high, the overall layout area of the chip circuit is reduced, the mismatch effect is reduced, and it can be spliced with MOS tubes and other macro cells with standard unit structures to realize chip layout automation design.

[0030] Second, the present invention automatically adds pins and pin labels during the macro cell layout generation process. By adding peripheral structures (such as power rails, ground rails, buffer structures, etc.), it can be universally applied to different technology nodes. It has been verified that it can realize a macro cell layout with a standard structure when applied to the 28nm PDK.

[0031] 3. The present invention standardizes the horizontal width and vertical height of the independent unit structure. The horizontal width and vertical height of the independent unit structure are integer multiples of the central polysilicon pitch (CPP) and the power-ground (P / G) pitch (PGP), respectively. All independent unit structures have power rails and ground rails. This standardization ensures the height consistency of all independent unit structures and maintains horizontal splicing, which facilitates the subsequent row-based placement of independent unit structures, so that they can be seamlessly spliced with digital standard units. The generated layout complies with DRC and LVS rules, and the symmetry and matching constraints of the analog circuit are achieved through hierarchical PnR. Therefore, after the macro unit (Macro) layout is automatically generated, the present invention does not require manual adjustment, has high efficiency, and can support the automation of digital-analog mixed circuit layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a flow chart of the present invention;

[0033] Figure 2 A schematic diagram of an existing single-finger Pcell, i.e., a parameterized cell provided in the PDK;

[0034] Figure 3 Schematic diagram of the standard cell structure (hidden metal layer) in the digital standard cell library;

[0035] Figure 4 A schematic diagram showing the addition of power rails and ground rails to a portion of the structure of the present invention, with metal shapes retained for the gate pin, drain pin, and source pin;

[0036] Figure 5 Schematic diagram of the overall unit structure of the present invention;

[0037] Figure 6 Schematic diagram of the structure of the left side buffer structure in the present invention (the right side buffer structure is the right mirror image of the left side);

[0038] Figure 7 The final overall unit structure principle diagram and layout diagram of the present invention;

[0039] Figure 8 A schematic structural diagram of a macro cell layout obtained by re-layouting the final overall cell structure using the macro cell (Macro) principle diagram with a standard cell structure of the present invention;

[0040] Figure 9The following are actual layout diagrams of macro cells (differential pairs) with a length of 30 nm and a width of 400 nm, and with 6 and 16 interdigital fingers, automatically generated in a 28 nm process using a macro cell with a standard cell structure according to the present invention. The first diagram has 6 interdigital fingers, and the second diagram has 16 interdigital fingers.

[0041] In the figure: 1-redundant polysilicon, 2-power track, 3-ground track, 4-interpolation finger, 5-first metal layer M1, 6-pin label, 7-contact hole, 8-through hole, 9-second metal layer M2, 10-diffusion region, 11-layout and wiring boundary, 12-gate pin width. DETAILED DESCRIPTION

[0042] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0043] A method for automatically generating a macrocell layout having a standard cell structure, characterized by comprising the following steps:

[0044] Step 1: Generate a single-finger parameterized unit with the same channel width and channel length as the target macrocell layout, which is defined as a MOS tube single-finger Pcell; wherein, the MOS tube single-finger Pcell is a parameterized unit provided in the PDK, PDK stands for Process Design Kit, and the number of fingers of the single-finger parameterized unit is 1; the MOS tube single-finger Pcell is as follows Figure 2 shown.

[0045] Step 2: Embed the power rail and ground rail in the MOS tube single-finger Pcell, and reserve metal shapes for the gate pin, source pin and drain pin set on the second metal layer Metal 2 to form an independent unit structure; the power rail and ground rail are realized by copying the power rail and ground rail of the standard inverter structure in the target process digital standard cell library. Figure 3As shown. The horizontal width of the independent unit structure is an integer multiple of the CPP pitch, and the vertical height is an integer multiple of the PGP pitch, wherein CPP represents the central polysilicon pitch and PGP represents the power-ground pitch. Standardize the horizontal width and vertical height of the independent unit structure, the horizontal width and vertical height of the independent unit structure are integer multiples of the central polysilicon pitch (Central PolyPitch, CPP) and the power-ground (Power-Ground, P / G) pitch (Power-Ground Pitch, PGP), respectively. All independent unit structures have power rails and ground rails; this standardization ensures the height consistency of all independent unit structures and maintains horizontal splicing, which facilitates the subsequent placement of row-based independent unit structures, so that they can be seamlessly spliced with digital standard units. The generated layout complies with DRC and LVS rules, and the symmetry and matching constraints of the analog circuit are achieved through hierarchical PnR. Therefore, after the macro unit (Macro) layout is automatically generated, the present invention does not require manual adjustment, has high efficiency, and can support the automation of digital-analog mixed circuit layout. Among them, the independent unit structure is as follows Figure 4 shown.

[0046] Step 3: Horizontally mirror the independent unit structure until the number of independent unit structures is equal to the number of interdigitation fingers of the target macro unit layout; in the horizontal mirroring process, the latter horizontal mirroring is a horizontal mirroring of the independent unit structure obtained in the previous one.

[0047] Step 4: Align all independent unit structures according to the gate width and arrange them horizontally, and use the second metal layer Metal 2 to horizontally connect the gate pins, source pins and drain pins of each independent unit structure to form a routing track to build the overall unit structure; wherein, the overall unit structure is as follows Figure 5 shown.

[0048] Step 5: Set through holes at the gate pin, source pin and drain pin of each independent unit structure of the overall unit structure to connect different metal layers, and set a left buffer structure and a right buffer structure on both sides of the overall unit structure to form the final overall unit structure, wherein the left buffer structure is as follows: Figure 6As shown; the gate pin is connected to the second metal layer Metal 2 and the gate layer ga through a through hole, the source pin and the drain pin are connected to the second metal layer Metal2 and the active area layer od through a through hole, and the gate pin, drain pin and source pin are respectively marked with the gate pin mark, drain pin mark and source pin mark, and the left buffer structure intercepts the left part of the PRBoundary of the target process standard inverter, and extends it to the right by a CPP distance and then copies it to the left side of the overall unit structure, wherein the CPP distance represents the center polysilicon spacing, and the PRBoundary represents the layout and routing boundary; the right buffer structure intercepts the right part of the PRBoundary of the target process standard inverter, and extends it to the left by a CPP distance and then copies it to the right side of the overall unit structure; the left buffer structure and the right buffer structure include redundant polysilicon (dummy poly), PRBoundary, power rail and ground rail. Pins and pin marks are automatically added during the target macro unit layout generation process to complete the final overall unit structure. The final overall unit structure is as shown in FIG. Figure 7 shown.

[0049] Step 6: Reconstruct the layout according to the final overall unit structure and the target macro unit schematic diagram and output the GDS file of the macro unit, that is, obtain the target macro unit layout. Reconstructing the layout means that the final overall unit structure generates port pins, metal traces, through holes, contact holes and pins (including gate pins, source pins and drain pins) according to the macro unit schematic diagram. Among them, the target macro unit layout is as follows: Figure 8 As shown. After verification, it can realize the macro cell layout with standard structure when applied to 28nm. Among them, the target macro cell layout of 28nm is as follows Figure 9 shown.

[0050] After generating a single-finger Pcell for the MOS tube, power rails, ground rails, gate pins, source pins, and drain pins are added to the single-finger Pcell for the MOS tube to form an independent unit structure. The independent unit structure can be regarded as a core similar to a Pcell of the same size, plus some peripheral structures. Each independent unit structure has a power rail and a ground rail. Such standardization ensures that all independent unit structures have a uniform height on the one hand, and maintains horizontal splicing on the other hand, and helps to form an overall unit structure by placing all independent unit structures based on rows in the subsequent placement stage (horizontal mirroring). The left buffer structure and the right buffer structure are respectively added to the left and right sides of the overall unit structure to ensure that when multiple macro unit layouts with standard unit structures are adjacent to each other on the left and right, sufficient spacing is left between adjacent macro unit layouts with standard unit structures by adding the left buffer structure and the right buffer structure in the adjacent overall unit structure, thereby avoiding any gap or overlapping DRC errors. After the GDS file is generated, the digital automatic layout and routing tool Automated Place and Route (APR) implements automatic placement and routing between macrocell layouts and other circuit components, supporting seamless splicing of mixed-analog circuit layouts. No further manual adjustments are required during automatic layout, greatly reducing the time, effort, and cost required for layout drawing. There is no need to solve complex DRC and LVS issues. The required macrocell layout can be generated in seconds, ensuring that the generated macrocell layout meets the design specifications and can accurately meet the performance requirements of the macrocell, fully meeting the needs of macrocell layout design. In addition, independent cell structures are horizontally mirrored according to the required finger width and channel length of the macrocell, thereby realizing the design requirements of macrocell layouts of arbitrary width and length. Therefore, when used in mixed-analog circuit design, it can be seamlessly connected with digital standard cells and can be arranged adjacently in all directions, thus realizing the application of the automatic digital PnR engine. Combined with digital standard cells, it can realize automatic placement and routing of analog mixed-signal circuits, and has broad application prospects in analog mixed-signal circuits and analog circuits. Therefore, after the target macro cell (Macro) layout is automatically generated, no manual adjustment is required, which is highly efficient.

[0051] Example

[0052] In order to verify the performance of the automatic generation method of the macro cell layout with a standard cell structure of the present invention, the automatic generation method of the macro cell layout with a standard cell structure of the present invention is used to generate a macro cell (differential pair structure) layout with a standard cell structure of 30 nm in length, 400 nm in width, and 8 and 16 interdigits in a 28 nm PDK (Process Design Kit). Figure 9 shown.

[0053] In summary, the present invention provides a method for automatically generating a macrocell layout with a standard cell structure. After generating a single-finger Pcell of a MOS tube, a power rail, a ground rail, a buffer structure, a gate pin, a source pin, and a drain pin are added to form an independent cell structure. The independent cell structure is then horizontally mirrored according to the number of MOS tube fingers, aligned according to the width of the gate pin, and arranged horizontally to form an overall cell structure. The second layer of metal, Metal 2, is horizontally connected to form a routing track. Source pin labels, drain pin labels, and gate pin labels are added to each independent cell structure of the overall cell structure, and through-holes of different metal layers are added to the source pin, drain pin, and gate pin, respectively. Furthermore, the through-hole on the gate pin connects the second metal layer, Metal 2, to the gate layer, and the through-holes on the source and drain pins connect the second metal layer, Metal 2, to the gate layer. Then, according to the pin connection relationship in the macro unit schematic, the layout connection is reconstructed, that is, the port pins, metal traces, through holes, contact holes and pin annotations are regenerated to output the GDS file of the macro unit. Therefore, after the macro unit (Macro) layout is automatically generated, no manual adjustment is required, which is highly efficient and can support the automation of mixed analog and digital circuit layout.

[0054] The above are only representative embodiments of the present invention in many specific application scopes and do not constitute any limitation on the protection scope of the present invention. Any technical solutions formed by transformation or equivalent replacement fall within the scope of protection of the present invention.

Claims

1. A method for automatically generating a macro cell layout having a standard cell structure, characterized in that: The steps include: Step 1: Generate a single-finger parameterized cell with the same channel width and length as the target macrocell layout, which is defined as a MOS tube single-finger Pcell. The MOS tube single-finger Pcell is a parameterized cell provided in the PDK, where PDK stands for Process Design Kit. Step 2: Embed the power rail and ground rail in the same position as the power rail and ground rail of the digital standard cell in the PDK in the MOS tube single-finger Pcell, and reserve metal shapes for the gate pin, source pin, and drain pin set on the second metal layer Metal 2 to form an independent unit structure; Step 3: Mirror and copy the independent unit structure horizontally until the number of independent unit structures is equal to the number of interpolation fingers of the target macro unit layout; Step 4: Align all independent unit structures according to the gate width and arrange them horizontally. Use the second metal layer Metal2 to horizontally connect the gate pins, source pins, and drain pins of each independent unit structure to form a routing track to construct the overall unit structure. Step 5: Setting through holes at the gate pin, source pin, and drain pin of each independent unit structure of the overall unit structure to connect different metal layers, and setting a left buffer structure and a right buffer structure on both sides of the overall unit structure to form a final overall unit structure; Step 6: Reconstruct the layout according to the final overall unit structure and the target macro unit schematic diagram and output the GDS file of the macro unit to obtain the target macro unit layout.

2. The method for automatically generating a macrocell layout having a standard cell structure according to claim 1, wherein: In step 1, the number of interpolation fingers of the single interpolation finger parameterization unit is 1.

3. The method for automatically generating a macrocell layout having a standard cell structure according to claim 1, wherein: The power rail and ground rail in step 2 are implemented by copying the power rail and ground rail of the standard inverter structure in the digital standard cell library of the target process.

4. The method for automatically generating a macrocell layout having a standard cell structure according to claim 1, wherein: The horizontal width of the independent unit structure in step 2 is an integer multiple of the CPP pitch, and the vertical height is an integer multiple of the PGP pitch, where CPP represents the center polysilicon pitch and PGP represents the power-ground pitch.

5. The method for automatically generating a macrocell layout having a standard cell structure according to claim 1, wherein: In the horizontal mirroring process in step 3, the subsequent horizontal mirroring is a horizontal mirroring of the independent unit structure obtained in the previous time, wherein the mirroring axis of the horizontal mirroring is the vertical center of the independent unit structure obtained in the previous time.

6. The method for automatically generating a macrocell layout having a standard cell structure according to claim 1, wherein: In step 5, the gate pin is connected to the second metal layer Metal 2 and the gate layer through a through hole, and the source pin and the drain pin are connected to the second metal layer Metal 2 and the active area layer through a through hole; In step 5, the gate pin, drain pin and source pin are respectively marked with a gate pin mark, a drain pin mark and a source pin mark.

7. The method for automatically generating a macrocell layout having a standard cell structure according to claim 1, wherein: In step 5: The left buffer structure intercepts the left part of the PRBoundary of the target process standard inverter, extends it to the right by a CPP distance, and then copies it to the left side of the overall unit structure. The CPP distance represents the center polysilicon spacing, and the PRBoundary represents the layout and routing boundary. The right buffer structure intercepts the right part of the PRBoundary of the target process standard inverter, extends it to the left by a CPP distance, and then copies it to the right side of the overall unit structure.

8. The method for automatically generating a macrocell layout having a standard cell structure according to claim 1, wherein: The reconstructed layout obtained in step 5 refers to the generation of port pins, metal traces, through holes, contact holes and pin annotations for the final overall unit structure according to the macro unit schematic.

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