Macro-cell legalization method, system and equipment for FPGA (Field Programmable Gate Array) chip and medium
By obtaining the coordinate sequence of macrocells connecting design cells and determining the optimal region anchor point, and combining the simulated annealing algorithm to optimize the macrocell position, the problem of non-timing optimal macrocell coordinates in traditional methods is solved, thus improving the layout quality of FPGA chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-20
- Publication Date
- 2026-04-07
AI Technical Summary
Traditional macrocell validation methods rely on global layout coordinates, which leads to non-time-optimal macrocell coordinates. In particular, when resource utilization is high, macrocell coordinates tend to cluster, affecting layout quality.
By obtaining the coordinates of the design units directly connected to the macrocells, sorting them to form X-coordinate sequences and Y-coordinate sequences, determining the optimal region boundary values and anchor points, and using the simulated annealing algorithm to minimize the distance between the macrocells and anchor points, the legal placement positions are optimized.
This reduces the deviation between macrocell positions and anchor points, optimizes the layout timing performance of FPGA chips, and ensures that legal placement positions comply with physical constraints.
Smart Images
Figure CN121809375A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of integrated circuit technology, specifically relating to a method, system, device, and medium for macrocell legalization of FPGA chips. Background Technology
[0002] The chip placement process typically includes three stages: global placement, legalization, and detailed placement. Macro cell legalization is a crucial step in the FPGA (Field Programmable Gate Array) design and placement process. A macro cell is a large logic module in an FPGA composed of multiple standard cells, such as RAM (Random Access Memory) or DSP (Digital Signal Processor) modules. Accurately placing it in its legal location on the chip is an important prerequisite for achieving better placement timing performance.
[0003] Traditional macrocell legalization methods use the coordinates calculated by the global layout as anchor points, causing the layout result to depend entirely on the global layout output. However, due to the inherent volatility of the global layout, the calculated macrocell coordinates are often not the temporally optimal positions. Especially in scenarios with high resource utilization, the global layout struggles to effectively diffuse the distribution density of macrocells, leading to the clustering of coordinates among multiple macrocells. This results in a significant deviation between the legalized macrocell positions and the anchor points, impacting the overall layout quality. Summary of the Invention
[0004] This application provides a method, system, device, and medium for macrocell legalization of FPGA chips, which can avoid the limitations of global placement in determining macrocell anchor points, reduce the deviation between the legalized macrocell position and the anchor point, and optimize the placement timing performance of FPGA chips.
[0005] To address the aforementioned technical problems, in a first aspect, this application provides a method for macrocell legalization in FPGA chips, comprising the following steps: Perform global placement of the FPGA design netlist to determine the initial positions of macrocells and other design cells in the global placement coordinate system; Obtain the coordinate positions of other design units directly connected to each of the macro units in the global layout coordinate system; The coordinate positions of all other design units connected to each macro unit are sorted along the X-axis and Y-axis directions respectively to obtain the X-coordinate sequence and Y-coordinate sequence corresponding to each macro unit; The boundary values of the optimal region are determined based on the X-coordinate sequence and the Y-coordinate sequence, and the anchor points of the corresponding macrocells are determined based on the boundary values. Minimize the distance between the candidate placement location of each macrocell and its corresponding anchor point to determine the legal placement location of each macrocell on the FPGA chip.
[0006] As a further improvement to this application, the step of sorting the coordinate positions of all other design units connected to each macrocell along the X-axis and Y-axis directions respectively to obtain the X-coordinate sequence and Y-coordinate sequence corresponding to each macrocell includes: Extract the corresponding X and Y coordinate values from the coordinate positions of all other design units connected to each macrocell; Sort all the X coordinate values in ascending order to obtain the X coordinate sequence corresponding to the macrounit; Furthermore, all the Y-coordinate values are sorted in ascending order to obtain the Y-coordinate sequence corresponding to the macrounit.
[0007] As a further improvement to this application, the step of determining the boundary values of the optimal region based on the X-coordinate sequence and the Y-coordinate sequence includes: When the length of the coordinate sequence is even, the two X coordinate values located at the center position in the X coordinate sequence are used as the left and right boundary values of the optimal region in the X-axis direction, and the two Y coordinate values located at the center position in the Y coordinate sequence are used as the lower and upper boundary values of the optimal region in the Y-axis direction. When the length of the coordinate sequence is odd, the two X coordinate values adjacent to the center position of the X coordinate sequence are used as the left and right boundary values of the optimal region in the X-axis direction, and the two Y coordinate values adjacent to the center position of the Y coordinate sequence are used as the lower and upper boundary values of the optimal region in the Y-axis direction.
[0008] As a further improvement to this application, the step of determining the anchor point of the corresponding macrocell based on the boundary value includes: The X-coordinate of the anchor point is half the difference between the right and left boundary values of the optimal region in the X-axis direction, and the Y-coordinate of the anchor point is half the difference between the upper and lower boundary values of the optimal region in the Y-axis direction.
[0009] As a further improvement to this application, minimizing the distance between the candidate placement location of each macrocell and its corresponding anchor point to determine the legal placement location of each macrocell on the FPGA chip includes: With the optimization objective of minimizing the distance between the candidate placement position of the macrocell and the corresponding anchor point, the legal placement position is determined from the candidate placement position set of the FPGA chip by means of simulated annealing algorithm, and the coordinate position of the macrocell is updated to the corresponding legal placement position.
[0010] As a further improvement of this application, the termination condition of the simulated annealing algorithm is to reach the set maximum number of iterations, or the change in the distance from the candidate placement position of the macrocell to the anchor point is less than a preset threshold in a consecutive preset number of iterations.
[0011] As a further improvement to this application, the optimal region is a rectangle.
[0012] Secondly, this application provides a macrocell legitimization system for FPGA chips, comprising: Placement cells are used to perform global placement of the FPGA design netlist and determine the initial positions of macro cells and other design cells in the global placement coordinate system. The acquisition unit is used to acquire the coordinate positions of other design units directly connected to each of the macro units in the global layout coordinate system. A sorting unit is used to sort the coordinate positions of all other design units connected to each macro unit along the X-axis and Y-axis directions respectively, to obtain the X-coordinate sequence and Y-coordinate sequence corresponding to each macro unit; An anchor point determination unit is used to determine the boundary value of the optimal region based on the X coordinate sequence and the Y coordinate sequence, and to determine the anchor point of the corresponding macro unit according to the boundary value; A simulation unit is used to minimize the distance between the candidate placement position of each macrocell and the corresponding anchor point in order to determine the legal placement position of each macrocell on the FPGA chip.
[0013] Thirdly, this application provides a computer device, the computer device including a processor and a memory coupled to the processor, the memory storing a calculation program, the computer program being executed by the processor causing the processor to perform the steps of the macrocell legalization method for FPGA chips described above.
[0014] Fourthly, this application provides a computer-readable storage medium storing a computer program that is executed by a processor to implement the above-described macrocell legalization method for FPGA chips.
[0015] The macrocell legalization method, system, device, and medium for FPGA chips provided in this application have the following beneficial effects: This application obtains the initial positions of macrocells and other design units through global layout, providing a basic coordinate reference for subsequent anchor point calculation. Instead of directly using the macrocell coordinates of the global layout as anchor points, it extracts the coordinate positions of other design units directly connected to each macrocell. By using the coordinate positions of all other design units connected to each macrocell, the optimal region and anchor point of the macrocell are determined, avoiding the limitations of global layout in determining macrocell anchor points. Finally, the legal placement position of the macrocell is determined by minimizing the distance between the candidate placement position of the macrocell and the anchor point. This not only reduces the deviation between the legalized macrocell position and the anchor point, but also ensures that the legal placement position conforms to the physical constraints of the FPGA chip, effectively optimizing the placement timing performance of the FPGA chip. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only a part of the embodiments of this application, and not all of the embodiments. For those skilled in the art, other drawings obtained from these drawings without creative effort are all within the scope of protection of this application.
[0017] Figure 1 This is a flowchart of a macrocell legalization method for FPGA chips provided in an embodiment of this application.
[0018] Figure 2 This is a specific embodiment of the macrocell legalization method for FPGA chips provided in this application.
[0019] Figure 3 This is a flowchart illustrating the process of obtaining the X-coordinate sequence and Y-coordinate sequence in the macrocell legalization method for FPGA chips provided in this application embodiment.
[0020] Figure 4 This is a flowchart of the method for determining anchor points in the macrocell legalization method for FPGA chips provided in the embodiments of this application.
[0021] Figure 5 This is a block diagram of a macrocell legitimization system for FPGA chips provided in an embodiment of this application.
[0022] Figure 6 A schematic diagram of the structure of a computer device provided in an embodiment of this application.
[0023] Figure 7 This is a schematic diagram of the structure of the storage medium provided in the embodiments of this application. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.
[0025] To make the description of this disclosure more detailed and complete, illustrative descriptions of the implementation methods and specific embodiments of this application are provided below; however, this is not the only form of implementing or utilizing the specific embodiments of this application. The implementation methods cover the features of multiple specific embodiments and the method steps and their order for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equivalent functions and step sequences. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.
[0027] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The word "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more. Other quantifiers should be understood similarly. The preferred embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. Furthermore, the embodiments of this application and the features in the embodiments can be combined with each other without conflict.
[0028] The chip placement process typically includes three stages: global placement, legalization, and detailed placement. Macro cell legalization is a crucial step in the FPGA (Field Programmable Gate Array) design and placement process. A macro cell is a large logic module in an FPGA composed of multiple standard cells, such as RAM (Random Access Memory) or DSP (Digital Signal Processor) modules. Accurately placing it in its legal location on the chip is an important prerequisite for achieving better placement timing performance.
[0029] Traditional macrocell legalization methods use the coordinates calculated by the global layout as anchor points, causing the layout result to depend entirely on the global layout output. However, due to the inherent volatility of the global layout, the calculated macrocell coordinates are often not the optimal positions in time. Especially in scenarios with high resource utilization, the global layout struggles to effectively diffuse the distribution density of macrocells, causing the coordinates of multiple macrocells to cluster together. This results in a significant deviation between the legalized macrocell positions and the anchor points, affecting the overall layout quality.
[0030] In view of this, please refer to Figures 1-7 This application proposes a method, system, device, and medium for macrocell legalization of FPGA chips, which can avoid the limitations of global layout in determining macrocell anchor points, reduce the deviation between the legalized macrocell position and the anchor point, and optimize the layout timing performance of FPGA chips.
[0031] Please refer to Figure 1 The flowchart below shows a method for macrocell legalization of FPGA chips provided in this application. The method includes the following steps: Step S1: Perform global placement of the FPGA design netlist to determine the initial positions of macrocells and other design cells in the global placement coordinate system; In the embodiments of this application, the above-mentioned FPGA design netlist is a netlist that has completed technology mapping, that is, it has converted and mapped common logic gates such as AND gates and OR gates to the corresponding technology mapping netlist formed in the target FPGA chip architecture. The technology mapping netlist usually contains each logic unit in the circuit and the connection relationship between them.
[0032] Furthermore, a preliminary and rough global layout of the FPGA design netlist is required to quickly calculate the approximate location of each logic unit and output the initial positions of macrocells and other design units in the global layout coordinate system.
[0033] It is understandable that the global layout coordinate system mentioned above is a continuous coordinate system dedicated to the global layout stage. It is only used to characterize the relative distribution trend between macro elements and other design elements. The initial position refers to the preliminary determined position of macro elements and other design elements in the global layout coordinate system, not the final placement position.
[0034] Step S2: Obtain the coordinate positions of other design units directly connected to each of the macro units in the global layout coordinate system; Please refer to Figure 2 This is a flowchart of obtaining the X-coordinate sequence and Y-coordinate sequence in the macrocell legalization method for FPGA chips provided in the embodiments of this application. In the figure, the circle numbered 0 represents a macrocell, the circles numbered 1-6 represent other design units, the curve with arrows represents the connection relationship between the macrocell numbered 0 and the other design units numbered 1-6, the dashed box in the figure is the "bounding box", that is, the minimum bounding box of other design units, and the solid box is the "optimum box" optimal area used to determine the anchor point later.
[0035] In this embodiment of the application, taking a macro unit shown in the figure as an example, when determining the anchor point of the macro unit, it is necessary to first obtain other design units directly connected to the macro unit according to the connection relationship, and then obtain the coordinate positions of all other design units in the global layout coordinate system.
[0036] It should be noted that the direct connection here refers to other design units that are logically related to the current macro unit. The curves in the figure are used to represent the connection relationship between the macro unit and other design units. It is feasible to determine the connection relationship by using straight lines or other lines. This application does not limit this.
[0037] It can be observed that there is a connection between the macro unit numbered 0 and the other design units numbered 1-6. Therefore, it is necessary to obtain the coordinate positions of the other design units numbered 1-6 in the global layout coordinate system.
[0038] Specifically, in this embodiment, the coordinates of the other design unit numbered 1 in the global layout coordinate system are (X1, Y1), the coordinates of the other design unit numbered 2 in the global layout coordinate system are (X2, Y2), the coordinates of the other design unit numbered 3 in the global layout coordinate system are (X3, Y3), the coordinates of the other design unit numbered 4 in the global layout coordinate system are (X4, Y4), the coordinates of the other design unit numbered 5 in the global layout coordinate system are (X5, Y5), and the coordinates of the other design unit numbered 6 in the global layout coordinate system are (X6, Y6).
[0039] Step S3: Sort the coordinate positions of all other design units connected to each macro unit along the X-axis and Y-axis respectively to obtain the X-coordinate sequence and Y-coordinate sequence corresponding to each macro unit; As an optional implementation method, please refer to Figure 3 This is a flowchart illustrating the method for obtaining X-coordinate and Y-coordinate sequences in the macrocell legalization method for FPGA chips provided in this application embodiment. The method involves sorting the coordinate positions of all other design units connected to each macrocell along the X-axis and Y-axis directions respectively to obtain the X-coordinate and Y-coordinate sequences corresponding to each macrocell, including: Step S30: Extract the corresponding X and Y coordinate values from the coordinate positions of all other design units connected to each macrocell; Step S31: Sort all the X coordinate values in ascending order to obtain the X coordinate sequence corresponding to the macro unit; Step S32: And, sort all the Y coordinate values in ascending order to obtain the Y coordinate sequence corresponding to the macro unit.
[0040] In this embodiment of the application, after determining the other design units directly connected to the macro unit, it is necessary to obtain the coordinate positions of all other design units, and then sort the coordinate positions of all other design units in ascending order along the X-axis and Y-axis directions respectively to obtain the X-coordinate sequence and Y-coordinate sequence corresponding to each macro unit.
[0041] For details, please continue to refer to... Figure 2 From the coordinate positions of the other design units numbered 1-6, the corresponding X coordinate values X1, X2, X3, X4, X5, and X6 are extracted. Combined with the coordinate distribution shown in the attached figure, all X coordinate values are sorted in ascending order to obtain the X coordinate sequence corresponding to the macro unit as (X1, X6, X5, X2, X4, X3).
[0042] Furthermore, the corresponding Y coordinate values Y1, Y2, Y3, Y4, Y5, and Y6 are extracted. Combined with the coordinate distribution shown in the attached figure, all Y coordinate values are sorted in ascending order to obtain the Y coordinate sequence corresponding to the macro unit as (Y5, Y6, Y4, Y2, Y3, Y1). This makes the scattered coordinate values form an orderly distribution in the global layout coordinate system, providing a basis for subsequently determining the boundary values and anchor points of the optimal region.
[0043] Step S4: Determine the boundary values of the optimal region based on the X-coordinate sequence and the Y-coordinate sequence, and determine the anchor points of the corresponding macrocells according to the boundary values; As an optional implementation method, please refer to Figure 4 This is a flowchart illustrating the process of determining anchor points in the macrocell legalization method for FPGA chips provided in this application embodiment. The determination of the boundary values of the optimal region based on the X-coordinate sequence and Y-coordinate sequence includes: Step S40: When the length of the coordinate sequence is even, the two X coordinate values located at the center position in the X coordinate sequence are used as the left and right boundary values of the optimal region in the X-axis direction, and the two Y coordinate values located at the center position in the Y coordinate sequence are used as the lower and upper boundary values of the optimal region in the Y-axis direction. Step S41: When the length of the coordinate sequence is odd, the two X coordinate values adjacent to the center position of the X coordinate sequence are used as the left and right boundary values of the optimal region in the X-axis direction, and the two Y coordinate values adjacent to the center position of the Y coordinate sequence are used as the lower and upper boundary values of the optimal region in the Y-axis direction.
[0044] In one specific embodiment provided in this application, please continue to refer to... Figure 2 The X-coordinate sequence corresponding to the macrocell numbered 0 is (X1, X6, X5, X2, X4, X3), and the corresponding Y-coordinate sequence is (Y5, Y6, Y4, Y2, Y3, Y1).
[0045] Furthermore, since the lengths of the X-coordinate sequence and the Y-coordinate sequence are even numbers, the two X-coordinate values located at the center position in the X-coordinate sequence are selected as the left and right boundary values of the optimal region in the X-axis direction, that is, X5 and X2 are selected as the left and right boundary values of the optimal region in the X-axis direction.
[0046] Based on this, two Y coordinate values located at the center position in the Y coordinate sequence are selected as the upper and lower boundary values of the optimal region in the Y-axis direction, that is, Y4 and Y2 are selected as the lower and upper boundary values of the optimal region in the Y-axis direction.
[0047] For example, the lengths of the X-coordinate sequence and the Y-coordinate sequence may be odd, such as the X-coordinate sequence being (X1, X5, X2, X4, X3) and the Y-coordinate sequence being (Y1, Y2, Y3, Y4, Y5).
[0048] Since the center position of the X coordinate sequence is X2, it is necessary to select two adjacent X coordinate values of X2, namely X5 and X4, as the left and right boundary values of the optimal region in the X-axis direction.
[0049] Furthermore, the coordinate value of the center position of the Y coordinate sequence is Y3. Therefore, it is necessary to select two adjacent Y coordinate values of Y3, namely Y2 and Y4, as the lower and upper boundary values of the optimal region in the Y-axis direction.
[0050] As an optional implementation, the above-described method of determining the anchor point of the corresponding macrocell based on boundary values includes: Step S42: Take half of the difference between the right boundary value and the left boundary value of the optimal region in the X-axis direction as the X coordinate of the anchor point, and take half of the difference between the upper boundary value and the lower boundary value of the optimal region in the Y-axis direction as the Y coordinate of the anchor point.
[0051] In this embodiment of the application, once the left and right boundary values of the optimal region in the X-axis direction, and the lower and upper boundary values of the optimal region in the Y-axis direction are determined, the optimal region is thus determined. Figure 2 The "optimum box" shown is the optimal area used to determine the anchor point.
[0052] In an optional embodiment, since the right boundary value in the X-axis direction is larger and the left boundary value in the X-axis direction is smaller, this application uses half of the difference between the right boundary value and the left boundary value in the X-axis direction of the optimal region as the X coordinate of the anchor point, and obtains the X coordinate of the anchor point corresponding to the macrocell as (X2-X5) / 2.
[0053] Furthermore, since the upper boundary value in the Y-axis direction is larger and the lower boundary value in the Y-axis direction is smaller, this application uses half of the difference between the upper and lower boundary values in the Y-axis direction of the optimal region as the Y coordinate of the anchor point, thus obtaining the Y coordinate of the anchor point corresponding to the macrocell as (Y2-Y4) / 2.
[0054] As an optional implementation, this application preferably sets the optimal region as a rectangle. In practical applications, the shape of the optimal region can be adaptively adjusted according to the coordinate distribution characteristics of other design units connected to the macro unit. This application does not impose any limitation on the specific shape of the optimal region.
[0055] In this way, the anchor point of the macrocell is determined by the coordinate distribution of other design units directly connected to it, avoiding the influence of global layout fluctuations on the anchor point determination, and making the anchor point more in line with the actual timing requirements of the macrocell.
[0056] Step S5: Minimize the distance between the candidate placement position of each macrocell and the corresponding anchor point to determine the legal placement position of each macrocell on the FPGA chip.
[0057] As an optional implementation, minimizing the distance between the candidate placement location of each macrocell and its corresponding anchor point to determine the legal placement location of each macrocell on the FPGA chip includes: With the optimization objective of minimizing the distance between the candidate placement position of the macrocell and the corresponding anchor point, the legal placement position is determined from the candidate placement position set of the FPGA chip by means of simulated annealing algorithm, and the coordinate position of the macrocell is updated to the corresponding legal placement position.
[0058] As an optional implementation, the termination condition of the above simulated annealing algorithm is to reach the set maximum number of iterations, or the change in the distance from the candidate placement position of the macrocell to the anchor point is less than a preset threshold in a consecutive preset number of iterations.
[0059] In the embodiments of this application, the simulated annealing (SA) algorithm is preferably used to minimize the distance between the candidate placement position of each macrocell and the corresponding anchor point. The simulated annealing algorithm is a stochastic optimization algorithm derived from the physical annealing process. In this application, minimizing the distance between the candidate placement position of the macrocell and the corresponding anchor point is taken as the optimization objective of the simulated annealing algorithm.
[0060] In an optional embodiment, the candidate placement location set refers to the set of physically allowed placement locations on the FPGA chip that conform to the physical size of the macrocell and do not conflict with other macrocells or other design units. This application minimizes the distance between the candidate placement locations of the macrocell and the corresponding anchor points through a simulated annealing algorithm, so that the legal placement location of the macrocell on the FPGA chip that is finally determined can both meet the physical location constraints of the FPGA chip and minimize the distance to the corresponding anchor point.
[0061] Specifically, this application first assigns an initial solution to the current macrocell. This initial solution should satisfy the set of candidate placement positions corresponding to the macrocell. Then, in each iteration, a perturbation is performed randomly, such as moving a macrocell to another candidate placement position, in order to perturb the current solution and generate a new solution. The algorithm stops when the number of iterations reaches the set maximum number of iterations, or when the change in the distance from the candidate placement position to the anchor point of the corresponding macrocell is less than a preset threshold in a consecutive preset number of iterations. The final legal placement position is then output, and the coordinate position of the macrocell is updated to the corresponding legal placement position output, thus completing the legalization of the current macrocell.
[0062] It should be noted that the simulated annealing algorithm is a widely used optimization algorithm in the field of FPGA chip layout. Its specific implementation steps and working principle are existing technologies well known to those skilled in the art. This application does not improve the simulated annealing algorithm itself, but rather combines the simulated annealing algorithm with the determination of macrocell anchor points. Therefore, the simulated annealing algorithm will not be described in further detail here.
[0063] In addition to the simulated annealing algorithm, other optimization algorithms that can minimize the distance between the candidate placement position of each macrocell and the corresponding anchor point, and determine the legal placement position of each macrocell on the FPGA chip, are also feasible and should be known by those skilled in the art.
[0064] The macrocell legalization method for FPGA chips provided in this application obtains the initial positions of macrocells and other design units through global layout, providing a basic coordinate reference for subsequent anchor point calculation. Instead of directly using the macrocell coordinates of the global layout as anchor points, it extracts the coordinate positions of other design units directly connected to each macrocell. By using the coordinate positions of all other design units connected to each macrocell, the optimal region and anchor point of the macrocell are determined, avoiding the limitations of global layout in determining macrocell anchor points. Finally, the legal placement position of the macrocell is determined by minimizing the distance between the candidate placement position of the macrocell and the anchor point. This not only reduces the deviation between the legalized macrocell position and the anchor point, but also ensures that the legal placement position conforms to the physical constraints of the FPGA chip, effectively optimizing the placement timing performance of the FPGA chip.
[0065] Based on the above-described macrocell legalization method for FPGA chips, this application also provides a macrocell legalization system for FPGA chips. Please refer to... Figure 5 This is a block diagram of a macrocell legalization system for FPGA chips provided in an embodiment of this application. The macrocell legalization system includes: Placement cells are used to perform global placement of the FPGA design netlist and determine the initial positions of macro cells and other design cells in the global placement coordinate system. The acquisition unit is used to acquire the coordinate positions of other design units directly connected to each of the macro units in the global layout coordinate system. A sorting unit is used to sort the coordinate positions of all other design units connected to each macro unit along the X-axis and Y-axis directions respectively, to obtain the X-coordinate sequence and Y-coordinate sequence corresponding to each macro unit; An anchor point determination unit is used to determine the boundary value of the optimal region based on the X coordinate sequence and the Y coordinate sequence, and to determine the anchor point of the corresponding macro unit according to the boundary value; A simulation unit is used to minimize the distance between the candidate placement position of each macrocell and the corresponding anchor point in order to determine the legal placement position of each macrocell on the FPGA chip.
[0066] For other details regarding the implementation techniques of each unit in the macro-unit legalization system provided in the above embodiments, please refer to the description in the macro-unit legalization method in the above embodiments, which will not be repeated here.
[0067] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system-type embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.
[0068] Please refer to Figure 6 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. The computer device 60 includes a processor 61 and a memory 62 coupled to the processor 61.
[0069] The memory 62 stores a calculation program. When the computer program is executed by the processor 61, the processor 61 performs the steps of the comprehensive testing method for the SSD system disk in the above embodiment.
[0070] The processor 61 can also be referred to as a CPU (Central Processing Unit). The processor 61 may be an integrated circuit chip with signal processing capabilities. The processor 61 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor can be a microprocessor or any conventional processor.
[0071] Please refer to Figure 7This is a schematic diagram of the structure of the storage medium provided in the embodiments of this application. The computer-readable storage medium of this application embodiment stores a computer program 70. The computer program 70 is executed by a processor to implement the artificial intelligence-based actuarial analysis method in the above embodiments. The computer program 70 can be stored in the above storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media that can store program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, or computer devices such as computers, servers, mobile phones, and tablets. The server can be an independent server or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms.
[0072] It should be noted that, in the several embodiments provided in this application, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed between each other can be through some interfaces, or indirect coupling or communication connection between devices or units, and can be electrical, mechanical, or other forms.
[0073] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.
[0074] For example, for various devices and products applied to or integrated into chips, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into chip modules, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The unit can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, all of their modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.
[0075] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0076] The above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this application; however, the embodiments of this application are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this application, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this application.
Claims
1. A method for macrocell legalization in FPGA chips, characterized in that, Includes the following steps: Perform global placement of the FPGA design netlist to determine the initial positions of macrocells and other design cells in the global placement coordinate system; Obtain the coordinate positions of other design units directly connected to each of the macro units in the global layout coordinate system; The coordinate positions of all other design units connected to each macro unit are sorted along the X-axis and Y-axis directions respectively to obtain the X-coordinate sequence and Y-coordinate sequence corresponding to each macro unit; The boundary values of the optimal region are determined based on the X-coordinate sequence and the Y-coordinate sequence, and the anchor points of the corresponding macrocells are determined based on the boundary values. Minimize the distance between the candidate placement location of each macrocell and its corresponding anchor point to determine the legal placement location of each macrocell on the FPGA chip.
2. The macrocell legalization method for FPGA chips as described in claim 1, characterized in that, The step of sorting the coordinate positions of all other design units connected to each macrocell along the X-axis and Y-axis respectively to obtain the X-coordinate sequence and Y-coordinate sequence corresponding to each macrocell includes: Extract the corresponding X and Y coordinate values from the coordinate positions of all other design units connected to each macrocell; Sort all the X coordinate values in ascending order to obtain the X coordinate sequence corresponding to the macrounit; Furthermore, all the Y-coordinate values are sorted in ascending order to obtain the Y-coordinate sequence corresponding to the macrounit.
3. The macrocell legalization method for FPGA chips as described in claim 1, characterized in that, The determination of the boundary values of the optimal region based on the X-coordinate sequence and the Y-coordinate sequence includes: When the length of the coordinate sequence is even, the two X coordinate values located at the center position in the X coordinate sequence are used as the left and right boundary values of the optimal region in the X-axis direction, and the two Y coordinate values located at the center position in the Y coordinate sequence are used as the lower and upper boundary values of the optimal region in the Y-axis direction. When the length of the coordinate sequence is odd, the two X coordinate values adjacent to the center position of the X coordinate sequence are used as the left and right boundary values of the optimal region in the X-axis direction, and the two Y coordinate values adjacent to the center position of the Y coordinate sequence are used as the lower and upper boundary values of the optimal region in the Y-axis direction.
4. The macrocell legalization method for FPGA chips as described in claim 3, characterized in that, The step of determining the anchor point of the corresponding macrocell based on the boundary value includes: The X-coordinate of the anchor point is half the difference between the right and left boundary values of the optimal region in the X-axis direction, and the Y-coordinate of the anchor point is half the difference between the upper and lower boundary values of the optimal region in the Y-axis direction.
5. The macrocell legalization method for FPGA chips as described in claim 1, characterized in that, Minimizing the distance between the candidate placement location of each macrocell and its corresponding anchor point to determine the legal placement location of each macrocell on the FPGA chip includes: With the optimization objective of minimizing the distance between the candidate placement position of the macrocell and the corresponding anchor point, the legal placement position is determined from the candidate placement position set of the FPGA chip by means of simulated annealing algorithm, and the coordinate position of the macrocell is updated to the corresponding legal placement position.
6. The macrocell legalization method for FPGA chips as described in claim 5, characterized in that, The termination condition of the simulated annealing algorithm is to reach the set maximum number of iterations, or the change in the distance from the candidate placement position of the macrocell to the anchor point is less than a preset threshold in a consecutive preset number of iterations.
7. The macrocell legalization method for FPGA chips as described in any one of claims 1-6, characterized in that, The optimal region is a rectangle.
8. A macrocell legitimization system for FPGA chips, characterized in that, include: The placement unit is used to perform global placement of the FPGA design netlist and determine the initial positions of macro cells and other design units in the global placement coordinate system. The acquisition unit is used to acquire the coordinate positions of other design units directly connected to each of the macro units in the global layout coordinate system. A sorting unit is used to sort the coordinate positions of all other design units connected to each macro unit along the X-axis and Y-axis directions respectively, to obtain the X-coordinate sequence and Y-coordinate sequence corresponding to each macro unit; An anchor point determination unit is used to determine the boundary value of the optimal region based on the X coordinate sequence and the Y coordinate sequence, and to determine the anchor point of the corresponding macro unit according to the boundary value; A simulation unit is used to minimize the distance between the candidate placement position of each macrocell and the corresponding anchor point in order to determine the legal placement position of each macrocell on the FPGA chip.
9. A computer device, characterized in that, The computer device includes a processor and a memory coupled to the processor, the memory storing a calculation program that, when executed by the processor, causes the processor to perform the steps of the macrocell legalization method for an FPGA chip as described in any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that is executed by a processor to implement the macrocell legalization method for an FPGA chip as described in any one of claims 1-7.