Area array transducer and preparation method

Abstract

The invention belongs to the technical field of ultrasonic instruments, and provides an area array transducer and a preparation method. The area array transducer comprises a piezoelectric wafer, an anisotropic conductive backing and an integrated circuit chip, the anisotropic conductive backing is arranged below the piezoelectric wafer, the anisotropic conductive backing comprises an insulating substrate and conductors, and the conductors are uniformly distributed in the insulating substrate; the conductor is columnar and is vertically arranged, and the top and the bottom of the conductor penetrate through the insulating substrate; the integrated circuit chip is disposed under the anisotropic conductive backing. According to the area array transducer, the piezoelectric wafer and the integrated circuit chip are arranged on the upper surface and the lower surface of the anisotropic conductive backing respectively, the anisotropic conductive backing serves as a complex of the acoustic sound absorption layer and the electrical interconnection layer, a traditional layered structure is broken through, the piezoelectric wafer and the anisotropic conductive backing are directly connected, and a good sound absorption effect can be achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of ultrasonic instruments, and in particular to a planar array transducer and a preparation method thereof. Background Art

[0002] The general composition of a surface array transducer includes an acoustically transparent layer, an acoustic matching layer, a piezoelectric array, an application-specific integrated circuit (ASIC), and a backing layer; the backing layer is closely attached to the rear end of the piezoelectric array, playing a good sound absorption role and reducing the interference of the ultrasonic signal at the acoustic rear end of the piezoelectric array.

[0003] For area array transducers, the piezoelectric array needs to be electrically connected to the application-specific integrated circuit (ASIC). If the backing layer is placed behind the ASIC, it will be difficult for the backing layer to effectively absorb sound. At the same time, the direct connection between the ASIC and the piezoelectric array places extremely high process requirements on the cutting of the piezoelectric array. The main defects of current area array transducers include the following: (1) The backing layer of existing area array transducers is usually located at the back end of the ASIC, resulting in limited sound absorption performance (the sound wave reflectivity increases by ≥15%); (2) When the ASIC is directly electrically connected to the piezoelectric array, the cutting process tolerance is very strict (the cutting accuracy must be controlled within ±5μm), which can easily damage the ASIC chip; (3) The traditional backing and ASIC layered structure results in an increase in device thickness (overall thickness ≥ 1.5 mm), which makes it difficult to meet miniaturization requirements.

[0004] (4) Low processing efficiency of micro-hole arrays: Thousands of array elements need to be mechanically drilled or molded, the processing time for a single piece exceeds 8 hours, and the yield rate is less than 60%. Summary of the Invention

[0005] In response to the defects in the existing technology, the present invention provides a planar array transducer based on anisotropic conductive backing and a preparation method to solve the problem that the current planar array transducer places the backing layer at the back end of the integrated circuit, making it difficult for the backing layer to play a good sound absorption role and at the same time not conducive to the subsequent cutting of the piezoelectric array.

[0006] In a first aspect, the present invention provides an area array transducer, comprising: A piezoelectric chip, wherein an array element is provided on the piezoelectric chip; An anisotropic conductive backing is disposed under the piezoelectric wafer; the anisotropic conductive backing comprises an insulating substrate and a conductor, the conductor being uniformly distributed in the insulating substrate; the conductor is columnar and vertically disposed, with the top and bottom of the conductor penetrating the insulating substrate; The integrated circuit chip is arranged under the anisotropic conductive backing.

[0007] As can be seen from the above technical solution, the piezoelectric chip and the integrated circuit chip of the area array transducer provided by the present invention are respectively arranged on the upper and lower surfaces of the anisotropic conductive backing. The anisotropic conductive backing serves as a composite of an acoustic sound absorption layer and an electrical interconnection layer, breaking through the traditional layered structure. The piezoelectric chip and the anisotropic conductive backing are directly connected, which can play a better sound absorption role. At the same time, the anisotropic conductive backing also serves as a buffer layer between the piezoelectric chip and the integrated circuit chip, protecting the integrated circuit from damage during the cutting process of the piezoelectric array.

[0008] Optionally, the difference in sound velocity Δv between the conductor and the insulating substrate is less than 50 m / s, and the difference in acoustic impedance ΔZ is less than 2MRayl.

[0009] Optionally, the conductor is formed by mixing and curing silver powder, epoxy resin, and aluminum oxide powder in a mass ratio of (65-75):(20-25):(5-10).

[0010] Optionally, the insulating substrate is formed by mixing and curing epoxy resin, tungsten powder, and hollow glass microspheres in a volume ratio of (30-35): (50-60): (5-10).

[0011] Optionally, array elements are provided on the piezoelectric wafer, and the conductors are provided corresponding to the array elements; the conductors are cylindrical and have a diameter of 5-10 μm.

[0012] It can be seen from the above technical solution that the larger the diameter of the conductor, the better the conductivity. However, the larger the diameter of the conductor, the higher the consistency, which is not conducive to preparation. Therefore, the diameter of the conductor is set to 5-10μm to achieve a balance between conductivity and production cost.

[0013] In a second aspect, the present invention provides a method for preparing an area array transducer, which is used to prepare the area array transducer according to any possible implementation of the first aspect, comprising: S1. The insulating substrate slurry is mixed and cured to form an insulating substrate; S2. forming a microwell array on an insulating substrate by etching with a DRIE process; S3. The conductive slurry is poured into the microporous array according to the gradient pressure, sintered at a low temperature, and solidified to form a backing structure; S4. The upper and lower surfaces of the backing structure are polished to form the anisotropic conductive backing; S5. bonding the piezoelectric wafer to the upper surface of the anisotropic conductive backing; S6. Disposing the integrated circuit chip on the lower surface of the anisotropic conductive backing.

[0014] It can be seen from the above technical solution that the preparation method of the area array transducer provided by the present invention first uses deep reactive ion etching to form a micropore array on an insulating substrate, thereby improving the efficiency of single processing; then, a conductive slurry is poured into the micropore array by gradient pressure infusion to form a conductor, thereby ensuring the porosity of the conductor and achieving complete filling of the conductor slurry in the micropore array; and the conductor slurry is solidified by a low-temperature sintering process to reduce the resistivity of the conductor.

[0015] Optionally, the method for forming the microwell array comprises: polishing the upper surface of the insulating substrate to form a sputtering layer; coating a photoresist on the upper surface of the sputtering layer, and then performing photolithography to form a pattern; Electroplating is performed according to an electroplating pattern to form an electroplating layer, and then the photoresist is removed; The microwell array is formed by etching.

[0016] Optionally, the gradient pressure perfusion includes: Pretreatment period: ≤10 -3 Pre-treating the micropore array and the conductive slurry under Pa-level vacuum to remove surface adsorbed gas and dissolved gas in the slurry; Low pressure osmotic period: maintain 10 -2 Pa-level vacuum accelerates the formation of gas overflow channels; High-pressure densification period: pulse vacuum is intermittently activated at 2.5-3 MPa to forcibly dissolve residual microbubbles; Pressure curing period: 10 -3 Pa-level vacuum ensures that there is no gas interlayer at the interface.

[0017] It can be seen from the above technical solution that by pouring conductive slurry into the micropore array through gradient pressure pouring to form a conductor, the pouring effect of the conductor slurry can be improved and the resistivity can be reduced.

[0018] Optionally, the pretreatment period is 10-30 minutes, the low-pressure infiltration period is 5-15 minutes, the high-pressure densification period is 3-10 minutes, and the pressure-maintaining curing period is 10-30 seconds.

[0019] Optionally, the low-temperature sintering temperature is 120-150° C., and the sintering time is 1 hour.

[0020] By adopting the above technical solution, this application has the following beneficial effects: In the area array transducer provided by the present invention, the piezoelectric wafer and the integrated circuit chip are respectively arranged on the upper and lower surfaces of an anisotropic conductive backing. The anisotropic conductive backing serves as a composite of an acoustic sound absorption layer and an electrical interconnection layer, breaking through the traditional layered structure. The piezoelectric wafer and the anisotropic conductive backing are directly connected, which can provide a good sound absorption effect. At the same time, the anisotropic conductive backing also serves as a buffer layer between the piezoelectric wafer and the integrated circuit chip, protecting the integrated circuit from damage during the cutting process of the piezoelectric array. The preparation method of the area array transducer provided by the present invention first uses deep reactive ion etching to form a micropore array on an insulating substrate, thereby improving the efficiency of single processing; then, a conductive paste is poured into the micropore array by gradient pressure infusion to form a conductor, thereby ensuring the porosity of the conductor and achieving complete filling of the conductor paste in the micropore array; and the conductor paste is solidified by a low-temperature sintering process to reduce the resistivity of the conductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly describes the drawings required for the specific embodiments or the description of the prior art. Similar elements or parts are generally identified by similar reference numerals throughout the drawings. Elements or parts in the drawings are not necessarily drawn to scale.

[0022] Figure 1 A schematic diagram of an area array transducer provided by an embodiment of the present invention is shown; Figure 2 A schematic diagram showing a product obtained in step S201 in the method for preparing an area array transducer provided in an embodiment of the present invention is shown; Figure 3 A schematic diagram showing a product obtained in step S202 of the method for preparing an area array transducer provided in an embodiment of the present invention is shown; Figure 4 A schematic diagram showing a product obtained in step S203 in the method for preparing an area array transducer provided in an embodiment of the present invention is shown; Figure 5 A schematic diagram showing a product obtained in step S204 in the method for preparing an area array transducer provided in an embodiment of the present invention is shown; Figure 6 A schematic diagram showing a product obtained in step S3 of the method for preparing an area array transducer provided in an embodiment of the present invention is shown; Figure 7 A schematic diagram of a product obtained in step S4 of the method for preparing an area array transducer provided in an embodiment of the present invention is shown.

[0023] Reference numerals: 1-piezoelectric wafer; 2-anisotropic conductive backing; 21-insulating substrate; 22-conductor; 3-integrated circuit chip; 4-sputtering layer; 5-photoresist; 6-electroplating layer; 7-microwell array. DETAILED DESCRIPTION

[0024] The following embodiments of the technical solution of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention and are therefore only examples and are not intended to limit the scope of protection of the present invention.

[0025] It should be noted that, unless otherwise specified, the technical or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0026] Example 1 like Figure 1 As shown, this embodiment provides a planar array transducer, including a piezoelectric chip 1, an anisotropic conductive backing 2 and an integrated circuit chip 3; the anisotropic conductive backing 2 is arranged under the piezoelectric chip 1; the anisotropic conductive backing 2 includes an insulating substrate 21 and a conductor 22, and the conductor 22 is uniformly distributed in the insulating substrate 21; the conductor 22 is columnar and vertically arranged, and the top and bottom of the conductor 22 are respectively arranged to pass through the upper surface and the lower surface of the insulating substrate 21; the integrated circuit chip 3 is arranged under the anisotropic conductive backing 2.

[0027] The conductor 22 is formed by curing a mixture of silver powder, epoxy resin, and alumina powder in a mass ratio of (65-75):(20-25):(5-10). The insulating substrate 21 is formed by curing a mixture of epoxy resin, tungsten powder, and hollow glass microspheres in a volume ratio of (30-35):(50-60):(5-10). The difference in acoustic velocity Δv between the conductor 22 and the insulating substrate 21 is less than 50 m / s, and the difference in acoustic impedance ΔZ is less than 2MRayl, reducing acoustic transmission loss by over 40%.

[0028] In one specific embodiment, the conductor 22 is formed by curing a mixture of silver powder, epoxy resin, and alumina powder in a mass ratio of 75:20:5. The insulating substrate 21 is formed by curing a mixture of epoxy resin, tungsten powder, and hollow glass microspheres in a volume ratio of 35:60:5. The resulting insulating substrate 21 has an acoustic impedance of 5.5 MRayl, and the resulting conductor 22 has an acoustic impedance of 6 MRayl.

[0029] Currently, the acoustic impedance of the backing layer of an ultrasonic probe is generally 3-10 MRayl, where impedance Z = sound velocity * density. By adjusting the ratio of the above materials, the sound velocity and density of the material can be changed to achieve the purpose of changing the impedance.

[0030] Specifically, the particle size of the tungsten powder is 1-3 μm, and the diameter of the hollow glass microspheres is 30-80 μm.

[0031] By adopting the technical solution of this embodiment, an anisotropic conductive backing 2 is arranged between the piezoelectric chip 1 and the integrated circuit chip 3, and vertical conductivity and lateral insulation are achieved by the conductor 22 passing through the insulating substrate 21. While achieving the sound absorption effect of the backing for the piezoelectric chip 1, the anisotropic conductive backing 2 also serves as a buffer layer between the piezoelectric chip 1 and the integrated circuit chip 3, protecting the integrated circuit from damage during the cutting process of the piezoelectric array.

[0032] Example 2 This embodiment provides a method for preparing the area array transducer provided in Example 1, comprising: S1. Mix and solidify the insulating substrate slurry to form an insulating substrate 21; the initial thickness of the insulating substrate 21 is 0.1-0.2 mm.

[0033] S2. A microhole array 7 is formed on the insulating substrate 21 through a DRIE process, which increases the single-shot processing efficiency by 5 times. The holes formed by the microhole array 7 are circular holes. The diameter is determined by the bump size of the integrated circuit chip. The depth affects the height of the conductor and the thickness of the insulating substrate remaining after polishing. It is determined according to the acoustic attenuation requirements of the anisotropic conductive backing.

[0034] Specifically, the method for forming the micropore array 7 in step S2 includes: S201. Figure 2 As shown, the upper surface of the insulating substrate 21 is polished and a sputtered layer 4 is formed. Cr is first sputtered as an adhesion layer, followed by Au; the sputtered Cr is 20-50nm, and the sputtered Au is 150-300nm. The purpose of sputtering is to provide a conductive medium for the subsequent electroplating step.

[0035] S202. Figure 3 As shown, a photoresist 5 is coated on the upper surface of the sputtered layer 4 and then patterned by photolithography. The photoresist 5 forms a thick film with a thickness of 7-10 μm.

[0036] S203. Figure 4 As shown, electroplating is performed according to the plating pattern to form the plating layer 6, and then the photoresist is removed.

[0037] S204. Figure 5 As shown, a micropore array 7 is formed by etching; the etching rate is 4 μm / min, and the SF6 / O2 gas ratio is 3:1.

[0038] S3. Figure 6As shown, the conductive paste is poured into the micropore array 7 according to the gradient pressure to achieve complete filling of the conductive paste in the micropores, with a porosity of less than 0.5%; and low-temperature sintering is performed to form a backing matrix. The low-temperature sintering temperature is 120-150°C and the time is 1 hour, so that the resistivity of the conductor is reduced to 10 -6 Ω·m order of magnitude.

[0039] The gradient pressure perfusion specifically includes the following steps: Pretreatment period: vacuum environment (≤10 -3 The micropore array 7 and the conductive slurry are pretreated at 400 Pa to remove the surface adsorbed gas and the dissolved gas in the slurry, thereby creating an environment without initial gas interference for subsequent pressurization.

[0040] Low pressure osmotic period: maintain 10 -2 Pa-level vacuum accelerates the formation of gas overflow channels; low pressure is used to push the slurry to initially wet the pore wall and establish a continuous flow path.

[0041] High-pressure densification period: pulse vacuum is intermittently activated at 2.5-3 MPa (e.g. 1-3 times per second) to forcibly dissolve the remaining microbubbles; the volume of the bubbles is compressed by high pressure, and the air-slurry separation is achieved by vacuum suction to ensure the quality of the conductor. -3 Grade 1 vacuum is difficult to achieve, and the vacuum is continuously pumped intermittently during high pressure densification until the vacuum reaches 10 -3 Level, it enters the pressure holding and curing period.

[0042] Pressure curing period: Apply ultimate vacuum before curing (10 -3 Pa) for 10-30 seconds to ensure that there is no gas interlayer at the interface; maintain pressure to prevent slurry from shrinking.

[0043] S4. Figure 7 As shown, both the upper surface and the lower surface of the backing substrate are polished to form an anisotropic conductive backing 2 .

[0044] Specifically, the thickness of the anisotropic conductive backing 2 is 500 μm, and the vertically arranged conductors 22 enable only vertical conductivity, while the lateral electrodes are insulated. The anisotropic conductive backing 2 also has the function of absorbing ultrasonic signals directed backward from the piezoelectric wafer 1 .

[0045] See also Figure 6 The portion removed by grinding includes the remaining electroplating layer 6, the sputtering layer 4 and the portion of the insulating substrate 21 that is not etched through the bottom of the microhole array 7.

[0046] S5. Bond a PZT-5H piezoelectric wafer 1 (thickness 200 μm) to the upper surface of the anisotropic conductive backing.

[0047] S6. The integrated circuit chip 3 is placed on the lower surface of the anisotropic conductive backing 2, and can be interconnected with the bottom of the conductor 22 by a flip-chip bonding process. Figure 1 As shown, the overall package thickness of the area array transducer is controlled at 0.8 mm.

[0048] Table 1

[0049] Table 1 shows the performance and process parameters of the area array transducer produced using the method for producing an area array transducer provided in this embodiment. It can be seen that the method provided in this embodiment reduces the interference of ultrasonic signals at the acoustic backend of the piezoelectric chip 1, while also reducing the overall package size of the area array transducer. It also simplifies the subsequent process requirements for the piezoelectric array, and protects the integrated circuit chip from damage when cutting the piezoelectric array.

[0050] The above embodiments are merely provided to provide a detailed description of the technical solutions of the present application. However, the descriptions of the above embodiments are intended only to facilitate understanding of the methods of the embodiments of the present invention and should not be construed as limiting the embodiments of the present invention. Any changes or substitutions that can be readily conceived by a person skilled in the art should fall within the scope of protection of the embodiments of the present invention.

Claims

1. A planar array transducer, characterized in that: include: Piezoelectric chips; An anisotropic conductive backing, disposed below the piezoelectric wafer; The anisotropic conductive backing comprises an insulating substrate and a conductor, wherein the conductor is evenly distributed in the insulating substrate; the conductor is vertically arranged, and the top and bottom of the conductor are respectively arranged to pass through the upper surface and the lower surface of the insulating substrate; The integrated circuit chip is arranged under the anisotropic conductive backing.

2. The area array transducer according to claim 1, characterized in that: The difference in acoustic velocity Δv between the conductor and the insulating substrate is less than 50 m / s, and the difference in acoustic impedance ΔZ is less than 2 MRayl.

3. The area array transducer according to claim 2, characterized in that: The conductor is formed by mixing and curing silver powder, epoxy resin and aluminum oxide powder in a mass ratio of (65-75): (20-25): (5-10).

4. The area array transducer according to claim 3, characterized in that: The insulating substrate is formed by mixing and curing epoxy resin, tungsten powder and hollow glass microspheres in a volume ratio of (30-35): (50-60): (5-10).

5. The area array transducer according to claim 3, characterized in that: Array elements are arranged on the piezoelectric wafer, and the conductors are arranged corresponding to the array elements; the conductors are cylindrical and have a diameter of 5-10 μm.

6. A method for preparing the area array transducer according to any one of claims 1 to 5, characterized in that: include: S1. The insulating substrate slurry is mixed and cured to form an insulating substrate; S2. forming a microwell array on an insulating substrate by etching with a DRIE process; S3. The conductive slurry is poured into the microporous array according to the gradient pressure, sintered at a low temperature, and solidified to form a backing structure; S4. The upper and lower surfaces of the backing structure are polished to form the anisotropic conductive backing; S5. bonding the piezoelectric wafer to the upper surface of the anisotropic conductive backing; S6. Disposing the integrated circuit chip on the lower surface of the anisotropic conductive backing.

7. The method according to claim 6, characterized in that The method for forming the microwell array comprises: polishing the upper surface of the insulating substrate to form a sputtering layer; coating a photoresist on the upper surface of the sputtering layer, and then performing photolithography to form a pattern; Electroplating is performed according to an electroplating pattern to form an electroplating layer, and then the photoresist is removed; The microwell array is formed by etching.

8. The method according to claim 6, wherein the gradient pressure perfusion comprises: Pretreatment period: ≤10 -3 Pre-treating the micropore array and the conductive slurry under Pa-level vacuum to remove surface adsorbed gas and dissolved gas in the slurry; Low pressure osmotic period: maintain 10 -2 Pa-level vacuum accelerates the formation of gas overflow channels; High-pressure densification period: pulse vacuum is intermittently activated at 2.5-3 MPa to forcibly dissolve residual microbubbles; Pressure curing period: 10 -3 Pa-level vacuum ensures that there is no gas interlayer at the interface.

9. The method according to claim 8, characterized in that The pretreatment period is 10-30 minutes, the low-pressure infiltration period is 5-15 minutes, the high-pressure densification period is 3-10 minutes, and the pressure-maintaining curing period is 10-30 seconds.

10. The method according to claim 6, characterized in that The temperature of low-temperature sintering is 120-150°C, and the sintering time is 1 hour.

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