Preparation method of patterned thin film structure

Abstract

The invention provides a preparation method of a patterned thin film structure, and relates to the field of micro device preparation. According to the method, the first dielectric layer and the photoresist pattern are etched at the same etching rate, so that the first dielectric layer is etched to form the target pattern, the target pattern is the same as the photoresist pattern, and after etching is completed, the notch is formed in the bottom of the side wall of the target pattern. The method comprises the following steps of: depositing a first dielectric layer on a substrate, depositing a second dielectric layer on the first dielectric layer, backfilling a gap by utilizing a filling part of the second dielectric layer, covering the filling part on the second dielectric layer to form a covering part, and etching off the redundant second dielectric layer by adopting an etching mode, namely etching off the covering part. And by adopting a backfilling and re-etching mode, the gap can be effectively repaired, so that the complete morphology of the target pattern is formed.

Description

Technical Field

[0001] The present invention relates to the field of micro-device preparation, and in particular to a method for preparing a patterned thin film structure. Background Art

[0002] When processing MEMS devices, there are special requirements for the morphology obtained after the film layer is patterned. For example, the special morphology of non-equal height structures requires a 1:1 etching method with an etching rate of 1:1 to transfer the photoresist pattern to the etched material. Since the dielectric layer is mostly an insulator with poor conductivity, the secondary electrons generated during the etching process are not easily conducted and are more likely to accumulate charges at locations such as the sidewalls of the pattern, thereby generating a local electric field, causing ion deflection, and increasing the ion concentration at the corners of the sidewalls of the pattern, thereby forming microgrooves. In the actual process, the solution of selecting an etching rate of 1:1 greatly limits the adjustable space of the etching process. It is very difficult to meet the special morphology requirements and eliminate the gaps by controlling the etching process parameters. Therefore, it is urgent to design a technical solution that can eliminate the gaps while meeting the special morphology requirements. Summary of the Invention

[0003] One object of the present invention is to provide a method for preparing a patterned thin film structure to solve the technical problem in the prior art that the gap cannot be eliminated under special etching conditions.

[0004] In particular, the present invention provides a method for preparing a patterned thin film structure, comprising the following steps:

[0005] Providing a Si substrate;

[0006] Depositing an etch stop layer and a first dielectric layer in sequence on the Si substrate;

[0007] Coating a photoresist on the first dielectric layer and forming a photoresist pattern by a photolithography process, wherein the photoresist pattern is a non-contour pattern;

[0008] Using the photoresist pattern as a mask, etching the photoresist pattern and the first dielectric layer to etch the first dielectric layer into a target pattern, wherein the target pattern is identical to the photoresist pattern, a notch is formed at the bottom of the sidewall of the target pattern, and the etching rates of the photoresist pattern and the first dielectric layer are the same;

[0009] Depositing a second dielectric layer on the first dielectric layer, the second dielectric layer comprising a filling portion and a covering portion, the filling portion filling the gap, and the covering portion covering the first dielectric layer;

[0010] The covering portion of the second dielectric layer is etched to obtain the patterned thin film structure.

[0011] Optionally, the thickness of the second dielectric layer accounts for 15%-20% of the thickness of the target pattern.

[0012] Optionally, the patterned thin film structure is applied to an optical performance device, and the material of the second dielectric layer is the same as that of the first dielectric layer;

[0013] The material of the first dielectric layer includes any one of silicon oxide, silicon nitride, SOG, and FSG.

[0014] Optionally, the patterned thin film structure is applied to an electrical device, and the material of the second dielectric layer is the same as or different from the material of the first dielectric layer.

[0015] Optionally, when the material of the second dielectric layer is the same as that of the first dielectric layer, the material of the first dielectric layer includes any one of silicon oxide, silicon nitride, SOG, and FSG;

[0016] When the material of the first dielectric layer is different from the material of the second dielectric layer, the material of the first dielectric layer is silicon nitride, and the material of the second dielectric layer is silicon oxide.

[0017] Optionally, in the step of etching the covering portion of the second dielectric layer to obtain the patterned thin film structure, an etching selectivity ratio between the covering portion and the first dielectric layer is in a range of 10:1-20:1.

[0018] Optionally, in the step of etching the covering portion of the second dielectric layer to obtain the patterned thin film structure, the etching gas is a mixed gas of C4F8, CO, and Ar or a mixed gas of C4F8, O2, and Ar.

[0019] Optionally, if the first dielectric layer and the second dielectric layer are made of the same material, the step of depositing the second dielectric layer on the first dielectric layer may further include:

[0020] The first dielectric layer is cleaned to remove organic matter and particles.

[0021] Optionally, if the first dielectric layer and the second dielectric layer are made of different materials, the step of depositing the second dielectric layer on the first dielectric layer may further include:

[0022] The first dielectric layer is subjected to plasma treatment using a preset gas, where the preset gas includes either O 2 or Ar.

[0023] Optionally, the step of etching the covering portion of the second dielectric layer to obtain the patterned thin film structure further includes the following steps:

[0024] The temperature is raised to a preset temperature to anneal the patterned thin film structure, wherein the preset temperature is any value between 400° C. and 600° C.

[0025] In the present invention, the first dielectric layer and the photoresist pattern are etched at the same etching rate, thereby etching the first dielectric layer to form a target pattern. The target pattern is the same as the photoresist pattern. After the etching is completed, a gap is formed at the bottom of the sidewall of the target pattern. In the present invention, a second dielectric layer is deposited on the first dielectric layer to address the formed gap. The gap is backfilled with the filling portion of the second dielectric layer and covered on the second dielectric layer to form a covering portion. Thereafter, the excess second dielectric layer is etched away by etching, that is, the covering portion is etched away. The present invention uses the backfilling and re-etching method without changing the original etching conditions to effectively repair the gap, thereby forming a complete target pattern morphology.

[0026] Based on the following detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings, those skilled in the art will become more aware of the above and other objects, advantages and features of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Hereinafter, some specific embodiments of the present invention will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings:

[0028] Figure 1 is a schematic flow chart of a method for preparing a patterned thin film structure according to one embodiment of the present invention;

[0029] Figure 2 is a schematic structural diagram after a photoresist pattern is formed on a first dielectric layer according to one embodiment of the present invention;

[0030] Figure 3 is a schematic structural diagram after etching a portion of the photoresist pattern and the first dielectric layer according to one embodiment of the present invention;

[0031] Figure 4 is a schematic structural diagram after etching of the photoresist pattern and the first dielectric layer according to one embodiment of the present invention;

[0032] Figure 5 is a schematic structural diagram after a second dielectric layer is deposited on a first dielectric layer according to one embodiment of the present invention;

[0033] Figure 6 3 is a schematic structural diagram after etching the covering portion of the second dielectric layer according to an embodiment of the present invention.

[0034] Figure 7 is a schematic flow chart of a method for preparing a patterned thin film structure according to another embodiment of the present invention;

[0035] Figure 8 is a schematic flow chart of a method for preparing a patterned thin film structure according to yet another embodiment of the present invention.

[0036] Reference numerals:

[0037] 100 - patterned thin film structure, 10 - Si substrate, 20 - etching stop layer, 30 - first dielectric layer, 40 - photoresist pattern, 31 - target pattern, 32 - gap, 50 - second dielectric layer, 51 - covering portion, 52 - filling portion. DETAILED DESCRIPTION

[0038] Figure 1 is a schematic flow chart of a method for preparing a patterned thin film structure 100 according to an embodiment of the present invention. Figure 2 is a schematic structural diagram after a photoresist pattern 40 is formed on the first dielectric layer according to one embodiment of the present invention. Figure 3 FIG. 1 is a schematic structural diagram after etching a portion of the photoresist pattern 40 and the first dielectric layer 30 according to an embodiment of the present invention. Figure 4 FIG. 1 is a schematic structural diagram after etching the photoresist pattern 40 and the first dielectric layer 30 according to an embodiment of the present invention. Figure 5 is a schematic structural diagram after a second dielectric layer 50 is deposited on a first dielectric layer 30 according to an embodiment of the present invention. Figure 6 FIG. 1 is a schematic structural diagram of the second dielectric layer 50 after etching the covering portion 51 according to an embodiment of the present invention. Figures 1 to 6 As shown, in a specific embodiment, the method for preparing the patterned thin film structure 100 includes the following steps:

[0039] Step S100, providing a Si substrate 10;

[0040] Step S200 , depositing an etch stop layer 20 and a first dielectric layer 30 in sequence on a Si substrate 10 ;

[0041] Step S300, coating a photoresist on the first dielectric layer 30, and forming a photoresist pattern 40 by a photolithography process, wherein the photoresist pattern 40 is a non-contour pattern;

[0042] Step S400, etching the photoresist pattern 40 and the first dielectric layer 30 using the photoresist pattern 40 as a mask to etch the first dielectric layer 30 into a target pattern 31. The target pattern 31 is identical to the photoresist pattern 40. A notch 32 is formed at the bottom of the sidewall of the target pattern 31. The photoresist pattern 40 and the first dielectric layer 30 are etched at the same rate.

[0043] Step S500 , depositing a second dielectric layer 50 on the first dielectric layer 30 , wherein the second dielectric layer 50 includes a filling portion 52 and a covering portion 51 , wherein the filling portion 52 fills the gap 32 and the covering portion 51 covers the first dielectric layer 30 ;

[0044] In step S600 , the covering portion 51 of the second dielectric layer 50 is etched to obtain a patterned thin film structure 100 .

[0045] In this embodiment, the first dielectric layer 30 and the photoresist pattern 40 are etched at the same etching rate, thereby etching the first dielectric layer 30 to form a target pattern 31. The target pattern 31 is identical to the photoresist pattern 40. After etching, a gap 32 is formed at the bottom of the sidewall of the target pattern 31. To address the gap 32, the present invention deposits a second dielectric layer 50 on the first dielectric layer 30. The gap 32 is backfilled with the filling portion 52 of the second dielectric layer 50, covering the second dielectric layer 50 to form a covering portion 51. The excess second dielectric layer 50 is then etched away, that is, the covering portion 51 is etched away. The present invention uses a backfill and re-etching method without changing the original etching conditions to effectively repair the gap 32, thereby forming a complete target pattern 31. Here, because the photoresist pattern 40 is no longer present when the second dielectric layer 50 is etched, it is no longer subject to the etch selectivity limit, and an etching process that does not form the gap 32 can be used.

[0046] In step S200 , the material of the etch stop layer 20 is Al, AlCu, Ti, TiN, Si or poly.

[0047] In step S300 , the photolithography process may be sequentially performing exposure, development, and thermal reflow processing, or sequentially performing grayscale exposure and development processing, thereby forming a non-contour pattern.

[0048] In some embodiments, the thickness of the second dielectric layer 50 is 15%-20% of the thickness of the target pattern 31 , for example, 15%, 16%, 17%, 18%, 19% or 20%, depending on design requirements.

[0049] In some embodiments, the patterned thin film structure 100 is applied to an optical device, and the material of the second dielectric layer 50 is the same as the material of the first dielectric layer 30. The material of the first dielectric layer 30 includes any one of silicon oxide, silicon nitride, SOG (Spin-On Glass), and FSG (Fluorinated Silicon Dioxide). In other words, if the photoresist pattern 40 is an optically functional pattern, such as a microlens pattern, it is necessary to ensure that the materials of the first dielectric layer 30 and the second dielectric layer 50 are consistent. In other words, it is necessary to ensure that the refractive index of the first dielectric layer 30 and the second dielectric layer 50 are the same, and there is no delamination between the first dielectric layer 30 and the second dielectric layer 50, so as to avoid affecting the function of the optical device.

[0050] In some embodiments, the patterned thin film structure 100 is applied to an electrical performance device, and the material of the second dielectric layer 50 is the same as or different from the material of the first dielectric layer 30. Specifically, when the material of the second dielectric layer 50 is the same as the material of the first dielectric layer 30, the material of the first dielectric layer 30 includes any one of silicon oxide, silicon nitride, SOG, and FSG. For example, when silicon oxide is used, usually during the chemical vapor deposition process, the newly deposited SiO2 will chemically combine with the underlying SiO2 through Si-O-Si bonds to form a continuous integral structure without forming a weak boundary layer. The CVD process, especially HDPCVD, is not affected by the "shadow effect" and can diffuse deep into the gap 32, filling the gap 32 at the bottom of the pattern and effectively repairing the gap 32.

[0051] This embodiment utilizes chemical vapor deposition to improve the ability to fill gaps 32. The silicon oxide is deposited twice, eliminating delamination at the interface. This allows for repairing gaps 32 caused during the non-contour dielectric patterning process. Using a photoresist-free etch-back process for the second dielectric layer 50 eliminates gaps 32 during the etch-back process, resulting in defect-free sidewalls for the resulting non-contour pattern.

[0052] When the material of the first dielectric layer 30 and the material of the second dielectric layer 50 are different, the material of the first dielectric layer 30 is silicon nitride and the material of the second dielectric layer 50 is silicon oxide. It can be understood that if the photoresist pattern 40 is a structural pattern, such as for forming a surface microstructure or a support layer, the selection of different materials for the first dielectric layer 30 and the second dielectric layer 50 will not affect the electrical function. Specifically, if the material of the first dielectric layer 30 is silicon nitride, HDP (High Density Plasma) will be used to fill the silicon oxide later. At this time, only the oxide is filled in to repair the morphology of the gap 32 and retain the target pattern 31 formed by the initial etching of the first dielectric layer 30 through an appropriate etching selectivity. Here, the first dielectric layer 30 and the second dielectric layer 50 can also be made of other different materials, as long as the first dielectric layer 30 and the second dielectric layer 50 are non-conductive and the first dielectric layer 30 and the second dielectric layer 50 do not separate in subsequent processes. The specific selection is based on design requirements.

[0053] In some embodiments, in step S600, the etching selectivity ratio between the covering portion 51 and the first dielectric layer 30 is in the range of 10:1-20:1, for example, 10:1, 11:1, 12:1, 13:1, 14:1, 15:1, 16:1, 17:1, 18:1, 19:1, or 20:1. In one embodiment, the etching rate of the covering portion 51 of the second dielectric layer 50 can be 200 nm / min, and the etching rate of the first dielectric layer 30 can be 20 nm / min. This embodiment selects an appropriate etching selectivity ratio so that excess second dielectric layer 50 can be etched away without destroying the original morphology of the first dielectric layer 30.

[0054] In some embodiments, in step S600, the etching gas is a mixture of C4F8, CO, and Ar, or a mixture of C4F8, O2, and Ar. It can be understood that when performing back etching, the gas formula with a high selectivity of oxide to SiN is a mixture of C4F8, CO, and Ar, or a mixture of C4F8, O2, and Ar.

[0055] Figure 7 FIG. 1 is a schematic flow chart of a method for preparing a patterned thin film structure 100 according to another embodiment of the present invention. Figure 7 As shown, in a preferred embodiment, if the first dielectric layer 30 and the second dielectric layer 50 are made of the same material, then before step S500, the following steps are further included:

[0056] In step S410 , the first dielectric layer 30 is cleaned to remove organic matter and particles.

[0057] This embodiment can prevent organic matter and particles from remaining by cleaning the first dielectric layer 30. That is, before the critical step of depositing the second dielectric layer 50, the surface of the first dielectric layer 30 must be completely clean to avoid residual organic contaminants, which can affect the adhesion between the subsequently deposited second dielectric layer 50 and the first dielectric layer 30, as well as the electrical performance of the ultimately fabricated microdevice.

[0058] Figure 8 FIG. 1 is a schematic flow chart of a method for preparing a patterned thin film structure 100 according to another embodiment of the present invention. Figure 8 As shown, in another embodiment, if the materials of the first dielectric layer 30 and the second dielectric layer 50 are different, then before step S500, the following steps are further included:

[0059] In step S410 ′, the first dielectric layer 30 is subjected to a plasma treatment using a preset gas, where the preset gas includes either O 2 or Ar.

[0060] In this embodiment, when the first dielectric layer 30 and the second dielectric layer 50 are made of different materials, O2 or Ar is used to remove organic residues, thereby increasing the surface energy, increasing the hydrophilicity, and improving the wettability and adhesion of the first dielectric layer 30. It can be understood that when the first dielectric layer 30 and the second dielectric layer 50 are made of the same material, the first dielectric layer 30 only needs to be cleaned normally and plasma treatment is not necessarily required. However, when the first dielectric layer 30 and the second dielectric layer 50 are made of different materials, plasma treatment of the first dielectric layer 30 is required to improve adhesion.

[0061] In some embodiments, if the materials of the first dielectric layer 30 and the second dielectric layer 50 are different, the following steps are further included after step S600:

[0062] In step S700 , the temperature is raised to a preset temperature to anneal the patterned thin film structure 100 . The preset temperature is any value between 400° C. and 600° C.

[0063] Here, the preset temperature may be 400°C, 450°C, 500°C, 550°C, or 600°C.

[0064] This embodiment can improve the interface bonding state and enhance the stability through annealing treatment, which is conducive to the densification and interface reconstruction of the HDP oxide.

[0065] This embodiment addresses the problem of gaps 32 formed after etching the first dielectric layer 30. By depositing the second dielectric layer 50 after etching the first dielectric layer 30, the gaps 32 at the bottom of the sidewalls of the target pattern 31 can be effectively filled, thereby improving the integrity and reliability of the overall structure.

[0066] The performance improvement effect of the patterned thin film structure 100 prepared according to the embodiment of the present invention will be further described below in conjunction with specific embodiments.

[0067] Example 1:

[0068] An AlCu layer and a first dielectric layer 30 are sequentially deposited on a Si substrate 10. A photoresist is coated on the first dielectric layer 30, and a photoresist pattern 40 is formed through exposure, development, and thermal reflow. The photoresist pattern 40 is a non-contoured pattern. The photoresist pattern 40 and the first dielectric layer 30 are then etched using the photoresist pattern 40 as a mask to etch the first dielectric layer 30 into a target pattern 31. The target pattern 31 is identical to the photoresist pattern 40, with a notch 32 formed at the bottom of the sidewall of the target pattern 31. The photoresist pattern 40 and the first dielectric layer 30 have the same etching rate. A second dielectric layer 50 is then deposited on the first dielectric layer 30, with a filling portion 52 of the second dielectric layer 50 filling the notch 32 and a covering portion 51 covering the first dielectric layer 30. Finally, the covering portion 51 is etched to produce a patterned thin film structure 100. The first dielectric layer 30 is a silicon oxide layer, and the second dielectric layer 50 is also a silicon oxide layer. The thickness of the second dielectric layer 50 accounts for 18% of the thickness of the target pattern 31 .

[0069] Example 2:

[0070] The only difference from Example 1 is:

[0071] The first dielectric layer 30 is a silicon nitride layer, and the second dielectric layer 50 is a silicon oxide layer.

[0072] Comparative Example 1:

[0073] The only difference from Example 1 is:

[0074] After the first dielectric layer 30 is etched into the target pattern 31 , a patterned thin film is directly prepared without filling and etching back, that is, without depositing the second dielectric layer 50 .

[0075] Comparative Example 2:

[0076] The only difference from Example 1 is:

[0077] The thickness of the second dielectric layer 50 accounts for 30% of the thickness of the target pattern 31 .

[0078] Comparative Example 3:

[0079] The only difference from Example 1 is:

[0080] The thickness of the second dielectric layer 50 accounts for 8% of the thickness of the target pattern 31 .

[0081] Table 1 is a performance comparison table of Example 1, Example 2, Example 3 and Comparative Example 1.

[0082] Table 1

[0083]

[0084] As can be seen from Table 1, Example 1 uses the same material as the first dielectric layer 30 for backfilling, and the thickness of the second dielectric layer 50 is appropriate, with good adhesion and good interface consistency, which is most conducive to the complete filling of the gap 32 and the improvement of subsequent device performance, and is suitable for applications with high requirements for both electrical and optical performance. Although Example 2 uses different materials, SiN and SiO2 are still good in process compatibility, and the device performance is medium to high. Comparative Example 1 does not fill the gap 32, which is likely to cause structural collapse, subsequent process damage or unstable performance. In Comparative Example 2, the second dielectric layer 50 is too thick to cover. Although the gap 32 can be filled, the back etching is difficult to accurately control due to the excessive thickness of the second dielectric layer 50, which is easy to change the target pattern 31 and the pattern conformality is poor. In Comparative Example 3, the thickness of the second dielectric layer 50 is too thin, resulting in the gap 32 not being completely filled, which will affect the device performance.

[0085] At this point, those skilled in the art will recognize that, although a number of exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications consistent with the principles of the present invention may be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be understood and deemed to cover all such other variations or modifications.

Claims

1. A method for preparing a patterned thin film structure, characterized in that: The following steps are involved: Providing a Si substrate; Depositing an etch stop layer and a first dielectric layer in sequence on the Si substrate; Coating a photoresist on the first dielectric layer and forming a photoresist pattern by a photolithography process, wherein the photoresist pattern is a non-contour pattern; Using the photoresist pattern as a mask, etching the photoresist pattern and the first dielectric layer to etch the first dielectric layer into a target pattern, wherein the target pattern is identical to the photoresist pattern, a notch is formed at the bottom of the sidewall of the target pattern, and the etching rates of the photoresist pattern and the first dielectric layer are the same; Depositing a second dielectric layer on the first dielectric layer, the second dielectric layer comprising a filling portion and a covering portion, the filling portion filling the gap, and the covering portion covering the first dielectric layer; The covering portion of the second dielectric layer is etched to obtain the patterned thin film structure.

2. The preparation method according to claim 1, characterized in that The thickness of the second dielectric layer accounts for 15%-20% of the thickness of the target pattern.

3. The preparation method according to claim 2, characterized in that The patterned thin film structure is applied to optical performance devices, and the material of the second dielectric layer is the same as that of the first dielectric layer; The material of the first dielectric layer includes any one of silicon oxide, silicon nitride, SOG, and FSG.

4. The preparation method according to claim 2, characterized in that The patterned thin film structure is applied to an electrical device, and the material of the second dielectric layer is the same as or different from the material of the first dielectric layer.

5. The preparation method according to claim 4, characterized in that When the material of the second dielectric layer is the same as that of the first dielectric layer, the material of the first dielectric layer includes any one of silicon oxide, silicon nitride, SOG, and FSG; When the material of the first dielectric layer is different from the material of the second dielectric layer, the material of the first dielectric layer is silicon nitride, and the material of the second dielectric layer is silicon oxide.

6. The preparation method according to any one of claims 1 to 5, characterized in that In the step of etching the covering portion of the second dielectric layer to obtain the patterned thin film structure, an etching selectivity ratio between the covering portion and the first dielectric layer is in a range of 10:1-20:

1.

7. The preparation method according to claim 6, characterized in that In the step of etching the covering portion of the second dielectric layer to obtain the patterned thin film structure, the etching gas is a mixed gas of C4F8, CO, and Ar or a mixed gas of C4F8, O2, and Ar.

8. The preparation method according to claim 3 or 4, characterized in that If the first dielectric layer and the second dielectric layer are made of the same material, the step of depositing the second dielectric layer on the first dielectric layer may further include: The first dielectric layer is cleaned to remove organic matter and particles.

9. The preparation method according to claim 4, characterized in that If the materials of the first dielectric layer and the second dielectric layer are different, the step of depositing the second dielectric layer on the first dielectric layer may further include: The first dielectric layer is subjected to plasma treatment using a preset gas, where the preset gas includes either O 2 or Ar.

10. The preparation method according to claim 9, characterized in that The step of etching the covering portion of the second dielectric layer to obtain the patterned thin film structure further includes the following steps: The temperature is raised to a preset temperature to anneal the patterned thin film structure, wherein the preset temperature is any value between 400° C. and 600° C.

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