Electronic device

Abstract

The invention relates to an electronic device. The electronic device comprises a first substrate, a packaging part, a first sensing wafer, a first processing wafer, a second processing wafer and a first colloid, the package is disposed on the first surface of the first substrate and defines a first cavity with the first substrate. One of the first substrate and the packaging piece is provided with a second cavity. The second cavity is provided with a first open end and a first bottom wall which are opposite to each other. The first opening end faces the direction away from the first cavity, and the first bottom wall is located between the first opening end and the first cavity. The first sensing wafer is located in the first cavity. The first sensing wafer is electrically connected to the first processing wafer. The second processing wafer is arranged in the second cavity. The second process wafer is air-isolated from the first cavity. The first colloid is filled in the second cavity and at least covers the second processing wafer.

Description

Technical Field

[0001] The present application relates to the technical field of electronic devices, and in particular to an electronic device. Background Art

[0002] In electronic devices, multiple sensors are often integrated into the same package. However, this approach not only makes it difficult to miniaturize the package, but also places chips with different functions in the same cavity, which can easily cause mutual interference (such as signal interference or thermal effects), thereby reducing the sensing performance of the electronic device. Summary of the Invention

[0003] Based on this, the present invention provides an electronic device that can dispose a sensing chip and a processing chip in different cavities, thereby reducing interference of the processing chip on the sensing chip during operation and achieving better sensing performance.

[0004] An electronic device, comprising:

[0005] A first substrate having a first surface and a second surface opposite to each other, and a through hole penetrating the first substrate and connecting the first surface and the second surface;

[0006] a package disposed on the first surface of the first substrate and defining a first cavity with the first substrate, wherein one of the first substrate and the package has a second cavity, the second cavity having a first open end and a first bottom wall opposite to each other, the first open end facing away from the first cavity, and the first bottom wall located between the first open end and the first cavity;

[0007] a first sensing chip disposed on the first surface of the first substrate, located in the first cavity and covering the through hole, wherein the first sensing chip is electrically connected to the first processing chip;

[0008] a second processing wafer disposed in the second chamber, wherein the second processing wafer is isolated from the air in the first chamber; and

[0009] The first colloid is filled in the second cavity and at least covers the second processing wafer.

[0010] In one embodiment, the first substrate has a second cavity extending from the second surface toward the first surface.

[0011] In one embodiment, a first processing wafer is disposed in the second cavity of the first substrate, adjacent to the second processing wafer, and the first colloid further covers the first processing wafer.

[0012] In one embodiment, the first colloid has a top surface away from the first bottom wall of the second cavity, and the top surface is flush with or does not exceed the second surface of the first substrate.

[0013] In one embodiment, the electronic device further comprises:

[0014] The metal plate is disposed on the top surface of the first colloid, covers the second cavity and is electrically connected to the first substrate. The metal plate has an opening, and the opening exposes a portion of the top surface of the first colloid.

[0015] In one embodiment, the metal plate extends to cover the second surface of the first substrate, and an air gap is formed between the metal plate and the first colloid.

[0016] In one embodiment, a surface of the metal plate that is relatively far away from the top surface of the first colloid is flush with or does not exceed the second surface of the first substrate.

[0017] In one embodiment, the electronic device further includes:

[0018] The second sensing chip is disposed in the second cavity of the first substrate and is adjacent to the second processing chip. The first colloid also covers the second sensing chip.

[0019] In one embodiment, the electronic device further includes:

[0020] The second sensing chip is disposed on the first surface of the first substrate and located in the first cavity. The second sensing chip is electrically connected to the second processing chip via the first substrate.

[0021] In one embodiment, the package includes:

[0022] a second substrate, disposed on the first surface of the first substrate and having an opening penetrating the second substrate; and

[0023] The third substrate is disposed on the second substrate and has a third surface and a fourth surface opposite to each other, and the second cavity extends from the third surface to the fourth surface. The first surface of the first substrate, the opening of the second substrate, and the fourth surface of the third substrate define a space of the first cavity. The second substrate includes at least one conductive path. The first substrate is electrically connected to the third substrate via the at least one conductive path of the second substrate.

[0024] In one embodiment, a first processing chip is disposed in the second cavity of the third substrate, adjacent to the second processing chip, and the first colloid further covers the first processing chip.

[0025] In one embodiment, the first colloid has a top surface away from the first bottom wall of the second cavity, and the top surface is flush with or does not exceed the third surface of the third substrate.

[0026] In one embodiment, the electronic device further comprises:

[0027] The metal plate is disposed on the top surface of the first colloid, extends to cover the second cavity and is electrically connected to the third substrate. The metal plate has an opening, and the opening exposes a portion of the top surface of the first colloid.

[0028] In one embodiment, the metal plate extends to cover the third surface of the third substrate, and an air gap is formed between the metal plate and the first colloid.

[0029] In one embodiment, the first substrate has a third cavity extending from the second surface toward the first surface. The third cavity has a second opening end and a second bottom wall opposite to each other. The second opening end faces away from the first cavity, and the second bottom wall is located between the second opening end and the first cavity. The first processing wafer is disposed in the third cavity of the first substrate.

[0030] In one embodiment, the electronic device further comprises:

[0031] The second sensing chip is disposed on the fourth surface of the third substrate and is located in the first cavity. The second sensing chip is electrically connected to the second processing chip via the third substrate.

[0032] In one embodiment, the electronic device further comprises:

[0033] The second sensing chip is disposed in the second cavity of the third substrate and is adjacent to the second processing chip. The first colloid also covers the second sensing chip.

[0034] In one embodiment, the electronic device further comprises:

[0035] The second colloid is filled in the third cavity of the first substrate and at least covers the first processing wafer.

[0036] In one embodiment, the electronic device further comprises:

[0037] The metal plate is disposed on the top surface of the second colloid and is electrically connected to the first substrate. The metal plate has an opening, and the opening exposes a portion of the top surface of the second colloid.

[0038] In one embodiment, the electronic device further includes:

[0039] A plurality of conductive elements are disposed on the second surface of the first substrate and are electrically connected to the first processing chip and the second processing chip.

[0040] Based on the above, in the design of the electronic device of this application, the package and substrate define a first cavity, while one of the first substrate and package has a second cavity. The first sensing chip is located in the first cavity, while the second processing chip is located in the second cavity and is isolated from the air of the first cavity. This design allows the sensing chip and processing chip to be placed in different cavities, reducing interference caused by the processing chip on the sensing chip during operation, thereby enabling the electronic device of this application to achieve better sensing performance.

[0041] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present invention.

[0043] Figure 2 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present invention.

[0044] Figure 3 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present invention.

[0045] Figure 4 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present invention.

[0046] Figure 5 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present invention.

[0047] Figure 6 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present invention.

[0048] Figure 7 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present invention.

[0049] Figure 8 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present invention.

[0050] Figure 9 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present invention.

[0051] Description of reference numerals:

[0052] 10, 20, 30, 40: Adhesive layer

[0053] 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h, 100i: electronic devices

[0054] 110a, 110f, 110h: first substrate

[0055] 111: first surface

[0056] 112:Through hole

[0057] 113: Second surface

[0058] 115: Conductive parts

[0059] 120a, 120f: Package

[0060] 122f: second substrate

[0061] 123: Open

[0062] 124f: third substrate

[0063] 125, 126: Joints

[0064] 127: Third surface

[0065] 129: Fourth Surface

[0066] 130: first sensor chip

[0067] 131:Diaphragm

[0068] 132: Back panel

[0069] 133: vent hole

[0070] 140a, 140f, 140h: first processing wafer

[0071] 142: Insulation layer

[0072] 144: Internal circuit structure

[0073] 150a, 150f: second processing wafer

[0074] 160a, 160b, 160d, 160e, 160f, 160h: first colloid

[0075] 162a, 162b, 162d, 162e, 162f, 162h: top surface

[0076] 165h: Second colloid

[0077] 167h: Top surface

[0078] 170a, 170e, 170i: second sensing chip

[0079] 180b, 180c, 180d, 180f, 180g, 190h: Metal plates

[0080] 181b, 181c, 181d, 181f, 181g, 191h: Open

[0081] 182b, 182d, 182g, 192h: Surface

[0082] E1, E1': first opening end

[0083] E2, E2': first bottom wall

[0084] E3: Second open end

[0085] E4: Second bottom wall

[0086] G1, G2: air gap

[0087] P1, P2, P3, P4, P5: electromagnetic protection cavity

[0088] S1, S1': first cavity

[0089] S2, S2': second cavity

[0090] S3: The third cavity

[0091] T: Conductive path

[0092] W1, W2, W3: welding wire DETAILED DESCRIPTION

[0093] Directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings and do not imply an absolute orientation.

[0094] The present invention will be more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, dimensions, or sizes of layers or regions in the drawings may be exaggerated for clarity. Identical or similar reference numbers denote identical or similar elements, and their detailed description will not be repeated in the following paragraphs. Furthermore, descriptions of well-known structures, methods, and materials may be omitted to avoid obscuring the description of the various principles of the present invention.

[0095] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section.

[0096] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0097] Figure 1 is a cross-sectional diagram of an electronic device according to an embodiment of the present invention. Figure 1 In this embodiment, the electronic device 100a includes a first substrate 110a, a package 120a, a first sensor chip 130, a first processing chip 140a, a second processing chip 150a, and a first colloid 160a. The first substrate 110a has a first surface 111 and a second surface 113 opposite to each other, and a through hole 112 that passes through the first substrate 110a and connects the first surface 111 and the second surface 113. The package 120a is disposed on the first surface 111 of the first substrate 110a and defines a first cavity S1 with the first substrate 110a. One of the first substrate 110a and the package 120a has a second cavity S2. The second cavity S2 has a first opening end E1 and a first bottom wall E2 opposite to each other. The first opening end E1 faces away from the first cavity S1, and the first bottom wall E2 is located between the first opening end E1 and the first cavity S1. A first sensor chip 130 is disposed on the first surface 111 of the first substrate 110a and is located in the first chamber S1, covering the through-hole 112. The first sensor chip 130 is electrically connected to the first processing chip 140a. A second processing chip 150a is disposed in the second chamber S2. The second processing chip 150a is isolated from the air in the first chamber S1. A first colloid 160a is filled in the second chamber S1 and at least covers the second processing chip 150a.

[0098] Specifically, in this embodiment, the first substrate 110a has a second cavity S2 extending from the second surface 113 toward the first surface 111. In some embodiments, the second cavity S2 is specifically a groove. The first opening E1 of the second cavity S2 serves as an entrance to the cavity. It faces away from the first cavity S1 (i.e., outward), not toward the first cavity S1. The first bottom wall E2 of the second cavity S2 serves as a structure placement area. In some embodiments, the first substrate 110a may be a circuit substrate, such as, but not limited to, a printed circuit board (PCB). The package 120a may be bonded to the first surface 111 of the first substrate 110a via a bonding member 125, thereby defining the first cavity S1 with the first substrate 110a. In some embodiments, the package 120a may be made of, but not limited to, a metal material such as stainless steel, brass, or copper, and may provide electromagnetic shielding. In some embodiments, the bonding element 125 may be a conductive metal material, such as a solder ball, solder paste, or a wafer bump, but is not limited thereto.

[0099] The first sensor chip 130 of this embodiment is, for example, disposed on the first surface 111 of the first substrate 110a through the adhesive layer 10 and covers the through-hole 112. The first sensor chip 130 may include a diaphragm 131 and an air vent 133 formed on the diaphragm 131, wherein external air outside the through-hole 112 can circulate through the air vent 133. In some embodiments, the first sensor chip 130 may also include a back plate 132 having a plurality of through-holes, wherein the back plate 132 may be made of a suitable insulating material, which is not limited here. In some embodiments, the first sensor chip 130 may be, for example, a microphone element to sense pressure changes generated by external sound wave vibrations, but is not limited thereto.

[0100] In this embodiment, the first processing chip 140a is disposed on the first surface 111 of the first substrate 110a, for example, through an adhesive layer 20, adjacent to the first sensing chip 130, and located within the first cavity S1. The first sensing chip 130 is electrically connected to the first processing chip 140a, for example, through bonding wires W1, and the first processing chip 140a is electrically connected to the first substrate 110a, for example, through bonding wires W2. In some embodiments, the first processing chip 140a may further include an insulating layer 142 and an internal wiring structure 144, wherein the insulating layer 142 covers the bonding wires W1 and W2, and the internal wiring structure 144 is electrically connected to the bonding wires W1 and W2. The insulating layer 142 and the internal wiring structure 144 may be any suitable components for the first processing chip 140a and are not limited herein. In some embodiments, the first processing chip 140a may be an application-specific integrated circuit (ASIC) to receive and process the signals measured by the first sensing chip 130.

[0101] The second processing chip 150a of this embodiment is, for example, disposed in the second cavity S2 of the first substrate 110a through the adhesive layer 30. The second processing chip 150a is electrically connected to the first substrate 110a through the welding wire W3, for example, wherein the active surface of the second processing chip 150a faces downward, while the active surface of the first processing chip 140a faces upward. Here, the active surface refers to the surface of the semiconductor structure on which the conductive pads are configured. Since the second processing chip 150a is located in the second cavity S2 and the second processing chip 150a is isolated from the air of the first cavity S1, the heat generated by the second processing chip 150a during operation can be isolated in the second cavity S2, and can be prevented from being transferred to the first cavity S1 and affecting the operation of the first sensor chip 130, which means that thermal interference between chips can be avoided. Furthermore, the first colloid 160a filled in the second cavity S2 can form a stress buffer structure in the first substrate 110a, thereby strengthening the overall rigidity of the first substrate 110a and preventing the first substrate 110a from being damaged and / or warped during high-temperature processes.

[0102] Furthermore, in this embodiment, the first adhesive 160a completely fills the second cavity S2, enveloping the second handle wafer 150a and the bonding wires W3. This effectively protects the second handle wafer 150a and the bonding wires W3, reduces the risk of bonding wires W3 breaking during bonding to the first substrate 110a, and enhances structural reliability. In some embodiments, the first adhesive 160a has a top surface 162a that is spaced from the first bottom wall E2 of the second cavity S2 and is flush with the second surface 113 of the first substrate 110a. In some embodiments, the top surface 162a of the first adhesive 160a is located between the first bottom wall E2 and the second surface 113, meaning that the first adhesive 160a does not protrude beyond the second surface 113 of the first substrate 110a. In some embodiments, the second cavity S2 can be considered a potting cavity, but is not limited thereto.

[0103] In addition, the electronic device 100a of this embodiment further includes a second sensing chip 170a, which is disposed on the first surface 111 of the first substrate 110a, for example, through an adhesive layer 40, and is located in the first cavity S1. The second sensing chip 170a can be electrically connected to the first substrate 110a, for example, through a bonding wire W4, and the second sensing chip 170a can be electrically connected to the second processing chip 150a via the first substrate 110a. In some embodiments, the second sensing chip 170a is, for example, an environmental sensor element to sense air conditions from the external environment. For example, the second sensing chip 170a can be a barometer, but is not limited thereto. In some embodiments, when the second sensing chip 170a is a pressure sensing element, it can have a structure (not shown) similar to the diaphragm 131 of the first sensing chip 130, so as to obtain the desired physical quantity through the deformation of the diaphragm in response to pressure. In some embodiments, when the second sensing chip 170a is a temperature sensor, it may not have a structure similar to the diaphragm 131 of the first sensing chip 130. Therefore, the specific design of the second sensing chip 170a can be determined based on the physical quantity it is intended to sense and is not limited herein. In some embodiments, the second processing chip 150a may be an application-specific integrated circuit (ASIC) to receive and process the signals measured by the second sensing chip 170a.

[0104] Furthermore, the electronic device 100a of this embodiment may further include a plurality of conductive members 115, which are separately disposed on the second surface 113 of the first substrate 110a and electrically connected to the first substrate 110a, the first processing chip 140a, and the second processing chip 150a. In some embodiments, the conductive members 115 may be electrodes, for example, and their material may be, but is not limited to, solder paste.

[0105] In short, in this embodiment, the package 120a and substrate 110a define a first cavity S1, while the first substrate 110a has a second cavity S2 extending from the second surface 113 toward the first surface 111. The first sensing chip 130 is located in the first cavity S1, while the second processing chip 150a is located in the second cavity S2 and is airtightly isolated from the first cavity S1. This design allows the first sensing chip 130 and the second processing chip 150a to be placed in different cavities, reducing interference from the second processing chip 150a on the first sensing chip 130 during operation. This, in turn, allows the electronic device 100a of this embodiment to achieve better sensing performance.

[0106] It must be noted here that the following embodiments continue to use the component numbers and some contents of the above embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the above embodiments, and the following embodiments will not be repeated.

[0107] Figure 2 is a cross-sectional diagram of an electronic device according to another embodiment of the present invention. Figure 1 as well as Figure 2 The electronic device 100b of this embodiment is similar to the aforementioned electronic device 100a, except that the main difference between the two is that in this embodiment, the electronic device 100b further includes a metal plate 180b, which is disposed on the top surface 162b of the first colloid 160b, covers the second cavity S2, and is electrically connected to the first substrate 110a.

[0108] Specifically, in this embodiment, the top surface 162b of the first colloid 160b is located between the first bottom wall E2 of the second cavity S2 and the second surface 113 of the first substrate 110a, meaning that the top surface 162b of the first colloid 160b does not extend beyond the second surface 113 of the first substrate 110a. In some embodiments, a surface 182b of the metal plate 180b, which is relatively remote from the top surface 162b of the first colloid 160b, is flush with the second surface 113 of the first substrate 110a. In some embodiments, the surface 182b of the metal plate 180b is located between the top surface 162b of the first colloid 160b and the second surface 113 of the first substrate 110a, meaning that the metal plate 180b does not extend beyond the second surface 113 of the first substrate 110a. Furthermore, to ensure pressure balance between the second cavity S2 and the outside world, the metal plate 180b of this embodiment may have an opening 181b, where the opening 181b exposes a portion of the top surface 162b of the first colloid 160b. The metal plate 180 b and the first substrate 110 a are grounded, and the metal plate 180 b and the second cavity S2 of the first substrate 110 a define an electromagnetic protection cavity P1 , ie, a Faraday cage, which can enhance the anti-interference capability of the second processing chip 150 a .

[0109] Figure 3 is a cross-sectional diagram of an electronic device according to another embodiment of the present invention. Figure 2 as well as Figure 3 The electronic device 100c of this embodiment is similar to the aforementioned electronic device 100b, with the primary difference being that in this embodiment, a metal plate 180c is disposed on the top surface 162b of the first colloid 160b and extends to cover the second surface 113 of the first substrate 110a. An air gap G1 is defined between the metal plate 180c and the top surface 162b of the first colloid 160b. Furthermore, to ensure pressure balance between the second cavity S2 and the external environment, the metal plate 180c of this embodiment may have an opening 181c, which exposes a portion of the top surface 162b of the first colloid 160b.

[0110] Figure 4 is a cross-sectional diagram of an electronic device according to another embodiment of the present invention. Figure 1 as well as Figure 4 The electronic device 100d of this embodiment is similar to the aforementioned electronic device 100a, with the primary difference being that in this embodiment, a first processing chip 140d is disposed within the second cavity S2 of the first substrate 110a, adjacent to the second processing chip 150a. The first processing chip 140d is electrically connected to the first substrate 110a, for example, via bonding wires W2. In this embodiment, the first adhesive 160d not only covers the second processing chip 150a and bonding wires W3, but also the first processing chip 140d and bonding wires W2. This effectively protects the first processing chip 140d, the second processing chip 150a, and the bonding wires W2 and W3, reducing the risk of wires W2 and W3 breaking during bonding to the first substrate 110a and improving structural reliability.

[0111] In addition, the electronic device 100d of this embodiment further includes a metal plate 180d, which is disposed on the top surface 162d of the first colloid 160d and electrically connected to the first substrate 110a. Specifically, in this embodiment, the top surface 162d of the first colloid 160d is located between the first bottom wall E2 of the second cavity S2 and the second surface 113 of the first substrate 110a, meaning that the top surface 162d of the first colloid 160d does not extend beyond the second surface 113 of the first substrate 110a. In some embodiments, a surface 182d of the metal plate 180d, which is relatively remote from the top surface 162d of the first colloid 160d, is flush with the second surface 113 of the first substrate 110a. In some embodiments, the surface 182d of the metal plate 180d is located between the top surface 162d of the first colloid 160d and the second surface 113 of the first substrate 110a, meaning that the metal plate 180d does not extend beyond the second surface 113 of the first substrate 110a. In some embodiments, a surface 182d of the metal plate 180d is flush with the second surface 113 of the first substrate 110a. Furthermore, to ensure pressure balance between the second cavity S2 and the external environment, the metal plate 180d of this embodiment may have an opening 181d, which exposes a portion of the top surface 162d of the first colloid 160d. The metal plate 180d and the first substrate 110a are grounded, and the metal plate 180d and the second cavity S2 of the first substrate 110a define an electromagnetic shielding cavity P2, forming a Faraday cage, which enhances the anti-interference capabilities of the first processing chip 140d and the second processing chip 150a.

[0112] Since the first processing chip 140d and the second processing chip 150a of this embodiment are both disposed in the second chamber S2, they belong to different chambers from the first sensing chip 130 and the second sensing chip 170a disposed in the first chamber S1. This effectively reduces the interference caused by the first processing chip 140d and the second processing chip 150a on the first sensing chip 130 and the second sensing chip 170a during operation, thereby enabling the electronic device 100d of this embodiment to have better sensing performance.

[0113] Figure 5 is a cross-sectional diagram of an electronic device according to another embodiment of the present invention. Figure 1 as well as Figure 5The electronic device 100e of this embodiment is similar to the aforementioned electronic device 100a, with the primary difference being that in this embodiment, a second sensor chip 170e is disposed within the second cavity S2 of the first substrate 110a, for example, through an adhesive layer 40, adjacent to the second processing chip 150a. The second sensor chip 170e may be electrically connected to the first substrate 110a, for example, through bonding wires W4. The second sensor chip 170e may also be electrically connected to the second processing chip 150a via the first substrate 110a. In this embodiment, the first adhesive 160e not only covers the second processing chip 150a and bonding wires W3, but also covers the second sensor chip 170e and bonding wires W4. This effectively protects the second sensor chip 170e, the second processing chip 150a, and the bonding wires W3 and W4, reducing the risk of wires W3 and W4 breaking during bonding to the first substrate 110a and improving structural reliability. Here, the top surface 162e of the first colloid 160e does not exceed the second surface 113 of the first substrate 110a, but the present invention is not limited thereto.

[0114] Figure 6 is a cross-sectional diagram of an electronic device according to another embodiment of the present invention. Figure 1 as well as Figure 6 The electronic device 100f of this embodiment is similar to the aforementioned electronic device 100a, except that the structure of the package 120f in this embodiment is different from that of the aforementioned package 120a.

[0115] In detail, the package 120f of this embodiment includes a second substrate 122f and a third substrate 124f. The second substrate 122f is disposed on the first surface 111 of the first substrate 110f and has an opening 123 that passes through the second substrate 122f. The third substrate 124f is disposed on the second substrate 122f and has a third surface 127 and a fourth surface 129 that are opposite to each other, and a second cavity S2' that extends from the third surface 127 to the fourth surface 129. In other words, the package 120f of this embodiment has a second cavity S2'. Further, the second cavity S2' has a first open end E1' and a first bottom wall E2' that are opposite to each other. The first open end E1' faces away from the first cavity S1', and the first bottom wall E2' is located between the first open end E1' and the first cavity S1'. Here, the first surface 111 of the first substrate 110f, the opening 123 of the second substrate 122f, and the fourth surface 129 of the third substrate 124f define a first cavity S1'. The second substrate 122f can be bonded to the fourth surface 127 of the third substrate 124f via a bonding member 126. In some embodiments, the bonding member 126 can be, for example, a conductive metal material such as a solder ball, solder paste, or a wafer bump, but is not limited thereto. The second substrate 122f electrically connects the first substrate 110f and the third substrate 124f. In some embodiments, the second substrate 122f includes at least one conductive path (two conductive paths T are schematically shown), wherein the first substrate 110f is electrically connected to the third substrate 124f via the conductive path T of the second substrate 122f. In some embodiments, the second substrate 122f and the third substrate 124f can each be a circuit substrate, such as, but not limited to, a printed circuit board (PCB).

[0116] Furthermore, in this embodiment, the first processing chip 140f is disposed in the second cavity S2' of the third substrate 124f, adjacent to the second processing chip 150f. The first adhesive 160f not only covers the second processing chip 150f and the bonding wires W3, but also covers the first processing chip 140f and the bonding wires W2. This effectively protects the first and second processing chips 140f, 150f, the bonding wires W2, and W3, reducing the risk of wire W2 and W3 breaking during bonding with the third substrate 124f, thereby increasing structural reliability. The first adhesive 160f has a top surface 162f that is spaced away from the first bottom wall E2' of the second cavity S2'. In some embodiments, the top surface 162f of the first adhesive 160f is located between the third surface 127 of the third substrate 124f and the first bottom wall E2' of the second cavity S2'. In some embodiments, the top surface 162f of the first adhesive 160f is flush with the third surface 127 of the third substrate 124f.

[0117] Furthermore, the electronic device 100f of this embodiment further includes a metal plate 180f, which is disposed on the top surface 162f of the first colloid 160f, extends to cover the second cavity S2', and is electrically connected to the third substrate 124f. The metal plate 180f extends to cover the third surface 127 of the third substrate 124f. In other words, the metal plate 180f can be directly disposed on the third surface 127 of the third substrate 124f. Here, the metal plate 180f is not in direct contact with the top surface 162f of the first colloid 160f, but rather has an air gap G2. Furthermore, to ensure pressure balance between the second cavity S2' and the outside world, the metal plate 180f of this embodiment has an opening 181f, which exposes a portion of the top surface 162f of the first colloid 160f. The metal plate 180f and the third substrate 124f are grounded, and the metal plate 180f and the second cavity S2' of the third substrate 124f define an electromagnetic protection cavity P3, ie, a Faraday cage, which can enhance the anti-interference capability of the first processing chip 140f and the second processing chip 150f.

[0118] Since the first processing chip 140f and the second processing chip 150f of this embodiment are both disposed in the second cavity S2′, they belong to different cavities from the first sensing chip 130 and the second sensing chip 170a disposed in the first cavity S1′. This effectively reduces the interference of the first processing chip 140f and the second processing chip 150f on the first sensing chip 130 and the second sensing chip 170a during operation, thereby enabling the electronic device 100f of this embodiment to have better sensing performance.

[0119] Figure 7 is a cross-sectional diagram of an electronic device according to another embodiment of the present invention. Figure 6 as well as Figure 7 The electronic device 100g of this embodiment is similar to the aforementioned electronic device 100f, except that the main difference between the two is that in this embodiment, the metal plate 180g is directly disposed on the top surface 162f of the first colloid 160f, and a surface 182g of the metal plate 180g that is relatively away from the top surface 162f of the first colloid 160f is flush with or does not exceed the third surface 127 of the third substrate 124f.

[0120] Figure 8 is a cross-sectional diagram of an electronic device according to another embodiment of the present invention. Figure 6 as well as Figure 8The electronic device 100h of this embodiment is similar to the electronic device 100f described above, except that the main difference between the two is that in this embodiment, the first substrate 110h further has a third cavity S3 extending from the second surface 113 to the first surface 111. The third cavity S3 has a second opening end E3 and a second bottom wall E4 opposite to each other. The second opening end E3 faces away from the first cavity S1', and the second bottom wall E4 is located between the second opening end E3 and the first cavity S1'. The first processing chip 140h is disposed in the third cavity S3 of the first substrate 110h. At this time, the first cavity S1' is located between the second cavity S2' and the third cavity S3, and the second sensing chip 170h is disposed on the fourth surface 129 of the third substrate 124f and is located in the first cavity S1'. The second sensing chip 170h is electrically connected to the second processing chip 150f via the third substrate 124f. That is, the first glue 160h only covers the second handling wafer 150f and the bonding wire W3, wherein the top surface 162h of the first glue 160h is flush with the third surface 127 of the third substrate 124f, and the metal plate 180f directly contacts the top surface 162h of the first glue 160h and extends onto the third surface 127 of the third substrate 124f.

[0121] Furthermore, the electronic device 100h of this embodiment further includes a second colloid 165h, which fills the third cavity S3 of the first substrate 110h and covers at least the first handle chip 140h. Specifically, the second colloid 165h covers the first handle chip 140h and the bonding wires W2, thereby effectively protecting the first handle chip 140h and the bonding wires W2, reducing the risk of bonding wires W2 breaking during bonding to the first substrate 110h, and improving structural reliability. The second colloid 165h has a top surface 167h that is spaced apart from the second bottom wall E4 of the third cavity S3. In some embodiments, the top surface 167h of the second colloid 165h is located between the second bottom wall E4 of the third cavity S3 and the second surface 113, meaning that the top surface 167h of the second colloid 165h does not extend beyond the second surface 113 of the first substrate 110h. Furthermore, the electronic device 100h of this embodiment further includes a metal plate 190h disposed on the top surface 167h of the second colloid 165h. To ensure pressure balance within the third cavity S3 and the external environment, the metal plate 190h of this embodiment has an opening 191h that exposes a portion of the top surface 167h of the second colloid 165h. In some embodiments, a surface 192h of the metal plate 190h, which is relatively distal to the top surface 167h of the second colloid 165h, is flush with the second surface 113 of the first substrate 110h. The metal plate 190h and the first substrate 110h are grounded, and the third cavity S3 formed by the metal plate 190h and the first substrate 110h defines an electromagnetic shielding cavity P5, forming a Faraday cage that enhances the anti-interference capability of the first processing wafer 140h.

[0122] Since the first processing chip 140h and the second processing chip 150f of this embodiment are respectively disposed in the third chamber S3 and the second chamber S2', they belong to different chambers from the first sensing chip 130 and the second sensing chip 170h disposed in the first chamber S1'. This can effectively reduce the interference caused by the first processing chip 140h and the second processing chip 150f on the first sensing chip 130 and the second sensing chip 170h during operation, thereby enabling the electronic device 100h of this embodiment to have better sensing performance.

[0123] Figure 9 is a cross-sectional diagram of an electronic device according to another embodiment of the present invention. Figure 8 as well as Figure 9 The electronic device 100i of this embodiment is similar to the aforementioned electronic device 100h, with the primary difference being that in this embodiment, the second sensor chip 170i is disposed within the second cavity S2' of the third substrate 124f, adjacent to the second processing chip 150f, for example, through an adhesive layer 40. The second sensor chip 170i can be electrically connected to the third substrate 124f, for example, through bonding wires W4. The second sensor chip 170i can also be electrically connected to the second processing chip 150f via the third substrate 124f. In addition to covering the second processing chip 150f and bonding wires W3, the first adhesive 160h of this embodiment further covers the second sensor chip 170i and bonding wires W4. This effectively protects the second sensor chip 170i, the second processing chip 150f, and the bonding wires W3 and W4, reducing the risk of wires W3 and W4 breaking during bonding to the third substrate 124f and improving structural reliability.

[0124] In summary, in the electronic device design of the present invention, the package and substrate define a first cavity, while one of the first substrate and package defines a second cavity. The first sensing chip is located in the first cavity, while the second processing chip is located in the second cavity, isolated from the air surrounding the first cavity. This design allows the sensing chip and processing chip to be placed in separate cavities, minimizing interference from the processing chip on the sensing chip during operation, thereby enabling the electronic device of the present invention to achieve better sensing performance.

[0125] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Anyone with ordinary skill in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent applications.

Claims

1. An electronic device, characterized in that: The electronic device comprises: A first substrate having a first surface and a second surface opposite to each other, and a through hole penetrating the first substrate and connecting the first surface and the second surface; a package disposed on the first surface of the first substrate and defining a first cavity with the first substrate, wherein one of the first substrate and the package has a second cavity, the second cavity having a first open end and a first bottom wall opposite to each other, the first open end facing away from the first cavity, and the first bottom wall located between the first open end and the first cavity; a first sensing chip disposed on the first surface of the first substrate, located in the first cavity and covering the through hole, wherein the first sensing chip is electrically connected to the first processing chip; a second processing wafer disposed in the second chamber, wherein the second processing wafer is isolated from the air in the first chamber; and The first colloid is filled in the second cavity and at least covers the second processing wafer.

2. The electronic device according to claim 1, wherein: The first substrate has a second cavity extending from the second surface toward the first surface.

3. The electronic device according to claim 2, wherein: The first processing chip is disposed in the second cavity of the first substrate, adjacent to the second processing chip, and the first colloid further covers the first processing chip.

4. The electronic device according to claim 2, wherein: The first colloid has a top surface away from the first bottom wall of the second cavity, and the top surface is flush with or does not exceed the second surface of the first substrate.

5. The electronic device according to claim 2, wherein: The electronic device further comprises: The metal plate is disposed on the top surface of the first colloid, covers the second cavity and is electrically connected to the first substrate. The metal plate has an opening, and the opening exposes a portion of the top surface of the first colloid.

6. The electronic device according to claim 5, wherein: The metal plate extends to cover the second surface of the first substrate, and an air gap is formed between the metal plate and the first colloid.

7. The electronic device according to claim 5, wherein: A surface of the metal plate that is relatively far away from the top surface of the first colloid is flush with or does not exceed the second surface of the first substrate.

8. The electronic device according to claim 2, wherein: The electronic device further comprises: The second sensing chip is disposed in the second cavity of the first substrate and is adjacent to the second processing chip. The first colloid also covers the second sensing chip.

9. The electronic device according to claim 1, wherein: The electronic device further comprises: The second sensing chip is disposed on the first surface of the first substrate and located in the first cavity. The second sensing chip is electrically connected to the second processing chip via the first substrate.

10. The electronic device according to claim 1, wherein: The package comprises: a second substrate, disposed on the first surface of the first substrate and having an opening penetrating the second substrate; and The third substrate is disposed on the second substrate and has a third surface and a fourth surface opposite to each other, and the second cavity extends from the third surface to the fourth surface. The first surface of the first substrate, the opening of the second substrate, and the fourth surface of the third substrate define a space of the first cavity. The second substrate includes at least one conductive path. The first substrate is electrically connected to the third substrate via the at least one conductive path of the second substrate.

11. The electronic device according to claim 10, wherein: The first processing chip is disposed in the second cavity of the third substrate, adjacent to the second processing chip, and the first colloid further covers the first processing chip.

12. The electronic device according to claim 10, wherein: The first colloid has a top surface away from the first bottom wall of the second cavity, and the top surface is flush with or does not exceed the third surface of the third substrate.

13. The electronic device according to claim 10, wherein: The electronic device further comprises: The metal plate is disposed on the top surface of the first colloid, extends to cover the second cavity and is electrically connected to the third substrate. The metal plate has an opening, and the opening exposes a portion of the top surface of the first colloid.

14. The electronic device according to claim 13, wherein: The metal plate extends to cover the third surface of the third substrate, and an air gap is formed between the metal plate and the first colloid.

15. The electronic device according to claim 10, wherein: The first substrate has a third cavity extending from the second surface toward the first surface. The third cavity has a second opening end and a second bottom wall opposite to each other. The second opening end faces away from the first cavity, and the second bottom wall is located between the second opening end and the first cavity. The first processing wafer is disposed in the third cavity of the first substrate.

16. The electronic device according to claim 15, wherein: The electronic device further comprises: The second sensing chip is disposed on the fourth surface of the third substrate and is located in the first cavity. The second sensing chip is electrically connected to the second processing chip via the third substrate.

17. The electronic device according to claim 15, wherein: The electronic device further comprises: The second sensing chip is disposed in the second cavity of the third substrate and is adjacent to the second processing chip. The first colloid also covers the second sensing chip.

18. The electronic device according to claim 15, wherein: The electronic device further comprises: The second colloid is filled in the third cavity of the first substrate and at least covers the first processing wafer.

19. The electronic device according to claim 18, wherein: The electronic device further comprises: The metal plate is disposed on the top surface of the second colloid and is electrically connected to the first substrate. The metal plate has an opening, and the opening exposes a portion of the top surface of the second colloid.

20. The electronic device according to claim 1, wherein The electronic device further comprises: A plurality of conductive elements are disposed on the second surface of the first substrate and are electrically connected to the first processing chip and the second processing chip.

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