A self-gain signal compensation amplifier

Abstract

The application discloses a self-gain signal compensation amplifier, which comprises a plurality of operational amplifiers, a plurality of digital potentiometers, a plurality of inverters, a plurality of diodes, a plurality of resistors, a counter, a gate, and an AND gate. The operational amplifier U1 in the plurality of operational amplifiers is connected with one end of the resistance R1 and the SIN end in phase, connected with the sixth pin of the digital potentiometer U5 and one end of the resistance R9 in reverse phase, and connected with the third pin and the fifth pin of the digital potentiometer U5, the same phase end of the operational amplifier U7 and the Out end. The input end of the inverter U2 is connected with the anode of the diode D1 and the anode of the diode D2, and the output end is connected with the seventh pin of the digital potentiometer U4. The first pin of the flip-flop U3 is connected with the output end of the inverter U6, the second pin is connected with the sixth pin, the seventh pin of the digital potentiometer U5 and the eleventh pin of the gate U10, and the third pin is connected with the output end of the AND gate U11. The third pin of the digital potentiometer U4 is connected with the reverse phase end of the operational amplifier U7, the same phase end of the operational amplifier U8, the reverse phase end of the operational amplifier U9 and one end of the resistance R8.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a self-gain signal compensation amplifier. BACKGROUND

[0002] The core role of signal gain is to solve the adaptability problem between the original signal and the processing system. The original signal output by the sensor is often extremely weak, such as millivolt-level output of a strain gauge and microampere-level current of a photodiode. These signals cannot be effectively quantized by an analog-to-digital converter (ADC) directly (a typical ADC needs a volt-level input), and thus these weak signals need to be boosted to an amplitude range suitable for processing. However, due to the amplitude span between different signal sources, which may differ by several orders of magnitude, when a single gain is used, either the strong signal will be distorted due to exceeding the processing range, or the weak signal will still be below the system detection threshold. SUMMARY

[0003] In order to solve the above technical problems, the self-gain signal compensation amplifier aims to provide a self-gain signal compensation amplifier, which comprises a plurality of operational amplifiers, a plurality of digital potentiometers, a plurality of inverters, a plurality of diodes, a plurality of resistors, a counter, a gate, and an AND gate, wherein the operational amplifier U1 in the plurality of operational amplifiers is connected to one end of the resistor R1, the SIN terminal, the sixth pin of the digital potentiometer U5, one end of the resistor R9, the third and fifth pins of the digital potentiometer U5, the non-inverting terminal of the operational amplifier U7, and the Out terminal; the input terminal of the inverter U2 is connected to the anode of the diode D1 and the anode of the diode D2, and the output terminal is connected to the seventh pin of the digital potentiometer U4; the first pin of the flip-flop U3 is connected to the output terminal of the inverter U6, the second pin is connected to the sixth pin, the seventh pin of the digital potentiometer U5, and the eleventh pin of the gate U10, and the third pin is connected to the output terminal of the AND gate U11; the third pin of the digital potentiometer U4 is connected to the non-inverting terminal of the operational amplifier U7, the non-inverting terminal of the operational amplifier U8, the non-inverting terminal of the operational amplifier U9, and one end of the resistor R8; the second pin of the digital potentiometer U5 is connected to the IN2 terminal; the output terminal of the operational amplifier U7 is connected to the anode of the diode D1; the output terminal of the operational amplifier U8 is connected to the first input terminal of the AND gate U11; the output terminal of the operational amplifier U9 is connected to the fifteenth pin of the counter U12; one end of the resistor R16 is connected to the thirteenth pin of the gate U10, and the fourteenth pin is connected to the fourteenth pin of the counter U12; the second input terminal of the AND gate U11 is connected to the IN1 terminal; the thirteenth pin of the counter U12 is connected to the cathode of the diode D3; any pin of the output pins of the counter U12 except the second and third pins is connected to the anode of the diode D2, the anode of the diode D3, the second pin of the digital potentiometer U4, and the input terminal of the inverter U6; the fourth pin of the flip-flop U3, the eighth pin of the digital potentiometer U4, the eighth pin of the digital potentiometer U5, the sixteenth pin of the gate U10, the sixteenth pin of the counter U12, and the other end of the resistor R8 are connected to the power supply; the fourth, fifth, and sixth pins of the digital potentiometer U4, the fourth pin of the digital potentiometer U5, the sixth and seventh pins of the gate U10, the eighth pin of the counter U12, the other end of the resistor R1, the other end of the resistor R9, and the other end of the resistor R16 are connected to the ground.

[0004] Further, the self-gain signal compensation amplifier further comprises a plurality of resistors, wherein one end of the resistor R3 is connected to the second pin of the digital potentiometer U4; one end of the resistor R4 is connected to the second pin of the digital potentiometer U5; one end of the resistor R5 is connected to the sixth pin of the flip-flop U3; the resistor R6 is connected to the seventh pin of the digital potentiometer U4; one end of the resistor R15 is connected to the fifteenth pin of the counter U12; the other end of the resistor R3, the other end of the resistor R4, the other end of the resistor R5, the other end of the resistor R6, and the other end of the resistor R15 are connected to the ground.

[0005] Further, the self-gain signal compensation amplifier further comprises a plurality of resistors, wherein one end of the resistor R10 and one end of the resistor R12 are connected to the power supply; one end of the resistor R11 is connected to the other end of the resistor R10 and the non-inverting terminal of the operational amplifier U8; one end of the resistor R13 is connected to the other end of the resistor R12 and the non-inverting terminal of the operational amplifier U9; the other end of the resistor R11 and the other end of the resistor R13 are connected to the ground.

[0006] Further, the resistance R12 and the resistance R11 are adjustable resistances.

[0007] Further, the resistance R2 of the several resistances has one end connected to the input end of the inverter U2, the resistance R7 has one end connected to the third pin of the flip-flop U3, and the other end of the resistance R2 and the other end of the resistance R7 are grounded.

[0008] Further, the resistance R14 has one end connected to the second input end of the AND gate U11 and the other end grounded.

[0009] Further, the eleventh pin of the counter U12 is connected to the anode of the diode D2, the anode of the diode D3, the second pin of the digital potentiometer U4, and the input end of the inverter U6.

[0010] The present application has the following beneficial effects compared with the prior art:

[0011] The present application can automatically detect the maximum instantaneous value of the sinusoidal signal to automatically adjust the gain, so that the signal is always in the optimal gain range, and the precision control is supported throughout the process. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the prior art and the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0013] Figure 1 The circuit structure schematic diagram provided by the present application. DETAILED DESCRIPTION

[0014] In order to make the purpose and advantages of the present application more clear and explicit, the following will specifically describe the present application combined with embodiments. It should be understood that the following text is only used to describe one or several specific embodiments of the present application, and does not strictly limit the specific protection range of the present application.

[0015] The application discloses a kind of self-gain signal compensation amplifiers, including several operational amplifiers, several digital potentiometers, several inverters, several diodes, several resistors, counter, gate, and gate, the operational amplifier U1 in the several operational amplifiers, resistance R1 one end, SIN end, the sixth pin of digital potentiometer U5 is connected to the opposite phase end, resistance R9 one end, the third, fifth pin of digital potentiometer U5, operational amplifier U7 same phase end, Out end is connected;Inverter U2 input end is connected to the anode of diode D1, the anode of diode D2, the seventh pin of digital potentiometer U4 is connected to the output end;Trigger U3 first pin is connected to the output end of inverter U6, the second pin is connected to the sixth pin, the seventh pin of digital potentiometer U5, the eleventh pin of gate U10, the third pin is connected to the output end of and gate U11;The third pin of digital potentiometer U4 is connected to the opposite phase end of operational amplifier U7, the same phase end of operational amplifier U8, the opposite phase end of operational amplifier U9, resistance R8 one end;The second pin of digital potentiometer U5 is connected to IN2 end;The output end of operational amplifier U7 is connected to the anode of diode D1;The output end of operational amplifier U8 is connected to the first input end of and gate U11;The output end of operational amplifier U9 is connected to the fifteenth pin of counter U12;The thirteenth pin of gate U10 is connected to resistance R16 one end, the fourteenth pin is connected to the fourteenth pin of counter U12;The second input end of and gate U11 is connected to IN1 end;The thirteenth pin of counter U12 is connected to the cathode of diode D3;The output pin of counter U12 is connected to the anode of diode D2, the anode of diode D3, the second pin of digital potentiometer U4, the input end of inverter U6 except the second pin, the third pin;The fourth pin of trigger U3, the eighth pin of digital potentiometer U4, the eighth pin of digital potentiometer U5, the sixteenth pin of gate U10, the sixteenth pin of counter U12, the other end of resistance R8 is connected to power supply;The fourth pin, the fifth pin, the sixth pin of digital potentiometer U4, the fourth pin of digital potentiometer U5, the sixth pin, the seventh pin of gate U10, the eighth pin of counter U12, the other end of resistance R1, the other end of resistance R9, the other end of resistance R16 is connected to ground.

[0016] Specifically, it also includes several resistors, resistance R3 one end, the second pin of digital potentiometer U4 is connected;Resistance R4 one end, the second pin of digital potentiometer U5 is connected;Resistance R5 one end, the sixth pin of trigger U3 is connected;Resistance R6 is connected to the seventh pin of digital potentiometer U4;Resistance R15 one end, the fifteenth pin of counter U12 is connected;The other end of resistance R3, the other end of resistance R4, the other end of resistance R5, the other end of resistance R6, the other end of resistance R15 is connected to ground.

[0017] Specifically, it also includes several resistors, resistance R10 one end, resistance R12 one end, power supply is connected;Resistance R11 one end, the other end of resistance R10, the opposite phase end of operational amplifier U8 is connected;Resistance R13 one end, the other end of resistance R12, the opposite phase end of operational amplifier U9 is connected;The other end of resistance R11, the other end of resistance R13 is connected to ground.

[0018] In particular, the resistors R12 and R11 are adjustable resistors.

[0019] In particular, it also comprises a number of resistors, one end of the resistor R2 being connected to the input of the inverter U2, one end of the resistor R7 being connected to the third pin of the flip-flop U3, the other end of the resistor R2 and the other end of the resistor R7 being connected to ground.

[0020] In particular, it also comprises a resistor, one end of the resistor R14 being connected to the second input of the AND gate U11 and the other end being connected to ground.

[0021] In particular, the eleventh pin of the counter U12 is connected to the anode of the diode D2, the anode of the diode D3, the second pin of the digital potentiometer U4 and the input of the inverter U6.

[0022] The operational amplifier U1, the resistor R1, the digital potentiometer U5 and the resistor R9 in the scheme are used to increase the gain of the SIN waveform signal and output by Out. The digital potentiometer U5 is used to adjust the SIN gain by changing the resistance coefficient of the resistor R9. When the circuit is initially powered on, the SIN signal is pulled up to the operational amplifier U1 through the resistor R1, and the output of the operational amplifier U1 is fed back to the same-phase terminal of the operational amplifier U7 through the digital potentiometer U5. The inverted-phase terminal of the operational amplifier U7 samples the voltage at the 3-pin of the digital potentiometer U4 and the connection terminal of the resistor R8, and outputs the comparison result. The signal output by the operational amplifier U7 is used to control the digital potentiometer U4 to adjust the orientation. The signal output by the operational amplifier U7 is also inverted and output after passing through the anode of the diode D1, the cathode of the diode D1 and the input terminal of the inverter U2. The signal output by the inverter U2 is fed back to the 7-pin of the digital potentiometer U4. The 2-pin of the digital potentiometer U4 is connected to the resistor R3, and after the circuit of the resistor R3, the digital potentiometer U4 is started and pulls up the resistance of the digital potentiometer U4. The 3-pin of the digital potentiometer U4 and the connection terminal of the resistor R8 generate a gain voltage from the maximum instantaneous value of the SIN input waveform from the zero reference point and feed it back to the inverted-phase terminal of the operational amplifier U9 and the same-phase terminal of the operational amplifier U8. The same-phase terminal of the operational amplifier U9 is set to an offset reference voltage based on the zero reference point to detect whether the current SIN signal enters the vicinity of the zero reference range. The inverted-phase terminal of the operational amplifier U8 is set to an offset reference voltage approaching the distortion point. When the maximum instantaneous value gain voltage exceeds the reference voltage set at the inverted-phase terminal of the operational amplifier U8, the operational amplifier U8 outputs. IN1 is a self-gain start signal. When IN1 is input and the operational amplifier U8 has an output, the AND gate U11 outputs a signal to the 3-pin of the flip-flop U3. When the circuit is initially powered on, the 6-pin of the flip-flop U3 outputs a signal which is pulled up by the resistor R5 and fed back to the 7-pin of the digital potentiometer U5, so that the digital potentiometer U5 stops adjusting. The other feedback is to the 11-pin of the gate U10. The voltage at the 13-pin of the gate U10 is input to the counter U12 through the 14-pin of the gate U10. When the AND gate U11 outputs a signal, the 6-pin of the flip-flop U3 stops outputting, and the 7-pin of the digital potentiometer U5 is pulled down through the resistor R5 and then starts, and gradually reduces the resistance of the digital potentiometer U5 with the CLK clock signal, thereby reducing the gain. At the same time, the 11-pin of the gate U10 is connected to the resistor R5, and the CLK clock at the 12-pin of the gate U10 is input to the 14-pin of the counter U12 through the 14-pin of the gate U10. The output pins of the counter U12 gradually output, and except for the 2-pin and the 3-pin which cannot be connected, any pin can be selected to connect to the inverter U6 and the diode D3 to change the adjustment speed. In the figure, the 11-pin of the counter U12 is connected, and the adjustment speed of a single cycle is the fastest. Conversely, when the 4-pin of the counter U12 is connected, the adjustment speed is the slowest. When the 11-pin of the counter U12 is fed back to the diode D3 and the inverter U6, the signal fed back to the 13-pin of the counter U12 is interrupted through the diode D3, and the signal fed back to the inverter U6 is inverted and input to the flip-flop U3 to trigger the 6-pin of the flip-flop U3. The digital potentiometer U5 stops.When the gain is down, the signal of pin 13 of the gate U10 is input to the pin 14 of the gate U10 and the pin 14 of the gate U10 is input to the pin 14 of the counter U12, and the pin 11 of the counter U12 is fed back to the inverting input of the inverter U2 through the diode D2 and the digital potentiometer U4, the digital potentiometer U4 is started, and the other way is fed back to the pin 2 of the digital potentiometer U4, the digital potentiometer U4 is adjusted, when the voltage of the pin 3 of the digital potentiometer U4 and the connection end of the resistor R8 is lower than the offset reference voltage of the zero point based on the setting of the inverting terminal of the operational amplifier U9, the output signal of the operational amplifier U9 is input to the counter U12, the counter U12 is reset, and the counter U12 stops when the signal is input to the pin 14 of the gate U10 through the pin 13 of the gate U10, and the above process is repeated when the SIN signal is input again, the maximum instantaneous value gain voltage is generated from the zero reference point, and the above process is repeated until the offset reference voltage of the inverting terminal of the operational amplifier U8 is lower than the distortion point, at this time, the signal is in the best gain range, and the IN1 can be selected in two ways, the first one is for the maximum instantaneous voltage fluctuation amplitude, the IN1 input frequency can be selected according to the signal input frequency for real-time regulation and control, and the second one is for the replacement signal, the reset can be realized by detecting the plug-in or by inputting the signal through the IN2, and the best gain can be automatically adjusted again after the reset, the resistor R14 is added to pull up the output signal of the AND gate U11 when the manual test is realized by the independent integrated circuit, the reference voltage of the operational amplifier can be set through the power supply in addition to the fixed or adjustable resistor, the pull-down function of the chip is enabled when the pin 3 of the flip-flop U3, the input terminal of the inverter U2, the digital potentiometer U4, the pin 7 and the pin 2 of the digital potentiometer U5, and the pin 15 of the counter U12 are controlled, and the switch can be set between the input terminal of the inverter U2 and the ground, and the switch is closed when the whole circuit needs to be interrupted.

[0023] It is apparent for those skilled in the art that the present application is not limited to the details of the foregoing exemplary embodiments, and the present application can be realized in other concrete forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all aspects as illustrative and not restrictive, and the scope of the present application is defined by the appended claims rather than the foregoing description, and it is intended to embrace all changes falling within the meaning and range of equivalents of the claims. Any mark in the claims should not be considered as limiting the involved claims.

Claims

1. A self-gain signal compensating amplifier characterized by, The application relates to a signal processing circuit, which comprises a plurality of operational amplifiers, a plurality of digital potentiometers, a plurality of inverters, a plurality of diodes, a plurality of resistors, a counter, a gate, and a AND gate. The operational amplifier U1 of the plurality of operational amplifiers is connected to one end of the resistor R1, the SIN end, the sixth pin of the digital potentiometer U5, one end of the resistor R9, the third and fifth pins of the digital potentiometer U5, the non-inverting end of the operational amplifier U7, and the Out end. The input end of the inverter U2 is connected to the anode of the diode D1 and the anode of the diode D2, and the output end is connected to the seventh pin of the digital potentiometer U4. The first pin of the flip-flop U3 is connected to the output end of the inverter U6, the sixth pin, the seventh pin of the digital potentiometer U5, the eleventh pin of the gate U10, the third pin is connected to the output end of the AND gate U11. The third pin of the digital potentiometer U4 is connected to the non-inverting end of the operational amplifier U7, the non-inverting end of the operational amplifier U8, the non-inverting end of the operational amplifier U9, and one end of the resistor R8. The second pin of the digital potentiometer U5 is connected to the IN2 end. The output end of the operational amplifier U7 is connected to the anode of the diode D1. The output end of the operational amplifier U8 is connected to the first input end of the AND gate U11. The output end of the operational amplifier U9 is connected to the fifteenth pin of the counter U12. The thirteenth pin of the gate U10 is connected to one end of the resistor R16, and the fourteenth pin is connected to the fourteenth pin of the counter U12. The second input end of the AND gate U11 is connected to the IN1 end. The thirteenth pin of the counter U12 is connected to the cathode of the diode D3. The output pins of the counter U12, except the second and third pins, are connected to the anode of the diode D2, the anode of the diode D3, the second pin of the digital potentiometer U4, and the input end of the inverter U6. The fourth pin of the flip-flop U3, the eighth pin of the digital potentiometer U4, the eighth pin of the digital potentiometer U5, the sixteenth pin of the gate U10, the sixteenth pin of the counter U12, and the other end of the resistor R8 are connected to the power supply. The fourth, fifth and sixth pins of the digital potentiometer U4, the fourth pin of the digital potentiometer U5, the sixth and seventh pins of the gate U10, the eighth pin of the counter U12, the other end of the resistor R1, the other end of the resistor R9, and the other end of the resistor R16 are connected to the ground.

2. The self-gain signal compensating amplifier according to claim 1, wherein, The application further comprises a plurality of resistors, wherein one end of the resistor R3 is connected to the second pin of the digital potentiometer U4; one end of the resistor R4 is connected to the second pin of the digital potentiometer U5; one end of the resistor R5 is connected to the sixth pin of the flip-flop U3; the resistor R6 is connected to the seventh pin of the digital potentiometer U4; one end of the resistor R15 is connected to the fifteenth pin of the counter U12; the other end of the resistor R3, the other end of the resistor R4, the other end of the resistor R5, the other end of the resistor R6, and the other end of the resistor R15 are connected to the ground.

3. The self-gain signal compensating amplifier according to claim 1, wherein, The application further comprises a plurality of resistors, wherein one end of the resistor R10 and one end of the resistor R12 are connected to the power supply; one end of the resistor R11 is connected to the other end of the resistor R10 and the non-inverting end of the operational amplifier U8; one end of the resistor R13 is connected to the other end of the resistor R12 and the non-inverting end of the operational amplifier U9; the other end of the resistor R11 and the other end of the resistor R13 are connected to the ground.

4. The self-gain signal compensating amplifier of claim 1, wherein, The resistor R12 and the resistor R11 are adjustable resistors.

5. The self-gain signal compensating amplifier of claim 1, wherein, The application further comprises a plurality of resistors, wherein one end of the resistor R2 is connected to the input end of the inverter U2; one end of the resistor R7 is connected to the third pin of the flip-flop U3; the other end of the resistor R2 and the other end of the resistor R7 are connected to the ground.

6. The self-gain signal compensating amplifier of claim 1, wherein, Also included is a resistor R14, one end of which is connected to the second input of the AND gate U11, and the other end is connected to ground.

7. The self-gain signal compensating amplifier of claim 1, wherein, The eleventh pin of the counter U12 is connected to the anode of the diode D2, the anode of the diode D3, the second pin of the digital potentiometer U4, and the input of the inverter U6.

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