Voltage detector

Abstract

The present invention addresses the problem of preventing erroneous detection when the temperature characteristics of a detected voltage are flat and the minimum operating power supply voltage is low and is less than the minimum operating power supply voltage. A voltage detector includes a voltage detection circuit and a start-up circuit, the voltage detection circuit including: a first current mirror circuit to which a current of a first current source composed of a depletion mode MOS transistor is input; an enhanced first MOS transistor having a gate connected to the input terminal and a drain connected to the output terminal and the first current mirror circuit; and a switching circuit controlled by an enable signal input to the control terminal, the start-up circuit having a current detection circuit that outputs the enable signal when an output current of the second current mirror circuit that detects that a current input to the second current source is equal to or greater than a predetermined current, and outputs the enable signal when the output current of the second current mirror circuit is equal to or greater than the predetermined current. The voltage detection circuit outputs a detection signal corresponding to the voltage of the input terminal from the output terminal when the switching circuit receives the enable signal.

Description

Technical Field

[0001] The present invention relates to a voltage detector. Background Art

[0002] The structure of a conventional voltage detector is shown in FIG. Figure 3 middle.

[0003] Figure 3 The voltage detector is composed of a depletion-type N-type metal-oxide-semiconductor (NMOS) transistor 51 serving as a current source and an enhancement-type NMOS transistor 52 .

[0004] The NMOS transistor 51 operating as a constant current source has its drain connected to the power supply terminal, and its gate and source connected to the drain of the NMOS transistor 52. The NMOS transistor 52 has its gate connected to the input terminal, its source connected to the ground terminal, and its drain connected to the output terminal.

[0005] When the voltage VIN input to the input terminal is low and the NMOS transistor 52 is turned off, the detection signal DET output from the output terminal becomes a high level. When the voltage VIN rises, the detection signal DET changes from a high level to a low level. The voltage VIN at this time is called the detection voltage of the voltage detector. The detection voltage is obtained by setting the threshold voltage of the NMOS transistor 52 to Vt 52 , set the threshold voltage of NMOS transistor 51 to Vt 51 When Vt 52 +|Vt 51 | indicates.

[0006] The conventional voltage detector configured as described above can make the temperature characteristics of the detection voltage substantially flat by setting the NMOS transistor 51 and the NMOS transistor 52 to have substantially the same aspect ratio (W length / L length) (see, for example, Patent Document 1).

[0007] [Prior art literature]

[0008] [Patent Document]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2021-103860 Summary of the Invention

[0010] [Problems to be solved by the invention]

[0011] In the conventional voltage detector, when the NMOS transistors 51 and 52 have substantially the same aspect ratio, the minimum operating power supply voltage of the voltage detector is |Vt 51 |×2. For example, |Vt51 While it is around 0.2V at room temperature, it becomes around 0.3V at a high temperature of 85°C. Therefore, the minimum operating power supply voltage of conventional voltage detectors becomes around 0.6V at a high temperature of 85°C.

[0012] When the power supply voltage is lower than the minimum operating power supply voltage, the NMOS transistor 51 operates in a non-saturated region. Therefore, there is a problem that the detection signal DET becomes a low level even if the voltage VIN is lower than the desired detection voltage.

[0013] The present invention has been made in view of the above circumstances, and aims to provide a voltage detector having a flat temperature characteristic of a detection voltage and a low minimum operating power supply voltage, and preventing false detection when the voltage is lower than the minimum operating power supply voltage.

[0014] [Technical means to solve the problem]

[0015] The voltage detector according to the embodiment of the present invention is characterized in that it includes a voltage detection circuit and a startup circuit.

[0016] The voltage detection circuit comprises:

[0017] a first current source, one end of which is connected to the first power supply terminal and is composed of a depletion-type metal oxide semiconductor (MOS) transistor;

[0018] a first current mirror circuit, having an input terminal connected to the other end of the first current source and inputting the current of the first current source;

[0019] a first enhancement-type MOS transistor, having a gate connected to the input terminal, a drain connected to the output terminal and the output terminal of the first current mirror circuit, and inputting the output current of the first current mirror circuit; and

[0020] The switch circuit is controlled by an enable signal input to the control terminal.

[0021] The startup circuit comprises:

[0022] a second current source;

[0023] a second current mirror circuit, inputting the current of the second current source; and

[0024] The current detection circuit outputs the enable signal indicating enable when detecting the output current input to the second current mirror circuit and the output current becomes equal to or greater than a predetermined current.

[0025] The voltage detection circuit outputs a detection signal corresponding to the voltage of the input terminal from the output terminal when the switch circuit receives the enable signal indicating enable from the startup circuit.

[0026] [Effects of the Invention]

[0027] The present invention provides a voltage detector in which a constant current source of a voltage detection circuit is formed by a depletion-type MOS transistor and a current mirror circuit, and includes a startup circuit for detecting when the power supply voltage reaches or exceeds the minimum operating power supply voltage of the voltage detection circuit. Therefore, the temperature characteristic of the detection voltage is flat, and at the same time, the minimum operating power supply voltage is low, and no false detection occurs when the voltage is less than the minimum operating power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a circuit diagram showing an example of a voltage detector according to an embodiment of the present invention.

[0029] Figure 2 This is a circuit diagram showing another example of the voltage detector according to this embodiment.

[0030] Figure 3 This is a circuit diagram showing a conventional voltage detector.

[0031] [Explanation of Symbols]

[0032] 1: Voltage detector

[0033] 11: Input terminal

[0034] 12, 14: Output terminals

[0035] 13: Control terminal

[0036] 20: Voltage detection circuit

[0037] 21, 31: Current source

[0038] 25: Switching Circuit

[0039] 30: Startup circuit

[0040] 34: Current detection circuit

[0041] 40: Current source circuit DETAILED DESCRIPTION

[0042] Hereinafter, a voltage detector 1 according to an embodiment of the present invention will be described with reference to the drawings.

[0043] Figure 1 1 is a circuit diagram of the voltage detector 1 according to this embodiment.

[0044] The voltage detector 1 includes a voltage detection circuit 20 and a startup circuit 30. When the startup circuit 30 outputs an enable signal, the voltage detector 1 outputs a signal output by the voltage detection circuit 20 based on the input voltage VIN as a detection signal DET. In this embodiment, the detection signal DET goes low when the input voltage VIN exceeds the detection voltage.

[0045] The voltage detection circuit 20 includes: a depletion-type NMOS transistor 21 serving as a current source, an enhancement-type P-type metal oxide semiconductor (PMOS) transistor 22 and an enhancement-type PMOS transistor 23 constituting a current mirror circuit, an enhancement-type NMOS transistor 24, a switch circuit 25, an input terminal 11, an output terminal 12, and a control terminal 13.

[0046] The source and gate of NMOS transistor 21 are connected to the ground terminal, and the drain is connected to the input terminal of the current mirror circuit. PMOS transistor 22 and PMOS transistor 23 form a current mirror circuit. The drain of NMOS transistor 24 is connected to output terminal 12 and the output terminal of the current mirror circuit, and the gate is connected to input terminal 11. Switch circuit 25, which is controlled by enable signal EN input from control terminal 13, is connected, for example, between the source of NMOS transistor 24 and the ground terminal.

[0047] The startup circuit 30 includes a depletion-type NMOS transistor 31 serving as a current source, an enhancement-type PMOS transistor 32 and an enhancement-type PMOS transistor 33 forming a current mirror circuit, a current detection circuit 34, and an output terminal 14. The current detection circuit 34 is formed, for example, of a depletion-type NMOS transistor having a gate and a source connected thereto.

[0048] The source and gate of NMOS transistor 31 are connected to the ground terminal, and the drain is connected to the input terminal of the current mirror circuit. PMOS transistor 32 and PMOS transistor 33 form a current mirror circuit. Current detection circuit 34 is connected between the output terminal of the current mirror circuit and the ground terminal, and its output terminal is connected to output terminal 14.

[0049] Next, the operation of the voltage detector 1 will be described.

[0050] First, the operation of the voltage detection circuit 20 will be described.

[0051] When the startup circuit 30 outputs a signal indicating enable, the voltage detection circuit 20 switches the signal output from the output terminal 12 from a high level (e.g., power supply terminal voltage) to a low level (e.g., ground terminal voltage) when the voltage VIN of the input terminal 11 becomes equal to or higher than the detection voltage.

[0052] NMOS transistor 21 is a current source and generates a first reference current. A current mirror circuit formed by PMOS transistors 22 and 23 generates and outputs a second reference current based on the input first reference current. Switch circuit 25 is controlled by an enable signal EN input to control terminal 13. It is turned on when the enable signal EN is at a high level, indicating enable, and turned off when the enable signal EN is at a low level, indicating disable. When switch circuit 25 is on, a second reference current corresponding to the first reference current output by the current mirror circuit is input to the drain of NMOS transistor 24.

[0053] The detection voltage of the voltage detection circuit 20 becomes the gate voltage when the second reference current flows between the drain and source of the NMOS transistor 24. When the first reference current and the second reference current are equal and the aspect ratios of the NMOS transistors 21 and 24 are the same, the threshold voltage of the NMOS transistor 21 is set to Vt 21 , set the threshold voltage of NMOS transistor 24 to Vt 24 When Vt 24 +|Vt 21 The temperature characteristics of the detection voltage can be made substantially flat by setting the NMOS transistor 21 and the NMOS transistor 24 to have substantially the same aspect ratio (W length / L length).

[0054] The minimum operating power supply voltage of the voltage detection circuit 20 will be described.

[0055] In order to make the first reference current a predetermined current, the NMOS transistor 21 and the PMOS transistor 22 need to operate in the saturation region together. The power supply voltage for operating the NMOS transistor 21 and the PMOS transistor 22 in the saturation region together is Vov 22 +|Vt 22 |+|Vt 21 |Above. Vt 21 is the threshold voltage of the NMOS transistor 21, Vt 22 is the threshold voltage of the PMOS transistor 22, Vov 22 is an overdrive voltage at which the first reference current can flow through the PMOS transistor 22. That is, the power supply voltage is the lowest operating power supply voltage of the voltage detection circuit 20.

[0056] Here, regarding the first reference current, the current flowing through the NMOS transistor 21 is reduced, and the driving capability of the PMOS transistor 22 is set to be large. By setting in this way, Vov 22 with |Vt 22 |or|Vt 21| is a negligible value compared to |. Therefore, the minimum operating power supply voltage of the voltage detection circuit 20 becomes |Vt 22 |+|Vt 21 |. |Vt 22 | has a negative temperature characteristic, |Vt 21 | has a positive temperature characteristic, so the minimum operating power supply voltage of the voltage detection circuit 20 changes less with temperature. For example, at room temperature, | Vt 22 | is set to 0.2V, and |Vt 21 | is set to 0.2V. The minimum operating power supply voltage at room temperature becomes 0.4V, but |Vt 22 |with|Vt 21 | To offset temperature changes, the minimum operating power supply voltage at a high temperature of 85°C remains at 0.4V.

[0057] Therefore, the voltage detector 1 of this embodiment can suppress an increase in the minimum operating power supply voltage at high temperatures, and thus can reduce the minimum operating power supply voltage.

[0058] Next, the operation of the start-up circuit 30 will be described.

[0059] NMOS transistor 31 is a current source and outputs a third reference current. A current mirror circuit formed by PMOS transistor 32 and PMOS transistor 33 outputs a fourth reference current based on the input third reference current. When current detection circuit 34 detects that the fourth reference current has reached or exceeded a predetermined current, startup circuit 30 outputs a high-level enable signal EN from its output terminal to output terminal 14. For example, the aspect ratio of the NMOS transistor constituting current detection circuit 34 can be set slightly smaller than that of NMOS transistor 31.

[0060] The minimum operating power supply voltage of the start-up circuit 30 will be described.

[0061] In order to make the third reference current a predetermined current, it is necessary for the NMOS transistor 31 and the PMOS transistor 32 to operate in the saturation region. The power supply voltage for operating the NMOS transistor 31 and the PMOS transistor 32 in the saturation region is Vov 32 +|Vt 32 |+|Vt 31 |Above. Vt 31 is the threshold voltage of the NMOS transistor 31, Vt 32 is the threshold voltage of the PMOS transistor 32, Vov 32is the overdrive voltage of the PMOS transistor 32 required to flow the third reference current. That is, the power supply voltage is the minimum operating power supply voltage of the startup circuit 30. Furthermore, when the power supply voltage is lower than the minimum operating power supply voltage, the output terminal 14 is pulled down to a low level by the current detection circuit 34.

[0062] Here, regarding the third reference current, the current flowing through the NMOS transistor 31 is reduced, and the driving capability of the PMOS transistor 32 is set to be large. By setting in this way, Vov 32 with |Vt 32 |or|Vt 31 | is a negligible value compared to |. Therefore, the minimum operating power supply voltage of the startup circuit 30 becomes |Vt 32 |+|Vt 31 That is, similarly to the voltage detection circuit 20, the increase in the minimum operating power supply voltage at high temperatures can be suppressed, and thus the minimum operating power supply voltage can be lowered.

[0063] Next, an example of the relationship between the voltage detection circuit 20 and the start-up circuit 30 will be described.

[0064] The third reference current of the startup circuit 30 is set equal to the first reference current of the voltage detection circuit 20. The aspect ratio of the PMOS transistors 22 and 23 of the voltage detection circuit 20 is set to 1 (e.g., W = 10 μm, L = 10 μm). The aspect ratio of the PMOS transistors 32 and 33 of the startup circuit 30 is set to 0.8 (e.g., W = 8 μm, L = 10 μm).

[0065] In order to flow a predetermined current, the current mirror circuit requires the MOS transistor to operate in a saturation region. Therefore, the smaller the aspect ratio of the MOS transistor, the higher the drain-source voltage is required.

[0066] When set as described above, the power supply voltage required for the third reference current to flow through PMOS transistor 32 is higher than the power supply voltage required for the first reference current to flow through PMOS transistor 22. In other words, the minimum operating power supply voltage of startup circuit 30 is higher than the minimum operating power supply voltage of voltage detection circuit 20.

[0067] Therefore, the voltage detection circuit 20 is in a stably operating state when the startup circuit 30 outputs the enable signal EN at a high level.

[0068] Furthermore, by making the aspect ratio of the NMOS transistor 31 slightly larger than that of the NMOS transistor 21 , the minimum operating power supply voltage of the startup circuit 30 can be made higher than the minimum operating power supply voltage of the voltage detection circuit 20 .

[0069] Figure 2 This is a circuit diagram showing another example of the voltage detector according to this embodiment.

[0070] Figure 2 The voltage detector 1 includes a current source circuit 40 instead of the current source 21 and the current source 31 .

[0071] The current source circuit 40 includes a depletion-type NMOS transistor 41 serving as a current source and an enhancement-type NMOS transistor 42 forming a current mirror circuit.

[0072] The voltage detection circuit 20 includes an NMOS transistor 42, which replaces the current source 21, and an enhancement-type NMOS transistor 26, which forms a current mirror circuit. Furthermore, the voltage detection circuit 20 includes a switch circuit 25 between the output terminal 12 and the power supply terminal. The switch circuit 25 is controlled by an enable signal EN input to the control terminal 13, turning on when the enable signal EN is at a low level and off when the enable signal EN is at a high level. Specifically, the output terminal 12 is pulled up to the power supply voltage when the voltage detection circuit 20's operating power supply voltage is lower than the power supply voltage.

[0073] The startup circuit 30 includes an NMOS transistor 42 that replaces the current source 31 and an enhancement-type NMOS transistor 35 that constitutes a current mirror circuit.

[0074] Figure 2 The voltage detector 1 and Figure 1 The basic circuit operation of the voltage detector 1 is the same, and the relationship between the minimum operating power supply voltage of the voltage detection circuit 20 and the starting circuit 30 is also the same.

[0075] When the current source 21 and the current source 31 are designed to satisfy Figure 1 When the size becomes larger due to the conditions required by the circuit, Figure 2 The voltage detector 1 is effective as a method of reducing the size.

[0076] As described above, according to the voltage detector of this embodiment, the constant current source of the voltage detection circuit 20 is formed by a depletion-type NMOS transistor and a current mirror circuit, and the startup circuit 30 is included to detect when the power supply voltage becomes equal to or higher than the minimum operating power supply voltage of the voltage detection circuit 20. Therefore, the temperature characteristic of the detection voltage is flat, and the minimum operating power supply voltage is low, and no false detection occurs when the voltage is lower than the minimum operating power supply voltage.

[0077] Furthermore, the present invention is not limited to the above-described embodiments and can be implemented in various forms. Furthermore, various omissions, additions, substitutions, or modifications may be made without departing from the gist of the invention. These embodiments and their variations are intended to be within the scope and gist of the invention and are intended to be within the scope of the invention recited in the claims and their equivalents.

[0078] For example, the same effect can be achieved by replacing all NMOS transistors with PMOS transistors and reversing the circuit configuration. Furthermore, if, for example, the switch circuit 25 operates to control the output of the detection signal DET based on the enable signal EN, the location of the switch circuit 25 is not limited to these circuit diagrams. Furthermore, while an example is shown in which the current detection circuit 34 is configured using a depletion-type NMOS transistor with its gate and source connected, this is not a limitation. For example, the current detection circuit 34 may also be configured using a resistor, etc. Furthermore, for example, the logic of the signals of the voltage detector 1, the voltage detection circuit 20, and the startup circuit 30 may be modified as appropriate.

Claims

1. A voltage detector, characterized in that Including voltage detection circuit and startup circuit, The voltage detection circuit comprises: a first current source, one end of which is connected to the first power supply terminal and is composed of a depletion-type metal oxide semiconductor transistor; a first current mirror circuit, having an input terminal connected to the other end of the first current source and inputting the current of the first current source; a first enhancement-mode metal oxide semiconductor transistor, having a gate connected to the input terminal, a drain connected to the output terminal and the output terminal of the first current mirror circuit, and inputting the output current of the first current mirror circuit; and The switch circuit is controlled by the enable signal input to the control terminal. The startup circuit comprises: a second current source; a second current mirror circuit, inputting the current of the second current source; and The current detection circuit outputs the enable signal indicating enable when detecting the output current input to the second current mirror circuit and the output current becomes equal to or greater than a predetermined current. The voltage detection circuit outputs a detection signal corresponding to the voltage of the input terminal from the output terminal when the switch circuit receives the enable signal indicating enable from the startup circuit.

2. The voltage detector according to claim 1, wherein: The minimum operating power supply voltage of the startup circuit is set higher than the minimum operating power supply voltage of the voltage detection circuit.

3. The voltage detector according to claim 2, wherein: When the switch circuit receives the enable signal indicating enable, the first current mirror circuit outputs a current corresponding to the current of the first current source.

4. The voltage detector according to claim 1, wherein: comprising a current source circuit having a fourth current source, The first current source is formed by a third current mirror circuit, and the third current mirror circuit outputs a current based on the current of the fourth current source. The second current source is formed of a fourth current mirror circuit, and the fourth current mirror circuit outputs a current based on a current of the fourth current source.

5. The voltage detector according to claim 1, wherein: The switch circuit is connected between the source of the first metal oxide semiconductor transistor and the first power terminal.

6. The voltage detector according to claim 1, wherein: The switch circuit is connected between the output terminal of the voltage detection circuit and a second power supply terminal.

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