Voltage selector

Abstract

The voltage selector includes a first input for receiving a first input voltage, a second input for receiving a second input voltage, an output, a main selection circuit, and a reference circuit. The main selection circuit includes a selection unit for outputting a higher input voltage as an output voltage to the output terminal, and an auxiliary unit for pulling up the output voltage to the first input voltage according to the reference voltage when the first input voltage is equal to the second input voltage. The reference circuit pulls up the reference voltage according to the higher one of the first input voltage and the second input voltage, and pulls down the reference voltage when the first input voltage is equal to the second input voltage and the output voltage is lower than the first input voltage by a threshold voltage.

Description

Technical Field

[0001] The present disclosure relates to a voltage selector, and more particularly to a voltage selector with feedback control capability.

[0002] Prior Art

[0003] As electronic circuits become increasingly complex, they may require different voltage levels to perform different operations. For example, non-volatile memory circuits require a normal system voltage for read operations but a higher voltage for write operations. In this case, a voltage selector can be used to switch between different voltages depending on the operation being performed.

[0004] A voltage selector is designed to receive input voltages from two different input terminals and output the higher of the two input voltages. However, in conventional technology, when the two input voltages are at the same potential, the output terminal of the voltage selector becomes floating, causing the voltage selector to become unstable and risk leakage.

[0005] This prior art section provides background information only. The statements in this prior art section are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this prior art section shall be used as an admission that any part of this application (including this prior art section) constitutes prior art to the present disclosure. Summary of the Invention

[0006] One embodiment of the present disclosure provides a voltage selector. The voltage selector includes a first input terminal, a second input terminal, an output terminal, a main selection circuit, and a reference circuit. The first input terminal receives a first input voltage, and the second input terminal receives a second input voltage. The output terminal outputs an output voltage. The main selection circuit includes a selection unit and an auxiliary unit. The selection unit includes a first transistor coupled to the first input terminal and the output terminal, and a second transistor coupled to the second input terminal and the output terminal. When the first input voltage is higher than the second input voltage, the first transistor is turned on, and when the second input voltage is higher than the first input voltage, the second transistor is turned on. When the first input voltage is equal to the second input voltage, the auxiliary unit is controlled by a reference voltage and enabled to turn on at least one of a first electrical path between the first input terminal and the output terminal or a second electrical path between the second input terminal and the output terminal, thereby pulling up the output voltage. The reference circuit includes a pull-down unit. When the first input voltage is equal to the second input voltage and the output voltage is lower than the first input voltage by a threshold voltage, the pull-down unit pulls down the reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claims in conjunction with the accompanying drawings. Like reference numerals in different drawings refer to like elements.

[0008] Figure 1 A voltage selector according to a comparative embodiment of the present disclosure is shown.

[0009] Figure 2 A voltage selector according to an embodiment of the present disclosure is shown.

[0010] Figure 3 An embodiment of the present disclosure is shown. Figure 1 The voltage timing diagram of the input, output, and reference terminals of the voltage selector is shown.

[0011] Figures 4 to 8 FIG. 1 illustrates charging and discharging behaviors of a voltage selector during different periods according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] This application claims priority to and the benefit of U.S. Provisional Application No. 63 / 554,164, filed on February 16, 2024, and U.S. Regular Application No. 18 / 989,239, filed on December 20, 2024, the contents of which are incorporated herein by reference in their entirety.

[0013] Figure 1 A voltage selector 900 according to a comparative embodiment of the present disclosure is shown. The voltage selector 900 includes input terminals IN1 and IN2, P-type transistors M1P and M2P, and an output terminal OUT. The P-type transistor M1P includes a first terminal, a second terminal, and a control terminal. The first terminal of the P-type transistor M1P is coupled to the input terminal IN1 and is used to receive a first input voltage V1. The second terminal of the P-type transistor M1P is coupled to the output terminal OUT. The control terminal of the P-type transistor M1P is coupled to the input terminal IN2 and is used to receive a second input voltage V2. The P-type transistor M2P includes a first terminal, a second terminal, and a control terminal. The first terminal of the P-type transistor M2P is coupled to the input terminal IN2 and is used to receive the second input voltage V2. The second terminal of the P-type transistor M2P is coupled to the output terminal OUT. The control terminal of the P-type transistor M2P is coupled to the input terminal IN1 and is used to receive the first input voltage V1.

[0014] When the first input voltage V1 is higher than the second input voltage V2 (for example, V1 is 5V and V2 is 0V), the P-type transistor M1P is turned on and the P-type transistor M2P is turned off. In this case, the output terminal OUT outputs the first input voltage V1 as the output voltage VOUT.

[0015] However, when the first input voltage V1 and the second input voltage V2 are at the same potential (e.g., V1 and V2 are both 5V), both P-type transistors M1P and M2P are turned off, and the output terminal OUT becomes floating. In this case, the output voltage VOUT is pulled down by the load current, causing instability in the system using the voltage selector 900.

[0016] Figure 2 A voltage selector 100 according to an embodiment of the present disclosure is shown. The voltage selector 100 includes input terminals IN1 and IN2, an output terminal OUT, a main selection circuit 110, and a reference circuit 120.

[0017] Input terminal IN1 can receive a first input voltage V1, and input terminal IN2 can receive a second input voltage V2. Main selection circuit 110 includes a selection unit 112 and an auxiliary unit 114. When the first input voltage V1 is higher than the second input voltage V2, selection unit 112 can conduct an electrical path between input terminal IN1 and output terminal OUT. Furthermore, when the second input voltage V2 is higher than the first input voltage V1, selection unit 112 can conduct an electrical path between second input terminal IN2 and output terminal OUT. In this way, selection unit 112 can output the higher of input voltages V1 and V2.

[0018] When the first input voltage V1 is substantially equal to the second input voltage V2, the auxiliary unit 114 can conduct at least one of the electrical path between the input terminal IN1 and the output terminal OUT or the electrical path between the input terminal IN2 and the output terminal OUT based on the reference voltage VR. That is, when the first input voltage V1 is substantially equal to the second input voltage V2 and the output voltage VOUT is pulled down by the load current, the output terminal OUT can be charged via the electrical path connected to the input terminal IN1 and / or the electrical path connected to the input terminal IN2 conducted by the auxiliary unit 114. In this way, even when the first input voltage V1 is substantially equal to the second input voltage V2, the output terminal OUT does not float, and the output voltage VOUT can be adjusted to a voltage close to the first input voltage V1 or the second input voltage V2.

[0019] Reference circuit 120 generates a reference voltage VR, enabling auxiliary unit 114 to accordingly conduct an electrical path connected to input terminal IN1 and / or an electrical path connected to input terminal IN2. Reference circuit 120 includes a pull-up unit 122 and a pull-down unit 124. Pull-up unit 122 pulls up reference voltage VR based on the higher of first input voltage V1 and second input voltage V2. When first input voltage V1 equals second input voltage V2, pull-down unit 124 pulls down reference voltage VR. Thus, reference voltage VR can be properly controlled in various situations, thereby ensuring the stability of voltage selector 100.

[0020] Since the voltage selector 100 can maintain the stability of the output voltage VOUT regardless of whether one of the first input voltage V1 and the second input voltage V2 is higher than the other or the input voltage V1 and the second input voltage V2 are substantially the same, the voltage selector 100 helps reduce the risk of leakage current and improves the safety of the system using the voltage selector 100.

[0021] like Figure 2 As shown, the selection unit 112 may include P-type transistors M1P and M2P. The first P-type transistor M1P includes a first terminal, a second terminal, and a control terminal. The first terminal of the P-type transistor M1P is coupled to the input terminal IN1, the second terminal of the P-type transistor M1P is coupled to the output terminal OUT, and the control terminal of the P-type transistor M1P is coupled to the input terminal IN2. The P-type transistor M2P includes a first terminal, a second terminal, and a control terminal. The first terminal of the P-type transistor M2P is coupled to the input terminal IN2, the second terminal of the P-type transistor M2P is coupled to the output terminal OUT, and the control terminal of the P-type transistor M2P is coupled to the input terminal IN1. In addition, each of the P-type transistors M1P and M2P includes a base terminal coupled to the output terminal OUT.

[0022] Auxiliary unit 114 may include P-type transistors M3P and M4P. P-type transistor M3P includes a first terminal, a second terminal, and a control terminal. The first terminal of P-type transistor M3P is coupled to input terminal IN1, the second terminal of P-type transistor M3P is coupled to output terminal OUT, and the control terminal of P-type transistor M3P can receive reference voltage VR. P-type transistor M4P includes a first terminal, a second terminal, and a control terminal. The first terminal of P-type transistor M4P is coupled to input terminal IN2, the second terminal of P-type transistor M4P is coupled to output terminal OUT, and the control terminal of P-type transistor M4P can receive reference voltage VR. In addition, each of P-type transistors M3P and M4P includes a base terminal coupled to output terminal OUT.

[0023] The pull-up unit 122 may include a reference terminal REF for outputting a reference voltage VR, and P-type transistors M5P, M6P, M7P, and M8P. P-type transistor M5P includes a first terminal, a second terminal, and a control terminal. The first terminal of P-type transistor M5P is coupled to input terminal IN1, and the control terminal of P-type transistor M5P is coupled to input terminal IN2. P-type transistor M6P includes a first terminal, a second terminal, and a control terminal. The first terminal of P-type transistor M6P is coupled to the second terminal of P-type transistor M5P, the second terminal of P-type transistor M6P is coupled to reference terminal REF, and the control terminal of P-type transistor M6P is coupled to output terminal OUT. P-type transistor M7P includes a first terminal, a second terminal, and a control terminal. The first terminal of P-type transistor M7P is coupled to input terminal IN2, and the control terminal of P-type transistor M7P is coupled to input terminal IN1. P-type transistor M8P includes a first terminal, a second terminal, and a control terminal. A first terminal of P-type transistor M8P is coupled to a second terminal of P-type transistor M7P, a second terminal of P-type transistor M8P is coupled to a reference terminal REF, and a control terminal of P-type transistor M8P is coupled to an output terminal OUT. Furthermore, P-type transistors M5P, M6P, M7P, and M8P are formed on the same N-type well, and well-junction diodes D5-D8 are formed between the source / drain terminals of P-type transistors M5P, M6P, M7P, and M8P and the N-type well. Well-junction diodes D5-D8 can be considered a single effective diode. Therefore, each of P-type transistors M5P, M6P, M7P, and M8P further includes a base terminal coupled to each other, and the bodies of P-type transistors M5P, M6P, M7P, and M8P are further coupled to the reference terminal REF.

[0024] The pull-down unit 124 may include two current mirrors 1241 and 1242. The current mirrors 1241 and 1242 may be coupled to the input terminal IN1 and the second terminal IN2, respectively, and may conduct a discharge current according to the output voltage VOUT to pull down the reference voltage VR.

[0025] In some embodiments, current mirror 1241 may include a P-type transistor M9P and N-type transistors M1N and M2N. P-type transistor M9P includes a first terminal, a second terminal, and a control terminal. The first terminal of P-type transistor M9P is coupled to input terminal IN1, and the control terminal of P-type transistor M9P is coupled to output terminal OUT. N-type transistor M1N includes a first terminal, a second terminal, and a control terminal. The first terminal of N-type transistor M1N is coupled to the second terminal of P-type transistor M9P, the second terminal of N-type transistor M1N is coupled to system terminal NS for receiving a system voltage VS, and the control terminal of N-type transistor M1N is coupled to the first terminal of N-type transistor M1N. In some embodiments, system terminal NS may be ground, and the system voltage may be ground. N-type transistor M2N includes a first terminal, a second terminal, and a control terminal. The first terminal of N-type transistor M2N is coupled to reference terminal REF, the second terminal of N-type transistor M2N is coupled to system terminal NS, and the control terminal of N-type transistor M2N is coupled to the control terminal of N-type transistor M1N. In addition, the P-type transistor M9P further includes a base terminal coupled to the output terminal OUT, and the N-type transistors M1N and M2N each further include a base terminal coupled to the system terminal NS.

[0026] Furthermore, current mirror 1242 may include a P-type transistor M10P, and N-type transistors M3N and M4N. P-type transistor M10P includes a first terminal, a second terminal, and a control terminal. The first terminal of P-type transistor M10P is coupled to input terminal IN2, and the control terminal of P-type transistor M10P is coupled to output terminal OUT. N-type transistor M3N includes a first terminal, a second terminal, and a control terminal. The first terminal of N-type transistor M3N is coupled to the second terminal of P-type transistor M10P, the second terminal of N-type transistor M3N is coupled to system terminal NS, and the control terminal of N-type transistor M3N is coupled to the first terminal of N-type transistor M3N. N-type transistor M4N includes a first terminal, a second terminal, and a control terminal. The first terminal of N-type transistor M4N is coupled to reference terminal REF, the second terminal of N-type transistor M4N is coupled to system terminal NS, and the control terminal of N-type transistor M4N is coupled to the control terminal of N-type transistor M3N. In addition, the P-type transistor M10P further includes a base terminal coupled to the output terminal OUT, and the N-type transistors M3N and M4N each further include a base terminal coupled to the system terminal NS.

[0027] Figure 3 FIG. 4 shows a voltage timing diagram of the input terminals IN1 and IN2 , the output terminal OUT, and the reference terminal REF according to an embodiment of the present disclosure. Figures 4 to 8 According to an embodiment of the present disclosure, Figure 3 The charging and discharging behaviors of the voltage selector 100 in different periods.

[0028] exist Figure 3During the period T1 shown, the first input voltage V1 becomes higher than the second input voltage V2. For example, the first input voltage V1 may be 5V and the second input voltage V2 may be 0V. In this case, Figure 4 As shown, the P-type transistor M1P is turned on, thereby completing the electrical path between the input terminal IN1 and the output terminal OUT. In this way, the circuit in which the P-type transistor M1P is turned on can charge the output terminal OUT, thereby pulling the output voltage VOUT up to a potential substantially the same as the first input voltage V1 (e.g., 5V).

[0029] Furthermore, during period T1, as the output voltage VOUT is pulled up to the first input voltage V1, P-type transistors M2P, M6P, M7P, M8P, M9P, and M10P are turned off, and the reference terminal REF is charged via the well-junction diodes D5-D8 of the P-type transistors M5P, M6P, M7P, and M8P. This pulls the reference voltage VR up to a level lower than the first input voltage V1 by the threshold voltage Vth of the effective diode formed by the well-junction diodes D5-D8. In some embodiments, if the threshold voltage Vth of the effective diode is 0.6V, the reference voltage VR is 4.4V during period T1.

[0030] During the period T2, the second input voltage V2 is also increased to the same potential as the first input voltage V1, for example, 5 V. In this case, the P-type transistors M1P, M2P, M5P, M6P, M7P, M8P, M9P, and M10P are turned off, while the P-type transistors M3P and M4P can be weakly turned on according to the potential of the reference voltage VR, as shown in FIG. Figure 5 In this case, if the load coupled to the output terminal OUT does not consume a large amount of current, the output voltage VOUT can be substantially maintained at the same potential as that during the period T1 (eg, 5V).

[0031] During the period starting from period T3, transistors M1P, M2P, M5P, M6P, M7P, M8P, M9P, and M10P are turned off, and the output voltage VOUT decreases, for example due to an increase in the load current. As the load current continues to discharge the output terminal OUT, the output voltage VOUT continues to decrease. However, when the output voltage VOUT is lower than the first input voltage V1 by the threshold voltage of the P-type transistors M9P and M10P, as shown in period T4, the P-type transistors M9P and M10P are turned on. In some embodiments, the P-type transistors M1P to M10P may have the same threshold voltage of 0.6V. Therefore, when the output voltage VOUT is reduced to 4.4V, the P-type transistors M9P and M10P are turned on. However, the present disclosure is not limited to this.

[0032] In period T4, if Figure 6 As shown, P-type transistors M9P and M10P are turned on, thus enabling current mirrors 1241 and 1242. In this case, N-type transistors M1N to M4N are also turned on, and the reference voltage VR is pulled down by the current conducted by N-type transistors M2N and M4N.

[0033] In the period T5 after the period T4, as the reference voltage VR is pulled low, the P-type transistor M3P and the P-type transistor M4P are turned on, so that the output terminal OUT can be charged. Figure 7 As shown in Figure 1 , the output voltage VOUT can be pulled up. Specifically, when the output voltage VOUT drops to a specific voltage, the current mirrors 1241 and 1242 in the pull-down unit 124 are activated, thereby pulling the reference voltage VR down to a specific voltage and turning on the P-type transistors M3P and M4P in the auxiliary unit 114. This further increases the output voltage VOUT. In some embodiments, the current mirrors 1241 and 1242 can be considered as a pair of simultaneously activated duplicate circuits to simultaneously pull down the reference voltage VR. In this case, if the pull-down capability is sufficient, one of the current mirrors 1241 and 1242 can be omitted. However, when the first input voltage V1 and the second input voltage V2 are not exactly the same, since the two current mirrors 1241 and 1242 are coupled to different input terminals IN1 and IN2, at least one of the current mirrors 1241 and 1242 will be activated accordingly, helping to improve stability.

[0034] Then, in the period T6 following the period T5, as the output voltage VOUT is gradually pulled up to a potential close to the first input voltage V1 or the second input voltage V2, the P-type transistors M9P and M10P are eventually turned off, and the current mirrors 1241 and 1242 are disabled. Figure 8 As shown, the well-junction diodes D5 - D8 of the P-type transistors M5P, M7P, M6P, and M8P can help pull up the reference voltage VR, so that the reference voltage VR returns to the previous potential of the reference voltage VR in the period T1 .

[0035] In some embodiments, the lower the output voltage VOUT is pulled during periods T3 and T4, the stronger the current conducted by current mirrors 1241 and 1242. In this case, reference voltage VR is pulled down to a lower potential, thereby enhancing the driving capability of P-type transistors M3P and M4P in auxiliary unit 114. Therefore, due to the feedback control scheme provided by voltage selector 100, output voltage VOUT can be compensated more quickly.

[0036] like Figure 3As shown in the timing diagram, when the first input voltage V1 and the second input voltage V2 are equal and the output voltage VOUT decreases due to an increase in load current, the voltage selector 100 can adjust the output voltage VOUT back to a potential close to the first input voltage V1 or the second input voltage V2, thereby preventing the risk of leakage current caused by floating the voltage terminal REF. Furthermore, because the reference voltage VR of the control auxiliary unit 114 can be controlled simultaneously by the pull-up drive capability provided by the pull-up unit 122 and the pull-down drive capability provided by the pull-down unit 124, the reference voltage VR is protected from the risk of noise coupling, enabling the voltage selector 100 to achieve excellent stability.

[0037] In some embodiments, to minimize the DC current conducted by P-type transistors M3P and M4P when one of the first input voltage V1 and the second input voltage V2 is higher than the other, P-type transistors M3P and M4P may be configured to have smaller dimensions. For example, the width-to-length ratio of P-type transistors M1P and M2P may be greater than the width-to-length ratio of P-type transistors M3P and M4P.

[0038] Furthermore, since the P-type transistors M5P to M8P need to charge the reference terminal REF through the well-junction diodes D5-D8, the P-type transistors M5P to M8P can have larger junction areas. For example, the junction areas of the P-type transistors M5P to M8P can be larger than the junction areas of the N-type transistors M2N and M4N.

[0039] Furthermore, to ensure that reference voltage VR can be pulled low when current mirrors 1241 and 1242 are enabled, the driving capability of N-type transistors M2N and M4N should be greater than the junction charging capability of P-type transistors M5P through M8P. For example, the width-to-length ratio of P-type transistors M5P through M8P can be smaller than the width-to-length ratio of N-type transistors M2N and M4N. Furthermore, because the current ratio of current mirrors 1241 and 1242 can be configured based on transistor size, the width-to-length ratio of N-type transistors M2N and M4N can be greater than the width-to-length ratio of N-type transistors M1N and M3N, thereby minimizing the DC current conducted by N-type transistors M1N and M3N.

[0040] In summary, the voltage selector provided in the embodiments of the present disclosure utilizes a feedback control scheme to control the output voltage in various scenarios, thereby avoiding the risk of leakage current caused by leaving the voltage terminal floating. Furthermore, because the voltage selector includes a pull-down unit and a pull-up unit, it can control the reference voltage to trigger output voltage compensation, thereby also avoiding the risk of noise coupling. Consequently, the voltage selector provided in the embodiments of the present disclosure achieves excellent stability.

[0041] Explanation of symbols

[0042] 900,100: Voltage selector

[0043] M1P, M2P, M3P, M4P, M5P: P-type transistors

[0044] M6P,M7P,M8P,M9P,M10P: P-type transistors M1N,M2N,M3N,M4N: N-type transistors

[0045] IN1, IN2: input terminal

[0046] V1, V2: input voltage

[0047] VOUT: output voltage

[0048] OUT: output terminal

[0049] 110: Main selection circuit

[0050] 112:Selection Unit

[0051] 114: Auxiliary unit

[0052] 120: Reference Circuit

[0053] 122: Pull-up unit

[0054] 124: Pull-down unit

[0055] VR: Reference voltage

[0056] REF: Reference end

[0057] NS: System side

[0058] 1241,1242: Current mirror

[0059] D5, D6, D7, D8: Well-junction diodes

[0060] Vth: threshold voltage

[0061] T1, T2, T3, T4, T5, T6: period

Claims

1. A voltage selector, characterized in that: Include: a first input terminal for receiving a first input voltage; a second input terminal for receiving a second input voltage; an output terminal for outputting an output voltage; A main selection circuit comprising: a selection unit comprising a first transistor coupled between the first input terminal and the output terminal, and a second transistor coupled between the second input terminal and the output terminal, wherein the first transistor is configured to be turned on when the first input voltage is higher than the second input voltage, and the second transistor is configured to be turned on when the second input voltage is higher than the first input voltage; as well as an auxiliary unit, configured to be enabled under the control of a reference voltage, and to conduct at least one of a first electrical path between the first input terminal and the output terminal or a second electrical path between the second input terminal and the output terminal when the first input voltage is equal to the second input voltage, so as to pull up the output voltage; and A reference circuit includes: A pull-down unit is used to pull down the reference voltage when the first input voltage is equal to the second input voltage and the output voltage is lower than the first input voltage by a threshold voltage, so as to enable the auxiliary unit to conduct the first electrical path or the second electrical path.

2. The voltage selector according to claim 1, wherein: a first transistor comprising a first terminal coupled to the first input terminal, a second terminal coupled to the output terminal, and a control terminal coupled to the second input terminal; a second transistor comprising a first terminal coupled to the second input terminal, a second terminal coupled to the output terminal, and a control terminal coupled to the first input terminal; and The first transistor and the second transistor are P-type transistors.

3. The voltage selector as claimed in claim 2, wherein the auxiliary unit comprises: a third P-type transistor comprising a first terminal coupled to the first input terminal, a second terminal coupled to the output terminal, and a control terminal for receiving the reference voltage; and A fourth P-type transistor includes a first terminal coupled to the second input terminal, a second terminal coupled to the output terminal, and a control terminal for receiving the reference voltage. 4 . The voltage selector as claimed in claim 3 , wherein base terminals of the first transistor, the second transistor, the third P-type transistor, and the fourth P-type transistor are coupled to the output terminal. 5 . The voltage selector as claimed in claim 3 , wherein the reference circuit further comprises a pull-up unit for pulling up the reference voltage according to a higher one of the first input voltage and the second input voltage.

6. The voltage selector as claimed in claim 5, wherein the pull-up unit comprises: a reference terminal for outputting the reference voltage; a fifth P-type transistor comprising a first terminal coupled to the first input terminal, a second terminal, and a control terminal coupled to the second input terminal; a sixth P-type transistor comprising a first terminal coupled to the second terminal of the fifth P-type transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to the output terminal; a seventh P-type transistor comprising a first terminal coupled to the second input terminal, a second terminal, and a control terminal coupled to the first input terminal; and An eighth P-type transistor includes a first terminal coupled to the second terminal of the seventh P-type transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to the output terminal. 7 . The voltage selector as claimed in claim 6 , wherein base terminals of the fifth P-type transistor, the sixth P-type transistor, the seventh P-type transistor, and the eighth P-type transistor are coupled to the reference terminal.

8. The voltage selector as claimed in claim 6, wherein the pull-down unit comprises a first current mirror coupled between the first input terminal and a system terminal, and the pull-down unit is controlled by the output voltage to be enabled to conduct a discharge current to pull down the reference voltage.

9. The voltage selector as claimed in claim 8, wherein the first current mirror comprises: a ninth P-type transistor comprising a first terminal coupled to the first input terminal, a second terminal, and a control terminal coupled to the output terminal; a first N-type transistor comprising a first terminal coupled to the second terminal of the ninth P-type transistor, a second terminal coupled to a system terminal, and a control terminal coupled to the first terminal of the first N-type transistor; and A second N-type transistor includes a first terminal coupled to the reference terminal, a second terminal coupled to the system terminal, and a control terminal coupled to the control terminal of the first N-type transistor.

10. The voltage selector as claimed in claim 9, wherein the pull-down unit further comprises a second current mirror comprising: a tenth P-type transistor comprising a first terminal coupled to the second input terminal, a second terminal, and a control terminal coupled to the output terminal; a third N-type transistor comprising a first terminal coupled to the second terminal of the tenth P-type transistor, a second terminal coupled to the system terminal, and a control terminal coupled to the first terminal of the third N-type transistor; and A fourth N-type transistor includes a first terminal coupled to the reference terminal, a second terminal coupled to the system terminal, and a control terminal coupled to the control terminal of the third N-type transistor.

11. The voltage selector as claimed in claim 10, wherein the base terminals of the ninth P-type transistor and the tenth P-type transistor are coupled to the output terminal, and the base terminals of the first N-type transistor, the second N-type transistor, the third N-type transistor, and the fourth N-type transistor are coupled to the system terminal.

12. The voltage selector as claimed in claim 10, wherein during a first period in which the first input voltage is equal to the second input voltage and the output voltage is lower than the first input voltage by the threshold voltage: The ninth P-type transistor and the tenth P-type transistor are turned on, so that the first current mirror and the second current mirror are enabled; and The reference voltage is pulled down by the current conducted by the second N-type transistor and the fourth N-type transistor.

13. The voltage selector as claimed in claim 12, wherein in a second period after the first period: As the reference voltage is pulled low, the third P-type transistor and the fourth P-type transistor are turned on to pull the output voltage high to one of the first input voltage and the second input voltage.

14. The voltage selector as claimed in claim 13, wherein in a third period after the second period: As the output voltage is pulled high, the ninth P-type transistor and the tenth P-type transistor are turned off, so that the first current mirror and the second current mirror are disabled; and The well-junction diodes of the fifth P-type transistor and the seventh P-type transistor pull up the reference voltage.

15. The voltage selector as claimed in claim 10, wherein during a period in which the first input voltage is higher than the second input voltage: The first transistor is turned on to pull the output voltage up to the first input voltage; and The second transistor, the third P-type transistor, the fourth P-type transistor, the sixth P-type transistor, the seventh P-type transistor, the eighth P-type transistor, the ninth P-type transistor, and the tenth P-type transistor are turned off. 16 . The voltage selector as claimed in claim 10 , wherein a driving capability of the first transistor is greater than a driving capability of the third P-type transistor. 17 . The voltage selector as claimed in claim 10 , wherein a width-to-length ratio of the first transistor is greater than a width-to-length ratio of the third P-type transistor.

18. The voltage selector as described in claim 10, wherein the junction areas of the well-junction diodes of the fifth P-type transistor, the sixth P-type transistor, the seventh P-type transistor, and the eighth P-type transistor are larger than the junction areas of the well-junction diodes of the second N-type transistor and the fourth N-type transistor. 19 . The voltage selector as claimed in claim 18 , wherein a width-to-length ratio of the fifth P-type transistor, the sixth P-type transistor, the seventh P-type transistor, and the eighth P-type transistor is smaller than a width-to-length ratio of the second N-type transistor and the fourth N-type transistor. 20 . The voltage selector as claimed in claim 10 , wherein a width-to-length ratio of the second N-type transistor and the fourth N-type transistor is greater than a width-to-length ratio of the first N-type transistor and the third N-type transistor.

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