Instruction processing method

Abstract

The invention discloses an instruction processing method, the method is suitable for a CPU in an assembly line mode, each assembly line comprises a plurality of assembly line levels, each assembly line level has different processing functions, and the method comprises the following steps: performing instruction matching based on first indication information representing an instruction and second indication information representing a first assembly line level, determining whether the instruction needs to be subjected to bypass processing at the first pipeline level or not; the first assembly line level is an assembly line level to be entered in an assembly line for processing the instruction; if the instruction needs to be subjected to bypass processing on the first assembly line level, the first assembly line level is stopped, and bypass processing corresponding to the first assembly line level is carried out; and after the bypass processing is completed, continuously processing the instruction through a second pipeline stage in the pipeline and recovering the first pipeline stage. By adopting the method, assembly line-level instruction processing can be realized.

Description

Technical Field

[0001] The present application relates to the technical field of computer instruction processing, and in particular to an instruction processing method. Background Art

[0002] With the continuous advancement of electronic technology, programmable logic devices (PLDs) and application-specific integrated circuits (ASICs) are increasingly being used in electronic systems. PLDs offer advantages such as high flexibility and reprogrammability, while ASICs excel in performance and power consumption. However, existing solutions combining PLDs and ASICs have limitations. They rely solely on programs interacting with pre-designed high-level programming interfaces, failing to achieve active collaboration at the hardware level and failing to fully leverage their synergistic advantages.

[0003] Existing solutions modify, add, or delete central processing unit (CPU) behaviors through microcode, which is essentially a program, not hardware logic. Modifying, adding, or deleting CPU behaviors through microcode is essentially a program transformation that lacks precise control over hardware logic. Furthermore, it relies on the CPU executing microcode flawlessly. In other words, if there are vulnerabilities in the CPU's logic implementation, the microcode may lose its ability to smoothly modify, add, or delete CPU behaviors. Summary of the Invention

[0004] The present application provides an instruction processing method for implementing pipeline-level instruction processing.

[0005] In the first aspect, an embodiment of the present application provides an instruction processing method, which is applicable to a CPU in pipeline mode, wherein each pipeline includes multiple pipeline stages, and each pipeline stage has different processing functions. The method includes: performing instruction matching based on first indication information representing the instruction and second indication information representing the first pipeline stage, and determining whether the instruction needs to be bypassed in the first pipeline stage; the first pipeline stage is the pipeline stage to be entered in the pipeline for processing the instruction; if the instruction needs to be bypassed in the first pipeline stage, then pausing the first pipeline stage and performing bypass processing corresponding to the first pipeline stage; after the bypass processing is completed, continuing to process the instruction through the second pipeline stage in the pipeline and restoring the first pipeline stage.

[0006] Using this approach, the CPU's main components can be implemented as an ASIC, while the instruction bypass unit can be implemented as a PLD. This ensures high performance and low power consumption for the CPU's main components while ensuring high flexibility in the instruction bypass unit's hardware logic. This allows the bypass processing hardware logic to be added, deleted, and modified at will, especially after the CPU leaves the factory.

[0007] Using this method, even if the CPU's main components are implemented as ASICs and their logic cannot be arbitrarily added, deleted, or modified, instructions can be routed to the instruction bypass unit for bypass processing at the target pipeline stage through instruction matching. This ensures that the hardware logic can be freely added, deleted, or modified for both instructions and pipeline stages. In other words, even if the pipeline (and individual pipeline stages) are implemented as ASICs and cannot be modified, instruction matching can be used to route specific pipeline stages to the instruction bypass unit for specific instructions. Because the instruction bypass unit is implemented as a programmable logic device (PLD) and possesses variable hardware logic, it can effectively "replace" a specific pipeline stage, "delete" an existing pipeline stage, or "insert" a new pipeline stage, thus enabling precise control of the hardware logic. This approach also combines the synergistic advantages of ASIC efficiency with the logic flexibility of PLDs, achieving active collaboration at the hardware level.

[0008] Using the above method, the instruction matcher can be implemented as either a programmable logic device (PLD) or an integrated circuit (ASIC). The instruction matcher can match the instruction to the first pipeline stage. After the first pipeline stage is matched, the first pipeline stage is paused and bypass processing corresponding to the first pipeline stage is performed. After the bypass processing is completed, the instruction is allowed to continue execution from the second pipeline stage. In this way, the combination of the instruction matcher and the instruction bypass unit enables the mutual cooperation of instructions at the pipeline level. When the specific method of instruction matching is more complex, it can be implemented as a PLD for greater customizability. When the performance of instruction matching is the primary concern, it can be implemented as an ASIC to speed up the instruction matching operation.

[0009] In one possible implementation, instruction matching is performed based on first indication information representing the instruction and second indication information representing the first pipeline stage to determine whether the instruction needs to be bypassed at the first pipeline stage, including: for any matching item, determining whether the first indication information representing the instruction matches the mask and target value in the matching item; if the instruction matches, determining whether the second indication information representing the first pipeline stage is any pipeline stage in the target pipeline stage list in the matching item; if so, determining that the instruction needs to be bypassed at the first pipeline stage; otherwise, determining that the instruction does not need to be bypassed at the first pipeline stage.

[0010] By using the above method, by setting the mask, target value, and target pipeline stage list in each matching item, the instructions and pipeline stages that need to be bypassed can be flexibly set, thereby improving the flexibility and simplicity of instruction matching.

[0011] In one possible implementation, before determining whether the first indication information representing the instruction matches the mask and target value in the matching item, it also includes: using the first indication information to query the matching instruction cache to determine that the first indication information does not belong to the matching instruction cache; the matching instruction cache includes the indication information of the representation instruction that can successfully match the mask and target value in any matching item and the target pipeline level list of the corresponding matching item.

[0012] Using the above method, the matching instruction cache is used to cache matching results. If the first indication information of the instruction is within the matching instruction cache, then the information stored in the matching instruction cache can be used to determine whether the first pipeline stage is any pipeline stage in the pipeline stage list of the matching item being matched, without the need to perform instruction matching again. If the first indication information of the instruction is not within the matching instruction cache, it cannot be determined whether the instruction successfully matches the mask and target value in the matching item, so instruction matching is required. In this way, determining the matching result of the instruction can be accelerated based on the matching instruction cache.

[0013] In one possible implementation, before performing instruction matching based on the first indication information representing the instruction and the second indication information representing the first pipeline level, it also includes: determining that the second indication information belongs to the total set of target pipeline levels, and the total set of target pipeline levels is obtained by summarizing the target pipeline level lists corresponding to each matching item.

[0014] Using the above method, the first pipeline stage may only require bypass processing if the second indication information of the first pipeline stage belongs to the total set of target pipeline stages. If the second indication information of the first pipeline stage does not belong to the total set of target pipeline stages, the first pipeline stage may not require bypass processing even if the first indication information of the instruction successfully matches the mask and the target value. In this way, based on the total set of target pipeline stages, it is possible to quickly determine whether the first pipeline stage of an instruction requires bypass processing.

[0015] In a possible implementation, the method further includes: if the second indication information does not belong to the total set of target pipeline stages, performing pipeline processing of the first pipeline stage on the instruction according to the pipeline.

[0016] In a possible implementation, stalling the first pipeline stage includes: inserting a bubble into the first pipeline stage in the pipeline, where the bubble has a characteristic of propagating to subsequent pipeline stages and the bubble does not require instruction matching.

[0017] In a possible implementation, the second pipeline stage is the first pipeline stage, or the next pipeline stage after the first pipeline stage in the pipeline, or any pipeline stage after the first pipeline stage in the pipeline.

[0018] In a possible implementation, the method is executed by an instruction matcher located in any pipeline stage; the any pipeline stage is any pipeline stage in the pipeline except the instruction fetch pipeline stage.

[0019] In a possible implementation, the method is executed by an instruction matcher located outside the pipeline.

[0020] In one possible implementation, if the instruction needs to be bypassed at the first pipeline stage, the first pipeline stage is paused, including: if the instruction needs to be bypassed at both the first pipeline stage and the third pipeline stage, the first pipeline stage is paused and the instruction bypass unit is instructing to bypass the instruction at the first pipeline stage and the third pipeline stage; the third pipeline stage is N consecutive pipeline stages located after the first pipeline stage in the pipeline; N is greater than or equal to 1.

[0021] By adopting the above method, for pipeline stages that need to be continuously bypassed in an instruction, the instruction bypass unit can complete the bypass processing of multiple pipeline stages at one time, and can merge the logic of continuous pipeline stages to eliminate intermediate results and improve the processing efficiency of continuous pipeline stages.

[0022] In one possible implementation, the target pipeline stage list in any matching item includes one or more consecutive pipeline stages in the pipeline.

[0023] In a possible implementation, before continuing to process the instruction through the second pipeline stage, the method further includes: determining whether the bubble inserted into the first pipeline stage reaches the second pipeline stage; otherwise, waiting for the bubble to reach the second pipeline stage.

[0024] In one possible implementation, the instruction is continued to be processed by the second pipeline stage in the pipeline, including: if the second pipeline stage is the first pipeline stage or the third pipeline stage, then the first indication information and the indication information corresponding to the second pipeline stage do not need to be matched with the instruction.

[0025] In one possible implementation, the instruction that requires bypass processing is used to obtain or record the current clock, and the target pipeline stage list in the matching item includes a write-back pipeline stage or a pipeline stage that accesses the clock; the result of the bypass processing is input to the second pipeline stage in the pipeline, replacing the data input of the second pipeline stage, and the result is clock information that is unrelated to the current clock or inaccurate clock information.

[0026] By adopting the above method, the instruction for obtaining or recording the current clock is set as the instruction that needs to be bypassed. By setting the instruction bypass result of the write-back pipeline stage or the instruction bypass result of the pipeline stage that accesses the clock to clock information that is unrelated to the current clock or inaccurate clock information, the side channel attack problem can be alleviated.

[0027] In one possible implementation, an instruction requiring bypass processing has an error in the CPU hardware implementation, and the error results in an unexpected instruction result; the result of the bypass processing is empty, and the target pipeline stage list in the matching item includes the pipeline stage located at the head of the pipeline, and the second pipeline stage is the pipeline stage located at the tail of the pipeline; or the result of the bypass processing is to cause an exception, and the target pipeline stage list in the matching item includes any pipeline stage.

[0028] By adopting the above method, an instruction with an error in the hardware implementation of the CPU that causes an unexpected result is set as an instruction that needs to be bypassed. By setting the instruction bypass result of the pipeline level of the instruction to empty or causing an exception, the erroneous execution of the illegal instruction can be corrected.

[0029] In a second aspect, an embodiment of the present application provides a central processing unit (CPU), which includes: an instruction matcher for executing a method as in any possible implementation of the first aspect; an instruction bypass unit for bypass processing the instruction based on the instruction of the instruction matcher, obtaining a bypass processing result and feeding it back to the instruction matcher.

[0030] In one possible implementation, the instruction matcher includes a bypass decision unit, a matching unit, and a matching item storage unit; the matching item storage unit stores at least one matching item; the bypass decision unit is used to obtain first indication information representing the instruction and second indication information representing the first pipeline stage; the matching unit is used to match the instruction based on the first indication information and each matching item; the bypass decision unit is also used to pause the first pipeline stage and restore the first pipeline stage if the instruction needs to be bypassed at the first pipeline stage.

[0031] In one possible implementation, the instruction matcher also includes a matching instruction cache; the matching instruction cache includes indication information representing instructions that can successfully match the mask and target value in any matching item and a target pipeline stage list of the corresponding matching item; the bypass decision unit is also used to use the first indication information to query the matching instruction cache before performing instruction matching through the matching unit to determine that the first indication information does not belong to the matching instruction cache.

[0032] In one possible implementation, the instruction matcher also includes a total set of target pipeline stages, which is obtained by summarizing the target pipeline stage lists corresponding to each matching item; the bypass decision unit is also used to determine that the second indication information belongs to the total set of target pipeline stages before instruction matching is performed through the matching unit.

[0033] In one possible implementation, the bypass decision unit is specifically used to generate an instruction matching request based on first indication information representing the instruction and send it to the matching unit; and receive the instruction matching result of the matching unit; the matching unit is specifically used to receive the instruction matching request, and after determining that there is a matching item that matches the first indication information, send the target pipeline level list in the matching item to the bypass decision unit; the bypass decision unit is also used to determine whether bypass processing is required based on the second indication information and the target pipeline level list.

[0034] In a third aspect, an embodiment of the present application provides an instruction processing device, which includes: a memory for storing computer programs or instructions; and a processor for calling the computer programs or instructions stored in the memory to execute a method as in any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0036] Figure 1 A schematic diagram of pipelined instruction processing provided in an embodiment of the present application; Figure 2 A flowchart corresponding to an instruction processing method provided in an embodiment of the present application; Figure 3 A schematic diagram of a pipeline-level instruction processing method provided in an embodiment of the present application; Figure 4 A schematic diagram of another pipeline-level instruction processing method provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of an instruction processing device 5000 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] To make the objectives, technical solutions, and advantages of this application more clear, this application will be further described in detail below with reference to the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0038] ASICs are integrated circuits designed specifically to meet the requirements of specific electronic systems. Their circuit structure and functionality are tailored to specific applications. Once an ASIC is manufactured, its internal logic is fixed and cannot be altered. Currently, if a logic flaw exists in an ASIC, there's no way to fundamentally fix it; mitigation is the only way to mitigate it. Mitigation solutions typically involve microcode, which is essentially a program, not hardware logic. While microcode can manipulate the operation and internal states of an ASIC, this is essentially a program transformation and cannot precisely control hardware logic. Furthermore, it relies on the ASIC executing the microcode without errors. A typical CPU is essentially an ASIC. Therefore, it's necessary to develop a method that allows for the precise modification, addition, and deletion of CPU behavior without disrupting normal operation due to logic vulnerabilities in the CPU.

[0039] Furthermore, existing PLD and ASIC integration solutions have certain limitations. They rely solely on programs interacting with pre-designed high-level programming interfaces, failing to achieve active collaboration at the hardware level and thus failing to fully leverage their synergy. Therefore, it is necessary to develop a method that enables PLD and ASIC to collaborate at a more detailed and fundamental level.

[0040] Based on this, an embodiment of the present application provides an instruction processing method for implementing pipeline-level instruction processing.

[0041] To facilitate understanding, some terms involved in this application are first explained.

[0042] An instruction is a shorthand term for a machine code instruction, the foundation of program execution. The core of a machine code instruction is its opcode. The decoder must first determine the opcode before it can determine the arrangement and meaning of the operands, and then send the instruction to the subsequent pipeline stages for execution according to the behavior defined in the instruction set.

[0043] Pipelining is an essential component of modern computer processors. It involves breaking down the instruction processing process into multiple steps and executing them in parallel across multiple hardware processing units to accelerate instruction execution. Pipelining is a fixed form of hardware logic. Pipelining implementations vary, and different CPUs may have varying numbers of pipeline stages. The most classic pipeline design is the five-stage pipeline. The five-stage pipeline consists of instruction fetch (IF), decode (ID), execute (EX), memory access (MEM), and write back (WB). IF fetches the instruction to be executed from memory; ID parses and interprets the fetched instruction; EX performs arithmetic, logical, and control transfer operations based on the decoded result, particularly the operation type and operands; MEM handles memory-related operations, including reading data and storing results; and WB writes the execution result to the corresponding register for subsequent instructions. Figure 1 A pipelined instruction processing diagram provided in an embodiment of the present application. Figure 1 It can be seen that Figure 1 The following diagram shows the execution of five instructions in the pipeline. Each instruction enters a different stage in a different clock cycle, and each rectangular box represents a stage of an instruction in the pipeline. It can be seen that under the same clock, the subsequent stage of one instruction can be executed, and the previous stage of another instruction can also be executed. This overlapping execution can improve processor efficiency. The embodiments of the present application do not limit the number of pipeline stages in the pipeline.

[0044] Figure 2 This is a flowchart corresponding to an instruction processing method provided in an embodiment of the present application. The method is applicable to a CPU in pipeline mode, where each pipeline includes multiple pipeline stages, each pipeline stage having different processing functions. The flowchart can be executed by the CPU, such as Figure 2 As shown, the process includes the following steps: In step 201, the CPU performs instruction matching based on first indication information representing the instruction and second indication information representing the first pipeline stage, and determines whether the instruction needs to be bypassed in the first pipeline stage, where the first pipeline stage is the pipeline stage to be entered in the pipeline for processing the instruction.

[0045] Specifically, the first indication information of the instruction can be the machine code of the instruction, the address of the instruction in memory, or the internal number of the instruction. The instruction can be determined based on the first indication information. The second indication information of the first pipeline stage can be indication information representing the name of the first pipeline stage, where the first pipeline stage is the pipeline stage to be entered in the pipeline for processing the instruction. Instruction matching is performed based on the first indication information representing the instruction and the second indication information of the first pipeline stage to determine whether the instruction needs to be bypassed in the first pipeline.

[0046] There are many ways to match instructions, including tree matching and graph matching. Optionally, instruction matching is performed based on first indication information representing the instruction and second indication information representing the first pipeline stage to determine whether the instruction needs to be bypassed at the first pipeline stage, including: for any matching item, determining whether the first indication information representing the instruction matches the mask and target value in the matching item; if the instruction matches, determining whether the second indication information representing the first pipeline stage is any pipeline stage in the target pipeline stage list in the matching item; if so, determining that the instruction needs to be bypassed at the first pipeline stage; otherwise, determining that the instruction does not need to be bypassed at the first pipeline stage.

[0047] Specifically, instruction matching can be achieved through target values and masks. Any matching item includes a mask and a target value. The mask is used to indicate the binary bits involved in the matching in each instruction; the target value is used to compare with the instruction to be matched. Any matching item also includes a target pipeline stage list. Any pipeline stage in the target pipeline stage list can be any one or more pipeline stages in the pipeline except instruction fetch. Matching is performed with each matching item based on the first indication information representing the instruction. If the first indication information representing the instruction successfully matches the mask and target value in the matching item, it is further determined whether the target pipeline stage list of the matching item in the match includes the first pipeline stage. If it does, it can be determined that the first pipeline stage of the instruction needs to be bypassed. Otherwise, the first pipeline stage of the instruction does not need to be bypassed. If bypassing is not required, the first pipeline stage is executed normally in the pipeline.

[0048] Take an 8-bit instruction and matching item as an example, as shown in Table 1.

[0049] Table 1

[0050] Here, 1 indicates that the binary bit is 1, 0 indicates that the binary bit is 0, and x indicates that the binary bit can have any value. As can be seen from Table 1, if the binary numbers of the instruction and the target value under the bit with the mask set to 1 are the same, then the instruction successfully matches the matching item. Furthermore, the matching item also includes a target pipeline stage list. For example, if the pipeline stage in the target pipeline stage list of the matching item is a decoding stage, and the pipeline stage to be entered in the pipeline of the instruction is a decoding stage, then the pipeline stage to be entered by the instruction needs to be bypassed; if the pipeline stage to be entered in the pipeline of the instruction is not a decoding stage, then the pipeline stage to be entered by the instruction is executed normally.

[0051] Optionally, the instruction set can be either a fixed-length or variable-length instruction set. Instructions in a variable-length instruction set are not unique in length. For variable-length instruction sets, the mask and target values are both of maximum length. Bits set to 0 in the mask allow non-existent bits to pass the match, but bits set to 1 in the mask require the corresponding bits in the instruction to exist. Instructions shorter than the maximum length can be matched in two ways: aligning the high bits or aligning the low bits. If instructions in a variable-length instruction set can be either 8 or 12 bits long, and the mask and target values are both 12 bits long, assuming that instructions shorter than the maximum length are aligned to the high bits during matching, then if at least four consecutive bits in the lowest order of the mask are 0, the match will match both 8-bit and 12-bit instructions. Conversely, if any of the four lowest order bits of the mask are 1, the match will only match 12-bit instructions.

[0052] Assuming that instructions shorter than the maximum length are aligned with the low bits during matching, then when the highest bit of the mask has at least 4 consecutive binary bits that are 0, this match can match both 8-bit long instructions and 12-bit long instructions; conversely, if any of the last 4 binary bits of the mask is 1, this match can only match 12-bit instructions.

[0053] Therefore, for variable-length instruction sets, the same match term may match instructions of two different lengths, which may seem ambiguous. However, this problem can be avoided by writing the match term appropriately.

[0054] For example, the instruction length of some variable-length instruction sets is directly determined by the opcode. Then, as long as the matching item includes the matching of the opcode, there is actually no ambiguity in the instruction length.

[0055] Therefore, to ensure that the match does not create instruction length ambiguity for variable-length instruction sets, ensure that the matching bits include the opcode bits. If matching the first-level opcode is sufficient to determine the instruction length, then only the first-level opcode bits are included. Otherwise, if matching the opcodes from levels 1 to n is sufficient to determine the instruction length, then the opcode bits from levels 1 to n are included.

[0056] Alternatively, some variable-length instruction sets may be too complex, so we can also add a new parameter to the matching item, namely the instruction length. This parameter is used to specify the expected instruction length of this matching item. If the instruction length is not equal to this parameter, then the match must be considered failed.

[0057] Optionally, an embodiment of the present application further includes a matching instruction cache, wherein the matching instruction cache includes indication information representing instructions that can successfully match the mask and target value in any matching item and a target pipeline stage list of the corresponding matching item, wherein the corresponding matching item represents a matching item that has successfully matched according to the matching instruction cache. Before determining whether the first indication information representing the instruction matches the mask and target value in the matching item, it also includes using the first indication information to query the matching instruction cache to determine that the first indication information does not belong to the matching instruction cache. This is because if the first indication information of the instruction belongs to the matching instruction cache, then it can be directly determined based on the information stored in the matching instruction cache whether the first pipeline stage belongs to the pipeline stage in the target pipeline stage list of the matching item in the match, and there is no need to perform instruction matching again; if the first indication information of the instruction does not belong to the matching instruction cache, it cannot be determined whether the instruction successfully matches the matching item, so instruction matching is required. In this way, the matching result of the instruction can be determined faster based on the matching instruction cache.

[0058] Optionally, an embodiment of the present application also includes a total set of target pipeline levels, and the total set of target pipeline levels is obtained by summarizing the target pipeline level lists corresponding to each matching item. In a complex pipeline, there can be as many as dozens of pipeline levels, and the target pipeline level lists corresponding to each matching item are counted to obtain the total set of target pipeline levels. Before performing instruction matching based on the first indication information representing the instruction and the second indication information representing the first pipeline level, it is also included to determine whether the second indication information belongs to the total set of target pipeline levels. This is because only if the second indication information of the first pipeline level belongs to the total set of target pipeline levels, the first pipeline level may need to be bypassed. If the second indication information of the first pipeline level does not belong to the total set of target pipeline levels, even if the first indication information of the instruction successfully matches the mask and target value of the matching item, the first pipeline level may not need to be bypassed. In this way, the determination of whether bypass processing is required for the first pipeline stage of an instruction can be accelerated based on the target pipeline stage set. For example, if a pipeline stage does not belong to the target pipeline stage set, then upon entering that pipeline stage, it is clear that bypass processing is not required, without even querying the instruction matching result. Furthermore, if the first pipeline stage does not belong to the target pipeline stage set, the instruction is pipeline-processed at the first pipeline stage according to the pipeline.

[0059] Step 202: If the instruction needs to be bypassed at the first pipeline stage, the first pipeline stage is paused and the bypass processing corresponding to the first pipeline stage is performed.

[0060] Furthermore, if it is determined that the instruction requires bypass processing at the first pipeline stage, the first pipeline stage is paused, and the processing results of the previous pipeline stage are sent to the bypass processing unit. Optionally, pausing the first pipeline stage includes inserting a bubble into the first pipeline stage in the pipeline. The bubble has the characteristic of propagating to subsequent pipeline stages and does not require instruction matching. The bubble will propagate to subsequent pipeline stages, thus ensuring that subsequent pipeline stages will not use the meaningless output of the previous pipeline stage due to the pause of the previous pipeline stage. If the bubble is inserted for other reasons, that is, not by the instruction matcher, such as to avoid danger, such a bubble will also cause the pipeline stage to pause and will propagate backward. The instruction matcher does not need to perform instruction matching on any bubble or query the matching instruction cache.

[0061] Step 203: After the bypass process is completed, the CPU continues to process the instruction through the second pipeline stage in the pipeline and resumes the first pipeline stage.

[0062] Specifically, after the instruction is processed by the bypass corresponding to the first pipeline stage, the instruction is continued to be processed by the second pipeline stage in the pipeline, and the first pipeline stage is restored. The second pipeline stage is the target pipeline stage for resumption of execution. The second pipeline stage can be the first pipeline stage, the next pipeline stage after the first pipeline stage in the pipeline, or any pipeline stage after the first pipeline stage in the pipeline. Restoring the first pipeline stage allows other instructions to continue to execute in the first pipeline stage.

[0063] Optionally, the above method is executed by an instruction matcher located in any pipeline stage in the CPU, and any pipeline stage is any pipeline stage in the pipeline except the instruction fetch pipeline stage, that is, the instruction matcher can complete instruction matching only after the instruction fetch has been completed.

[0064] In one possible implementation, continuing to process the instruction through the second pipeline stage in the pipeline also includes, if the bypass processing corresponding to the first pipeline stage produces a bypass processing result, inputting the bypass processing result into the second pipeline stage in the pipeline to replace the data input of the second pipeline stage.

[0065] For example, as shown in Table 2, there are five instructions, each of which will flow through five pipeline stages in sequence. After instruction 3 completes the instruction fetch stage, it is determined that instruction 3 requires bypass processing in pipeline stage 1 (the first pipeline stage). Therefore, starting from clock cycle 4, pipeline stage 1 is paused and instruction 3 is bypassed. As a result, instructions 4 through 5 cannot enter pipeline stage 1 for execution. The bypass processing takes two clock cycles. In clock cycle 6, after instruction 3 completes bypass processing in the first pipeline stage, processing continues in pipeline stage 2 (the second pipeline stage) and pipeline stage 1 is resumed (i.e., unpaused). Since the second pipeline stage is not the first pipeline stage, pipeline stage 1 will now process the subsequent instruction. Therefore, in clock cycle 6, instruction 4 enters pipeline stage 1 for execution. Simultaneously, since the second pipeline stage is pipeline stage 2, instruction 3 enters pipeline stage 2.

[0066] In this example, from the results, instruction 3 flows through the instruction fetch stage, the bypass processing corresponding to pipeline stage 1, pipeline stage 2, pipeline stage 3, and pipeline stage 4 in sequence, that is, pipeline stage 1 is replaced by bypass processing; the remaining instructions flow through all 5 pipeline stages in sequence.

[0067] The replacement of pipeline stage 1 with bypass processing depends on the specific logic implemented in the bypass processing. For example, the effects include but are not limited to the permutations and combinations of sub-operations of the following two operations: a) Replace pipeline stage 1 with an alternative implementation of pipeline stage 1 (possibly with bug fixes); or, skip pipeline stage 1.

[0068] b) A new pipeline stage is inserted before pipeline stage 1 (which may be an alternative implementation); and / or, a new pipeline stage is inserted after pipeline stage 1 (which may be an alternative implementation); or, no new pipeline stage is inserted.

[0069] The alternative implementation of pipeline stage 1 and the new pipeline stage are implemented in a bypass process.

[0070] Table 2

[0071] Figure 3 A schematic diagram of a pipeline-level instruction processing method provided in an embodiment of the present application is provided. Figure 3 The instruction matcher in can be located in any pipeline stage or can be independent of each pipeline stage. In both implementations, each pipeline stage can query the instruction matching result; the only constraint is that the instruction matching can only be performed after the instruction fetch is completed. Figure 3 It can be seen that after the instruction fetch stage, before the first pipeline stage is executed, it is checked whether the first pipeline stage needs to be bypassed. If the first pipeline stage is not in the total set of target pipeline stages, the pipeline stage is executed normally, that is, the first pipeline stage does not need to be bypassed. In this case, there is no need to consider whether the instruction matching is completed; if the first pipeline stage is in the total set of target pipeline stages, the first pipeline stage is paused and waits for the instruction matching. If the instruction matching is successful but the first pipeline stage does not belong to the target pipeline stage list of the matching items in the matching, the pipeline stage is also executed normally; if the instruction matching is successful and the first pipeline stage belongs to the target pipeline stage list of the matching items in the matching, the result of the previous pipeline stage is sent to the bypass. After the bypass processing is completed, the instruction is continued to be processed through the second pipeline stage in the pipeline and the first pipeline stage is restored.

[0072] Optionally, the above method may also be executed by an instruction matcher located outside the pipeline in the CPU. Figure 4 A schematic diagram of another pipeline-level instruction processing method provided in an embodiment of the present application is provided. Figure 4 The instruction matcher in is located outside the pipeline.

[0073] An embodiment of the present application also provides a CPU, which includes an instruction matcher and an instruction bypass unit. The instruction matcher is used to execute the above-mentioned instruction processing method, and the instruction bypass unit is used to bypass the instruction based on the instruction of the instruction matcher, obtain the bypass processing result and feed it back to the instruction matcher.

[0074] Optionally, the instruction matcher includes a bypass decision unit, a matching unit and a matching item storage unit, wherein the matching item storage unit stores at least one matching item, and the matching item storage unit provides matching items for use by the matching unit when performing matching. The matching item storage unit can also generate or update the total set of target pipeline stages.

[0075] Specifically, the bypass decision unit is configured to obtain first indication information representing an instruction and second indication information representing a first pipeline stage; and further configured to pause and resume the first pipeline stage if the instruction requires bypass processing at the first pipeline stage. The matching unit is configured to perform instruction matching based on the first indication information and each matching item.

[0076] For example, the bypass decision unit will receive the first indication information of the instruction to be processed by each pipeline stage and the second indication information of the pipeline stage. Such indication information may be output by the pipeline stage to the bypass decision unit, or may be input by other units in the CPU that maintain the pipeline state, which is not limited here. Figure 4 In the figure, the lines from each pipeline stage to the bypass decision unit are dashed, indicating that the pipeline stage does not necessarily output the instruction information directly. The matching unit receives the first instruction information from the bypass decision unit and matches the instruction based on the first instruction information and the matching items stored in the matching item storage unit. If a match is successful, the instruction matching result also includes a list of target pipeline stages for the corresponding matching items.

[0077] Optionally, the instruction matcher also includes a matching instruction cache for caching indication information of instructions that can successfully match the mask and target value in any matching item and a target pipeline stage list of the corresponding matching item. Before performing instruction matching on the first indication information of the instruction, the matching instruction cache is queried using the first indication information to determine whether the first indication information does not belong to the matching instruction cache; if it does, the target pipeline stage list can be determined directly based on the query result (i.e., the cached matching result). In this way, the bypass decision unit can quickly determine whether the instruction needs to perform instruction matching based on the matching instruction cache, and quickly obtain the cached matching result when querying for matching. Optionally, the matching instruction cache can store no fewer than the total number of pipeline stages in the cached results.

[0078] Optionally, the instruction matcher further includes a total set of target pipeline stages, where the total set of target pipeline stages includes a list of target pipeline stages corresponding to each matching item. Before performing instruction matching through the matching unit, it is determined whether the second indication information belongs to the total set of target pipeline stages; if not, it can be quickly determined that the first pipeline stage does not need to be bypassed and can continue to be processed by the first pipeline stage in the pipeline. It should be noted that if matching items are subsequently added, deleted, or modified, the total set of target pipeline stages may change.

[0079] Optionally, the bypass decision unit is further specifically configured to generate an instruction matching request based on the first indication information representing the instruction, and send the request to the matching unit; the matching unit receives the instruction matching request from the bypass decision unit, performs a match, determines the matching items that match the first indication information, and then sends the target pipeline stage list in the matching items to the bypass decision unit. The bypass decision unit is further configured to determine whether bypass processing is required based on the second indication information and the target pipeline stage list. In other words, the instruction matching request does not need to include the second indication information of the first pipeline stage, but only needs to include the first indication information of the instruction; the second indication information is processed by the bypass decision unit after the instruction is matched, as described above.

[0080] Specifically, the bypass decision unit determines whether the first pipeline stage needs to be paused based on certain criteria, such as when the instruction match has not yet completed and the first pipeline stage belongs to the total set of target pipeline stages. The pause at this point is to wait for the instruction match to complete before making a final decision on whether to bypass the process or execute normally. At this point, the first pipeline stage should be paused at least until the instruction match is completed, meaning that bubbles are continuously inserted into the first pipeline stage during this period. Subsequently, based on the result of the instruction match, a decision is made as to whether to bypass the first pipeline stage. If so, the first pipeline stage is paused until the instruction is bypassed; otherwise, the first pipeline stage is allowed to continue executing. For another example, a quick decision to pause the first pipeline stage can be made based on the cached instruction match result output by the matching instruction cache as described above; or a quick decision to not pause the first pipeline stage can be made based on the total set of target pipeline stages as described above.

[0081] It is understandable that if the first pipeline stage is the instruction fetch stage, there is no need to stall the first pipeline stage, because if the instruction fetch stage is stalled, no instructions can enter the pipeline.

[0082] If at least one matching item matches the instruction, and the target pipeline stage list in the matching item contains the first pipeline stage, the first pipeline stage also needs to be paused. The pause is to bypass the first pipeline stage and allow the instruction to enter the bypass. At this time, the first pipeline stage should be paused until the instruction bypass unit completes processing the instruction. Pausing the first pipeline stage can be inserting a bubble into the first pipeline stage. At the same time as or after inserting the bubble into the first pipeline stage, the instruction and the instruction information of the first pipeline stage and the input of the first pipeline stage are sent to the instruction bypass unit. The input of the first pipeline stage is the output of the previous pipeline stage in the pipeline. Based on this information, the instruction bypass unit can execute the instruction according to the specified behavior of the first pipeline stage. After execution, the result of the instruction bypass is returned to the bypass decision unit.

[0083] After receiving the instruction bypass result, the bypass decision unit stops inserting bubbles into the first pipeline stage and instead inserts the instruction bypass result into the input of the second pipeline stage, which is typically the stage immediately following the first. At this point, the second pipeline stage no longer receives the output of the preceding pipeline stage, but instead receives the instruction bypass result. In effect, the output of the preceding pipeline stage is now the output of the bubble, propagating the bubble to subsequent pipeline stages. By inserting the instruction bypass result into the second pipeline stage, it is effectively prevented from receiving bubbles, effectively terminating bubble propagation after the instruction bypass result is generated, allowing the pipeline to efficiently resume normal execution.

[0084] Furthermore, if there are multiple consecutive pipeline stages that need to be bypassed, for example, assuming that there are 3 consecutive pipeline stages that need to be bypassed, called A, B, and C, then after pipeline stage A completes the bypass, its bypass result is sent to the bypass decision unit and then output to pipeline stage B. Since pipeline stage B also needs to be bypassed, its input, that is, the bypass result of pipeline stage A, will be sent to the instruction bypass unit by the bypass decision unit, and pipeline stage B will also start to be inserted with cavitations at this time; after pipeline stage B completes the bypass, its bypass result is sent to the bypass decision unit and then output to pipeline stage C. Since pipeline stage C also needs to be bypassed, its input, that is, the bypass result of pipeline stage B, will be sent to the instruction bypass unit by the bypass decision unit, and pipeline stage C will also start to be inserted with cavitations at this time; wait until pipeline stage C completes the bypass. After the bypass is completed, the bypass result is sent to the bypass decision unit and then output to the subsequent pipeline stage to resume the normal execution of the pipeline.

[0085] The above process does not cause errors in the bypass execution results. However, because each consecutive pipeline stage needs to trigger instruction bypass separately, and the intermediate results, namely the bypass results of pipeline stages A and B, are forced to be transmitted repeatedly, it is inefficient. Furthermore, because the consecutively bypassed pipeline stages must be implemented separately in the instruction bypass unit, they must generate intermediate results, which is not conducive to optimizing the logic implementation in the instruction bypass unit. If these consecutively bypassed pipeline stages are implemented together, eliminating the intermediate results, more logic optimization can be applied. Therefore, the embodiments of the present application propose a more optimal implementation method.

[0086] Specifically, the target pipeline stage list in any matching item includes one or more consecutive pipeline stages. The first pipeline stage triggers a successful instruction match. The bypass decision unit can determine which pipeline stages need to be bypassed for this bypassed instruction based on the matched instruction matching item. Further, it determines which pipeline stages in the subsequent and consecutive pipeline stages adjacent to the first pipeline stage need to be bypassed. These pipeline stages, together with the first pipeline stage, constitute the set of consecutive pipeline stages that need to be bypassed. Among them, the first pipeline stage can also be called the first consecutive pipeline stage to be bypassed.

[0087] The bypass decision unit only needs to insert bubbles into the first pipeline stage, and there is no need to insert bubbles into other pipeline stages in the continuous pipeline stages that need to be bypassed. This is because bubbles will propagate backward, and other pipeline stages may be processing other instructions. Inserting bubbles into them rashly will destroy the processing results of other instructions; since bubbles propagate backward and bubbles do not participate in instruction matching and instruction bypass, other pipeline stages in the continuous pipeline stages that need to be bypassed will not trigger instruction matching due to this bypassed instruction.

[0088] It should be noted that bubbles need to be continuously inserted into the first pipeline stage during instruction bypass.

[0089] After or while inserting the bubble into the first pipeline stage, the bypass decision unit transmits the instruction and the input of the first pipeline stage to the instruction bypass unit, and also transmits a list of consecutive pipeline stages that need to be bypassed to the instruction bypass unit.

[0090] If the instruction needs to be bypassed at the first pipeline stage, the first pipeline stage is paused, including: if the instruction needs to be bypassed at both the first pipeline stage and the third pipeline stage, the first pipeline stage is paused and the instruction bypass unit is instructed to bypass the instruction at the first pipeline stage and the third pipeline stage, wherein the third pipeline stage is N consecutive pipeline stages located after the first pipeline stage in the pipeline, and N is greater than or equal to 1.

[0091] At this time, the first pipeline stage and the third pipeline stage together constitute the aforementioned continuous pipeline stage list that needs to be bypassed.

[0092] That is to say, the instruction bypass unit can complete the bypass processing of multiple pipeline stages at one time according to this list, that is, execute the instruction according to the specified behavior of these consecutive pipeline stages, but it is not necessary to implement the logic of these consecutive pipeline stages separately. Instead, the logic of these pipeline stages can be merged together to implement it.

[0093] When returning an instruction bypass result, the instruction bypass unit is further configured to specify a second pipeline stage; that is, to specify the pipeline stage into which the instruction bypass result should be inserted. In one possible implementation, the second pipeline stage is specified as the next pipeline stage after the third pipeline stage in the pipeline; that is, the second pipeline stage is specified as the next pipeline stage after the last pipeline stage in a list of consecutive pipeline stages to be bypassed.

[0094] In particular, before returning the bypass processing result of the bypassed instruction to the second pipeline stage in the pipeline, the method further includes: determining whether the bubble inserted into the first pipeline stage reaches the second pipeline stage; otherwise, waiting for the bubble to reach the second pipeline stage.

[0095] For example, as shown in Table 3, there are 5 instructions in total, and each instruction will flow through 5 pipeline stages in sequence. After instruction 3 completes the instruction fetch stage, since it is determined that instruction 3 needs to be bypassed in pipeline stage 1 (the first pipeline stage), pipeline stage 1 is paused and instruction 3 is bypassed starting from clock cycle 4. Therefore, instructions 4 to 5 cannot enter pipeline stage 1 for execution. The bypass processing takes a total of 2 clock cycles. At clock cycle 6, after the bypass processing corresponding to the first pipeline stage is completed, instruction 3 continues to be processed through pipeline stage 4 (the second pipeline stage) in the pipeline, and pipeline stage 1 is restored (that is, unpaused); since the second pipeline stage is not the first pipeline stage, pipeline stage 1 will process subsequent instructions at this time. Therefore, in clock cycle 6, instruction 4 enters pipeline stage 1 for execution; at the same time, since the second pipeline stage is pipeline stage 3, instruction 3 skips pipeline stages 2 and 3, and goes to pipeline stage 1. The first bubble inserted is inserted in clock cycle 4, and will reach pipeline stages 2, 3, and 4 in clock cycles 5, 6, and 7 respectively. Although the bypass processing has been completed in clock cycle 6, since the bubble has not reached pipeline stage 4 at this time, instruction 2 will first enter pipeline stage 4 to be processed. At clock cycle 7, due to the arrival of the bubble, pipeline stage 4 can process instruction 3 (at this time, there is no need to process the bubble anymore. All we have to do is to confirm its arrival, rather than processing the bubble itself - as long as the bubble arrives, instruction 3 can be processed).

[0096] In this example, from the results, instruction 3 flows through the instruction fetch stage, the bypass processing corresponding to pipeline stage 1, and pipeline stage 4 in sequence, that is, pipeline stages 1, 2, and 3 are replaced by bypass processing; the remaining instructions flow through all 5 pipeline stages in sequence.

[0097] The replacement of pipeline stages 1, 2, and 3 with bypass processing depends on the specific logic implemented in the bypass processing. For example, the effects include but are not limited to the permutations and combinations of the sub-operations of the following four operations: c) Replace pipeline stage 1 with an alternative implementation of pipeline stage 1 (possibly with bug fixes); or, skip pipeline stage 1.

[0098] d) Replace pipeline stage 2 with an alternative implementation of pipeline stage 2 (possibly with bug fixes) or skip pipeline stage 2.

[0099] e) Replace the original pipeline stage 2 with an alternative implementation of pipeline stage 3 (possibly with bug fixes) or skip pipeline stage 3.

[0100] f) A new pipeline stage is inserted before pipeline stage 1 (which may be an alternative implementation); and / or a new pipeline stage is inserted between pipeline stage 1 and an alternative implementation of pipeline stage 2 (both of which may be alternative implementations); and / or a new pipeline stage is inserted between pipeline stage 2 and an alternative implementation of pipeline stage 3 (both of which may be alternative implementations); and / or a new pipeline stage is inserted after pipeline stage 3 (which may be an alternative implementation); or, no new pipeline stage is inserted.

[0101] The alternative implementation of pipeline stage 1 or 2 or 3 and the new pipeline stage are implemented in bypass processing.

[0102] Table 3

[0103] In one possible implementation, the bypass decision unit determines that the first bubble inserted into the first pipeline stage due to the current instruction bypass has currently arrived at or has previously arrived at the second pipeline stage, and thus determines that the bubble inserted into the first pipeline stage has arrived at the second pipeline stage.

[0104] If it's determined that the bubble inserted into the first pipeline stage hasn't reached the second pipeline stage, wait for the first bubble inserted into the first pipeline stage due to this instruction bypass to reach the second pipeline stage before proceeding to the next step (i.e., the next paragraph). If it's determined that the bubble previously inserted into the first pipeline stage has had enough time to propagate to the second pipeline stage, proceed directly to the next step. If the first bubble inserted into the first pipeline stage due to this instruction bypass hasn't reached the second pipeline stage, it means the bypass unit has completed the bypass process extremely quickly, so quickly that the second pipeline stage, or even other subsequent pipeline stages that need to be bypassed, may still be processing the earlier instruction. Directly inserting the bypass instruction without waiting would disrupt the execution of these earlier instructions. Therefore, by assessing the propagation of bubbles and waiting as needed, the integrity of the instruction stream and the correctness of program execution can be guaranteed. It should be noted that the waiting for the first bubble inserted into the first pipeline stage due to the current instruction bypass to reach the second pipeline stage only affects the timing of inserting the instruction bypass result into the second pipeline stage, and does not affect the restoration of the first pipeline stage; in other words, when the bypass processing is completed, the first pipeline stage can be restored, regardless of whether the bubble inserted into the first pipeline stage reaches the second pipeline stage.

[0105] The bypass decision unit inserts the instruction bypass result into the second pipeline stage according to the instruction bypass unit's instructions. At this point, all consecutive pipeline stages that need to be bypassed can be considered to have completed bypass for this instruction. For this instruction, the pipeline continues normal execution from the second pipeline stage.

[0106] The end result of this implementation is consistent with the end result of each consecutive pipeline stage triggering instruction bypass separately, so it can improve efficiency and performance while ensuring execution correctness.

[0107] In order to better explain the pipeline processing process of multiple instructions, the following Table 4 is provided. In Table 4, the second pipeline stage is the pipeline stage after the first pipeline stage.

[0108] Table 4

[0109] For example, as shown in Table 4, there are five instructions, each of which will flow through five pipeline stages in sequence. After instruction 1 completes the instruction fetch stage, it is determined that instruction 1 requires bypass processing in pipeline stage 1 (the first pipeline stage). Therefore, starting from clock cycle 2, pipeline stage 1 is paused and instruction 1 is bypassed. As a result, instructions 2 through 5 cannot enter pipeline stage 1 for execution. The bypass processing takes a total of four clock cycles. In clock cycle 6, after instruction 1 completes bypass processing in the first pipeline stage, processing continues in pipeline stage 3 (the second pipeline stage) and pipeline stage 1 is resumed (i.e., unpaused). Since the second pipeline stage is not the first pipeline stage, pipeline stage 1 will now process the subsequent instruction. Therefore, in clock cycle 6, instruction 2 enters pipeline stage 1 for execution. At the same time, since the second pipeline stage is pipeline stage 3, instruction 1 skips pipeline stage 2 and enters pipeline stage 3 directly.

[0110] In this example, the results show that instruction 1 flows through the instruction fetch stage, the bypass processing corresponding to pipeline stage 1, pipeline stage 3, and pipeline stage 4 in sequence, that is, pipeline stages 1 and 2 are replaced by bypass processing; the remaining instructions flow through all 5 pipeline stages in sequence.

[0111] The replacement of pipeline stages 1 and 2 with bypass processing depends on the specific logic implemented in the bypass processing. For example, the effects include but are not limited to the permutations and combinations of sub-operations of the following three operations: a) Replace pipeline stage 1 with an alternative implementation of pipeline stage 1 (possibly with bug fixes); or, skip pipeline stage 1.

[0112] b) Replace pipeline stage 2 with an alternative implementation of pipeline stage 2 (possibly with bug fixes) or skip pipeline stage 2.

[0113] c) A new pipeline stage is inserted before pipeline stage 1 (which may be an alternative implementation); and / or, a new pipeline stage is inserted between an alternative implementation of pipeline stage 1 and pipeline stage 2 (both of which may be alternative implementations); and / or, a new pipeline stage is inserted after pipeline stage 2 (which may be an alternative implementation); or, no new pipeline stage is inserted.

[0114] The alternative implementation of pipeline stage 1 or 2 and the new pipeline stage are implemented in bypass processing.

[0115] Optionally, the instruction bypass unit can also insert the instruction bypass result into the first pipeline stage that triggered the bypass, rather than into the next or other subsequent pipeline stages; in other words, the second pipeline stage is allowed to be the first pipeline stage. That is, although an instruction is sent to the instruction bypass unit at a certain pipeline stage due to a matching entry, the instruction bypass unit can return the input of this pipeline stage intact or after certain modifications to this pipeline stage, so that the instruction is still executed using the circuitry of this pipeline stage at this pipeline stage, rather than using the instruction bypass unit. Determining whether a bubble inserted into the first pipeline stage has reached the second pipeline stage also includes: if the second pipeline stage is the first pipeline stage, then determining that the bubble inserted into the first pipeline stage has reached the second pipeline stage. In other words, if the second pipeline stage is the first pipeline stage, it can be unconditionally assumed that the bubble has reached the second pipeline stage.

[0116] For example, some matches may be too complex to be implemented solely with the instruction matcher. Therefore, the instruction bypass unit can also perform a secondary match on the bypassed instruction to determine whether the first pipeline stage in the instruction actually needs to be bypassed. If not, the input of the first pipeline stage is returned intact to the pipeline stage, effectively preventing the pipeline stage from being bypassed.

[0117] For example, this implementation method may also be due to a logical defect in the implementation of the first pipeline stage, and this error can be corrected by simply correcting its input (in other words, pre-processing its input); or, due to a logical defect in the implementation of the previous pipeline stage of the first pipeline stage in the pipeline, this error can be corrected by simply correcting the output of the previous pipeline stage (in other words, post-processing its output). Since the output of the previous pipeline stage is the input of the first pipeline stage, the above two situations are equivalent in behavior and can both be regarded as pre-processing the input of the first pipeline stage. In this case, although the logical defect can be corrected by allowing the instruction bypass unit to completely bypass the first pipeline stage or its previous pipeline stage in the pipeline, since the execution speed of the instruction bypass unit may be slower than the original pipeline stage, completely bypassing this pipeline stage will result in a significant performance degradation. Therefore, instructions can still flow through the original pipeline stages, but their inputs or outputs can be corrected by the instruction bypass unit. This can repair the logic defects of the pipeline stages while maintaining high performance. This is equivalent to partially bypassing these pipeline stages. In this case, when the instruction bypass result is output to the original pipeline stage, an instruction match is temporarily skipped for this pipeline stage, allowing the first pipeline stage in the pipeline to directly process the corrected pipeline stage input.

[0118] For example, if there are four pipeline stages, A, B, and C, among which the implementation of B has a logical defect, if the input of B needs to be corrected, pipeline stage B is included in the list of pipeline stages that need to be bypassed in the matching item (that is, the target pipeline stage list), and the instruction bypass unit, after receiving the input of pipeline stage B, corrects it and outputs it to pipeline stage B as the instruction bypass result; if the output of B needs to be corrected, the next pipeline stage of pipeline stage B is included in the list of pipeline stages that need to be bypassed in the matching item, that is, pipeline stage C. After receiving the input of pipeline stage C, which is actually the output of pipeline stage B, the instruction bypass unit corrects it and outputs it to pipeline stage C as the instruction bypass result. In summary, if the input of pipeline stage X is to be repaired, pipeline stage X is used as the first pipeline stage, and the instruction bypass result is inserted into pipeline stage X after the bypass result is generated (i.e., pipeline stage X is used as the second pipeline stage); if the output of pipeline stage X is to be repaired, the pipeline stage X+1 next to pipeline stage X in the pipeline is used as the first pipeline stage, and the instruction bypass result is inserted into pipeline stage X+1 after the bypass result is generated (i.e., pipeline stage X+1 is used as the second pipeline stage).

[0119] Optionally, a pipeline stage can be inserted before or after a pipeline stage. For example, suppose there are four pipeline stages: instruction fetch, A, B, and C, and pipeline stage X is implemented in the instruction bypass unit. To insert pipeline stage X between stages B and C, pipeline stage C is included in the list of pipeline stages to be bypassed in the matching item. The instruction bypass unit receives the input of pipeline stage C, which is actually the output of pipeline stage B, and uses this input to execute pipeline stage X. It then outputs the result of pipeline stage X as the instruction bypass result to pipeline stage C. In summary, to insert pipeline stage X between pipeline stages Y and Y+1, pipeline stage Y+1 becomes the first pipeline stage, and after the bypass result is generated, the instruction bypass result is inserted into pipeline stage Y+1 (i.e., pipeline stage Y+1 becomes the second pipeline stage).

[0120] In order to better explain the pipeline processing process of multiple instructions, the following Table 5 is provided. In Table 5, the second pipeline stage is the first pipeline stage.

[0121] Table 5

[0122] For example, as shown in Table 5, there are five instructions, each of which will flow through five pipeline stages in sequence. After instruction 3 completes pipeline stage 1, it is determined that instruction 3 requires bypass processing in pipeline stage 2 (the first pipeline stage). Therefore, starting from clock cycle 5, pipeline stage 2 is paused and instruction 3 is bypassed. As a result, instructions 4 through 5 cannot enter pipeline stage 2 for execution. The bypass processing takes a total of three clock cycles. In clock cycle 8, after instruction 3 completes bypass processing in the first pipeline stage, it continues to be processed by pipeline stage 2 (the second pipeline stage). Since the second pipeline stage is still the first pipeline stage, pipeline stage 2 must first process instruction 3 in clock cycle 8 (no longer pausing for bypass processing, but directly processing by pipeline stage 2). Pipeline stage 2 will not continue processing subsequent instructions until after processing instruction 3. Therefore, it will not begin processing instruction 4 until clock cycle 9.

[0123] In this example, from the results, instruction 3 flows through the following sequence: instruction fetch stage, pipeline stage 1, the bypass corresponding to pipeline stage 2, pipeline stage 2, pipeline stage 3, pipeline stage 4, which is equivalent to inserting bypass processing between pipeline stages 1 and 2; the remaining instructions flow through all 5 pipeline stages in sequence.

[0124] The insertion of bypass processing between pipeline stages 1 and 2 depends on the specific logic implemented in the bypass processing. For example, the effects include but are not limited to the following scenarios: inserting a new pipeline stage, skipping the bypass processing, and modifying the output of pipeline stage 1 before inputting it into pipeline stage 2. The new pipeline stage is implemented in the bypass processing; the skipping of the bypass processing may be due to the logic in the bypass processing combining various conditions and ultimately determining that the instruction does not need to be bypassed; the modification of the output of pipeline stage 1 before inputting it into pipeline stage 2 is equivalent to the input of the bypass processing being the output of pipeline stage 1 (the previous pipeline stage of the first pipeline stage in the pipeline), which is modified by the bypass processing logic and outputted as the result of the bypass processing, and the result of the bypass processing is input into pipeline stage 2 (the second pipeline stage).

[0125] Optionally, after returning the bypass processing result of the bypassed instruction to the second pipeline stage in the pipeline, the method further includes: if the second pipeline stage is the first pipeline stage or the third pipeline stage, then no instruction matching is required for the first indication information and the indication information corresponding to the second pipeline stage. In other words, after the bypass decision unit transmits the list of consecutive pipeline stages to be bypassed to the instruction bypass unit, the instruction bypass unit only processes the first portion of the consecutive pipeline stages and sends the bypass processing results of the first portion of the consecutive pipeline stages to the second pipeline stage. If the second pipeline stage is the first pipeline stage or the third pipeline stage, then the instruction bypass unit determines that the second pipeline stage and the pipeline stages in the list of consecutive pipeline stages to be bypassed that follow the second pipeline stage do not need to be bypassed. At this time, the second pipeline stage and the pipeline stages that follow the second pipeline stage in the set of consecutive pipeline stages to be bypassed each temporarily skip one instruction matching for the instruction. In other words, for the pipeline stages in the set of consecutive pipeline stages that need to be bypassed, if the instruction will flow through these pipeline stages again due to resuming normal execution, instruction matching for the instruction is temporarily skipped once at these pipeline stages. It should be noted that this is only a temporary, one-time skipping of instruction matching. When the same instruction flows to these pipeline stages in the future, it should still be matched to allow it to enter the bypass processing according to the matching result; if the bypass processing result again indicates that the second pipeline stage is the first pipeline stage or the third pipeline stage, then refer to this paragraph again for processing.

[0126] Using the above method, the instruction matcher can be made into a PLD or ASIC, and the instruction bypass unit can be made into a PLD. The combination of the instruction matcher and the instruction bypass unit can realize a pipeline-level instruction processing method, which can realize operations such as modifying, adding or deleting CPU behavior.

[0127] Based on the above instruction processing method, an embodiment of the present application further proposes a method for correcting logic defects in an ASIC using instruction bypass.

[0128] For side-channel attacks, since side-channel attacks always require measuring the side effects of hardware, the following instruction sequence is often repeatedly executed during the measurement phase of the side-channel attack: Step 1: Get and record the current clock; Step 2: Execute instructions that may be affected by the aforementioned side effects; Step 3: Get and record the current clock.

[0129] Steps 1 and 3 can be used to determine the execution time of step 2. After repeatedly executing this instruction sequence, an attacker can use statistical analysis to determine the execution time of step 2 under different conditions. The statistical characteristics obtained from this analysis can be used to leak sensitive information through side channels. For example, in the cache side channel used by both Meltdown and Spectre, the aforementioned side effect affects the access latency of each element in the array. Therefore, the access latency of each element in the array must always be measured (corresponding to step 2 above). Therefore, the following loop execution pattern exists: obtain and record the current clock; access an array element; obtain and record the current clock.

[0130] Optionally, mask matching is used as the instruction matching method. The mask of the matching item should select the bit where the opcode of the instruction used to obtain the current clock is located, and the corresponding target value is the opcode of the instruction used to obtain the current clock. If there are multiple opcode stages, all opcodes at each stage are included in the mask and target value. If the instruction used to obtain or record the current clock requires bypass processing, the target pipeline stage list in the matching item includes a write-back pipeline stage or a pipeline stage that accesses the clock. The result of the bypass processing is input to a second pipeline stage in the pipeline, replacing the input of the second pipeline stage. The result of the bypass processing is clock information that is unrelated to the current clock or inaccurate clock information. In one possible implementation, for this instruction, the write-back stage is bypassed (i.e., the write-back stage is selected as the first pipeline stage), which is the pipeline stage that writes to the register. The instruction bypass unit adds randomness to the value to be written to the register or directly modifies it to a meaningless value. The instruction bypass unit can write the new value to the register on its own, in which case the bypass result can be inserted into the next stage after the write-back stage (i.e., the next pipeline stage after the write-back stage in the pipeline is selected as the second pipeline stage); alternatively, the instruction bypass unit can simply insert the new value into the write-back stage as the instruction bypass result (i.e., the write-back stage is selected as the second pipeline stage), and the write-back stage completes the final register write. In another possible implementation, for this instruction, the pipeline stage used to access the clock is bypassed (i.e., the pipeline stage used to access the clock is selected as the first pipeline stage), and the instruction bypass unit uses a meaningless value as the bypass result to be inserted into the next pipeline stage (i.e., the next pipeline stage after the pipeline stage used to access the clock is selected as the second pipeline stage).

[0131] Based on the above-mentioned instruction processing method, an embodiment of the present application also proposes a method for utilizing instruction processing to prevent certain instructions from being executed. Instructions that require bypass processing are errors in the CPU hardware implementation, which result in unexpected instruction results. There are two ways to prevent the instruction from being executed: one is to ignore such instructions, and the other is to trigger an exception. If the implementation method is to ignore, the instruction bypass unit directly outputs the bypass result as an empty result after receiving such instructions. Preferably, the pipeline stage that needs to be bypassed can be designated as a pipeline stage near the beginning of the pipeline to improve performance. More preferably, the second pipeline stage can be designated as a pipeline stage near the end of the pipeline to improve performance. If the implementation method is to trigger an exception, the instruction bypass unit directly completes the bypass by triggering an exception after receiving such instructions, and there is no restriction on the pipeline stage to be bypassed. That is, if the implementation method is to ignore, the target pipeline stage list in the matching item includes the pipeline stage at the head of the pipeline, and the second pipeline stage is the pipeline stage at the end of the pipeline. If the implementation is to throw an exception, the target pipeline stage argument list in the match contains any pipeline stage.

[0132] Figure 5 This is a structural diagram of an instruction processing device 5000 provided in an embodiment of the present application. Figure 5 As shown, it includes at least one processor 501 and a memory 502 connected to the at least one processor 501. The specific connection medium between the processor 501 and the memory 502 is not limited in the embodiment of the present application. Figure 5 For example, the processor 501 and the memory 502 are connected via a bus. The bus can be divided into an address bus, a data bus, a control bus, and the like.

[0133] In an embodiment of the present application, the memory 502 stores instructions that can be executed by at least one processor 501. The at least one processor 501 can implement the steps of the above-mentioned instruction processing method by executing the instructions stored in the memory 502.

[0134] The processor 501 is the control center of the computer device. It can connect the various parts of the computer device using various interfaces and lines, and perform resource settings by running or executing instructions stored in the memory 502 and calling data stored in the memory 502. Optionally, the processor 501 may include one or more processing units. The processor 501 may integrate an application processor and a modem processor. The application processor mainly processes the operating system, user interface, and application programs, while the modem processor mainly processes wireless communications. It is understood that the modem processor may not be integrated into the processor 501. In some embodiments, the processor 501 and the memory 502 may be implemented on the same chip. In some embodiments, they may also be implemented on separate chips.

[0135] The processor 501 can be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly implemented as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor.

[0136] Memory 502, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs, and modules. Memory 502 may include at least one type of storage medium, such as flash memory, a hard disk, a multimedia card, a card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, a magnetic disk, an optical disk, and the like. Memory 502 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. In the embodiments of the present application, memory 502 may also be a circuit or any other device capable of performing a storage function, used to store program instructions and / or data.

[0137] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0138] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0139] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0140] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0141] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A method for processing an instruction, characterized in that: A CPU in pipeline mode, wherein each pipeline includes a plurality of pipeline stages, each pipeline stage having a different processing function, and the method includes: performing instruction matching based on first indication information representing the instruction and second indication information representing a first pipeline stage, and determining whether the instruction requires bypass processing at the first pipeline stage; the first pipeline stage being a pipeline stage to be entered in a pipeline for processing the instruction; If the instruction needs to be bypassed at the first pipeline stage, pausing the first pipeline stage and performing the bypass processing corresponding to the first pipeline stage; After the bypass process is completed, the instruction continues to be processed by the second pipeline stage in the pipeline and the first pipeline stage is restored.

2. The method according to claim 1, characterized in that Performing instruction matching based on first indication information representing the instruction and second indication information representing the first pipeline stage, and determining whether the instruction needs to be bypassed at the first pipeline stage, includes: For any matching item, determine whether the first indication information representing the instruction matches the mask and target value in the matching item; if the instruction matches, determine whether the second indication information representing the first pipeline stage is any pipeline stage in the target pipeline stage list in the matching item; if so, determine that the instruction needs to be bypassed at the first pipeline stage; otherwise, determine that the instruction does not need to be bypassed at the first pipeline stage.

3. The method according to claim 2, characterized in that Before determining whether the first indication information representing the instruction matches the mask and the target value in the matching item, the method further includes: Use the first indication information to query the matching instruction cache and determine that the first indication information does not belong to the matching instruction cache; the matching instruction cache includes indication information representing instructions that can successfully match the mask and target value in any matching item and a target pipeline stage list of the corresponding matching item.

4. The method according to claim 1, wherein Before performing instruction matching based on the first indication information representing the instruction and the second indication information representing the first pipeline stage, the method further includes: It is determined that the second indication information belongs to a total set of target pipeline stages, where the total set of target pipeline stages is obtained by summarizing target pipeline stage lists corresponding to respective matching items.

5. The method according to any one of claims 1 to 4, characterized in that The second pipeline stage is the first pipeline stage, or the next pipeline stage after the first pipeline stage in the pipeline, or any pipeline stage after the first pipeline stage in the pipeline.

6. The method according to any one of claims 1 to 4, characterized in that The method is executed by an instruction matcher located in any pipeline stage; the any pipeline stage is any pipeline stage in the pipeline except the instruction fetch pipeline stage.

7. The method according to any one of claims 1 to 4, characterized in that If the instruction needs to be bypassed at the first pipeline stage, pausing the first pipeline stage includes: If the instruction needs to be bypassed in both the first pipeline stage and the third pipeline stage, the first pipeline stage is paused and the instruction bypass unit is instructed to bypass the first pipeline stage and the third pipeline stage for the instruction; the third pipeline stage is N consecutive pipeline stages located after the first pipeline stage in the pipeline; N is greater than or equal to 1.

8. The method according to claim 7, characterized in that Continuing to process the instruction through a second pipeline stage in the pipeline includes: If the second pipeline stage is the first pipeline stage or the third pipeline stage, instruction matching does not need to be performed on the first indication information and the indication information corresponding to the second pipeline stage.

9. The method according to claim 2, characterized in that The instruction that needs to be bypassed is used to obtain or record the current clock, and the target pipeline stage list in the matching item includes a write-back pipeline stage or a pipeline stage that accesses the clock; the result of the bypass processing is input to the second pipeline stage in the pipeline, replacing the data input of the second pipeline stage, and the result of the bypass processing is clock information that is unrelated to the current clock or inaccurate clock information.

10. The method according to claim 2, characterized in that The instruction that needs to be bypassed has an error in the CPU hardware implementation, and the error causes an unexpected instruction result; the result of the bypass processing is empty, the target pipeline stage list in the matching item includes the pipeline stage located at the head of the pipeline, and the second pipeline stage is the pipeline stage located at the tail of the pipeline; or the result of the bypass processing is to cause an exception, and the target pipeline stage list in the matching item includes any pipeline stage.

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