Electronic device

Abstract

An electronic device includes a base layer, a circuit layer on the base layer, and an element layer on the circuit layer and including a light emitting element and a light receiving element. The circuit layer includes pixel driving circuits connected to the light emitting elements, sensor driving circuits connected to the light receiving elements, gate wires connected to the pixel driving circuits, first read-out lines connected to a first group of sensor driving circuits among the sensor driving circuits, and second read-out lines connected to a second group of sensor driving circuits among the sensor driving circuits. Second readout lines connected to a second group of sensor driving circuits among the sensor driving circuits, connecting lines electrically connected to the second readout lines, respectively, in the display area, and a shield pattern between the gate wiring and the connecting lines.

Description

Technical Field

[0001] The embodiments described herein relate to an electronic device in which a non-display area is reduced in size. Background Art

[0002] An electronic device may provide functions that enable a user to interact with the electronic device. For example, an electronic device may display images to provide information to the user, and may sense user input such as a user's touch or biometric information. To sense or identify biometric information, the electronic device may use capacitive sensing technology for sensing changes in capacitance between electrodes in the electronic device, optical sensing technology for sensing incident light using an optical sensor, or ultrasonic sensing technology for sensing vibration using a piezoelectric element. Summary of the Invention

[0003] Embodiments of the present disclosure provide an electronic device having a biometric information recognition function, and in which the area of a non-display region is relatively small (eg, reduced) when compared to some existing display devices.

[0004] According to an embodiment, an electronic device having a display area and a non-display area includes a base layer, a circuit layer on the base layer, and an element layer including a light emitting element and a light receiving element on the circuit layer and in the display area.

[0005] The circuit layer includes a pixel driving circuit connected to a light-emitting element, a sensor driving circuit connected to a light-receiving element, a data line connected to the pixel driving circuit, a gate wiring connected to the pixel driving circuit, a first readout line connected to a first group of sensor driving circuits among the sensor driving circuits, a second readout line spaced apart from the first readout line in a first direction and connected to a second group of sensor driving circuits among the sensor driving circuits, connecting lines electrically connected to the second readout lines respectively in the display area, and a shielding pattern overlapping with the gate wiring and the connecting line when viewed from above the plane and arranged between the gate wiring and the connecting line in a normal direction perpendicular to the plane.

[0006] According to an embodiment, an electronic device having a display area and a non-display area includes a base layer, a circuit layer on the base layer, and an element layer on the circuit layer and including light emitting elements and light receiving elements disposed corresponding to the display area.

[0007] The circuit layer includes a pixel driving circuit connected to the light-emitting element, a sensor driving circuit connected to the light-receiving element, a data line connected to the pixel driving circuit, a gate wiring connected to the pixel driving circuit, a voltage line connected to the pixel driving circuit, a first readout line connected to a first group of sensor driving circuits among the sensor driving circuits, a second readout line spaced apart from the first readout line in a first direction and connected to a second group of sensor driving circuits among the sensor driving circuits, vertical connection lines electrically connected to the second readout lines and crossing the gate wiring in the display area, and a shield pattern overlapping the gate wiring and the vertical connection line. The shield pattern extends from at least one of the voltage lines and is between the gate wiring and the vertical connection line in a normal direction perpendicular to the plane. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0009] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0010] Figure 2A is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0011] Figure 2B is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0012] Figure 3 is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0013] Figure 4A is a circuit diagram illustrating a pixel and a sensor according to an embodiment of the present disclosure.

[0014] Figure 4B It shows Figure 4A The waveform diagrams of the pixel and sensor operations are shown in FIG.

[0015] Figure 5A is a plan view of a display panel according to an embodiment of the present disclosure.

[0016] Figure 5B yes Figure 5A An enlarged view of a portion of the display panel is shown in FIG.

[0017] Figure 6 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0018] Figure 7A is a plan view showing a portion of a display panel according to an embodiment of the present disclosure.

[0019] Figure 7B yes Figure 7A An enlarged view of portion BB of the display panel is shown in FIG.

[0020] Figure 7C It is along Figure 7B A cross-sectional view taken along line II' shown in FIG.

[0021] Figure 8A is a plan view showing a portion of a display panel according to an embodiment of the present disclosure.

[0022] Figure 8B yes Figure 8A An enlarged view of portion CC of the display panel is shown in FIG.

[0023] Figure 8C It is along Figure 8B A cross-sectional view taken along line II-II' shown in FIG.

[0024] Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 9E 、 Figure 9F 、 Figure 9G and Figure 9H is a plan view illustrating an arrangement of a patterned circuit layer in a display panel according to an embodiment of the present disclosure.

[0025] Figure 10A is a plan view showing a portion of a display panel according to an embodiment of the present disclosure.

[0026] Figure 10B yes Figure 10A An enlarged view of a portion EE of the display panel is shown in FIG.

[0027] Figure 11A is a plan view showing a portion of a display panel according to an embodiment of the present disclosure.

[0028] Figure 11B yes Figure 11A An enlarged view of a portion FF of the display panel is shown in FIG.

[0029] Figure 12A and Figure 12B is a cross-sectional view illustrating a light emitting element and a light receiving element in a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] In this specification, a component (or region, layer, part, etc.) referred to as being "on," "connected to," or "coupled to" another component means that the component can be directly on, directly connected to, or directly coupled to the other component, or a third component can exist between them.

[0031] The same reference numerals in different drawings represent similar or identical components. In addition, in the drawings, the thickness, proportion and size of components may be exaggerated for ease of illustration or description.

[0032] Terms such as first, second, etc. can be used to describe various components, but these components should not be limited by these terms. These terms can only be used to distinguish one component from other components. For example, without departing from the scope of this disclosure, the first component can be referred to as the second component instead, and similarly, the second component can be referred to as the first component instead. Unless otherwise stated, terms in the singular can include plural forms. As used herein, the term "and / or" includes all combinations of one or more of the relevant components.

[0033] Terms such as "below," "beneath," "above," and "over" are used herein to describe the relationship of components shown in the drawings. These terms are relative concepts and can be described based on the directions shown in the drawings.

[0034] When used herein, terms such as “comprises,” “includes,” and “has” specify the presence of stated features, quantities, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof.

[0035] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having meanings corresponding to the contextual meanings in the relevant technical field, and terms used herein should not be interpreted as having idealized or overly formal meanings unless clearly defined as having such meanings in the present disclosure.

[0036] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0037] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure. Figure 2A is based on Figure 1 An exploded perspective view of an electronic device according to an embodiment of the present invention. Figure 2B is based on Figure 1 A cross-sectional view of an electronic device according to an embodiment of the present invention.

[0038] refer to Figure 1 、 Figure 2A and Figure 2B The electronic device DD according to an embodiment of the present disclosure may have a rectangular shape having short sides parallel to a first direction DR1 and long sides parallel to a second direction DR2 intersecting the first direction DR1. However, the electronic device DD is not limited thereto and may have various shapes such as a circular shape, a polygonal shape other than the rectangular shape, or the like.

[0039] The electronic device DD may be an electrically activated device. The electronic device DD may include various embodiments and may be used in various applications. For example, the electronic device DD may be applied to or used in electronic devices such as smart watches, tablet computers, laptop computers, smart TVs, and the like.

[0040] The third direction DR3 is a normal direction substantially perpendicular to a plane defined by the first and second directions DR1 and DR2. The expression "when viewed from above a plane" used herein may mean when viewed with a line of sight in a direction opposite to the third direction DR3.

[0041] An upper surface of the electronic device DD may be defined as a display surface IS and may be parallel to a plane defined by the first and second directions DR1 and DR2. An image IM generated by the electronic device DD may be provided to a user through the display surface IS.

[0042] The display surface IS can be divided into a transmissive area TA and a bezel area BZA. The transmissive area TA may be the area on which the image IM is displayed. A user can visually recognize the image IM through the transmissive area TA. In this embodiment, the transmissive area TA is shown as a rounded quadrilateral. However, this is exemplary, and the transmissive area TA can have various shapes and is not limited to the illustrated embodiment.

[0043] The bezel area BZA is adjacent to the transmissive area TA. The bezel area BZA may have a fixed color, such as black. The bezel area BZA may surround the transmissive area TA. Thus, the bezel area BZA may define the shape or boundary of the transmissive area TA. However, this example is illustrative, and the bezel area BZA may be adjacent to only one side of the transmissive area TA or may be omitted.

[0044] The electronic device DD can sense external input applied to the electronic device DD from outside the electronic device DD. The external input can be of various types. For example, the external input can be a part of the user's body that contacts the electronic device DD (e.g., the user's hand US_F) or a separate device (e.g., an active pen or digitizer). The external input is not limited to contact, but can correspond to other actions applied near the electronic device DD or applied at a specific distance adjacent to the electronic device DD (e.g., hovering). In addition, the external input can have various forms such as force, pressure, temperature, light, etc.

[0045] The electronic device DD can sense the user's biological information. A biological information sensing area capable of sensing the user's biological information can be set on the display surface IS of the electronic device DD. The biological information sensing area can cover the entire transmission area TA or only a portion of the transmission area TA. Figure 1 An example is shown in which the entire transmission area TA is used as the biological information sensing area.

[0046] The electronic device DD may include a window WM, a display module DM, and a housing EDC. In this embodiment, the window WM and the housing EDC are coupled to each other to form the exterior of the electronic device DD.

[0047] The front surface of the window WM defines the display surface IS of the electronic device DD. The window WM may include an optically transparent insulating material. For example, the window WM may include glass or plastic. The window WM may have a multi-layer structure or a single-layer structure. For example, the window WM may include a stack of plastic films attached together using an adhesive, or may include a glass substrate and a plastic film coupled to each other using an adhesive.

[0048] The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may display an image based on an electrical signal, and the input sensing layer ISL may sense an external input applied from outside the electronic device DD. The external input may take various forms such as those described above.

[0049] The display panel DP according to an embodiment of the present disclosure may be an emissive display panel, but the embodiment is not limited thereto. In some embodiments, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material, and the emission layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The emission layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods. Hereinafter, an embodiment in which the display panel DP is an organic light-emitting display panel is described as an example.

[0050] refer to Figure 2BThe display panel DP may include a base layer BL, a circuit layer DP_CL, a device layer DP_ED, and an encapsulation layer TFE. The display panel DP may be a flexible display panel. However, the present disclosure is not limited thereto. For example, the display panel DP may be a foldable display panel that folds about a folding axis, or the display panel DP may be a rigid display panel.

[0051] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, and its material is not particularly limited. In addition, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0052] The circuit layer DP_CL is on the base layer BL and between the base layer BL and the element layer DP_ED. The circuit layer DP_CL may include at least one insulating layer and a circuit element. Hereinafter, the insulating layer included in the circuit layer DP_CL is referred to as an intermediate insulating layer. The intermediate insulating layer may include at least one intermediate inorganic film and at least one intermediate organic film. The circuit element may include a plurality of pixel driving circuits for a plurality of pixels for displaying an image and a plurality of sensor driving circuits for a plurality of sensors for identifying external information. The external information may be biometric information. In an embodiment of the present disclosure, the sensor may be a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, a blood pressure measurement sensor, an illuminance sensor, etc. Alternatively, the sensor may be an optical sensor for optically identifying biometric information. The circuit layer DP_CL may also include signal lines connected to the pixel driving circuit and / or the sensor driving circuit.

[0053] The element layer DP_ED may include a light emitting element in a pixel and a light receiving element in a sensor. In an embodiment of the present disclosure, each light receiving element may be a photodiode or may include a photodiode. In one example, the light receiving element may be a sensor that senses light reflected by a user's fingerprint or reacts to light reflected by a user's fingerprint. Figures 6 to 12B The implementation of the circuit layer DP_CL and the element layer DP_ED is further described.

[0054] The encapsulation layer TFE seals and protects the element layer DP_ED. The encapsulation layer TFE may include at least one organic film and at least one inorganic film. The inorganic film may include an inorganic material and may protect the element layer DP_ED from moisture / oxygen. The inorganic film may include, but is not particularly limited to, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic film may include an organic material and may protect the element layer DP_ED from foreign matter such as dust particles.

[0055] The input sensing layer ISL may be formed on the display panel DP. The input sensing layer ISL may be directly on the encapsulation layer TFE. According to an embodiment of the present disclosure, a continuous process may form at least one upper layer of the display panel DP, and then form the input sensing layer ISL. That is, when the input sensing layer ISL is directly on the display panel DP, there is no adhesive film between the input sensing layer ISL and the encapsulation layer TFE. Alternatively, an adhesive film may be provided between the input sensing layer ISL and the display panel DP. In this case, the input sensing layer ISL may not be manufactured together with the display panel DP through a continuous process, and may be manufactured separately from the display panel DP, and then fixed to the upper surface of the display panel DP using an adhesive film.

[0056] The input sensing layer ISL can sense external input (e.g., a user's touch), can generate a specific input signal according to the external input, and can provide the input signal to the display panel DP. The input sensing layer ISL may include a plurality of sensing electrodes for sensing the external input. The sensing electrodes may sense the external input using a capacitive sensing process. The display panel DP may receive the input signal from the input sensing layer ISL and may generate an image corresponding to the input signal.

[0057] The display module DM may further include a color filter layer CFL. In an embodiment of the present disclosure, the color filter layer CFL may be on the input sensing layer ISL. However, the present disclosure is not limited thereto. The color filter layer CFL may be between the display panel DP and the input sensing layer ISL. The color filter layer CFL may include multiple color filters and a black matrix.

[0058] The structures of the input sensing layer ISL and the color filter layer CFL are further described below.

[0059] The electronic device DD according to an embodiment of the present disclosure may further include an adhesive layer AL. The adhesive layer AL may attach the window WM to the input sensing layer ISL. The adhesive layer AL may include an optically clear adhesive, an optically clear adhesive resin, or a pressure sensitive adhesive (PSA).

[0060] like Figure 2A As shown in FIG, the display module DM may further include a driver chip DIC and sensor chips SIC1 and SIC2. In an embodiment of the present disclosure, the driver chip DIC and the sensor chips SIC1 and SIC2 may be mounted on the display panel DP. The driver chip DIC and the sensor chips SIC1 and SIC2 may be adjacent to one end portion (hereinafter referred to as the first end portion) of the display panel DP. Although Figure 2AAn example is shown in which the driver chip DIC and the sensor chips SIC1 and SIC2 are adjacent to the first end portion of the display panel DP, but the present disclosure is not limited thereto. For example, the driver chip DIC may be disposed adjacent to the first end portion of the display panel DP, and the sensor chips SIC1 and SIC2 may be disposed adjacent to a second end portion of the display panel DP that is away from the first end portion.

[0061] In embodiments of the present disclosure, the sensor chips SIC1 and SIC2 may include a first sensor chip SIC1 on one side (hereinafter referred to as the first side) of a driver chip DIC and a second sensor chip SIC2 on a second side of the driver chip DIC that is different from the first side. Alternatively, the first sensor chip SIC1 and the second sensor chip SIC2 may be integrated into a single sensor chip, and the single sensor chip may be adjacent to the driver chip DIC. In the present disclosure, there are no particular limitations on the number of sensor chips SIC1 and SIC2 and the number of driver chips DIC.

[0062] The housing EDC may be coupled to the window WM. The housing EDC having the window WM provides an interior space for the electronic device DD. The display module DM may be housed in the interior space. The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include glass, plastic, or metal, or may include a plurality of frames and / or plates formed by a combination thereof. The housing EDC may stably protect the components in the interior space of the electronic device DD from external impacts. Although not shown, a battery module for providing power required for the overall operation of the electronic device DD may be provided between the display module DM and the housing EDC.

[0063] Figure 3 is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0064] refer to Figure 3 The electronic device DD includes a display panel DP, a panel driver, and a driving controller 100. In an embodiment of the present disclosure, the panel driver includes a data driver 200, a scan driver 300, an emission driver 350, a voltage generator 400, and a readout circuit 500.

[0065] The driving controller 100 receives the image signal RGB and the control signal CTRL. The driving controller 100 generates image data DATA by converting the data format of the image signal RGB according to the specification of the interface with the data driver 200. The driving controller 100 outputs a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal RCS.

[0066] The data driver 200 receives the third control signal DCS and the image data DATA from the driving controller 100. The data driver 200 converts the image data DATA into a data signal and outputs the data signal to a plurality of data lines DL1, DL2, ... and DLm described further below. The data signal may be an analog voltage corresponding to the grayscale value of the image data DATA. In an embodiment of the present disclosure, the data driver 200 may be embedded in Figure 2A The driver chip shown in DIC.

[0067] The scan driver 300 receives a first control signal SCS from the driving controller 100. The scan driver 300 may output a scan signal to the scan lines in response to the first control signal SCS.

[0068] The voltage generator 400 generates voltages required for the operation of the display panel DP. In the illustrated embodiment, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage Vint, a second initialization voltage Vaint, a bias voltage Vbias, and a reset voltage Vrst.

[0069] The display panel DP may include ( Figure 1 The display area DA corresponding to the transmissive area TA and the display area DA corresponding to the transmissive area TA are shown in FIG. Figure 1 The frame area BZA shown in FIG. 1 corresponds to the non-display area NDA.

[0070] The display panel DP may include a plurality of pixels PX disposed in a display area DA and a plurality of sensors FX disposed in the display area DA. In an embodiment of the present disclosure, each of the sensors FX may be disposed between two adjacent pixels PX. The pixels PX and the sensors FX may be arranged alternately along a first direction DR1 and a second direction DR2. However, the present disclosure is not limited thereto. That is, two or more pixels PX may be disposed between two adjacent sensors FX in the first direction DR1 among the plurality of sensors FX, or two or more pixels PX may be disposed between two adjacent sensors FX in the second direction DR2 among the plurality of sensors FX.

[0071] The display panel DP also includes initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, data lines DL1 to DLm, and readout lines RL1, RL2, ..., and RLh. The initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, and emission control lines EML1 to EMLn extend in a first direction DR1. The initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, and emission control lines EML1 to EMLn are spaced apart from one another in a second direction DR2. The data lines DL1 to DLm and readout lines RL1 to RLh extend in the second direction DR2 and are spaced apart from one another in the first direction DR1. Here, "n", "m", and "h" are natural numbers of 1 or greater.

[0072] The plurality of pixels PX are electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, and data lines DL1 to DLm. For example, each of the plurality of pixels PX may be electrically connected to four scan lines. However, this is not limiting, and the number of scan lines connected to each pixel PX may vary.

[0073] Multiple sensors FX are electrically connected to write scan lines SWL1 to SWLn and readout lines RL1 to RLh. Each of the multiple sensors FX can be electrically connected to one scan line. However, the present disclosure is not limited thereto. The number of scan lines connected to each sensor FX may vary. In an embodiment of the present disclosure, the number of readout lines RL1 to RLh may be less than or equal to the number of data lines DL1 to DLm. For example, the number of readout lines RL1 to RLh may correspond to 1 / 2, 1 / 4, or 1 / 8 of the number of data lines DL1 to DLm.

[0074] The scan driver 300 may be disposed in the non-display area NDA of the display panel DP. The scan driver 300 receives a first control signal SCS from the drive controller 100. In response to the first control signal SCS, the scan driver 300 may output an initialization scan signal to the initialization scan lines SIL1 to SILn and a compensation scan signal to the compensation scan lines SCL1 to SCLn. Furthermore, in response to the first control signal SCS, the scan driver 300 may output a write scan signal to the write scan lines SWL1 to SWLn and a black scan signal to the black scan lines SBL1 to SBLn. Optionally, the scan driver 300 may include a first scan driver and a second scan driver. The first scan driver may output an initialization scan signal and a compensation scan signal, and the second scan driver may output a write scan signal and a black scan signal.

[0075] The emission driver 350 may be disposed in the non-display area NDA of the display panel DP. The emission driver 350 receives a second control signal ECS from the drive controller 100. In response to the second control signal ECS, the emission driver 350 may output emission control signals to the emission control lines EML1 to EMLn. Alternatively, the scan driver 300 may be connected to the emission control lines EML1 to EMLn. In this case, the emission driver 350 may be omitted, and the scan driver 300 may output emission control signals to the emission control lines EML1 to EMLn.

[0076] The readout circuit 500 receives a fourth control signal RCS from the drive controller 100. In response to the fourth control signal RCS, the readout circuit 500 may receive or process a detection signal from the readout lines RL1 to RLh. The readout circuit 500 may process the detection signal received from the readout lines RL1 to RLh and may provide the processed detection signal S_FS to the drive controller 100. The drive controller 100 may recognize biological information based on the detection signal S_FS. In an embodiment of the present disclosure, the readout circuit 500 may be embedded in Figure 2A The sensor chips SIC1 and SIC2 are shown in FIG.

[0077] Figure 4A is a circuit diagram showing a pixel and a sensor according to an embodiment of the present disclosure, and Figure 4B It is shown in Figure 4A Waveform diagrams of emission and scanning signals during operation of the pixel and sensor shown in FIG.

[0078] Figure 4A Shown Figure 3. Each of the pixels PX may have the same circuit structure, so that the description of the circuit structure of the pixel PXij can be applied to all pixels PX, and detailed descriptions of other pixels will be omitted. Figure 4A Also shown Figure 3 . Each of the sensors FX may have the same circuit structure, so that the description of the circuit structure of the sensor FXdj can be applied to all sensors FX, and detailed descriptions of the other sensors will be omitted.

[0079] refer to Figure 4A , the pixel PXij is connected to the i-th data line DLi among the data lines DL1 to DLm, the j-th initialization scan line SILj among the initialization scan lines SIL1 to SILn, the j-th compensation scan line SCLj among the compensation scan lines SCL1 to SCLn, the j-th write scan line SWLj among the write scan lines SWL1 to SWLn, the j-th black scan line SBLj among the black scan lines SBL1 to SBLn, and the j-th emission control line EMLj among the emission control lines EML1 to EMLn.

[0080] The pixel PXij includes a light emitting element ED and a pixel driving circuit P_PD. The light emitting element ED may be a light emitting diode. In an embodiment of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer.

[0081] The pixel driving circuit P_PD includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8 and a capacitor Cst. At least one of the first transistor T1 to the eighth transistor T8 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. Some of the first transistor T1 to the eighth transistor T8 may be P-type transistors, and the other transistors may be N-type transistors. At least one of the first transistor T1 to the eighth transistor T8 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2 and the fifth transistor T5 to the eighth transistor T8 may be LTPS transistors. The third transistor T3 and the fourth transistor T4 may be NMOS transistors.

[0082] The configuration of the pixel driving circuit P_PD according to the present disclosure is not limited to Figure 4A The embodiment shown in . Figure 4AThe pixel driving circuit P_PD shown in FIG is merely an example, and various changes and modifications may be made to the configuration of the pixel driving circuit P_PD. For example, the first to eighth transistors T1 to T8 may all be P-type transistors or N-type transistors.

[0083] The jth initialization scan line SILj, the jth compensation scan line SCLj, the jth write scan line SWLj, the jth black scan line SBLj, and the jth emission control line EMLj can transmit the jth initialization scan signal SIj, the jth compensation scan signal SCj, the jth write scan signal SWj, the jth black scan signal SBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have a value similar to that input to the electronic device DD (reference signal). Figure 3 ) of the image signal RGB (reference Figure 3 ) corresponds to the voltage level.

[0084] In an embodiment of the present disclosure, a pixel PXij can be connected to a first drive voltage line VL1 and a second drive voltage line VL2, a first initialization voltage line VIL and a second initialization voltage line VAIL, and a bias voltage line VBL. The first drive voltage line VL1 can transmit a first drive voltage ELVDD to the pixel PXij, and the second drive voltage line VL2 can transmit a second drive voltage ELVSS to the pixel PXij. In addition, the first initialization voltage line VIL can transmit a first initialization voltage Vint to the pixel PXij, and the second initialization voltage line VAIL can transmit a second initialization voltage Vaint to the pixel PXij. The bias voltage line VBL can transmit a bias voltage Vbias to the pixel PXij.

[0085] The first transistor T1 is connected between a first driving voltage line VL1 receiving a first driving voltage ELVDD and the light-emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to the anode electrode of the light-emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end of the capacitor Cst (e.g., a first node N1). Based on the switching operation of the second transistor T2, the first transistor T1 can receive an i-th data signal Di transmitted from the i-th data line DLi and can provide a driving current Id to the anode electrode of the light-emitting element ED.

[0086] The second transistor T2 is connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line SWLj. The second transistor T2 can be turned on or off according to the j-th write scan signal SWj transmitted via the j-th write scan line SWLj, and can transmit the i-th data signal Di from the i-th data line DLi to the first electrode of the first transistor T1.

[0087] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line SCLj. The third transistor T3 can be turned on or off according to the j-th compensation scan signal SCj transmitted via the j-th compensation scan line SCLj, and can connect the first transistor T1 into a diode form by connecting the third electrode and the second electrode of the first transistor T1.

[0088] The fourth transistor T4 is connected between a first initialization voltage line VIL to which a first initialization voltage Vint is applied and a first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VIL through which the first initialization voltage Vint is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line SILj. The fourth transistor T4 is turned on or off according to the j-th initialization scan signal SIj transmitted via the j-th initialization scan line SILj. The turned-on fourth transistor T4 initializes the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1) by transmitting the first initialization voltage Vint to the first node N1.

[0089] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (eg, a gate electrode) connected to the j-th emission control line EMLj.

[0090] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode electrode of the light emitting element ED, and a third electrode (eg, a gate electrode) connected to the jth emission control line EMLj.

[0091] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on or off according to the jth emission control signal EMj transmitted through the jth emission control line EMLj. The first driving voltage ELVDD applied by the turned-on fifth transistor T5 can be compensated by the first transistor T1 connected in the form of a diode and then can be transmitted to the light emitting element ED.

[0092] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VAIL through which a second initialization voltage Vaint is transmitted, a second electrode connected to the second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line SBLj. The second initialization voltage Vaint may have a voltage level lower than or equal to that of the first initialization voltage Vint.

[0093] The eighth transistor T8 includes a first electrode connected to a bias voltage line VBL through which a bias voltage Vbias is transmitted, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (eg, a gate electrode) connected to the jth black scan line SBLj.

[0094] The seventh transistor T7 and the eighth transistor T8 are simultaneously turned on or off according to the jth black scan signal SBj transmitted through the jth black scan line SBLj. The second initialization voltage Vaint applied by the turned-on seventh transistor T7 can be transmitted to the anode electrode of the light-emitting element ED. Therefore, the anode electrode of the light-emitting element ED can be initialized to the second initialization voltage Vaint. The bias voltage Vbias applied by the turned-on eighth transistor T8 can be transmitted to the first electrode of the first transistor T1. Therefore, the bias voltage Vbias can be periodically applied to the first electrode of the first transistor T1. As a result, the degradation of display quality caused by the potential difference between the first electrode and the second electrode of the first transistor T1 increasing to a certain level or higher due to hysteresis can be prevented.

[0095] One end of the capacitor Cst is connected to the third electrode of the first transistor T1 as described above, and the other end of the capacitor Cst is connected to the first drive voltage line VL1. The cathode electrode of the light-emitting element ED may be connected to the second drive voltage line VL2 that transmits the second drive voltage ELVSS. The second drive voltage ELVSS may have a voltage level lower than the first drive voltage ELVDD. In an embodiment of the present disclosure, the second drive voltage ELVSS may have a voltage level lower than the first initialization voltage Vint and the second initialization voltage Vaint.

[0096] refer to Figure 4A and Figure 4B, the j-th emission control signal EMj has a high level during the non-light emission period NEP. Within the non-light emission period NEP, the j-th initialization scan signal SIj is activated, for example, to a high level. When the j-th initialization scan signal SIj having a high level is provided via the j-th initialization scan line SILj during an activation period AP1 (hereinafter referred to as a first activation period) of the j-th initialization scan signal SIj, the fourth transistor T4 is turned on in response to the j-th initialization scan signal SIj having a high level. The first initialization voltage Vint is transmitted to the third electrode of the first transistor T1 through the turned-on fourth transistor T4, and the first node N1 is initialized to the first initialization voltage Vint. Therefore, the first activation period AP1 can be defined as the initialization period of the pixel PXij.

[0097] Next, when the j-th compensation scan signal SCj is activated during an activation period AP2 (hereinafter, referred to as a second activation period) of the j-th compensation scan signal SCj and the j-th compensation scan signal SCj having a high level is provided through the j-th compensation scan line SCLj, the third transistor T3 is turned on. When the third transistor T3 is turned on, it connects the first transistor T1 in the form of a forward-biased diode. The first activation period AP1 may not overlap with the second activation period AP2.

[0098] During the second activation period AP2, the j-th write scan signal SWj is activated. The j-th write scan signal SWj has a low level during the activation period AP4 (hereinafter referred to as the fourth activation period). During the fourth activation period AP4, the second transistor T2 is turned on by the j-th write scan signal SWj having a low level. Then, the compensation voltage "Di-Vth" obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the i-th data signal Di provided by the i-th data line DLi is applied to the third electrode of the first transistor T1. That is, the potential of the third electrode of the first transistor T1 can be the compensation voltage "Di-Vth". The fourth activation period AP4 can overlap with the second activation period AP2. The duration of the second activation period AP2 can be greater than the duration of the fourth activation period AP4.

[0099] The first driving voltage ELVDD and the compensation voltage "Di-Vth" may be applied to opposite ends of the capacitor Cst, and charges corresponding to the difference between the voltages at the opposite ends of the capacitor Cst may be stored in the capacitor Cst. Here, a period during which the j-th compensation scan signal SCj has a high level may be referred to as a compensation period of the pixel PXij.

[0100] At the same time, during the second activation period AP2 of the j-th compensation scan signal SCj, the j-th black scan signal SBj is activated. The j-th black scan signal SBj has a low level during the activation period AP3 (hereinafter referred to as the third activation period). During the third activation period AP3, the seventh transistor T7 is turned on by receiving the j-th black scan signal SBj having a low level via the j-th black scan line SBLj. A portion of the drive current Id may escape through the seventh transistor T7 as a bypass current Ibp. The third activation period AP3 may overlap with the second activation period AP2. The duration of the second activation period AP2 may be greater than the duration of the third activation period AP3. The third activation period AP3 may precede the fourth activation period AP4 and may not overlap with the fourth activation period AP4.

[0101] When pixel PXij displays a black image, even if the minimum drive current of the first transistor T1 flows as the drive current Id, if the light-emitting element ED emits light, the pixel PXij cannot properly display a black image. Therefore, according to an embodiment of the present disclosure, the seventh transistor T7 in the pixel PXij can allocate a portion of the minimum drive current of the first transistor T1 as a bypass current Ibp to a current path other than the current path toward the light-emitting element ED. Here, the minimum drive current of the first transistor T1 refers to the current flowing to the first transistor T1 under the condition that the gate-source voltage (Vgs) of the first transistor T1 is lower than the threshold voltage (Vth), causing the first transistor T1 to be turned off. The minimum drive current (e.g., a current of approximately 10pA or less) flowing to the first transistor T1 under the condition that the first transistor T1 is turned off is transmitted to the light-emitting element ED, and a black grayscale image is displayed. When the pixel PXij displays a black image, the bypass current Ibp has a relatively large impact on the minimum drive current, while when the pixel PXij displays an image such as a normal image or a white image, the bypass current Ibp has a small impact on the drive current Id. Therefore, when the pixel PXij displays a black image, the current obtained by subtracting the bypass current Ibp escaped through the seventh transistor T7 from the drive current Id (i.e., the light emission current Ied) can be supplied to the light-emitting element ED, so that the pixel PXij can clearly display a black image. Therefore, the pixel PXij can use the seventh transistor T7 to achieve accurate black in the grayscale image, thereby improving the contrast.

[0102] Afterwards, the j-th emission control signal EMj supplied from the j-th emission control line EMLj changes from a high level to a low level. The fifth transistor T5 and the sixth transistor T6 are turned on by the j-th emission control signal EMj having a low level. Then, a drive current Id is generated according to the difference between the voltage of the third electrode of the first transistor T1 and the first drive voltage ELVDD. The drive current Id is supplied to the light-emitting element ED via the sixth transistor T6, and the light-emitting current Ied flows through the light-emitting element ED.

[0103] Reference again Figure 4A , the sensor FXdj is connected to the d-th readout line RLd, the j-th write scan line SWLj, and the reset control line SRL among the readout lines RL1 to RLh.

[0104] The sensor FXdj includes a light receiving element OPD and a sensor driving circuit O_SD. In an embodiment of the present disclosure, the light receiving element OPD may be an organic photodiode including an organic material as a photoelectric conversion layer. Figure 4A The structure in which the sensor FXdj includes one light receiving element OPD is shown, but the present disclosure is not limited thereto. For example, the sensor FXdj may include a plurality of light receiving elements OPD connected in parallel.

[0105] The anode electrode of the light receiving element OPD can be connected to the first sensing node SN1, and the cathode electrode of the light receiving element OPD can be connected to the second driving voltage line VL2 that transmits the second driving voltage ELVSS. The cathode electrode of the light receiving element OPD can be electrically connected to the cathode electrode of the light emitting element ED. In an embodiment of the present disclosure, the cathode electrode of the light receiving element OPD can be formed integrally with the cathode electrode of the light emitting element ED, and a common cathode electrode C_CE (reference Figure 6 ).

[0106] The sensor drive circuit O_SD includes three transistors ST1, ST2, and ST3. The three transistors ST1, ST2, and ST3 may be a reset transistor ST1, an amplifier transistor ST2, and an output transistor ST3, respectively. At least one of the reset transistor ST1, the amplifier transistor ST2, and the output transistor ST3 may be an oxide semiconductor transistor. In an embodiment of the present disclosure, the reset transistor ST1 may be an oxide semiconductor transistor, and the amplifier transistor ST2 and the output transistor ST3 may be LTPS transistors. However, the present invention is not limited thereto, and the reset transistor ST1 and the output transistor ST3 may be oxide semiconductor transistors, and the amplifier transistor ST2 may be an LTPS transistor.

[0107] Some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be P-type transistors, and the rest may be N-type transistors. In an embodiment of the present disclosure, the amplifying transistor ST2 and the output transistor ST3 may be PMOS transistors, and the reset transistor ST1 may be an NMOS transistor. However, without limitation thereto, the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may all be N-type transistors or P-type transistors.

[0108] One or more of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 (e.g., the reset transistor ST1) may be of the same type as the third transistor T3 and the fourth transistor T4 of the pixel PXij. The amplifying transistor ST2 and the output transistor ST3 may be of the same type as the first transistor T1, the second transistor T2, and the fifth to eighth transistors T5 to T8 of the pixel PXij.

[0109] The circuit configuration of the sensor drive circuit O_SD according to the present disclosure is not limited to Figure 4A The circuit configuration shown in . Figure 4A Only exemplary embodiments of the sensor driving circuit O_SD are shown, and various changes and modifications may be made to the configuration of the sensor driving circuit O_SD.

[0110] exist Figure 4A In an embodiment of the present disclosure, the reset transistor ST1 includes a first electrode that receives a reset voltage Vrst, a second electrode connected to the first sensing node SN1, and a third electrode (e.g., a gate electrode) that receives a reset control signal SR. The reset transistor ST1 can reset the potential of the first sensing node SN1 to the reset voltage Vrst in response to the reset control signal SR. The reset control signal SR can be a signal provided by a reset control line SRL. However, the present disclosure is not limited to this. Alternatively, the reset control signal SR can be a j-th compensation scan signal SCj provided by the j-th compensation scan line SCLj. That is, the reset transistor ST1 can receive the j-th compensation scan signal SCj provided from the j-th compensation scan line SCLj as the reset control signal SR. In an embodiment of the present disclosure, at least during the activation period of the reset control signal SR, the reset voltage Vrst can have a voltage level lower than the second drive voltage ELVSS. The reset voltage Vrst can be transmitted to the sensor FXdj via the reset voltage line VRL. The reset voltage Vrst can be a DC voltage maintained at a voltage level lower than the voltage level of the second drive voltage ELVSS.

[0111] The reset transistor ST1 may include a plurality of sub-reset transistors connected in series. For example, the reset transistor ST1 may include two sub-reset transistors (hereinafter referred to as a first sub-reset transistor and a second sub-reset transistor). In this case, the third electrode of the first sub-reset transistor and the third electrode of the second sub-reset transistor are connected to the reset control line SRL. In addition, the second electrode of the first sub-reset transistor and the first electrode of the second sub-reset transistor may be electrically connected to each other. In addition, the reset voltage Vrst may be applied to the first electrode of the first sub-reset transistor, and the second electrode of the second sub-reset transistor may be electrically connected to the first sensing node SN1. However, the number of sub-reset transistors is not limited thereto and may be modified in various ways.

[0112] The amplifier transistor ST2 includes a first electrode that receives a sensing drive voltage SLVD, a second electrode connected to the second sensing node SN2, and a third electrode (e.g., a gate electrode) connected to the first sensing node SN1. The amplifier transistor ST2 can be turned on according to the potential of the first sensing node SN1 and can apply the sensing drive voltage SLVD to the second sensing node SN2. In an embodiment of the present disclosure, the sensing drive voltage SLVD can be one of a first driving voltage ELVDD, a first initialization voltage Vint, and a second initialization voltage Vaint. When the sensing drive voltage SLVD is the first driving voltage ELVDD, the first electrode of the amplifier transistor ST2 can be electrically connected to the first driving voltage line VL1. When the sensing drive voltage SLVD is the first initialization voltage Vint, the first electrode of the amplifier transistor ST2 can be electrically connected to the first initialization voltage line VIL, and when the sensing drive voltage SLVD is the second initialization voltage Vaint, the first electrode of the amplifier transistor ST2 can be electrically connected to the second initialization voltage line VAIL.

[0113] The output transistor ST3 includes a first electrode connected to the second sensing node SN2, a second electrode connected to the dth readout line RLd, and a third electrode that receives an output control signal. In response to the output control signal, the output transistor ST3 can transmit the detection signal FSd to the dth readout line RLd. The output control signal can be the jth write scan signal SWj provided via the jth write scan line SWLj. In other words, the output transistor ST3 can receive the jth write scan signal SWj provided from the jth write scan line SWLj as the output control signal.

[0114] The light receiving element OPD of the sensor FXdj may be exposed to light during the light emission period of the light emitting element ED. The light may be light output from the light emitting element ED.

[0115] If the user's hand US_F (refer to Figure 1 ) contacts the display surface IS (reference Figure 1 ), the light receiving element OPD generates photocharges corresponding to the light reflected by the ridges and valleys between the ridges of the fingerprint. The amount of current flowing through the light receiving element OPD varies according to the photocharges generated. When the light receiving element OPD receives light reflected by the ridges of the fingerprint, the current flowing through the light receiving element OPD can be referred to as a first current, and when the light receiving element OPD receives light reflected by the valleys of the fingerprint, the current flowing through the light receiving element OPD can be referred to as a second current. The amount of light reflected by the ridges of the fingerprint and the amount of light reflected by the valleys of the fingerprint are different from each other, and the difference between the amounts of light appears as a difference between the first current and the second current. When the first current flows through the light receiving element OPD, the potential of the first sensing node SN1 can be referred to as a first potential, and when the second current flows through the light receiving element OPD, the potential of the first sensing node SN1 can be referred to as a second potential. In an embodiment of the present disclosure, the first current may be greater than the second current. In this case, the first potential may be lower than the second potential.

[0116] The amplifying transistor ST2 may be a source follower amplifier that generates a source-drain current proportional to the potential of the first sensing node SN1 input to the third electrode.

[0117] During the fourth activation period AP4, the j-th write scan signal SWj having a low level is supplied to the output transistor ST3 through the j-th write scan line SWLj. When the output transistor ST3 is turned on in response to the j-th write scan signal SWj having a low level, the detection signal FSd corresponding to the current flowing through the amplifying transistor ST2 may be output to the d-th readout line RLd.

[0118] When a reset control signal SR having a high level is provided through the reset control line SRL during the reset period, the reset transistor ST1 is turned on. The reset period can be defined as the activation period (i.e., the high level period) of the reset control signal SR. Alternatively, when the reset transistor ST1 is implemented with a P-type transistor, a reset control signal SR having a low level can be provided to the reset control line SRL during the reset period. During the reset period, the first sense node SN1 can be reset to a potential corresponding to the reset voltage Vrst. In an embodiment of the present disclosure, the reset voltage Vrst can have a voltage level lower than the second drive voltage ELVSS.

[0119] When the reset period ends, the light receiving element OPD may generate photo charges corresponding to the received light, and the generated photo charges may be accumulated in the first sensing node SN1 .

[0120] Figure 5A is a plan view of a display panel according to an embodiment of the present disclosure. Figure 5B yes Figure 5AFor ease of description and clarity of illustration, Figure 5A Only the data lines and the readout lines are shown, and the scan lines and the emission control lines are not shown.

[0121] refer to Figure 5A The display panel DP includes a display area DA and a non-display area NDA. Figure 3 ) and multiple sensor FX (reference Figure 3 ) in the display area DA. The driver chip DIC and the sensor chips SIC1 and SIC2 are mounted in the non-display area NDA.

[0122] Data lines DL1 to DLm (reference Figure 3 ) are connected to the plurality of pixels PX in the display area DA and are connected to the driver chip DIC in the non-display area NDA. Figure 3 ) is connected to a plurality of sensors FX in the display area DA, and is connected to the sensor chips SIC1 and SIC2 in the non-display area NDA.

[0123] The data lines DL1 to DLm may be divided into a first group and a second group. The first group includes a plurality of first data lines DL_G1, and the second group includes a plurality of second data lines DL_G2. The plurality of first data lines DL_G1 are spaced apart from each other along a first direction DR1, and the plurality of second data lines DL_G2 are spaced apart from each other along the first direction DR1. The plurality of first data lines DL_G1 are spaced apart from the plurality of second data lines DL_G2 in the first direction DR1.

[0124] A plurality of first data lines DL_G1 are connected to the pixel drive circuits P_PD of a first group of pixels among the plurality of pixels PX (also referred to as the first group of pixel drive circuits among the pixel drive circuits), and a plurality of second data lines DL_G2 are connected to the pixel drive circuits P_PD of a second group of pixels among the plurality of pixels PX (also referred to as the second group of pixel drive circuits among the pixel drive circuits). The first group of pixels and the first data lines DL_G1 are arranged in a first area A1, and the second group of pixels and the second data lines DL_G2 are arranged in a second area A2. The first area A1 includes a first-first area A1-1 and a first-second area A1-2, the first-first area A1-1 being on a first side relative to a centerline of the display panel DP parallel to the second direction DR2, and the first-second area A1-2 being on a second side relative to the centerline. The second area A2 includes a second-first area A2-1 arranged between the first-first area A1-1 and the non-display area NDA, and a second-second area A2-2 arranged between the first-second area A1-2 and the non-display area NDA.

[0125] The plurality of first data lines DL_G1 include a first-first data line DL1-1 in the first-first area A1-1 and a first-second data line DL1-2 in the first-second area A1-2. The plurality of second data lines DL_G2 include a second-first data line DL2-1 in the second-first area A2-1 and a second-second data line DL2-2 in the second-second area A2-2.

[0126] The first-first data line DL1-1 and the first-second data line DL1-2 are connected to the driver chip DIC. Figure 5A The example in which the first-first data line DL1-1 and the first-second data line DL1-2 are connected to the same driver chip DIC is shown, but the present disclosure is not limited thereto. For example, the first-first data line DL1-1 and the first-second data line DL1-2 may be connected to different driver chips, respectively.

[0127] The display panel DP further includes data link lines connecting the second data lines DL_G2 to the driver chip DIC. The data link lines include a plurality of vertical data link lines V_DCL extending along the first data lines DL_G1 in the second direction DR2 and a plurality of horizontal data link lines H_DCL extending in the first direction DR1.

[0128] The plurality of horizontal data link lines H_DCL include first horizontal data link lines H_DCL11, H_DCL12, and H_DCL13 (collectively referred to as first horizontal data link lines H_DCL1) and second horizontal data link lines H_DCL21, H_DCL22, and H_DCL23 (collectively referred to as second horizontal data link lines H_DCL2). The first horizontal data link lines H_DCL11 to H_DCL13 are connected to the second-first data line DL2-1, and the second horizontal data link lines H_DCL21 to H_DCL23 are connected to the second-second data line DL2-2. The plurality of vertical data link lines V_DCL include first vertical data link lines V_DCL1 and second vertical data link lines V_DCL2. The first vertical data link line V_DCL1 is connected to the first horizontal data link lines H_DCL11 to H_DCL13 , and the second vertical data link line V_DCL2 is connected to the second horizontal data link lines H_DCL21 to H_DCL23 .

[0129] Therefore, the first vertical data link line V_DCL1 is electrically connected to the second-first data line DL2-1 through the first horizontal data link lines H_DCL11 to H_DCL13, and the second vertical data link line V_DCL2 is electrically connected to the second-second data line DL2-2 through the second horizontal data link lines H_DCL21 to H_DCL23.

[0130] The first vertical data link lines V_DCL1 alternate with the first-first data lines DL1-1 in the first-first area A1-1, and the second vertical data link lines V_DCL2 alternate with the first-second data lines DL1-2 in the first-second area A1-2.

[0131] Portions of the plurality of horizontal data connection lines H_DCL and the plurality of vertical data connection lines V_DCL may be located in the display area DA. That is, portions of the plurality of data connection lines for connecting the second data line DL_G2 and the driver chip DIC are located in the display area DA. Therefore, the area of the region occupied by the data connection lines in the non-display area NDA can be reduced, and thus the dead space area of the display panel DP can be reduced.

[0132] The readout lines RL1 to RLh can be divided into a first group and a second group. The first group includes a plurality of first readout lines RL_G1, and the second group includes a plurality of second readout lines RL_G2. The plurality of first readout lines RL_G1 are spaced apart along a first direction DR1, and the plurality of second readout lines RL_G2 are spaced apart along the first direction DR1. The plurality of first readout lines RL_G1 are spaced apart from the plurality of second readout lines RL_G2 in the first direction DR1.

[0133] The plurality of first readout lines RL_G1 are connected to the sensor drive circuit O_SD (refer to FIG. Figure 4A ) (also referred to as a first group of sensor drive circuits among the plurality of sensors FX), and the plurality of second readout lines RL_G2 are connected to the sensor drive circuits O_SD of a second group of sensors among the plurality of sensors FX (also referred to as a second group of sensor drive circuits among the plurality of sensors FX). The first group of sensors and the first readout lines RL_G1 are in the second area A2, and the second group of sensors and the second readout lines RL_G2 are in the first area A1.

[0134] The plurality of first readout lines RL_G1 include first-first readout lines RL1-11, RL1-12, and RL1-13 and first-second readout lines RL1-21, RL1-22, and RL1-23. The first-first readout lines RL1-11 to RL1-13 are in the second-first region A2-1 and connected to the first sensor chip SIC1. The first-second readout lines RL1-21 to RL1-23 are in the second-second region A2-2 and connected to the second sensor chip SIC2.

[0135] The plurality of second readout lines RL_G2 include second-first readout lines RL2-11, RL2-12, and RL2-13 and second-second readout lines RL2-21, RL2-22, and RL2-23. The second-first readout lines RL2-11 to RL2-13 are in the first-first region A1-1 and electrically connected to the first sensor chip SIC1. The second-second readout lines RL2-21 to RL2-23 are in the first-second region A1-2 and electrically connected to the second sensor chip SIC2. The plurality of second readout lines RL_G2 may be between the first-first readout lines RL1-11 to RL1-13 and the first-second readout lines RL1-21 to RL1-23.

[0136] The display panel DP also includes connection lines electrically connected to the second readout lines RL_G2. The connection lines include a plurality of vertical connection lines V_RL extending along the first readout lines RL_G1 in the second direction DR2, and a plurality of horizontal connection lines H_RL extending in the first direction DR1. The vertical connection lines V_RL may include a first vertical connection line V_RL1 electrically connected to the first sensor chip SIC1 and a second vertical connection line V_RL2 electrically connected to the second sensor chip SIC2.

[0137] The first vertical connection lines V_RL1 may alternate with the first-first readout lines RL1-11 to RL1-13 in the first direction DR1. The second vertical connection lines V_RL2 may alternate with the first-second readout lines RL1-21 to RL1-23 in the first direction DR1.

[0138] The horizontal connection lines H_RL electrically connect the vertical connection lines V_RL to the second readout lines RL_G2. The horizontal connection lines H_RL include a first horizontal connection line H_RL1 connecting the first vertical connection line V_RL1 to the second-first readout lines RL2-11 to RL2-13, and a second horizontal connection line H_RL2 connecting the second vertical connection line V_RL2 to the second-second readout lines RL2-21 to RL2-23.

[0139] Portions of the plurality of horizontal connection lines H_RL and the plurality of vertical connection lines V_RL may be disposed within the display area DA. That is, portions of the plurality of connection lines for connecting the second readout line RL_G2 with the first and second sensor chips SIC1 and SIC2 may be disposed within the display area DA. Consequently, the area of the region occupied by the connection lines within the non-display area NDA can be reduced, thereby reducing the dead zone area of the display panel DP.

[0140] Even if the first sensor chip SIC1 or the second sensor chip SIC2 is disposed adjacent to the driver chip DIC, when the second readout line RL_G2 is connected to the first sensor chip SIC1 or the second sensor chip SIC2 via a connection line and the second data line DL_G2 is connected to the driver chip DIC via a data connection line, the readout line and the data line may not cross each other in the non-display area NDA. Therefore, the coupling capacitance between the readout line and the data line may be reduced, thereby improving the sensing accuracy of the sensor FX.

[0141] refer to Figure 5B The first and second readout lines RL_G1 and RL_G2 may be aligned with the scan lines SIL1 to SILn, SCL1 to SCLn, SWL1 to SWLn, and SBL1 to SBLn extending in the first direction DR1 (reference Figure 3 ) and emission control lines EML1 to EMLn (reference Figure 3 )cross.

[0142] In an embodiment of the present disclosure, the first-first readout lines RL1-11 to RL1-13 may cross the j-th initialization scan line SILj, the j-th compensation scan line SCLj, the j-th write scan line SWLj, the j-th black scan line SBLj, and the j-th emission control line EMLj once. Similarly, the second-first readout lines RL2-11 to RL2-13 may cross the j-th initialization scan line SILj, the j-th compensation scan line SCLj, the j-th write scan line SWLj, the j-th black scan line SBLj, and the j-th emission control line EMLj once.

[0143] A first coupling capacitor Ccp1 may be formed at an intersection where the first-first readout lines RL1-11 to RL1-13 cross the scan lines SIL1 to SILn, SCL1 to SCLn, SWL1 to SWLn, and SBL1 to SBLn, as well as the emission control lines EML1 to EMLn, and a second coupling capacitor Ccp2 may be formed at an intersection where the second-first readout lines RL2-11 to RL2-13 cross the scan lines SIL1 to SILn, SCL1 to SCLn, SWL1 to SWLn, and SBL1 to SBLn, as well as the emission control lines EML1 to EMLn.

[0144] In an embodiment of the present disclosure, the second-first readout lines RL2-11 to RL2-13 are connected to the first vertical connection line V_RL1 via the first horizontal connection line H_RL1. Since the first horizontal connection line H_RL1 extends in the first direction DR1, the first horizontal connection line H_RL1 does not intersect the j-th initialization scan line SILj, the j-th compensation scan line SCLj, the j-th write scan line SWLj, the j-th black scan line SBLj, and the j-th emission control line EMLj. However, since the first vertical connection line V_RL1 extends in the second direction DR2, the first vertical connection line V_RL1 may intersect the j-th initialization scan line SILj, the j-th compensation scan line SCLj, the j-th write scan line SWLj, the j-th black scan line SBLj, and the j-th emission control line EMLj. Therefore, third coupling capacitors Ccp3 may be formed at intersections where the first vertical link line V_RL1 crosses the scan lines SIL1 to SILn, SCL1 to SCLn, SWL1 to SWLn, and SBL1 to SBLn, and the emission control lines EML1 to EMLn.

[0145] Therefore, only the first coupling capacitor Ccp1 can act on the first-first readout lines RL1-11 to RL1-13, but the second coupling capacitor Ccp2 and the third coupling capacitor Ccp3 can act on the second-first readout lines RL2-11 to RL2-13. When the third coupling capacitor Ccp3 decreases, the difference between the coupling capacitance acting on the second-first readout lines RL2-11 to RL2-13 and the coupling capacitance acting on the first-first readout lines RL1-11 to RL1-13 can be reduced.

[0146] Reference below 7A to 8C A method of reducing the third coupling capacitance Ccp3 by applying a shielding pattern is described.

[0147] Figure 6 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0148] refer to Figure 6 , the display panel DP may include a base layer BL, a circuit layer DP_CL and an element layer DP_ED.

[0149] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. Specifically, the synthetic resin layer may be a polyimide-based resin layer, but the material thereof is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose resin, a siloxane-based resin, a polyamide resin, and a perylene-based resin. Furthermore, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0150] At least one inorganic layer is formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed from multiple layers. The multiple inorganic layers may constitute the barrier layer BRL and / or buffer layer BFL described below. The barrier layer BRL and buffer layer BFL may be selectively disposed or patterned.

[0151] The circuit layer DP_CL may include a barrier layer BRL and / or a buffer layer BFL. The barrier layer BRL prevents foreign matter from penetrating from the base layer BL or from outside the display panel DP. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Multiple silicon oxide layers and multiple silicon nitride layers may be provided. The silicon oxide layers and the silicon nitride layers may be alternately stacked one above the other.

[0152] A buffer layer (BFL) may be disposed on the barrier layer (BRL). The buffer layer (BFL) may improve the coupling between the base layer (BL) and the semiconductor patterns and / or conductive patterns in the circuit layer (DP_CL). The buffer layer (BFL) may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layers and the silicon nitride layers may be alternately stacked one above the other.

[0153] The semiconductor pattern is on the buffer layer BFL. Hereinafter, the semiconductor pattern directly on the buffer layer BFL or closest to the base layer BL is referred to as the first semiconductor pattern. The first semiconductor pattern may include a silicon semiconductor. The first semiconductor pattern may include polycrystalline silicon. However, the present invention is not limited thereto and the first semiconductor pattern may include amorphous silicon.

[0154] Figure 6 Only a portion of the first semiconductor pattern is shown, and the first semiconductor pattern may be additionally Figure 4A ) or another region of another pixel PX or sensor FX. The first semiconductor pattern may have different electrical properties depending on whether the region of the first semiconductor pattern is doped. The first semiconductor pattern may include doped regions and undoped regions. The doped regions may be doped with N-type dopants or P-type dopants. The P-type transistor includes a doped region doped with a P-type dopant, and the N-type transistor includes a doped region doped with an N-type dopant.

[0155] The doped region has a higher conductivity than the non-doped region and can be used as an electrode or a signal line. The non-doped region can substantially correspond to the active region (or channel) of the transistor. In other words, a portion of the first semiconductor pattern can be the active region of the transistor, another portion can be the source or drain of the transistor, and another portion can be a connecting signal line or a connecting electrode.

[0156] like Figure 6 As shown in , a first electrode S1, a channel portion C1, and a second electrode D1 of a first transistor T1 may be formed in a first semiconductor pattern. The first electrode S1 and the second electrode D1 of the first transistor T1 extend from the channel portion C1 in opposite directions.

[0157] exist Figure 6 , a portion of the connection signal line CSL formed by the semiconductor pattern is shown. Although not shown separately, the connection signal line CSL may be connected to the sixth transistor T6 (refer to FIG. 1 ) when viewed from above the plane. Figure 4A )'s second electrode.

[0158] The first insulating layer 10 is on the buffer layer BFL. The first insulating layer 10 is connected to the plurality of pixels PX (refer to Figure 3 ) together overlap and cover the first semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In an exemplary embodiment, the first insulating layer 10 may be a single silicon oxide layer. Not only the first insulating layer 10 but also the other insulating layers of the circuit layer DP_CL described below may be inorganic layers and / or organic layers, and each may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the aforementioned materials.

[0159] The third electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The third electrode G1 may be a first gate pattern layer GAT1 (refer to FIG. Figure 9B ). The third electrode G1 of the first transistor T1 overlaps the channel portion C1 of the first transistor T1. The third electrode G1 of the first transistor T1 may be used as a mask in a process of doping the first semiconductor pattern.

[0160] The second insulating layer 20 covering the third electrode G1 is on the first insulating layer 10. The second insulating layer 20 overlaps with the plurality of pixels PX. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single layer structure or a multilayer structure. In an exemplary embodiment, the second insulating layer 20 may be a single silicon oxide layer.

[0161] The upper electrode UE may be on the second insulating layer 20. The upper electrode UE may overlap with the third electrode G1. The upper electrode UE may be a second gate pattern layer GAT2 (refer to Figure 9C ) or may be a portion of the doped semiconductor pattern. A portion of the third electrode G1 and the upper electrode UE overlapping the portion of the third electrode G1 may define a capacitor Cst (refer to Figure 4A). In an embodiment of the present disclosure, the upper electrode UE may be omitted.

[0162] In an embodiment of the present disclosure, the second insulating layer 20 may be replaced with an insulating pattern, and the upper electrode UE may be on the insulating pattern. The upper electrode UE may be used as a mask during a process of forming the insulating pattern from the second insulating layer 20.

[0163] The third insulating layer 30 covering the upper electrode UE is on the second insulating layer 20. In an exemplary embodiment, the third insulating layer 30 may be a single silicon oxide layer. The semiconductor pattern is on the third insulating layer 30. Hereinafter, the semiconductor pattern directly on the third insulating layer 30 may be referred to as a second semiconductor pattern. The second semiconductor pattern may include a metal oxide semiconductor. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include a metal oxide of zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti). Alternatively, the oxide semiconductor may include a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) and its oxide. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO) or zinc tin oxide (ZTO).

[0164] Figure 6 Only a portion of the second semiconductor pattern is shown, and the second semiconductor pattern may be further provided in another area of the pixel PXij and other pixels PX or sensor FX. The second semiconductor pattern may include a plurality of regions distinguished according to whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter referred to as the reduction region) has a higher conductivity than the region where the metal oxide is not reduced (hereinafter referred to as the non-reduction region). The reduction region can be used as an electrode or a signal line. The non-reduction region may substantially correspond to the channel portion of the transistor. In other words, a portion of the second semiconductor pattern may be the channel portion of the transistor, and another portion may be the first electrode or the second electrode of the transistor.

[0165] The circuit layer DP_CL may further include a sensor driving circuit O_SD (refer to Figure 4A ) is a portion of a semiconductor pattern. For ease of description, Figure 6A reset transistor ST1 of a semiconductor pattern of a sensor drive circuit O_SD is shown. A first electrode STS1, a channel portion STA1, and a second electrode STD1 of the reset transistor ST1 may be formed in a second semiconductor pattern. In an embodiment of the present disclosure, the second semiconductor pattern may include a metal oxide. The first electrode STS1 and the second electrode STD1 may include a metal reduced from a metal oxide semiconductor. The first electrode STS1 and the second electrode STD1 may include a metal layer having a specific thickness from the upper surface of the second semiconductor pattern and including the reduced metal.

[0166] The fourth insulating layer 40 covers the first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1. The third electrode STG1 of the reset transistor ST1 is on the fourth insulating layer 40. In this embodiment, the third electrode STG1 may be a third gate pattern layer GAT3 (refer to FIG. Figure 9E ). The third electrode STG1 of the reset transistor ST1 overlaps with the channel portion STA1 of the reset transistor ST1. Although one third electrode STG1 is shown in this embodiment for ease of description, the reset transistor ST1 may include two or more third electrodes.

[0167] The fifth insulating layer 50 covering the third electrode STG1 is on the fourth insulating layer 40. In this embodiment, the fifth insulating layer 50 may include a silicon oxide layer and a silicon nitride layer. The fifth insulating layer 50 may include a plurality of silicon oxide layers and a plurality of silicon nitride layers alternately stacked one above the other.

[0168] At least one additional insulating layer is provided on the fifth insulating layer 50. In this embodiment, a sixth insulating layer 60 and a seventh insulating layer 70 may be provided on the fifth insulating layer 50. The sixth insulating layer 60 and the seventh insulating layer 70 may be organic layers and may have a single-layer structure or a multi-layer structure. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be a single polyimide-based resin layer. Without limitation, the sixth insulating layer 60 and the seventh insulating layer 70 may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose resin, a siloxane-based resin, a polyamide resin, and a perylene-based resin.

[0169] The first connection electrode CNE10 may be on the fifth insulating layer 50. The first connection electrode CNE10 is connected to the connection signal line CSL through a first contact hole CH1 penetrating the first insulating layer 10 to the fifth insulating layer 50. The second connection electrode CNE20 on the sixth insulating layer 60 may be connected to the first connection electrode CNE10 through a second contact hole CH2 penetrating the sixth insulating layer 60. In an embodiment of the present disclosure, at least one of the fifth insulating layer 50 to the seventh insulating layer 70 may be omitted, and one of the first connection electrode CNE10 and the second connection electrode CNE20 may also be omitted.

[0170] The third connection electrode CNE11 may be on the fifth insulating layer 50. The third connection electrode CNE11 is connected to the second electrode STD1 of the reset transistor ST1 through a third contact hole CH3 penetrating the fourth insulating layer 40 and the fifth insulating layer 50. The fourth connection electrode CNE21 may be connected to the third connection electrode CNE11 through a fourth contact hole CH4 penetrating the sixth insulating layer 60.

[0171] The first and third link electrodes CNE10 and CNE11 may be portions of the first data metal pattern, and the second and fourth link electrodes CNE20 and CNE21 may be portions of the second data metal pattern.

[0172] The horizontal data connection line H_DCL (see FIG. 5 ) may be disposed on the same layer as the first connection electrode CNE10 and the third connection electrode CNE11 (i.e., on the fifth insulating layer 50 ). However, the present disclosure is not limited thereto. The horizontal data connection line H_DCL may be disposed on the same layer as the third electrode G1 of the first transistor T1 (i.e., on the first insulating layer 10 ).

[0173] A portion of the readout wiring RL (ie, the first line portion RL_P1) may be on the same layer (ie, on the sixth insulating layer 60) as the second and fourth connection electrodes CNE20 and CNE21. The readout wiring RL may be Figure 3 The second and fourth connection electrodes CNE20 and CNE21 and the first line portion RL_P1 of the readout wiring RL are covered by the seventh insulating layer 70 .

[0174] Data wiring DL, vertical data connection line V_DCL (reference Figure 5A ), vertical reset voltage line V_VRL, vertical connection line V_RL (reference Figure 7A ) and a portion of the readout wiring RL (ie, the second line portion RL_P2) may be disposed on the seventh insulating layer 70. The data wiring DL may be Figure 3One of the data lines DL1 to DLm shown in FIG. The vertical reset voltage line V_VRL may be included in Figure 4A Components in the reset voltage line VRL shown in FIG.

[0175] The fifth connection electrode CNE30 and the sixth connection electrode CNE31 may be on the seventh insulating layer 70. The fifth connection electrode CNE30 may be connected to the second connection electrode CNE20 through a fifth contact hole CH5 penetrating the seventh insulating layer 70. The sixth connection electrode CNE31 may be connected to the fourth connection electrode CNE21 through a sixth contact hole CH6 penetrating the seventh insulating layer 70.

[0176] The data wiring DL, the vertical data link line V_DCL, the vertical link line V_RL, the vertical reset voltage line V_VRL, and the second line portion RL_P2 may be on the same layer as the fifth link electrode CNE30 and the sixth link electrode CNE31, but may be electrically insulated from the fifth link electrode CNE30 and the sixth link electrode CNE31. The eighth insulating layer 80 may cover the data wiring DL, the vertical data link line V_DCL, the vertical link line V_RL, the vertical reset voltage line V_VRL, the second line portion RL_P2, the fifth link electrode CNE30, and the sixth link electrode CNE31.

[0177] The element layer DP_ED is on the circuit layer DP_CL. The element layer DP_ED may include a light emitting element ED (refer to Figure 4A ) of the anode electrode P_AE and the light receiving element OPD (reference Figure 4A ) of the sensing anode electrode O_AE. Figure 6 As shown in FIG, the anode electrode P_AE of the light emitting element ED can be connected to the fifth connection electrode CNE30 through the seventh contact hole CH7 penetrating the eighth insulating layer 80. The sensing anode electrode O_AE of the light receiving element OPD can be connected to the sixth connection electrode CNE31 through the eighth contact hole CH8 penetrating the eighth insulating layer 80.

[0178] although Figure 6 The circuit layer DP_CL includes a fifth connection electrode CNE30 and a sixth connection electrode CNE31, but the present disclosure is not limited thereto. Alternatively, the fifth connection electrode CNE30 and the sixth connection electrode CNE31 may be omitted from the circuit layer DP_CL. In this case, the anode electrode P_AE may be directly connected to the second connection electrode CNE20, and the sensing anode electrode O_AE may be directly connected to the fourth connection electrode CNE21.

[0179] The element layer DP_ED further includes a pixel defining layer PDL disposed on the circuit layer DP_CL. The pixel defining layer PDL may include a light emitting opening OP1 corresponding to the light emitting element ED and a light receiving opening OP2 corresponding to the light receiving element OPD. The light emitting opening OP1 exposes at least a portion of the anode electrode P_AE of the light emitting element ED. The light emitting opening OP1 of the pixel defining layer PDL may define an emission area PXA. For example, a plurality of pixels PX (refer to Figure 3 ) may be arranged on the display panel DP (refer to Figure 3 ) plane. A region where a plurality of pixels PX are provided may be defined as a pixel region, and one pixel region may include an emission region PXA and a non-emission region NPXA adjacent to the emission region PXA. The non-emission region NPXA may surround the emission region PXA.

[0180] The light receiving opening OP2 overlaps with the sensing anode electrode O_AE of the light receiving element OPD. The light receiving opening OP2 of the pixel defining layer PDL may define a light receiving area SA. For example, a plurality of sensors FX (refer to Figure 3 ) can be arranged on the plane of the display panel DP according to a specific rule for placing openings in the pixel defining layer PDL. The area where the multiple sensors FX are provided can be defined as a sensing area, and one sensing area can include a light receiving area SA and a non-light receiving area NSA adjacent to the light receiving area SA. The non-light receiving area NSA can surround the light receiving area SA.

[0181] The emission layer P_EL is arranged to correspond to the light emitting opening OP1 defined in the pixel defining layer PDL, and the photoelectric conversion layer O_RL is arranged to correspond to the light receiving opening OP2 defined in the pixel defining layer PDL. Although a patterned emission layer P_EL is shown in this embodiment, the present disclosure is not limited to this. The common emission layer can be provided in common in multiple pixels PX. In this case, the common emission layer can generate white light or blue light. The common cathode electrode C_CE is commonly connected to the light emitting element ED and the light receiving element OPD. The common cathode electrode C_CE can face the sensing anode electrode O_AE and the anode electrode P_AE. The common cathode electrode C_CE is on the emission layer P_EL and the photoelectric conversion layer O_RL. The common cathode electrode C_CE can be provided in common in multiple pixels PX and multiple sensors FX.

[0182] Figure 7A is a plan view showing a portion of a display panel according to an embodiment of the present disclosure, and Figure 7B yes Figure 7A A magnified view of a portion of BB. Figure 7C It is along Figure 7BA cross-sectional view taken along line II' shown in FIG.

[0183] Each of the conductive pattern and the semiconductor pattern of the display panel DP may have a structure that is repeated across an area of the display panel DP according to a specific rule, and Figure 7A Some structures of the pixel driving circuit P_PD and the sensor driving circuit O_SD that can be repeated are shown.

[0184] refer to Figure 7A , voltage line on the display panel DP (reference Figure 5A ) display area DA (reference Figure 5A ) has a mesh shape. In the embodiment of the present disclosure, Figure 4A The first driving voltage line VL1, the second driving voltage line VL2, and the first initialization voltage line VIL and the second initialization voltage line VAIL shown in FIG may have a mesh shape formed by connecting horizontal lines and vertical lines. Figure 7A One voltage line (ie, the second initialization voltage line VAIL) is shown in FIG. 1 as an example, but the present disclosure is not limited thereto.

[0185] The second initialization voltage line VAIL includes a second horizontal initialization voltage line H_VAIL and a second vertical initialization voltage line V_VAIL. The second horizontal initialization voltage line H_VAIL extends in a first direction DR1, and the second vertical initialization voltage line V_VAIL extends in a second direction DR2. Therefore, the second initialization voltage line VAIL may include a mesh shape in the display area DA of the display panel DP.

[0186] The second horizontal initialization voltage line H_VAIL and the second vertical initialization voltage line V_VAIL may be on different layers of the circuit layer DP_CL. For example, the second horizontal initialization voltage line H_VAIL may be on the fourth insulating layer 40 (refer to FIG. Figure 6 ), and the second vertical initialization voltage line V_VAIL may be on the seventh insulating layer 70 (reference Figure 6 ). The second initialization voltage line VAIL may further include a second initialization connection pattern C_VAIL for connecting the second horizontal initialization voltage line H_VAIL and the second vertical initialization voltage line V_VAIL. In the embodiment of the present disclosure, the second initialization connection pattern C_VAIL may be formed on the sixth insulating layer 60 (refer to FIG. Figure 6 The second horizontal initialization voltage line H_VAIL may be connected to the second vertical initialization voltage line V_VAIL through a second initialization connection pattern C_VAIL.

[0187] With the second readout line RL_G2 (reference Figure 5AThe vertical connection line V_RL electrically connected to the first and second vertical initialization voltage lines V_VAIL extends in the second direction DR2. The vertical connection line V_RL may extend parallel to the second vertical initialization voltage line V_VAIL.

[0188] The vertical connection line V_RL may cross at least one gate wiring. In an embodiment of the present disclosure, each of the vertical connection lines V_RL may cross the first gate wiring SBL, the second gate wiring EML, the third gate wiring SWL (refer to Figure 8B ) and the fourth gate wiring SCL (reference Figure 8C ) intersect. The first gate wiring SBL may be Figure 3 One of the black scan lines SBL1 to SBLn shown in FIG, and the second gate wiring EML may be Figure 3 One of the emission control lines EML1 to EMLn shown in FIG. The third gate wiring SWL may be Figure 3 One of the write scan lines SWL1 to SWLn shown in FIG, and the fourth gate wiring SCL may be Figure 3 One of the compensation scan lines SCL1 to SCLn shown in FIG.

[0189] In order to reduce the third coupling capacitance Ccp3, the display panel DP includes a shield pattern provided in a region where each of the vertical connection lines V_RL crosses at least one of the first gate wiring SBL, the second gate wiring EML, the third gate wiring SWL, and the fourth gate wiring SCL. In an embodiment of the present disclosure, the shield pattern may include a first shield pattern S_SP1 extending from the second horizontal initialization voltage line H_VAIL. Figure 7B In the embodiment shown in , the first shield pattern S_SP1 may include a first shield portion SP1_1 parallel to the first direction DR1 and a second shield portion SP1_2 parallel to the second direction DR2. When viewed from above a plane, the first shield portion SP1_1 of the first shield pattern S_SP1 overlaps the vertical connection line V_RL, the first gate wiring SBL, and the second gate wiring EML, and is disposed between the vertical connection line V_RL and the first gate wiring SBL and the second gate wiring EML in a normal direction perpendicular to the plane.

[0190] The first shielding pattern S_SP1 may have the same potential as the second horizontal initialization voltage line H_VAIL (ie, the second initialization voltage Vaint). Since the second initialization voltage Vaint is a DC voltage, the first shielding pattern S_SP1 may have a constant potential.

[0191] refer to Figure 7CThe first gate wiring SBL and the second gate wiring EML are disposed on the first insulating layer 10. The second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 are sequentially stacked on the first gate wiring SBL and the second gate wiring EML. The second horizontal initialization voltage line H_VAIL and the first shield pattern S_SP1 are disposed on the fourth insulating layer 40. The first shield pattern S_SP1 may face the first gate wiring SBL and the second gate wiring EML, with the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 between the first shield pattern S_SP1 and the first gate wiring SBL and the second gate wiring EML.

[0192] The fifth insulating layer 50, the sixth insulating layer 60 and the seventh insulating layer 70 are stacked in sequence on the second horizontal initialization voltage line H_VAIL and the first shield pattern S_SP1. The vertical connection line V_RL is on the seventh insulating layer 70. The vertical connection line V_RL may face the first shield pattern S_SP1, and the fifth insulating layer 50, the sixth insulating layer 60 and the seventh insulating layer 70 are between the vertical connection line V_RL and the first shield pattern S_SP1. That is, the first shield pattern S_SP1 may be between the vertical connection line V_RL and the first gate wiring SBL and the second gate wiring EML in the third direction DR3. The third coupling capacitance Ccp3 formed between the vertical connection line V_RL and the first gate wiring SBL and the second gate wiring EML can be reduced by the first shield pattern S_SP1 having a constant potential, and thus the deviation of the coupling capacitance between the first readout line RL_G1 and the second readout line RL_G2 can be reduced. Therefore, the sensor FX (reference FX) caused by the deviation of the coupling capacitance can be prevented. Figure 3 ) deterioration of sensing accuracy.

[0193] Figure 8A is a plan view showing a portion of a display panel according to an embodiment of the present disclosure, and Figure 8B yes Figure 8A Magnified view of a portion of CC. Figure 8C It is along Figure 8B A cross-sectional view taken along line II-II' shown in FIG.

[0194] refer to Figure 8A The first initialization voltage line VIL includes a first horizontal initialization voltage line H_VIL and a first vertical initialization voltage line V_VIL. The first horizontal initialization voltage line H_VIL extends in a first direction DR1, and the first vertical initialization voltage line V_VIL extends in a second direction DR2. Therefore, the first initialization voltage line VIL can be arranged on the display panel DP (reference Figure 3 ) display area DA (reference Figure 3 ) has a mesh shape.

[0195] The first horizontal initialization voltage line H_VIL and the first vertical initialization voltage line V_VIL may be formed on the circuit layer DP_CL (reference Figure 6 ). For example, the first horizontal initialization voltage line H_VIL may be formed on a different layer of the fifth insulating layer 50 (refer to FIG. Figure 6 ), and the first vertical initialization voltage line V_VIL can be on the seventh insulating layer 70 (reference Figure 6 ). The first initialization voltage line VIL may further include a first initialization connection pattern C_VIL for connecting the first horizontal initialization voltage line H_VIL and the first vertical initialization voltage line V_VIL. In the embodiment of the present disclosure, the first initialization connection pattern C_VIL may be formed on the sixth insulating layer 60 (refer to Figure 6 The first horizontal initialization voltage line H_VIL may be connected to the first vertical initialization voltage line V_VIL through a first initialization connection pattern C_VIL.

[0196] In an embodiment of the present disclosure, the shield pattern may further include a second shield pattern S_SP2 extending from the first horizontal initialization voltage line H_VIL in a direction opposite to the second direction DR2. Therefore, the second shield pattern S_SP2 may have the same potential as the first horizontal initialization voltage line H_VIL (i.e., the first initialization voltage Vint). Since the first initialization voltage Vint is a DC voltage, the second shield pattern S_SP2 may have a constant potential.

[0197] like Figure 8B As shown in , when viewed from above the plane, the second shielding pattern S_SP2 overlaps with the vertical connection line V_RL, the third gate wiring SWL and the fourth gate wiring SCL, and is between the vertical connection line V_RL and the third gate wiring SWL and the fourth gate wiring SCL in the normal direction perpendicular to the plane.

[0198] refer to Figure 8C The third gate wiring SWL is on the first insulating layer 10 . The fourth gate wiring SCL includes a fourth-first gate wiring G2_SCL provided on the second insulating layer 20 and a fourth-second gate wiring G3_SCL provided on the fourth insulating layer 40 .

[0199] The third insulating layer 30 and the fourth insulating layer 40 are sequentially stacked on the fourth-first gate wiring G2_SCL, and the fifth insulating layer 50 is on the fourth-second gate wiring G3_SCL. The first horizontal initialization voltage line H_VIL and the second shield pattern S_SP2 are on the fifth insulating layer 50. The second shield pattern S_SP2 may face the third gate wiring SWL and the fourth-second gate wiring G3_SCL, with the fifth insulating layer 50 between the second shield pattern S_SP2 and the fourth-second gate wiring G3_SCL.

[0200] The sixth insulating layer 60 and the seventh insulating layer 70 are sequentially stacked on the first horizontal initialization voltage line H_VIL and the second shield pattern S_SP2. The vertical connection line V_RL is on the seventh insulating layer 70. The vertical connection line V_RL may face the second shield pattern S_SP2, with the sixth insulating layer 60 and the seventh insulating layer 70 between the vertical connection line V_RL and the second shield pattern S_SP2. In other words, the second shield pattern S_SP2 may be between the vertical connection line V_RL and the third gate wiring SWL and the fourth-second gate wiring G3_SCL in the third direction DR3.

[0201] In an embodiment of the present disclosure, when viewed from above, the first horizontal initialization voltage line H_VIL may overlap with the fifth gate wiring SIL. The fifth gate wiring SIL includes the fifth-first gate wiring G2_SIL on the second insulating layer 20 and the fifth-second gate wiring G3_SIL on the fourth insulating layer 40. That is, the first horizontal initialization voltage line H_VIL may be between the vertical connection line V_RL and the fifth-second gate wiring G3_SIL in the third direction DR3.

[0202] The third coupling capacitance Ccp3 formed between the vertical connection line V_RL and the third gate wiring SWL and the fourth-second gate wiring G3_SCL can be reduced by the second shield pattern S_SP2 having a constant potential, and thus the deviation of the coupling capacitance between the first readout line RL_G1 and the second readout line RL_G2 can be reduced. Therefore, the sensor FX (reference) caused by the deviation of the coupling capacitance can be prevented. Figure 3 ) deterioration of sensing accuracy.

[0203] 9A to 9H is a plan view illustrating an arrangement order of circuit layers according to an embodiment of the present disclosure. Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 9E 、 Figure 9F 、 Figure 9G and Figure 9His a plan view illustrating an arrangement of a patterned circuit layer in a display panel according to an embodiment of the present disclosure.

[0204] refer to 9A to 9H , when viewed from above a plane, each of the conductive pattern and the semiconductor pattern may have a structure that is repeated across a region of the circuit layer DP_CL according to a specific rule. 9A to 9H Some of the pixel driving circuits P_PD and some of the sensor driving circuits O_SD are shown.

[0205] refer to Figure 9A The first semiconductor pattern layer ACT1 may be on the buffer layer BFL. The first semiconductor pattern layer ACT1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor pattern layer ACT1 may include low-temperature polycrystalline silicon (LTPS).

[0206] The first semiconductor pattern layer ACT1 includes a first semiconductor pattern P_ACT1 included in the pixel driving circuit P_PD and a second semiconductor pattern S_ACT1 included in the sensor driving circuit O_SD.

[0207] refer to Figure 9B The first gate pattern layer GAT1 may be on the first insulating layer 10. The first gate pattern layer GAT1 may include a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive material. For example, the first gate pattern layer GAT1 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), or indium zinc oxide (IZO), but is not particularly limited thereto.

[0208] The first gate pattern layer GAT1 may include a first gate wiring SBL, a second gate wiring EML, a third gate wiring SWL, a first gate electrode GE1, and a second gate electrode GE2.

[0209] Each of the first gate wiring SBL, the second gate wiring EML, and the third gate wiring SWL may extend in the first direction DR1. The first gate wiring SBL may correspond to Figure 4A For example, the j-th black scan signal SBj (reference Figure 4A ) may be provided to the first gate wiring SBL. The first gate wiring SBL and the first semiconductor pattern P_ACT1 may constitute Figure 4A The seventh transistor T7.

[0210] The second gate wiring EML corresponds to Figure 4AFor example, the j-th emission control signal EMj (reference Figure 4A ) may be provided to the second gate wiring EML. The second gate wiring EML and the first semiconductor pattern P_ACT1 may constitute Figure 4A The fifth transistor T5 and the sixth transistor T6.

[0211] The third gate wiring SWL corresponds to Figure 4A For example, the j-th write scan signal SWj (reference Figure 4A ) may be provided to the third gate wiring SWL. The third gate wiring SWL together with the first semiconductor pattern P_ACT1 may constitute Figure 4A The second transistor T2, and the third gate wiring SWL together with the second semiconductor pattern S_ACT1 may constitute Figure 4A output transistor ST3.

[0212] Each of the first gate electrode GE1 and the second gate electrode GE2 may be an island-shaped region. The first gate electrode GE1 and the first semiconductor pattern P_ACT1 may constitute a Figure 4A The first gate electrode GE1 may correspond to the first transistor T1. Figure 6 The second gate electrode GE2 and the second semiconductor pattern S_ACT1 may constitute a third electrode G1 of the first transistor T1 shown in FIG. Figure 4A amplifying transistor ST2.

[0213] refer to Figure 9C The second insulating layer 20 may be on the first insulating layer 10 and may cover the first gate pattern layer GAT1. The second gate pattern layer GAT2 may be on the second insulating layer 20. The second gate pattern layer GAT2 may include metal, alloy, conductive metal oxide, or transparent conductive material.

[0214] The second gate pattern layer GAT2 may include a fourth-first gate wiring G2_SCL, a fifth-first gate wiring G2_SIL, a sixth-first gate wiring G2_SRL, and a capacitor electrode CSE.

[0215] The fourth-first gate wiring G2_SCL, the fifth-first gate wiring G2_SIL, and the sixth-first gate wiring G2_SRL may extend in the first direction DR1. The sixth-first gate wiring G2_SRL corresponds to the reset control line SRL (reference Figure 4A ) (or included in the reset control line SRL). The fourth-first gate wiring G2_SCL may correspond to the j-th compensation scan line SCLj (reference Figure 4A) (or may be included in the j-th compensation scan line SCLj). The fifth-first gate wiring G2_SIL may correspond to the j-th initialization scan line SILj (reference Figure 4A )(or may be included in the jth initialization scan line SILj).

[0216] The capacitor electrode CSE may overlap with the first gate electrode GE1 and may be an island-shaped region. For example, the capacitor electrode CSE and the first gate electrode GE1 may constitute a capacitor Cst (refer to Figure 4A ). The capacitor electrode CSE may correspond to Figure 6 An opening CSE_OP penetrating the capacitor electrode CSE may be formed in the capacitor electrode CSE, and the first gate electrode GE1 may be partially exposed through the opening CSE_OP.

[0217] refer to Figure 9D The third insulating layer 30 may be on the second insulating layer 20 and may cover the second gate pattern layer GAT2. The second semiconductor pattern layer ACT2 may be on the third insulating layer 30. The second semiconductor pattern layer ACT2 may include an oxide semiconductor. The second semiconductor pattern layer ACT2 may be in a different layer from the first semiconductor pattern layer ACT1 and may not overlap with the first semiconductor pattern layer ACT1.

[0218] The second semiconductor pattern layer ACT2 includes a third semiconductor pattern P_ACT2 included in the pixel driving circuit P_PD and a fourth semiconductor pattern S_ACT2 included in the sensor driving circuit O_SD.

[0219] refer to Figure 9E The fourth insulating layer 40 may be on the third insulating layer 30 and may cover the second semiconductor pattern layer ACT2. The third gate pattern layer GAT3 may be on the fourth insulating layer 40. The third gate pattern layer GAT3 may include metal, alloy, conductive metal oxide, or transparent conductive material.

[0220] The third gate pattern layer GAT3 may include a fourth-second gate wiring G3_SCL, a fifth-second gate wiring G3_SIL, a sixth-second gate wiring G3_SRL, a second-first horizontal initialization voltage line H_VAIL1, and a second-second horizontal initialization voltage line H_VAIL2. The fourth-second gate wiring G3_SCL, the fifth-second gate wiring G3_SIL, the sixth-second gate wiring G3_SRL, the second-first horizontal initialization voltage line H_VAIL1, and the second-second horizontal initialization voltage line H_VAIL2 extend in the first direction DR1.

[0221] The fifth-second gate wiring G3_SIL may overlap the fourth-first gate wiring G2_SCL and the third semiconductor pattern P_ACT2. In some embodiments, the fourth-second gate wiring G3_SCL may contact the fourth-first gate wiring G2_SCL through a contact portion. Therefore, the j-th compensation scan signal SCj applied to the fourth-first gate wiring G2_SCL may be provided to the fourth-second gate wiring G3_SCL. The fourth-first gate wiring G2_SCL, the third semiconductor pattern P_ACT2, and the fourth-second gate wiring G3_SCL may constitute Figure 4A The third transistor T3.

[0222] The fifth-second gate wiring G3_SIL may overlap the fifth-first gate wiring G2_SIL and the third semiconductor pattern P_ACT2. The fifth-second gate wiring G3_SIL may be electrically connected to the fifth-first gate wiring G2_SIL. The j-th initialization scan signal SIj may be provided to the fifth-second gate wiring G3_SIL through the fifth-first gate wiring G2_SIL. The fifth-first gate wiring G2_SIL, the third semiconductor pattern P_ACT2, and the fifth-second gate wiring G3_SIL may constitute Figure 4A The fourth transistor T4.

[0223] The sixth-second gate wiring G3_SRL may overlap the fourth semiconductor pattern S_ACT2. The sixth-second gate wiring G3_SRL and the fourth semiconductor pattern S_ACT2 may constitute Figure 4A The reset transistor ST1 of the sixth-second gate wiring G3_SRL can be connected to Figure 9C The sixth-first gate wiring G2_SRL shown in FIG is electrically connected.

[0224] The second-first horizontal initialization voltage line H_VAIL1 and the second-second horizontal initialization voltage line H_VAIL2 may be spaced apart from each other in the second direction DR2. Figure 4A ) may include a second-first initialization voltage line and a second-second initialization voltage line. The second-first initialization voltage line is connected to Figure 3At least one pixel among the plurality of pixels PX shown in FIG (particularly the first light-emitting element of the first pixel), and the second-second initialization voltage line is connected to another pixel among the plurality of pixels PX (for example, the second light-emitting element and the third light-emitting element of the second pixel and the third pixel). In an embodiment of the present disclosure, the first pixel includes a first light-emitting element that outputs light of a first color (for example, red light), the second pixel includes a second light-emitting element that outputs light of a second color (for example, green light), and the third pixel includes a third light-emitting element that outputs light of a third color (for example, blue light).

[0225] Here, the second-first horizontal initialization voltage line H_VAIL1 may be a component included in the second-first initialization voltage line, and the second-second horizontal initialization voltage line H_VAIL2 may be a component included in the second-second initialization voltage line. The second-first horizontal initialization voltage line H_VAIL1 applies the second-first horizontal initialization voltage as the second initialization voltage Vaint to the first pixel (refer to Figure 4A ), and the second-second horizontal initialization voltage line H_VAIL2 applies the second-second horizontal initialization voltage as the second initialization voltage Vaint to the second pixel and the third pixel. The second-second horizontal initialization voltage may have a voltage level different from that of the second-first horizontal initialization voltage.

[0226] The third gate pattern layer GAT3 further includes a first shield pattern S_SP1. The first shield pattern S_SP1 may extend from the second-first horizontal initialization voltage line H_VAIL1. However, the present disclosure is not limited thereto. For example, the first shield pattern S_SP1 may be disposed on the second-second horizontal initialization voltage line H_VAIL2, or the first shield pattern S_SP1 may be disposed on each of the second-first horizontal initialization voltage line H_VAIL1 and the second-second horizontal initialization voltage line H_VAIL2.

[0227] refer to Figure 9F , the fifth insulating layer 50 may be on the fourth insulating layer 40 and may cover at least a portion of the third gate pattern layer GAT3. The first data pattern layer SD1 may be on the fifth insulating layer 50. The first data pattern layer SD1 may include, for example, a metal, an alloy, a conductive metal oxide, or a transparent conductive material. Hereinafter, for ease of description and illustration, Figure 9F Only some of the components included in the first data pattern layer SD1 are shown.

[0228] The first data pattern layer SD1 may include a horizontal reset voltage line H_VRL, a bias voltage line VBL, a first horizontal initialization voltage line H_VIL, and a plurality of first connection electrode patterns C_CNE1.

[0229] The horizontal reset voltage line H_VRL, the bias voltage line VBL, and the first horizontal initialization voltage line H_VIL may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2.

[0230] The horizontal reset voltage line H_VRL may be included in Figure 4A The reset voltage line VRL is a component in the reset voltage line VRL. The reset voltage Vrst (reference Figure 4A ) can be provided to the horizontal reset voltage line H_VRL. The horizontal reset voltage line H_VRL can be electrically connected to the reset transistor ST1. The reset transistor ST1 can receive the reset voltage Vrst through the horizontal reset voltage line H_VRL. The bias voltage line VBL can correspond to Figure 4A Bias voltage Vbias (reference voltage VBL) Figure 4A ) can be provided to the bias voltage line VBL. The bias voltage line VBL can be connected to the eighth transistor T8 through the contact portion. The eighth transistor T8 can receive the bias voltage Vbias through the bias voltage line VBL.

[0231] The first horizontal initialization voltage line H_VIL may include Figure 4A The first initialization voltage Vint (reference Figure 4A ) can be provided to the first horizontal initialization voltage line H_VIL. The first horizontal initialization voltage line H_VIL can be connected to the fourth transistor T4 through the contact portion. The fourth transistor T4 can receive the first initialization voltage Vint through the first horizontal initialization voltage line H_VIL.

[0232] The plurality of first connection electrode patterns C_CNE1 may make contact with one of the first semiconductor pattern P_ACT1, the second semiconductor pattern S_ACT1, the third semiconductor pattern P_ACT2, and the fourth semiconductor pattern S_ACT2. The plurality of first connection electrode patterns C_CNE1 may electrically connect one of the first semiconductor pattern P_ACT1, the second semiconductor pattern S_ACT1, the third semiconductor pattern P_ACT2, and the fourth semiconductor pattern S_ACT2 to other wiring or lines. The plurality of first connection electrode patterns C_CNE1 may be connected to one of the first semiconductor pattern P_ACT1, the second semiconductor pattern S_ACT1, the third semiconductor pattern P_ACT2, and the fourth semiconductor pattern S_ACT2 through contact portions. The plurality of first connection electrode patterns C_CNE1 may include Figure 6 1 and 2. The first link electrode CNE10 and the third link electrode CNE11 are shown in FIG.

[0233] The first data pattern layer SD1 may further include a second shielding pattern S_SP2. In an embodiment of the present disclosure, the second shielding pattern S_SP2 may extend from the first horizontal initialization voltage line H_VIL.

[0234] The first data pattern layer SD1 may further include a horizontal data connection wiring D1_HCL. The horizontal data connection wiring D1_HCL may extend in the first direction DR1. In an embodiment of the present disclosure, the horizontal data connection wiring D1_HCL may be included in Figure 5A Components in the horizontal data connection line H_DCL shown in FIG.

[0235] refer to Figure 9G The sixth insulating layer 60 may be on the fifth insulating layer 50 and may cover at least a portion of the first data pattern layer SD1. The second data pattern layer SD2 may be on the sixth insulating layer 60. The second data pattern layer SD2 may include, for example, a metal, an alloy, a conductive metal oxide, or a transparent conductive material.

[0236] The second data pattern layer SD2 includes a first driving voltage line VL1, a shielding electrode wiring RSE, a readout wiring RL (reference Figure 6 ) and a plurality of connection patterns.

[0237] The first driving voltage line VL1 may overlap with the pixel driving circuit P_PD. The first driving voltage line VL1 may correspond to Figure 4A The first driving voltage line VL1. The first driving voltage ELVDD (reference Figure 4A ) can be provided to the first driving voltage line VL1. The first driving voltage line VL1 can be provided in a mesh shape in the display area DA of the display panel DP (refer to Figure 3 ). The first driving voltage line VL1 can be connected to the Figure 4A The fifth transistor T5 shown in FIG is connected to the capacitor Cst.

[0238] The shield electrode wiring RSE can be connected with Figure 9F , and can receive the reset voltage Vrst (reference voltage Vrst) through the horizontal reset voltage line H_VRL. Figure 4A ). When viewed from above in a planar manner, the shield electrode wiring RSE may be provided between the readout wiring RL and the data wiring DL (refer to Figure 9H ). Therefore, the shield electrode wiring RSE can perform a shielding function so that the detection signal output from the readout wiring RL is not coupled with the data signal.

[0239] The first line portion RL_P1 and the vertical reset voltage line V_VRL extend in the second direction DR2 and are spaced apart from each other in the first direction DR1. The readout wiring RL may correspond to Figure 3 The readout wiring RL can be connected to the readout wiring RL1 to RLh shown in FIG. Figure 4A The sensor drive circuit O_SD (especially the output transistor ST3) shown in FIG.

[0240] The plurality of connection patterns may include a second initialization connection pattern C_VAIL and a first initialization connection pattern C_VIL (refer to Figure 8A ).

[0241] The second data pattern layer SD2 may further include a plurality of second connection electrode patterns C_CNE2. The plurality of second connection electrode patterns C_CNE2 may include Figure 6 , and a second link electrode CNE20 and a fourth link electrode CNE21 are shown in FIG.

[0242] refer to Figure 9H The seventh insulating layer 70 may be on the sixth insulating layer 60 and may cover at least a portion of the second data pattern layer SD2. The third data pattern layer SD3 may be disposed on the seventh insulating layer 70. The third data pattern layer SD3 may include, for example, a metal, an alloy, a conductive metal oxide, or a transparent conductive material.

[0243] The third data pattern layer SD3 may include data wiring DL, vertical data connection wiring D3_DCL, second-first vertical initialization voltage line V_VAIL1 , vertical connection line V_RL, vertical reset voltage lines V_VRL1 and V_VRL2 , a second line portion RL_P2 of readout wiring RL, and a plurality of third connection electrode patterns C_CNE3 .

[0244] The data wiring DL, the vertical data link wiring D3_DCL, the second-first vertical initialization voltage line V_VAIL1, and the vertical link line V_RL may extend in the second direction DR2 and be spaced apart from each other in the first direction DR1.

[0245] The data wiring DL may correspond to Figure 3 The data lines DL1 to DLm are shown in FIG. The data wiring DL can be connected to Figure 4A The pixel driving circuit P_PD (particularly the second transistor T2) shown in FIG. The vertical data connection wiring D3_DCL may correspond to Figure 5A The vertical data connection line V_DCL shown in FIG. The vertical data connection wiring D3_DCL can be connected to Figure 9FThe horizontal data connection wiring D1_HCL shown in FIG is electrically connected.

[0246] The second-first vertical initialization voltage line V_VAIL1 is electrically connected to Figure 9E The third data pattern layer SD3 may further include a second-second vertical initialization voltage line electrically connected to the second-second horizontal initialization voltage line H_VAIL2. Figure 9F The first horizontal initialization voltage line H_VIL shown in FIG is electrically connected to the first vertical initialization voltage line V_VIL (refer to FIG. Figure 8A ).

[0247] The vertical reset voltage lines V_VRL1 and V_VRL2 may be included in Figure 4A The vertical reset voltage lines V_VRL1 and V_VRL2 can be connected to the reset voltage line VRL. Figure 9F By coupling the vertical reset voltage lines V_VRL1 and V_VRL2 and the horizontal reset voltage line H_VRL, the reset voltage line VRL may have a mesh shape.

[0248] The plurality of third connection electrode patterns C_CNE3 may include Figure 6 The fifth connection electrode CNE30 and the sixth connection electrode CNE31 are shown in FIG.

[0249] Figure 10A is a plan view showing a portion of a display panel according to an embodiment of the present disclosure, and Figure 10B yes Figure 10A A magnified view of part of the EE. Figure 11A is a plan view showing a portion of a display panel according to an embodiment of the present disclosure, and Figure 11B yes Figure 11A Magnified view of a portion of FF.

[0250] refer to Figure 10A and Figure 10B The second initialization voltage line VAIL includes a second horizontal initialization voltage line H_VAIL, a second vertical initialization voltage line V_VAIL, and a second initialization connection pattern C_VAIL for connecting the second horizontal initialization voltage line H_VAIL and the second vertical initialization voltage line V_VAIL. The second horizontal initialization voltage line H_VAIL extends in a first direction DR1, and the second vertical initialization voltage line V_VAIL extends in a second direction DR2. Therefore, the second initialization voltage line VAIL may have a mesh shape in the display area DA of the display panel DP.

[0251] With the second readout line RL_G2 (reference Figure 5A The vertical connection line V_RLa electrically connected to the vertical data connection wiring D3_DCL extends in the second direction DR2. The vertical connection line V_RLa may extend parallel to the vertical data connection wiring D3_DCL.

[0252] The vertical connection line V_RLa may cross at least one gate wiring. In an embodiment of the present disclosure, each of the vertical connection lines V_RLa may cross the first gate wiring SBL, the second gate wiring EML, the third gate wiring SWL, and the fourth gate wiring SCL. The first gate wiring SBL may be Figure 3 One of the black scan lines SBL1 to SBLn shown in FIG, and the second gate wiring EML may be Figure 3 One of the emission control lines EML1 to EMLn shown in FIG. The third gate wiring SWL may be Figure 3 One of the write scan lines SWL1 to SWLn shown in FIG, and the fourth gate wiring SCL may be Figure 3 One of the compensation scan lines SCL1 to SCLn shown in FIG.

[0253] In order to reduce the third coupling capacitance Ccp3 (reference Figure 5B ), the display panel DP includes a shield pattern in a region where each of the vertical connection lines V_RLa intersects at least one of the first gate wiring SBL, the second gate wiring EML, the third gate wiring SWL, and the fourth gate wiring SCL. In an embodiment of the present disclosure, the shield pattern may include a first shield pattern S_SP1a extending from the second horizontal initialization voltage line H_VAIL in the second direction DR2. Therefore, the first shield pattern S_SP1a may have the same potential as the second horizontal initialization voltage line H_VAIL (i.e., the second initialization voltage Vaint). Since the second initialization voltage Vaint is a DC voltage, the first shield pattern S_SP1a may have a constant potential.

[0254] When viewed from above the plane, the first shield pattern S_SP1a overlaps the vertical connection line V_RLa, the first gate wiring SBL, and the second gate wiring EML, and is located between the vertical connection line V_RLa and the first gate wiring SBL and the second gate wiring EML in the normal direction perpendicular to the plane.

[0255] refer to Figure 11A and Figure 11BThe first initialization voltage line VIL includes a first horizontal initialization voltage line H_VIL, a first vertical initialization voltage line V_VIL, and a first initialization connection pattern C_VIL for connecting the first horizontal initialization voltage line H_VIL and the first vertical initialization voltage line V_VIL. The first horizontal initialization voltage line H_VIL extends in a first direction DR1, and the first vertical initialization voltage line V_VIL extends in a second direction DR2.

[0256] In an embodiment of the present disclosure, the shield pattern may further include a second shield pattern S_SP2a extending from the first horizontal initialization voltage line H_VIL in a direction opposite to the second direction DR2. Therefore, the second shield pattern S_SP2a may have the same potential as the first horizontal initialization voltage line H_VIL (i.e., the first initialization voltage Vint). Since the first initialization voltage Vint is a DC voltage, the second shield pattern S_SP2a may receive the DC voltage.

[0257] When viewed from above the plane, the second shield pattern S_SP2a overlaps the vertical connection line V_RLa, the third gate wiring SWL and the fourth gate wiring SCL, and is provided between the vertical connection line V_RLa and the third gate wiring SWL and the fourth gate wiring SCL in the normal direction perpendicular to the plane.

[0258] exist Figure 10B and Figure 11B , the first and second shielding patterns S_SP1a and S_SP2a are shown as having a stripe shape. However, the present disclosure is not limited thereto, and the first and second shielding patterns S_SP1a and S_SP2a may have a structure extending in various shapes according to the design of the pixel PX and the sensor FX to overlap the gate wirings SBL, EML, SWL, and SCL.

[0259] Figure 12A and Figure 12B is a cross-sectional view illustrating a light emitting element and a light receiving element of a display panel according to an embodiment of the present disclosure.

[0260] refer to Figure 12A and Figure 12B, the first electrode layer is on the circuit layer DP_CL. The pixel defining layer PDL is formed on the first electrode layer. The first electrode layer may include a red anode electrode R_AE, a green anode electrode G_AE, and a blue anode electrode B_AE. The first light emitting opening OP1_1, the second light emitting opening OP1_2, and the third light emitting opening OP1_3 of the pixel defining layer PDL expose at least part of the red anode electrode R_AE, the green anode electrode G_AE, and the blue anode electrode B_AE, respectively. In an embodiment of the present disclosure, the pixel defining layer PDL may include a black material. The pixel defining layer PDL may, for example, include a black organic dye / pigment such as carbon black, aniline black, etc. The pixel defining layer PDL may be formed by mixing a blue organic material and a black organic material. The pixel defining layer PDL may also include a liquid-repellent organic material.

[0261] like Figure 12A As shown in , the display panel DP may include a first emission region PXA-R, a second emission region PXA-G, and a third emission region PXA-B, and a first non-emission region NPXA-R, a second non-emission region NPXA-G, and a third non-emission region NPXA-B adjacent to the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B. The non-emission regions NPXA-R, NPXA-G, and NPXA-B may surround the corresponding emission regions PXA-R, PXA-G, and PXA-B, respectively. In this embodiment, the first emission region PXA-R is defined as corresponding to the portion of the red anode electrode R_AE exposed by the first light emitting opening OP1_1. The second emission region PXA-G is defined as corresponding to the portion of the green anode electrode G_AE exposed by the second light emitting opening OP1_2. The third emission region PXA-B is defined as corresponding to the portion of the blue anode electrode B_AE exposed by the third light emitting opening OP1_3. A non-pixel region NPA may be defined between the first non-emission region NPXA-R, the second non-emission region NPXA-G, and the third non-emission region NPXA-B.

[0262] The emission layer may be disposed on the first electrode layer. The emission layer may include a red light-emitting layer R_EL, a green light-emitting layer G_EL, and a blue light-emitting layer B_EL. The red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may be located in regions corresponding to the first light-emitting opening OP1_1, the second light-emitting opening OP1_2, and the third light-emitting opening OP1_3, respectively. The red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may be formed to be separated from each other. Each of the red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may include an organic material and / or an inorganic material. The red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may generate light of a specific color. For example, the red light-emitting layer R_EL may generate red light, the green light-emitting layer G_EL may generate green light, and the blue light-emitting layer B_EL may generate blue light.

[0263] Although patterned red, green, and blue light-emitting layers R_EL, G_EL, and B_EL are shown in this embodiment, a single emission layer may be provided in the first, second, and third emission regions PXA_R, PXA_G, and PXA_B. In this case, the emission layer may generate white light or blue light. Furthermore, the emission layer may have a multilayer structure, for example, a tandem structure.

[0264] Each of the red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may include a low molecular weight organic material or a high molecular weight organic material as a light-emitting material. Alternatively, each of the red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may include a quantum dot material as a light-emitting material. The core of the quantum dot may be selected from Group II-VI compounds, Group III-V compounds, Group IV-VI compounds, Group IV elements, Group IV compounds, and combinations thereof.

[0265] The second electrode layer is on the red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL. The second electrode layer may include a red cathode electrode R_CE, a green cathode electrode G_CE, and a blue cathode electrode B_CE. The red cathode electrode R_CE, the green cathode electrode G_CE, and the blue cathode electrode B_CE may be electrically connected to each other. In an embodiment of the present disclosure, the red cathode electrode R_CE, the green cathode electrode G_CE, and the blue cathode electrode B_CE may have an integral shape. In this case, the red cathode electrode R_CE, the green cathode electrode G_CE, and the blue cathode electrode B_CE may be jointly arranged in the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B, the first non-emission region NPXA-R, the second non-emission region NPXA-G, and the third non-emission region NPXA-B, and the non-pixel area NPA.

[0266] The element layer DP_ED may further include a light receiving element OPD. The light receiving element OPD may be a photodiode. The pixel defining layer PDL may further include a light receiving opening OP2 corresponding to the light receiving element OPD.

[0267] The light receiving element OPD may include a sensing anode electrode O_AE, a photoelectric conversion layer O_RL, and a sensing cathode electrode O_CE. The sensing anode electrode O_AE may be part of the first electrode layer. That is, the sensing anode electrode O_AE may be on the circuit layer DP_CL and may be formed simultaneously with the red anode electrode R_AE, the green anode electrode G_AE, and the blue anode electrode B_AE using the same process.

[0268] The light receiving opening OP2 of the pixel defining layer PDL exposes at least a portion of the sensing anode electrode O_AE. The photoelectric conversion layer O_RL is on the sensing anode electrode O_AE exposed by the light receiving opening OP2. The photoelectric conversion layer O_RL may include an organic photosensitive material. The sensing cathode electrode O_CE may be on the photoelectric conversion layer O_RL. The sensing cathode electrode O_CE may be formed simultaneously with the red cathode electrode R_CE, the green cathode electrode G_CE, and the blue cathode electrode B_CE by the same process. In an embodiment of the present disclosure, the sensing cathode electrode O_CE may have a shape that is integrated with the red cathode electrode R_CE, the green cathode electrode G_CE, and the blue cathode electrode B_CE to form a common cathode electrode C_CE (reference Figure 6 ).

[0269] The encapsulation layer TFE is on the element layer DP_ED. The encapsulation layer TFE includes at least an inorganic layer or an organic layer. In an embodiment of the present disclosure, the encapsulation layer TFE may include two inorganic layers and an organic layer therebetween. In an embodiment of the present disclosure, the encapsulation layer TFE may include multiple inorganic layers and multiple organic layers alternately stacked one on top of the other.

[0270] The inorganic layer protects the red light-emitting element ED_R, the green light-emitting element ED_G, the blue light-emitting element ED_B, and the light-receiving element OPD from moisture / oxygen, and the organic layer protects the red light-emitting element ED_R, the green light-emitting element ED_G, the blue light-emitting element ED_B, and the light-receiving element OPD from foreign matter such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but is not particularly limited thereto. The organic layer may include an acrylic organic layer, but is not particularly limited thereto.

[0271] The electronic device DD includes an input sensing layer ISL on the display panel DP and a color filter layer CFL on the input sensing layer ISL.

[0272] The input sensing layer ISL may be directly on the packaging layer TFE. The input sensing layer ISL includes a first conductive layer ICL1, an insulating layer IL, a second conductive layer ICL2 and a protection layer PL. The first conductive layer ICL1 may be on the packaging layer TFE. Figure 12A and Figure 12B A structure in which the first conductive layer ICL1 is directly on the encapsulation layer TFE is shown, but the present disclosure is not limited thereto. The input sensing layer ISL may further include a base insulating layer between the first conductive layer ICL1 and the encapsulation layer TFE. In this case, the encapsulation layer TFE may be covered by the base insulating layer, and the first conductive layer ICL1 may be on the base insulating layer. In an embodiment of the present disclosure, the base insulating layer may include an inorganic insulating material.

[0273] The insulating layer IL may cover the first conductive layer ICL1. The second conductive layer ICL2 is on the insulating layer IL. Figure 12A and Figure 12B A structure in which the input sensing layer ISL includes the first conductive layer ICL1 and the second conductive layer ICL2 is shown, but the present disclosure is not limited thereto. For example, the input sensing layer ISL may include only one of the first conductive layer ICL1 and the second conductive layer ICL2.

[0274] A protective layer PL may be formed on the second conductive layer ICL2. The protective layer PL may include an organic insulating material. The protective layer PL may be used to protect the first conductive layer ICL1 and the second conductive layer ICL2 from moisture / oxygen and from foreign matter.

[0275] The color filter layer CFL may be on the input sensing layer ISL. The color filter layer CFL may be directly on the protective layer PL. The color filter layer CFL may include a first color filter CF_R, a second color filter CF_G, and a third color filter CF_B. The first color filter CF_R has a first color, the second color filter CF_G has a second color, and the third color filter CF_B has a third color. In an embodiment of the present disclosure, the first color may be red, the second color may be green, and the third color may be blue.

[0276] The color filter layer CFL may further include a dummy color filter DCF. In an embodiment of the present disclosure, when the region where the photoelectric conversion layer O_RL is provided is defined as a light receiving region SA and the region surrounding the light receiving region SA is defined as a non-light receiving region NSA, the region of the dummy color filter DCF may correspond to the light receiving region SA. The dummy color filter DCF may overlap with the light receiving region SA and the non-light receiving region NSA. In an embodiment of the present disclosure, the dummy color filter DCF may have the same color as one of the first color filter CF_R, the second color filter CF_G, and the third color filter CF_B. In an embodiment of the present disclosure, the dummy color filter DCF may have the same green color as the second color filter CF_G.

[0277] The color filter layer CFL may further include a black matrix BM. The black matrix BM may overlap with the non-pixel area NPA. The black matrix BM may overlap with the first conductive layer ICL1 and the second conductive layer ICL2 in the non-pixel area NPA. In an embodiment of the present disclosure, the black matrix BM may overlap with the non-pixel area NPA and the first non-emission area NPXA-R, the second non-emission area NPXA-G, and the third non-emission area NPXA-B. The black matrix BM may not overlap with the first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B.

[0278] The color filter layer CFL may further include an overcoat layer (OCL). The overcoat layer (OCL) may include an organic insulating material. The overcoat layer (OCL) may have a thickness sufficient to remove the step between the first color filter CF_R, the second color filter CF_G, and the third color filter CF_B. Without any particular limitations, the overcoat layer (OCL) may include any material having a specific thickness and capable of flattening the upper surface of the color filter layer (CFL). For example, the overcoat layer (OCL) may include an acrylic organic material.

[0279] refer to Figure 12B , when the electronic device DD (reference Figure 1 ) when operating, the red light emitting element ED_R, the green light emitting element ED_G, and the blue light emitting element ED_B can output light. The red light emitting element ED_R outputs red light in the red wavelength band, the green light emitting element ED_G outputs green light in the green wavelength band, and the blue light emitting element ED_B outputs blue light in the blue wavelength band.

[0280] In an embodiment of the present disclosure, the light receiving element OPD can receive light from a specific light emitting element (for example, the green light emitting element ED_G) among the red light emitting element ED_R, the green light emitting element ED_G, and the blue light emitting element ED_B. That is, the second light Lg1 can be output from the green light emitting element ED_G, and the light receiving element OPD can receive the second reflected light Lg2 obtained by reflecting the second light Lg1 from the user's fingerprint. The second light Lg1 and the second reflected light Lg2 can be green light in the green light wavelength band. The dummy color filter DCF is disposed above the light receiving element OPD. The color of the dummy color filter DCF can be green. Therefore, the second reflected light Lg2 can pass through the dummy color filter DCF and can be incident on the light receiving element OPD.

[0281] The red light output from the red light-emitting element ED_R and the blue light output from the blue light-emitting element ED_B may also be reflected by the user's hand US_F. For example, when the light obtained by reflecting the red light Lr1 output from the red light-emitting element ED_R by the user's hand US_F is defined as the first reflected light Lr2, the first reflected light Lr2 may not be able to pass through the dummy color filter DCF and may be absorbed by the dummy color filter DCF. Therefore, the first reflected light Lr2 cannot pass through the dummy color filter DCF and is not incident on the light receiving element OPD. Similarly, even if the blue light is reflected by the user's hand US_F, the blue light may be absorbed by the dummy color filter DCF. Therefore, only the second reflected light Lg2 can be provided to the light receiving element OPD.

[0282] As described above, the readout line can be divided into a first readout line and a second readout line, and the second readout line can be connected to the sensor IC via a connecting line. Portions of the connecting line can be disposed within the display area, thereby reducing the area occupied by the connecting line in the non-display area. Consequently, the dead zone area of the display panel can be reduced.

[0283] Furthermore, a shield pattern having a constant potential can be provided between the connection line and the gate wiring, and this shield pattern can reduce the coupling capacitance formed between the connection line and the gate wiring. Consequently, the variation in the coupling capacitance between the first readout line and the second readout line can be reduced. Consequently, degradation of the sensor's sensing accuracy due to the variation in coupling capacitance can be prevented.

[0284] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. An electronic device having a display area and a non-display area, the electronic device comprising: base layer; a circuit layer on the base layer; as well as an element layer on the circuit layer, the element layer including a light emitting element and a light receiving element in the display area, Wherein, the circuit layer includes: a pixel driving circuit connected to the light-emitting element; a sensor driving circuit connected to the light receiving element; a data line connected to the pixel driving circuit; a gate wiring connected to the pixel driving circuit; a first readout line connected to a first group of sensor drive circuits among the sensor drive circuits; a second readout line spaced apart from the first readout line in a first direction and connected to a second group of sensor drive circuits among the sensor drive circuits; connecting lines electrically connected to the second readout lines in the display area respectively; and The shield pattern is configured to overlap the gate wiring and the connection line when viewed from above a plane, and is provided between the gate wiring and the connection line in a normal direction perpendicular to the plane.

2. The electronic device according to claim 1, wherein The connecting line includes: a plurality of vertical connection lines extending along the first readout line; and a plurality of horizontal connection lines extending in the first direction and electrically connecting the plurality of vertical connection lines to the second readout lines, and When viewed from above the plane, the shielding pattern overlaps with the plurality of vertical connection lines.

3. The electronic device according to claim 2, wherein: The shield pattern is above the gate wiring and below the plurality of vertical connection lines.

4. The electronic device according to claim 3, wherein: The horizontal connection lines are provided on a layer different from the layer on which the vertical connection lines are provided, and The shielding pattern is provided on a layer different from the layer on which the vertical connection line is provided.

5. The electronic device according to claim 2, wherein: The circuit layer further includes a plurality of voltage lines connected to the pixel driving circuit, and The shielding pattern is connected to at least one of the voltage lines and has a constant potential. The electronic device according to claim 5 , wherein: The plurality of voltage lines include: a first initialization voltage line configured to apply a first initialization voltage to the pixel driving circuit; and a second initialization voltage line configured to apply a second initialization voltage to the pixel driving circuit, and The shielding pattern includes a first shielding pattern electrically connected to the second initialization voltage line.

7. The electronic device according to claim 6, wherein: The second initialization voltage line includes: a second horizontal initialization voltage line configured to extend in the first direction; and The second vertical initialization voltage line is configured to extend in a second direction crossing the first direction and is disposed on a layer different from a layer on which the second horizontal initialization voltage line is disposed.

8. The electronic device according to claim 7, wherein: The vertical connection line and the second vertical initialization voltage line are on the same layer, and The first shielding pattern extends from the second horizontal initializing voltage line.

9. The electronic device according to claim 8, wherein: The gate wiring includes: a first gate wiring configured to provide a black scan signal to a corresponding pixel driving circuit among the pixel driving circuits; a second gate wiring configured to provide an emission control signal to the corresponding pixel driving circuit; a third gate wiring configured to provide a write scan signal to the corresponding pixel driving circuit; and a fourth gate wiring configured to provide a compensation scanning signal to the corresponding pixel driving circuit, and Wherein, when viewed from above the plane, the first shielding pattern overlaps with the first gate wiring and the second gate wiring.

10. The electronic device according to claim 6, wherein: The shield pattern further includes a second shield pattern connected to the first initialization voltage line. The electronic device according to claim 10 , wherein: The first initialization voltage line includes: a first horizontal initialization voltage line configured to extend in the first direction; and A first vertical initialization voltage line is configured to extend in a second direction crossing the first direction and is disposed on a layer different from a layer on which the first horizontal initialization voltage line is disposed.

12. The electronic device according to claim 11, wherein: The vertical connection line and the first vertical initialization voltage line are on the same layer, and The second shielding pattern extends from the first horizontal initializing voltage line.

13. The electronic device according to claim 12, wherein: The gate wiring includes: a first gate wiring configured to provide a black scan signal to a corresponding pixel driving circuit among the pixel driving circuits; a second gate wiring configured to provide an emission control signal to the corresponding pixel driving circuit; a third gate wiring configured to provide a write scan signal to the corresponding pixel driving circuit; and a fourth gate wiring configured to provide a compensation scanning signal to the corresponding pixel driving circuit, and Wherein, when viewed from above the plane, the second shielding pattern overlaps with the third gate wiring and the fourth gate wiring.

14. The electronic device according to claim 1, wherein The data line includes: a first data line connected to a first group of pixel driving circuits among the pixel driving circuits; and a second data line spaced apart from the first data line in the first direction and connected to a second group of pixel driving circuits among the pixel driving circuits, and Wherein, the circuit layer further includes data connection lines in the display area that are electrically connected to the second data lines respectively.

15. The electronic device according to claim 1, further comprising: a driver chip electrically connected to the circuit layer; as well as a sensor chip, electrically connected to the circuit layer, The second readout line is connected to the sensor chip through the connecting line.

16. The electronic device according to claim 15, wherein: The driver chip and the sensor chip are adjacent to one side of the display area.

17. An electronic device having a display area and a non-display area, the electronic device comprising: base layer; a circuit layer on the base layer; as well as an element layer on the circuit layer, the element layer including a light emitting element and a light receiving element in the display area, Wherein, the circuit layer includes: a pixel driving circuit connected to the light-emitting element; a sensor driving circuit connected to the light receiving element; a data line connected to the pixel driving circuit; a gate wiring connected to the pixel driving circuit; a voltage line connected to the pixel driving circuit; a first readout line connected to a first group of sensor drive circuits among the sensor drive circuits; a second readout line spaced apart from the first readout line in a first direction and connected to a second group of sensor drive circuits among the sensor drive circuits; vertical connection lines electrically connected to the second readout lines in the display area, respectively, and arranged to intersect the gate wiring; and A shielding pattern is configured to overlap with the gate wiring and the vertical connection line when viewed from above a plane, and is arranged between the gate wiring and the vertical connection line in a normal direction perpendicular to the plane, wherein the shielding pattern extends from at least one of the voltage lines.

18. The electronic device according to claim 17, wherein: The voltage line includes: a first initialization voltage line configured to apply a first initialization voltage to the pixel driving circuit; and a second initialization voltage line configured to apply a second initialization voltage to the pixel driving circuit, and The shielding pattern includes a first shielding pattern electrically connected to the second initialization voltage line.

19. The electronic device according to claim 18, wherein: The second initialization voltage line includes: a second horizontal initialization voltage line extending in the first direction; and A second vertical initialization voltage line extends in a second direction crossing the first direction and is disposed on a layer different from a layer on which the second horizontal initialization voltage line is disposed.

20. The electronic device according to claim 19, wherein The vertical connection line and the second vertical initialization voltage line are on the same layer, and The first shielding pattern extends from the second horizontal initializing voltage line.

21. The electronic device according to claim 20, wherein: The gate wiring includes: a first gate wiring configured to provide a black scan signal to a corresponding pixel driving circuit among the pixel driving circuits; a second gate wiring configured to provide an emission control signal to the corresponding pixel driving circuit; a third gate wiring configured to provide a write scan signal to the corresponding pixel driving circuit; and a fourth gate wiring configured to provide a compensation scanning signal to the corresponding pixel driving circuit, and Wherein, when viewed from above the plane, the first shielding pattern overlaps with the first gate wiring and the second gate wiring.

22. The electronic device according to claim 18, wherein The shield pattern further includes a second shield pattern connected to the first initialization voltage line.

23. The electronic device according to claim 22, wherein: The first initialization voltage line includes: a first horizontal initialization voltage line extending in the first direction; and A first vertical initialization voltage line extends in a second direction crossing the first direction and is disposed on a layer different from a layer on which the first horizontal initialization voltage line is disposed.

24. The electronic device according to claim 23, wherein: The vertical connection line and the first vertical initialization voltage line are on the same layer, and The second shielding pattern extends from the first horizontal initializing voltage line.

25. The electronic device according to claim 24, wherein The gate wiring includes: a first gate wiring configured to provide a black scan signal to a corresponding pixel driving circuit among the pixel driving circuits; a second gate wiring configured to provide an emission control signal to the corresponding pixel driving circuit; a third gate wiring configured to provide a write scan signal to the corresponding pixel driving circuit; and a fourth gate wiring configured to provide a compensation scanning signal to the corresponding pixel driving circuit, and Wherein, when viewed from above the plane, the second shielding pattern overlaps with the third gate wiring and the fourth gate wiring.

26. The electronic device according to claim 17, further comprising: a driver chip electrically connected to the circuit layer; as well as a sensor chip, electrically connected to the circuit layer, The second readout line is connected to the sensor chip through the vertical connection line.

27. The electronic device according to claim 26, wherein: The driver chip and the sensor chip are disposed adjacent to one side of the display area.

Images