Method and device for analyzing reasons of abnormal power failure of flash memory device and power failure testing device

Abstract

The invention provides an analysis method and device for an abnormal power failure reason of a flash memory device and a power failure testing device.The analysis method for the abnormal power failure reason comprises the steps that a firmware log of the flash memory device with abnormal power failure is obtained and analyzed, the method comprises the following steps of: extracting to-be-analyzed data which is used for representing characteristics and / or change trend of a threshold voltage curve of the flash memory equipment and is used for power failure reason analysis in a firmware log, and performing field comparison on the basis of a standard threshold voltage curve library in various scenes corresponding to the flash memory equipment generated by a power failure test device; and locating and analyzing the reason of abnormal power failure of the flash memory equipment. According to the method, the reasons of abnormal power failure are comprehensively and meticulously positioned, equipment faults can be quickly checked, the problem solving efficiency is improved, powerful data support can be provided for optimization design and reliability evaluation of flash memory equipment, and the stability and performance of the equipment in a complex environment are improved.

Description

Technical Field

[0001] The present application relates to the technical field of storage products, and in particular to a method and device for analyzing the cause of abnormal power failure of a flash memory device, and a power failure testing device. Background Art

[0002] Flash memory devices are electronic storage devices based on non-volatile storage technology. They use floating-gate transistors or charge capture technology as their core. They store data electronically and the information is not lost after power failure. Common types include solid-state drives (SSDs), USB flash drives, SD cards, and embedded storage chips (such as eMMC, NAND Flash, SLC, and MLC). With advantages such as high-speed reading and writing, low power consumption, strong shock resistance, and compact size, they are widely used in consumer electronics, data centers, industrial control, and automotive electronics, and have become the mainstream solution for modern data storage.

[0003] For embedded devices, unexpected power outages of flash memory devices during use are common. These situations can lead to significant risks of data loss, device damage, and even system crashes. Therefore, targeted testing is crucial for ensuring reliability. Currently, the industry typically performs power-off tests on the entire device. While representative, this whole-device testing process can easily introduce other factors, such as the overall device capacitance and the voltage drop slope during a power outage, resulting in unrepresentative test results.

[0004] Traditional power-off testing solutions use programmable logic to control relays to output a power-off signal to the test board's main controller, which then controls the flash memory device to erase and write data to determine its performance during a power-off event. However, due to the lack of feedback and reliance on relays to output the power-off signal, the main controller cannot precisely control the power-off timing, resulting in an uncontrollable black-box test. The solution is to increase the number of tests and use random numbers to control the power-on and power-off times to fully cover abnormal power-off testing for all flash memory operation scenarios. This approach is time-consuming and difficult to reproduce. Crucially, the relationship between flash memory operation and power-off timing cannot be precisely controlled.

[0005] However, in reality, even if the flash memory device has been tested for power failure, users may still encounter abnormal power failure during use. In after-sales service, it is necessary not only to "discover the problem" but also to "locate the root cause."

[0006] Existing methods for analyzing the causes of abnormal power failures in flash memory devices mainly rely on log parsing, hardware signal capture, and firmware debugging interface backtracing. However, log information often only records the number of events and lacks correlation with the device's operating scenario at the time of power failure, resulting in blind spots in root cause identification in complex scenarios.

[0007] It can be seen that conducting power-off tests before the sale of flash memory devices and locating and analyzing the causes of power-off after the sale are necessary processes for technical verification, and are also key means to reduce after-sales costs and enhance user trust. Summary of the Invention

[0008] The present application provides a method and device for analyzing the cause of abnormal power failure of a flash memory device, and a power failure testing device, which can solve the technical problems of existing power failure testing of flash memory devices and positioning analysis of abnormal power supply causes, lack of effective feedback, and inability to achieve efficient testing and accurate positioning analysis.

[0009] In a first aspect, an embodiment of the present application provides a method for analyzing the cause of abnormal power failure of a flash memory device, comprising: Obtain and parse the firmware log of the flash memory device that experienced an abnormal power failure; Extracting data to be analyzed for power failure cause analysis from the firmware log, which is used to characterize characteristics and / or change trends of a threshold voltage curve of the flash memory device; Obtaining a library of standard threshold voltage curves corresponding to various scenarios of the flash memory device; The cause of abnormal power failure of the flash memory device is located and analyzed based on the data to be analyzed and the standard threshold voltage curve library under various scenarios.

[0010] In some embodiments, locating and analyzing the cause of the abnormal power failure of the flash memory device based on the data to be analyzed and the standard threshold voltage curve library under various scenarios includes: parsing the data to be analyzed to determine the working state of the flash memory device when power is lost; Selecting a standard threshold voltage curve library for a corresponding scenario according to the working state of the flash memory device when power is lost; Comparing the data to be analyzed with a threshold voltage curve in a standard threshold voltage curve library under the corresponding scenario to determine a time when the flash memory device loses power; An analysis result of a cause of abnormal power failure of the flash memory device is generated according to a scenario and time when the flash memory device loses power.

[0011] In some embodiments, the standard threshold voltage curve library under the multiple scenarios includes at least a standard threshold voltage curve library corresponding to when no power failure occurs during the erasing process and the writing process, a standard threshold voltage curve library corresponding to when no power failure occurs during the erasing process and a power failure occurs during the writing process, a standard threshold voltage curve library corresponding to when power failure occurs during the erasing process and no power failure occurs during the writing process, and a standard threshold voltage curve library corresponding to when power failure occurs during both the erasing process and the writing process.

[0012] In some embodiments, the library of standard threshold voltage curves under various scenarios is generated by selectively controlling the timing of cutting off power supply to the flash memory device during the erasing and writing processes of the flash memory device.

[0013] In some embodiments, during the erasing process of the flash memory device, controlling the timing of cutting off power to the flash memory device and generating a threshold voltage curve includes: In response to the first generation instruction, generate an erase instruction and output the erase instruction to the flash memory device; receiving first data returned by the flash memory device in response to the erase instruction after completing the erase operation; the first data including a first duration for the flash memory device to complete the erase operation and threshold voltage change data during the erase process; Fitting and generating a standard threshold voltage curve corresponding to the flash memory device being erased without power failure according to the first data; Selecting N time points within the first time period, and setting a power-off control instruction at at least one of the N time points, and outputting the instruction to the flash memory device; receiving second data returned by the flash memory device in response to the erase instruction and the power-off control instruction after completing the erase operation; the second data including threshold voltage change data of the flash memory device during the erase process; A standard threshold voltage curve corresponding to at least one power failure during the erasing process of the flash memory device is generated by fitting according to the second data.

[0014] In some embodiments, the N time points are N equally divided time points of the first duration.

[0015] In some embodiments, during a write process of the flash memory device, controlling a timing of cutting off power to the flash memory device and generating a threshold voltage curve includes: In response to the first generation instruction, generate an erase instruction and output the erase instruction to the flash memory device; After determining that the flash memory device completes the erasing action, generating a write instruction in response to a second generation instruction, and outputting the write instruction to the flash memory device; receiving third data transmitted back by the flash memory device in response to the write instruction after the flash memory device completes the write action; the third data including a second time duration for the flash memory device to complete the write action and threshold voltage change data during the write process; Fitting and generating a standard threshold voltage curve corresponding to a write process of the flash memory device without power failure according to the third data; selecting M time points within the second time period, and setting a power-off control instruction at at least one of the M time points, and outputting the instruction to the flash memory device; receiving fourth data returned by the flash memory device in response to the write instruction and the power-off control instruction in response to the completion of the write action; the fourth data including threshold voltage change data of the flash memory device during the write process; A standard threshold voltage curve corresponding to at least one power failure occurring during a writing process of the flash memory device is generated by fitting according to the fourth data.

[0016] In some embodiments, the M time points are M equally divided time points of the second duration.

[0017] In a second aspect, an embodiment of the present application provides a device for analyzing the cause of abnormal power failure of a flash memory device, comprising: Memory, used to store programs or instructions executed by the computer; A processor is used to execute the computer execution program or instruction to implement the method for analyzing the cause of abnormal power failure of the flash memory device as described in any embodiment of the first aspect.

[0018] In a third aspect, an embodiment of the present application provides a flash memory device power-off test apparatus, comprising: A power control module, connected between the input power supply and the power supply terminal of the flash memory device, for controlling whether the flash memory device is powered on; a control module, configured to generate and output a power-off control signal for controlling the power control module to be disconnected, and to generate an erase instruction for controlling the flash memory device to perform an erase action and / or a write instruction for performing a write action; a receiving module, configured to receive test data returned by the flash memory device in response to the erase instruction and / or write instruction when the flash memory device completes an erase action and / or a write action; the test data at least including threshold voltage change data corresponding to no power failure and at least one power failure during the erase and / or write process of the flash memory device; A processing module is used to process the test data to generate the flash memory device power-off test result, and / or to generate a standard threshold voltage curve library in multiple scenarios for analyzing the cause of abnormal power-off of the flash memory device based on the test data.

[0019] The embodiments of the present application provide a method and apparatus for analyzing the cause of abnormal power failures in flash memory devices, as well as a power failure testing apparatus. The method includes obtaining and parsing the firmware log of the flash memory device experiencing the abnormal power failure, extracting data from the firmware log that characterizes the characteristics and / or changing trends of the flash memory device's threshold voltage curve for power failure analysis, and locating and analyzing the cause of the abnormal power failure in the flash memory device based on a comparison with a library of standard threshold voltage curves corresponding to various scenarios of the flash memory device generated by the power failure testing apparatus. This method achieves comprehensive and detailed locating of the cause of the abnormal power failure, enabling rapid troubleshooting of device failures and improving problem-solving efficiency. It also provides strong data support for the optimized design and reliability assessment of flash memory devices, thereby improving the stability and performance of the devices in complex environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0021] Figure 1 A schematic diagram of the structure of a power-off test device for a flash memory device provided in one embodiment of the present application; Figure 2 A flowchart of a method for analyzing the cause of abnormal power failure of a flash memory device provided by an embodiment of the present application; Figure 3 A flowchart of establishing a standard threshold voltage curve library for an erase process provided by one embodiment of the present application; Figure 4 A schematic diagram of actively controlling power-off timing during an erasing process according to an embodiment of the present application; Figure 5 A flowchart of establishing a standard threshold voltage curve library for a write process provided by one embodiment of the present application; Figure 6 A schematic diagram of actively controlling power-off timing during a write process according to an embodiment of the present application; Figure 7 A flowchart of a method for analyzing the cause of abnormal power failure of a flash memory device provided by another embodiment of the present application; Figures 8a to 8d A comparison diagram of the threshold voltage curves of a flash memory device with and without power failure provided by an embodiment of the present application; wherein, Figure 8a and Figure 8b These are the threshold voltage curves when power is lost and when power is not lost during the erase process. Figure 8c and Figure 8d The threshold voltage curves are shown in Figure 1 when power is lost and when power is not lost during the writing process. Figure 9A schematic diagram of the structure of a device for analyzing causes of abnormal power failure of a flash memory device provided in one embodiment of the present application.

[0022] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0023] The present application is further described in detail below by means of specific embodiments in conjunction with the accompanying drawings. Similar elements in different embodiments are numbered with associated similar elements. In the following embodiments, many detailed descriptions are provided to enable the present application to be better understood. However, those skilled in the art will readily appreciate that some of the features may be omitted in different circumstances, or may be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification. This is to avoid the core portion of the present application being overwhelmed by excessive descriptions. For those skilled in the art, it is not necessary to describe these related operations in detail. They can fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0024] In addition, the features, operations, or characteristics described in the specification may be combined in any appropriate manner to form various embodiments. Furthermore, the steps or actions in the method description may be reordered or adjusted in a manner readily apparent to those skilled in the art. Therefore, the various sequences in the specification and drawings are provided solely for the purpose of clearly describing a particular embodiment and are not intended to be mandatory, unless otherwise specified.

[0025] The terms "first," "second," and so on, in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein. Furthermore, the objects distinguished by "first," "second," and so on generally refer to a class and do not limit the number of objects. For example, the first object can be one or more. Furthermore, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship. The terms "connection" and "coupling" used in this application, unless otherwise specified, include both direct and indirect connections (couplings).

[0026] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0027] Figure 1 This is a schematic diagram of a power-off test device for a flash memory device provided by an embodiment of the present application. Figure 1 As shown, the flash memory device power-off test apparatus provided in this embodiment at least includes a power control module 110 , a control module 120 , a receiving module 130 and a processing module 140 .

[0028] In this embodiment, the power control module 110 is connected between the input power supply and the power supply terminal of the flash memory device, and is used to control whether the input power supply is supplied to the flash memory device. In its on state, the power supply terminal of the flash memory device can obtain the VCC voltage from the input power supply, enabling it to complete erase and write operations and realize its storage function. In its off state, the power supply terminal of the flash memory device cannot obtain the VCC voltage from the input power supply, and the flash memory device is in a power-off state. In other words, by controlling the power control module 110 to be on or off, a power-off test of the flash memory device can be performed.

[0029] In some embodiments, the power control module 110 includes any one of a relay, a switch circuit, a logic control circuit, and a power management chip.

[0030] The first output terminal of the control module 120 is connected to the control terminal of the power control module 110 and is configured to generate a power-off control signal for controlling the power control module 110 to be disconnected, and transmit the signal to the control terminal of the power control module 110 via the first output terminal. In response to the power-off control signal, the control terminal of the power control module 110 disconnects itself, thereby severing the connection between the input power supply and the power supply terminal of the flash memory device, thereby controlling the power-off of the flash memory device. The second output terminal of the control module 120 is connected to the command receiving terminal of the flash memory device and is configured to generate at least an erase instruction for controlling the flash memory device to perform an erase operation and / or a write instruction for controlling the flash memory device to perform a write operation, and transmit the signal to the command receiving terminal of the flash memory device via the second output terminal. The flash memory device performs an erase operation and / or a write operation in response to the erase instruction and / or the write instruction.

[0031] The input end of the receiving module 130 is connected to the data output end of the flash memory device, and is at least used to receive test data returned by the flash memory device in response to the erase instruction and / or write instruction when the erase action and / or write action is completed; the test data at least includes the threshold voltage change data corresponding to no power failure and at least one power failure during the erase and / or write process of the flash memory device.

[0032] The input end of the processing module 140 is connected to the output end of the receiving module 130, and is at least used to receive test data and perform data processing on the test data to generate a flash memory device power-off test result, and / or to generate a standard threshold voltage curve library in various scenarios for analyzing the causes of abnormal power-off of the flash memory device based on the test data.

[0033] The flash memory device power-off test device provided in this embodiment integrates a power control module, a control module, a receiving module, and a processing module to achieve accurate simulation and comprehensive testing of power failures that occur in flash memory devices during the erasing or writing process. Compared with the traditional power-off test method of passively relying on relays to randomly trigger power-off signals, this test device accurately controls the power-off signal by actively controlling the relays, thereby achieving precise control of the timing of power failure. This improvement enables the test to simulate power-off scenarios for flash memory devices at specific operating stages (such as key nodes of erasing or writing), thereby more effectively capturing the behavioral characteristics of the device under abnormal power failures, significantly improving the pertinence and repeatability of the test, and providing more reliable data support for comprehensive evaluation of the power-off reliability of flash memory devices.

[0034] Based on the implementation of the above-mentioned flash memory device power-off test device, the test results obtained and the standard threshold voltage curve library under various scenarios generated based on the test data are further used to locate and analyze the cause of abnormal power-off of the flash memory device.

[0035] The following describes the test results output by the flash memory device power-off test apparatus and the application of a standard threshold voltage curve library for various scenarios generated based on the test data in locating and analyzing the cause of abnormal power-off of a flash memory device.

[0036] Figure 2 This is a flow chart of a method for analyzing the cause of abnormal power failure of a flash memory device provided by an embodiment of the present application. Figure 2 As shown, the method for analyzing the cause of abnormal power failure of a flash memory device provided in an embodiment of the present application specifically includes the following steps: Step S210: Obtain and analyze the firmware log of the flash memory device that experiences abnormal power failure.

[0037] Firmware logs are a collection of information automatically recorded by flash memory devices during operation, including key data such as device operations and status changes. During flash memory device operation, if an abnormal power outage occurs, the device's internal monitoring mechanism will immediately activate. Typically, during a power outage, the threshold voltage of a flash memory device will change due to factors such as power outages and changes in circuit status. The device automatically records these threshold voltage changes in a log using a specific format and rules. These records contain key information such as the voltage change value and time of occurrence. After obtaining the log, it needs to be parsed. Parsing converts the information stored in the log, which is encoded or formatted specifically, into a clear data form that is easy to understand and analyze.

[0038] Step S220: extracting data to be analyzed for power-off cause analysis from the firmware log, which is used to characterize the characteristics and / or change trends of the threshold voltage curve of the flash memory device.

[0039] After parsing the firmware log data, it's necessary to filter out information related to the flash memory device's threshold voltage curve. During an abnormal power outage, the device's threshold voltage can change due to factors such as power outages and circuit state changes. Extracting the flash memory device's voltage characteristics under different operating and environmental conditions, as recorded in the log, reveals these characteristics and changing trends, which are crucial for analyzing the cause of the abnormal power outage. Extracted data that characterizes the threshold voltage curve characteristics and / or changing trends serves as the data to be analyzed, providing a key basis for subsequent comparative analysis with the standard curve.

[0040] Step S230: Obtain a library of standard threshold voltage curves corresponding to various scenarios of the flash memory device.

[0041] In order to accurately analyze the cause of abnormal power failure of the flash memory device, it is necessary to establish a comprehensive reference standard to compare with the data to be analyzed extracted in step S220 to locate and identify the cause of the power failure.

[0042] In some embodiments, the standard threshold voltage curve library under various scenarios includes at least a standard threshold voltage curve library corresponding to when no power failure occurs during the erasing process and the writing process, a standard threshold voltage curve library corresponding to when no power failure occurs during the erasing process and a power failure occurs during the writing process, a standard threshold voltage curve library corresponding to when power failure occurs during the erasing process and no power failure occurs during the writing process, and a standard threshold voltage curve library corresponding to when power failure occurs during both the erasing process and the writing process.

[0043] In some embodiments, before analyzing the cause of an abnormal power failure in a flash memory device, the flash memory device power failure testing apparatus described in the above embodiments is used to simulate operating processes in various different scenarios. The timing of power failures is actively controlled during different operations. Combined with test data fed back by the flash memory device, a library of standard threshold voltage curves for various scenarios is established, serving as a reference standard for accurately analyzing the cause of abnormal power failures in the flash memory device. Based on the above flash memory device power failure testing apparatus, by actively selecting and controlling the timing of powering off the flash memory device during the flash memory device erase and write processes, a comprehensive reference standard is generated, establishing a library of standard threshold voltage curves for various scenarios.

[0044] Step S240: Locate and analyze the cause of the abnormal power failure of the flash memory device based on the data to be analyzed and a library of standard threshold voltage curves in various scenarios.

[0045] The data to be analyzed, extracted in step S220, is carefully compared and analyzed with the library of standard threshold voltage curves for various scenarios obtained in step S230. This comparison reveals differences between the threshold voltage characteristics of the analyzed data and the standard curves, such as voltage magnitude, rate of change, and fluctuation range. Based on these differences and combined with the normal operating conditions represented by the standard curves in different scenarios, the specific cause of the abnormal power failure in the flash memory device can be gradually identified, providing clear direction and basis for resolving the abnormal power failure issue.

[0046] To sum up, the method for analyzing the cause of abnormal power failure of a flash memory device provided in this embodiment obtains and parses the firmware log, accurately extracts the threshold voltage-related data to be analyzed, and obtains the analysis results by comparing it with the multi-scenario standard threshold voltage curve library. It achieves a comprehensive and detailed positioning of the cause of the abnormal power failure, can quickly troubleshoot device failures, improves problem-solving efficiency, and can also provide strong data support for the optimized design and reliability evaluation of flash memory devices, thereby improving the stability and performance of the device in complex environments.

[0047] The following describes in detail the process of establishing a standard threshold voltage curve library for the erasure process based on the above-mentioned flash memory device power-off test apparatus.

[0048] Figure 3 This is a flowchart of establishing a standard threshold voltage curve library for the erase process provided by one embodiment of the present application. Figure 3 As shown, when establishing a standard threshold voltage curve library for the erasing process provided by this embodiment, the timing of powering off the flash memory device is controlled during the erasing process of the flash memory device, and the threshold voltage curve is generated and recorded. Specifically, the following steps are included: Step S310: In response to the first generation instruction, generate an erase instruction and output it to the flash memory device.

[0049] When establishing a standard threshold voltage curve library for the erasure process, the above-mentioned flash memory device power-off test device will, after monitoring the first generation instruction input by the tester, trigger the response program to generate an erase instruction in response to the first generation instruction and output it to the flash memory device.

[0050] Step S320: receiving first data transmitted back by the flash memory device in response to the erase instruction after completing the erase operation; the first data includes a first duration for the flash memory device to complete the erase operation and threshold voltage change data during the erase process.

[0051] After receiving the erase instruction, the flash memory device will perform the erase operation according to the instruction. When the erase operation is completed, the flash memory device will return the relevant first data to the receiving module 130 of the power-off test device. Because the processing module 140 of the power-off test device needs to process the data transmitted by the receiving module 130 to generate test results and / or a standard threshold voltage curve library. Therefore, the first data must at least include the first duration for the flash memory device to complete the erase operation and the threshold voltage change data during the erase process. The first duration reflects the time period of the flash memory device under normal erase operation, which helps to accurately control the power-off timing of the flash memory device during the erase process. The change in threshold voltage is of great significance for understanding the performance and stability of the flash memory device during the erase process, and provides an original basis for subsequent data analysis and curve fitting.

[0052] Step S330: generating, based on the first data, a standard threshold voltage curve corresponding to an erasing process of the flash memory device without power failure.

[0053] After receiving the first data, the processing module 140 of the power-off test device performs a curve fitting operation based on the threshold voltage change data in the first data and the corresponding time information to generate a standard threshold voltage curve for the flash memory device when no power is lost during the erase process. This standard threshold voltage curve for the flash memory device when no power is lost during the erase process is the most basic curve in the standard threshold voltage curve library for the erase process and serves as a reference standard for the normal operation of the flash memory device. It helps to eliminate the possibility that an abnormal power loss of the flash memory device does not occur during the erase process.

[0054] Step S340: select N time points within the first time period, set a power-off control instruction at at least one of the N time points, and output the instruction to the flash memory device.

[0055] The most important part of the standard threshold voltage curve library for the erase process is simulating a power failure in the flash memory device during the erase process. Therefore, it is necessary to rationally select N time points within the first duration of the erase operation, obtained in step S320. After determining the time points, the control module 120 of the power failure test device sets a power failure control signal at at least one of these time points. In response to the power failure control signal, the power supply control module 110 cuts off power to the flash memory device at the corresponding time point. This controls the flash memory device to lose power at a specific time point, preparing for the acquisition of relevant data from the device during the power failure.

[0056] In some embodiments, the N time points are N equally divided time points of the first duration.

[0057] Dividing the first duration into N equal parts to determine N time points greatly enhances the regularity and comprehensiveness of the simulation. In terms of regularity, this evenly distributed time points facilitates observation and analysis of the flash memory device's performance during power outages at different stages. In terms of comprehensiveness, this approach covers all stages of the erase process, ensuring a comprehensive assessment of the device's ability to cope with power outages throughout the entire erase process, helping to more accurately identify potential issues.

[0058] Step S350: receiving second data returned by the flash memory device in response to the erase instruction and the power-off control instruction after completing the erase operation; the second data includes threshold voltage change data of the flash memory device during the erase process.

[0059] After simultaneously receiving the erase command and the power-off control command, the flash memory device executes the erase operation as instructed by the command and experiences a power-off event at a set time. After the erase operation is complete, the flash memory device transmits second data containing threshold voltage change data during the erase process back to the receiving module 130 of the power-off test apparatus. The second data, including threshold voltage change data during the erase process, reflects the actual performance of the flash memory device when a power-off event occurs during the erase process, particularly the change in threshold voltage under power-off interference, which facilitates in-depth analysis of the impact of power-off on the flash memory device.

[0060] Step S360: generating, based on the second data, a standard threshold voltage curve corresponding to at least one power failure during the erasing process of the flash memory device by fitting.

[0061] After receiving the second data, the processing module 140 of the power-off test device uses the threshold voltage variation data in the second data as a basis and combines the corresponding time information to generate a standard threshold voltage curve for the flash memory device when power is lost at least once during the erase process. These curves provide a more intuitive understanding of the impact of power loss on the threshold voltage variation of the flash memory device.

[0062] It can be understood that the flash memory device erase process is fitted and generated when at least one power failure occurs. That is, the flash memory device erase process is fitted and generated when there are multiple standard threshold voltage curves corresponding to one power failure. The curves include at least N standard threshold voltage curves corresponding to power failures occurring at the N time points determined above, and may also include multiple standard threshold voltage curves corresponding to power failures occurring at two or more of the N time points determined above.

[0063] Figure 4 This is a schematic diagram of actively controlling the power-off timing during the erasing process provided by an embodiment of the present application. Figure 4 As shown, 10 equally divided points can be set in the erase cycle to simulate the erase process and actively control the flash memory device to have at least 10 power-off conditions, so as to generate at least 10 standard threshold voltage curves corresponding to one power-off.

[0064] The following describes in detail the process of establishing a standard threshold voltage curve library for a write process based on the above-mentioned flash memory device power-off test apparatus.

[0065] Figure 5 This is a flowchart of establishing a standard threshold voltage curve library for a write process provided by an embodiment of the present application. Figure 5 As shown, when establishing a standard threshold voltage curve library for the writing process provided by this embodiment, the threshold voltage curve is generated and recorded during the writing process of the flash memory device by controlling the timing of cutting off the power supply of the flash memory device. Specifically, the following steps are included: Step S510: In response to the first generation instruction, generate an erase instruction and output it to the flash memory device.

[0066] Flash memory devices utilize blocks as their fundamental storage unit, based on their unique storage principles and data management mechanisms. Before writing data, the existing data within the block must be erased to restore the storage unit to a writable state. Therefore, before establishing a library of standard threshold voltage curves for the erase process, it's necessary to input commands to control the flash memory device to complete the data erase.

[0067] Step S520: After determining that the flash memory device completes the erasing operation, generate a write instruction in response to the second generation instruction, and output the write instruction to the flash memory device.

[0068] Step S530: receiving third data transmitted back by the flash memory device in response to the write instruction after the write operation is completed; the third data includes the second time duration for the flash memory device to complete the write operation and the threshold voltage change data during the write process.

[0069] Step S540: generating, based on the third data, a standard threshold voltage curve corresponding to a flash memory device writing process without power failure.

[0070] Step S550: select M time points within the second time period, set a power-off control instruction at at least one of the M time points, and output the instruction to the flash memory device.

[0071] In some embodiments, the M time points are M equally divided time points of the second duration.

[0072] Step S560: Receive fourth data returned by the flash memory device in response to the write instruction and the power-off control instruction to complete the write operation; the fourth data includes threshold voltage change data of the flash memory device during the write process.

[0073] Step S570: Generate, based on the fourth data, a standard threshold voltage curve corresponding to at least one power failure during the writing process of the flash memory device by fitting.

[0074] Steps S520-S570 specifically describe the process of controlling the timing of powering off the flash memory device during the write process, generating and recording the threshold voltage curve, and establishing a standard threshold voltage curve library for the write process. This process is identical or similar to the process of establishing a standard threshold voltage curve library for the erase process described in steps S320-S360, and is not detailed here to avoid repetition.

[0075] The standard threshold voltage curve library for establishing a writing process established through steps S510 to S570 includes at least a standard threshold voltage curve corresponding to a writing process without power failure, and multiple standard threshold voltage curves corresponding to a writing process with at least one power failure.

[0076] Figure 6 This is a schematic diagram of actively controlling the power-off timing during the writing process provided by an embodiment of the present application. Figure 6 As shown, 10 equally divided points can be set in the write cycle to simulate the write process and actively control the flash memory device to have at least 10 power failures, so as to generate at least 10 standard threshold voltage curves corresponding to one power failure.

[0077] Figure 7 This is a flow chart of a method for analyzing the cause of abnormal power failure of a flash memory device provided by another embodiment of the present application. Figure 7 As shown, step S240 in the above embodiment, locating and analyzing the cause of abnormal power failure of the flash memory device based on the data to be analyzed and the standard threshold voltage curve library in various scenarios, specifically includes the following steps: Step S710: Parse the data to be analyzed to determine the working state of the flash memory device when the power is off.

[0078] By carefully analyzing this data, we can extract characteristic parameters related to the device's working status, including at least information on whether the flash memory device was in different working states such as writing data, reading data, idle state, or erasing data when the power outage occurred. Clarifying the working status of the device at the time of power outage is the basis for subsequently accurately locating the cause of the abnormal power outage, allowing for more targeted analysis.

[0079] Step S720: Select a standard threshold voltage curve library corresponding to a scenario according to the working state of the flash memory device when power is lost.

[0080] Based on the above, it can be seen that the pre-stored standard threshold voltage curve library includes standard threshold voltage curve libraries for multiple scenarios, and each standard threshold voltage curve library for each scenario also contains multiple standard threshold voltage curves. Comparing the data to be analyzed with the standard threshold voltage curve library one by one would be very time-consuming. Therefore, after determining the operating state of the flash memory device when it loses power, based on the preliminarily determined power-off scenario, accurately selecting a standard threshold voltage curve library for the scenario that matches it from the standard threshold voltage curve library for multiple scenarios can significantly reduce data processing and improve efficiency.

[0081] Step S730 : Compare the data to be analyzed with the threshold voltage curve in the standard threshold voltage curve library under the corresponding scenario to determine the time when the flash memory device is powered off.

[0082] After determining the working state of the flash memory device when it loses power and the corresponding standard threshold voltage curve library, the threshold voltage change in the parsed data to be analyzed is compared with the curve in the standard threshold voltage curve library under the selected corresponding scenario to find the point in the data to be analyzed where there is a significant deviation from the standard curve. For example, when the voltage in the data to be analyzed suddenly drops or rises abnormally and does not match the smooth change of the standard curve, it can be preliminarily determined that the moment corresponding to this point is the moment when the device loses power.

[0083] Step S740: Generate an analysis result of the cause of the abnormal power failure of the flash memory device according to the scene and time when the flash memory device loses power.

[0084] After determining the scenario and specific time when the flash memory device loses power, combined with information such as the device operating characteristics in that scenario and the circuit status at the time of power failure, these factors are comprehensively considered and analyzed in depth, ultimately generating detailed analysis results on the cause of the abnormal power failure of the flash memory device, completing a comprehensive and detailed analysis of the cause of the abnormal power failure.

[0085] FIG8 is a comparison diagram of threshold voltage curves of a flash memory device with and without power failure provided by an embodiment of the present application.

[0086] like Figure 8a and Figure 8b The threshold voltage curves are shown in Figure 1 when power is lost and when power is not lost during the erase process. Figure 8a For the setting, power failure occurs at 5 / 10*t during the erase process. Figure 8a and Figure 8b The change in the threshold voltage curve during power failure can be seen intuitively. That is, by comparing the threshold voltage curves, it can be analyzed that the cause of the erase failure is that the power failure occurred when the erase period reached about 5 / 10*t.

[0087] In addition, after multiple tests, it was found that the flash memory that experienced abnormal power failure during the erasing period of 0~7 / 10*t was in a non-erased state according to the test results, while the flash memory that experienced abnormal power failure during the erasing period of 8 / 10~10 / 10*t was in an erased state according to the test results.

[0088] Further write operations were performed on the flash memory that experienced abnormal power failure during the erase process to detect whether data can be stably written to the flash memory that experienced abnormal power failure. After testing, the flash memory that experienced abnormal power failure during the erase period of 0~7 / 10*t had a large number of error bits in the programmed data, resulting in the data being unable to be accurately read successfully. However, the flash memory block that experienced abnormal power failure during the erase period of 8 / 10~10 / 10*t could accurately read the data after programming.

[0089] like Figure 8c and Figure 8d The threshold voltage curves are shown in Figure 1 when power is lost and when power is not lost during the writing process. Figure 8c The power is off at 7 / 10*t during the writing process. Figure 8c and Figure 8d The change in the threshold voltage curve of power failure can be seen intuitively, and the reason for the write failure can be analyzed as a power failure occurring around 7 / 10*t.

[0090] In addition, after testing, for flash memory blocks that experienced abnormal power failure during the write period of 0~4 / 10*t, the data written before the power failure was not written to the flash memory, and the flash memory was still in the erased state. During the write period of 5 / 10*t~8*t, a large number of error bits occurred due to abnormal power failure, resulting in the inability to accurately read the data. However, for flash memory blocks that experienced abnormal power failure during the write period of 9 / 10~10 / 10*t, the programmed data could be accurately read successfully.

[0091] Figure 9 This is a schematic diagram of a device for analyzing the cause of abnormal power failure of a flash memory device provided by an embodiment of the present application. Figure 9 As shown, the apparatus for analyzing the cause of abnormal power failure of a flash memory device provided in this embodiment includes a memory 910 and a processor 920 , and the memory 910 and the processor 920 may be connected via a bus.

[0092] In this embodiment, the memory 910 is used to store computer-executable instructions or commands.

[0093] The memory 910 may include a volatile memory or a non-volatile memory, or the memory 910 may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM) and direct rambus random access memory (DRRAM).

[0094] Memory 910 includes, but is not limited to, these and any other suitable types of memory.

[0095] In this embodiment, the processor 920 is used to execute a computer program or instruction to implement each process of any embodiment of the above-mentioned method for analyzing the cause of abnormal power failure of the flash memory device, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0096] The processor 920 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0097] An embodiment of the present application also provides a readable storage medium, which stores a program or instruction. When the program or instruction is executed by a processor, it implements the various processes of any embodiment of the above-mentioned method for analyzing the cause of abnormal power failure of the flash memory device and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0098] The processor may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0099] The readable storage medium includes a computer-readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk, etc.

[0100] An embodiment of the present application also provides a chip, which includes a processor and a communication interface, wherein the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the various processes of any embodiment of the above-mentioned method for analyzing the cause of abnormal power failure of the flash memory device, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0101] It is understandable that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0102] Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer program. When all or part of the functions in the above embodiments are implemented by computer program, the program can be stored in a computer-readable storage medium, and the storage medium can include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to implement the above functions. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor, all or part of the above functions can be implemented. In addition, when all or part of the functions in the above embodiments are implemented by computer program, the program can also be stored in a storage medium such as a server, another computer, disk, optical disk, flash disk or mobile hard disk, and saved in the memory of the local device by downloading or copying, or the system of the local device is updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be implemented.

[0103] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can make several simple deductions, modifications or replacements based on the ideas of the present application without departing from the scope of protection of the purpose of the present application and the claims. All of these are within the protection of the present application.

Claims

1. A method for analyzing the cause of abnormal power failure of a flash memory device, characterized in that: include: Obtain and parse the firmware log of the flash memory device that experienced an abnormal power failure; Extracting data to be analyzed for power failure cause analysis from the firmware log, which is used to characterize characteristics and / or change trends of a threshold voltage curve of the flash memory device; Obtaining a library of standard threshold voltage curves corresponding to various scenarios of the flash memory device; The cause of abnormal power failure of the flash memory device is located and analyzed based on the data to be analyzed and the standard threshold voltage curve library under various scenarios.

2. The method for analyzing the cause of abnormal power failure of a flash memory device according to claim 1, wherein: The locating and analyzing the cause of the abnormal power failure of the flash memory device based on the data to be analyzed and the standard threshold voltage curve library in multiple scenarios includes: parsing the data to be analyzed to determine the working state of the flash memory device when power is lost; Selecting a standard threshold voltage curve library for a corresponding scenario according to the working state of the flash memory device when power is lost; Comparing the data to be analyzed with a threshold voltage curve in a standard threshold voltage curve library under the corresponding scenario to determine a time when the flash memory device loses power; An analysis result of a cause of abnormal power failure of the flash memory device is generated according to a scenario and time when the flash memory device loses power.

3. The method for analyzing the cause of abnormal power failure of a flash memory device according to claim 1, wherein: The standard threshold voltage curve library under the multiple scenarios includes at least a standard threshold voltage curve library corresponding to no power failure during the erasing process and the writing process, a standard threshold voltage curve library corresponding to no power failure during the erasing process and a power failure during the writing process, a standard threshold voltage curve library corresponding to a power failure during the erasing process and no power failure during the writing process, and a standard threshold voltage curve library corresponding to power failure during both the erasing process and the writing process.

4. The method for analyzing the cause of abnormal power failure of a flash memory device according to any one of claims 1 to 3, characterized in that: The standard threshold voltage curve library under the various scenarios is generated by selecting and controlling the timing of cutting off the power supply to the flash memory device during the erasing process and the writing process of the flash memory device.

5. The method for analyzing the cause of abnormal power failure of a flash memory device according to claim 4, wherein: During the erasing process of the flash memory device, controlling the timing of cutting off the power supply of the flash memory device and generating a threshold voltage curve includes: In response to the first generation instruction, generate an erase instruction and output the erase instruction to the flash memory device; receiving first data returned by the flash memory device in response to the erase instruction after completing the erase operation; the first data including a first duration for the flash memory device to complete the erase operation and threshold voltage change data during the erase process; Fitting and generating a standard threshold voltage curve corresponding to the flash memory device being erased without power failure according to the first data; Selecting N time points within the first time period, and setting a power-off control instruction at at least one of the N time points, and outputting the instruction to the flash memory device; receiving second data returned by the flash memory device in response to the erase instruction and the power-off control instruction after completing the erase operation; the second data including threshold voltage change data of the flash memory device during the erase process; A standard threshold voltage curve corresponding to at least one power failure during the erasing process of the flash memory device is generated by fitting according to the second data.

6. The method for analyzing the cause of abnormal power failure of a flash memory device according to claim 5, wherein: The N time points are N equally divided time points of the first duration.

7. The method for analyzing the cause of abnormal power failure of a flash memory device according to claim 4, wherein: During a writing process of the flash memory device, controlling a timing of cutting off power supply to the flash memory device and generating a threshold voltage curve includes: In response to the first generation instruction, generate an erase instruction and output the erase instruction to the flash memory device; After determining that the flash memory device completes the erasing action, generating a write instruction in response to a second generation instruction, and outputting the write instruction to the flash memory device; receiving third data transmitted back by the flash memory device in response to the write instruction after the flash memory device completes the write action; the third data including a second time duration for the flash memory device to complete the write action and threshold voltage change data during the write process; Fitting and generating a standard threshold voltage curve corresponding to a write process of the flash memory device without power failure according to the third data; selecting M time points within the second time period, and setting a power-off control instruction at at least one of the M time points, and outputting the instruction to the flash memory device; receiving fourth data returned by the flash memory device in response to the write instruction and the power-off control instruction in response to the completion of the write action; the fourth data including threshold voltage change data of the flash memory device during the write process; A standard threshold voltage curve corresponding to at least one power failure occurring during a writing process of the flash memory device is generated by fitting according to the fourth data.

8. The method for analyzing the cause of abnormal power failure of a flash memory device according to claim 7, wherein: The M time points are M equally divided time points of the second duration.

9. A device for analyzing the cause of abnormal power failure of a flash memory device, characterized in that: At least: Memory, used to store programs or instructions executed by the computer; A processor is configured to execute the computer execution program or instruction to implement the method for analyzing the cause of abnormal power failure of a flash memory device according to any one of claims 1 to 8.

10. A flash memory device power-off test device, characterized in that: include: A power control module, connected between the input power supply and the power supply terminal of the flash memory device, for controlling whether the flash memory device is powered on; a control module, configured to generate and output a power-off control signal for controlling the power control module to be disconnected, and to generate an erase instruction for controlling the flash memory device to perform an erase action and / or a write instruction for performing a write action; a receiving module, configured to receive test data returned by the flash memory device in response to the erase instruction and / or write instruction when the flash memory device completes an erase action and / or a write action; the test data at least including threshold voltage change data corresponding to no power failure and at least one power failure during the erase and / or write process of the flash memory device; A processing module is used to process the test data to generate the flash memory device power-off test result, and / or to generate a standard threshold voltage curve library in multiple scenarios for analyzing the cause of abnormal power-off of the flash memory device based on the test data.

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