Circuit optimization method, system, apparatus, and medium based on model predictive control

Abstract

The application provides a circuit optimization method, system, device and medium based on model predictive control, relates to the technical field of integrated circuit design, and the method comprises the following steps: constructing a circuit knowledge graph and a simulation data lookup table according to a circuit design experience document and circuit simulation data; initializing a search feasible region of a design point according to the circuit knowledge graph and the simulation data lookup table, and performing multi-point exploration Bayesian optimization to obtain a candidate design point set of a current circuit; and combining a model predictive control framework to execute a reinforcement learning method according to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, so as to obtain an optimal design point of the current circuit and provide an optimal configuration of the current circuit. The application effectively reduces simulation calculation resource consumption, improves optimization efficiency, and ensures that the design meets multi-target performance requirements such as gain, power consumption and bandwidth.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, in particular to the field of optimized design of integrated circuits. BACKGROUND

[0002] The automatic optimization problem of high-robustness analog integrated circuit design aims to efficiently multi-objective optimize the performance indicators (such as gain, power consumption, bandwidth, etc.) in a complex and multi-dimensional design parameter space, so as to improve the stability, efficiency and reliability of electronic devices in various working environments. In the prior art, the optimization method based on genetic algorithm draws lessons from biological evolution theory to solve optimization problems by simulating the natural selection process, but it faces the problem of high computational cost when dealing with high-dimensional parameter space, and it is difficult to find a satisfactory solution under complex constraint conditions; as a kind of swarm intelligence technology, particle swarm optimization is suitable for solving complex optimization problems, although it is easy to implement and has good global search ability, but when dealing with high-dimensional, multi-constraint condition analog circuit design problems, it may need a long convergence time and easily fall into local optimal solution. The traditional Bayesian optimization method is a powerful global optimization tool, especially suitable for the case of expensive function evaluation, but when using Gaussian process as a proxy model, the computational overhead is large in high-dimensional, noisy design space, and the complexity of training and inference increases sharply with the increase of data volume. SUMMARY

[0003] The present application provides a circuit optimization method, system, device and medium based on model predictive control to solve one or more technical problems existing in the prior art, at least to provide a beneficial choice or create conditions.

[0004] In one aspect, the present application provides a circuit optimization method based on model predictive control, comprising the following steps:

[0005] According to the circuit design experience document and the circuit simulation data, a circuit knowledge graph and a simulation data lookup table are constructed; the circuit simulation data includes simulation data of a current circuit and simulation data of a historical circuit; the circuit knowledge graph is used to define entities, entity relationships and design experience rules in analog circuit design; the simulation data lookup table is used to store circuit performance indicators corresponding to different design points; each design point corresponds to a circuit design parameter combination;

[0006] According to the circuit knowledge graph and the simulation data lookup table, the search feasible region of the design point is initialized, and multi-point exploration Bayesian optimization is performed to obtain a candidate design point set of the current circuit;

[0007] Based on the simulation data lookup table, the circuit knowledge graph, and the candidate design point set, combined with the model predictive control framework, a reinforcement learning method is executed to obtain the optimal design point of the current circuit and provide the optimal configuration of the current circuit.

[0008] Further, based on the circuit knowledge graph and the simulation data lookup table, the search feasible region of the design point is initialized, and multi-point Bayesian optimization is performed to obtain the set of candidate design points for the current circuit, including:

[0009] Data is sampled from the simulation data lookup table to train a surrogate model; the surrogate model fits the nonlinear simulation results of the analog circuit design by constructing an objective function.

[0010] Based on the circuit knowledge graph and the simulation data lookup table, initialize the search feasible region of the design point;

[0011] By utilizing a multi-point acquisition function and combining it with the surrogate model, a multi-point exploration Bayesian optimization is performed in the search feasible region to explore and filter out a set of candidate design points for the current circuit.

[0012] Furthermore, the multi-point acquisition function satisfies the following formula:

[0013] ;

[0014] in, This represents the multi-point acquisition function. This indicates the number of design points in the candidate design point set. Indicates the first One design point; Indicates the first The weighted multi-objective expectation improvement function corresponds to each design point; the weighted multi-objective expectation improvement function satisfies the following formula:

[0015] ;

[0016] in, This represents the number of objective functions in the proxy model. Indicates the first One objective function, Indicates the first The design point corresponding to the first The objective function value, express The corresponding weighting coefficients, express The current optimal value, This represents the mathematical expectation function.

[0017] Further, the weighted multi-objective expected improvement function further comprises a constraint penalty term, the constraint penalty term being obtained according to the design experience rule; the weighted multi-objective expected improvement function satisfies the following formula:

[0018] ;

[0019] wherein, represents the number of constraint conditions, represents the violation penalty amount of the i th design point to the j th constraint condition, represents the i th design point, represents the j th constraint condition, represents the weight coefficient of the i th constraint condition. Further, the method comprises the following steps of: according to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, combining a model predictive control framework, performing a reinforcement learning method to obtain an optimal design point of the current circuit, and providing an optimal configuration of the current circuit.

[0020] According to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, initializing a state space and an action space of the reinforcement learning method; the state space is used to describe the state of the current circuit, including the candidate design point set and the corresponding performance indicators thereof; the action space is used to describe the adjustable action range corresponding to the candidate design point set and the step limit thereof, the boundary of which is constrained by the simulation data lookup table and the circuit knowledge graph.

[0021]

[0022] Inputting the state space and the action space into a policy network of the reinforcement learning method, combining a reward function of the reinforcement learning method, and outputting an optimized parameter set; the optimized parameter set refers to a set of circuit design parameters that are most likely to improve the performance of the circuit after optimization; the optimized parameter set is used as an initial parameter search domain of the model predictive control framework.

[0023] Using the model predictive control framework, constructing a multi-step optimization problem model, exploring and optimizing in the initial parameter search domain to obtain the optimal design point and provide the optimal configuration of the current circuit.

[0024] Further, the multi-step optimization problem model satisfies the following formula:

[0025] ;

[0026] wherein, represents the optimized parameter set of the future time steps from the current time step t to t+H, represents the current time step, represents the future time steps, ​represents the multi-step optimization problem model, represents the minimum value of the cumulative cost of the candidate actions for the future time steps at the current time step ; represents the state vector at time step in the state space, , represents a state prediction model constructed based on the simulation data lookup table; represents the optimization parameter set at time step ; represents the objective function at the current time step ; represents the number of constraint conditions, is used to represent the constraint penalty amount corresponding to the violation of the first constraint condition by the state vector and the optimization parameter set at time step ; represents the weight coefficient of the first constraint condition.

[0027] Further, the agent model is a machine learning model.

[0028] In another aspect, the present application provides a circuit optimization system based on model predictive control, including a knowledge-driven module, a preliminary Bayesian optimization module, and an advanced collaborative optimization module;

[0029] The knowledge-driven module is used to construct a circuit knowledge graph and a simulation data lookup table according to circuit design experience documents and circuit simulation data; the circuit simulation data includes simulation data of a current circuit and simulation data of historical circuits; the circuit knowledge graph is used to define entities, entity relationships, and design experience rules in analog circuit design; the simulation data lookup table is used to store circuit performance indicators corresponding to different design points; each design point corresponds to a combination of circuit design parameters;

[0030] The preliminary Bayesian optimization module is used to initialize the search feasible region of the design points according to the circuit knowledge graph and the simulation data lookup table, and to perform multi-point exploration Bayesian optimization to obtain a candidate design point set of the current circuit;

[0031] The advanced collaborative optimization module is used to obtain an optimal design point of the current circuit by combining a model predictive control framework and performing a reinforcement learning method according to the simulation data lookup table, the circuit knowledge graph, and the candidate design point set, and to provide an optimal configuration of the current circuit.

[0032] In another aspect, the present application provides a circuit optimization apparatus based on model predictive control, comprising: a processor and a memory; the memory is used to store a program; when the program is executed by the processor, the processor implements the aforementioned circuit optimization method based on model predictive control.

[0033] In another aspect, the present application provides a computer medium, wherein a processor executable program is stored, the processor executable program is used to implement the aforementioned circuit optimization method based on model predictive control when executed by a processor.

[0034] The beneficial effects of the present application are: the present application provides a circuit optimization method based on model predictive control, comprising: constructing a circuit knowledge graph and a simulation data lookup table according to circuit design experience documents and circuit simulation data; the circuit simulation data includes simulation data of a current circuit and simulation data of a historical circuit; the circuit knowledge graph is used to define entities, entity correlations and design experience rules in analog circuit design; the simulation data lookup table is used to store circuit performance indicators corresponding to different design points; each design point corresponds to a circuit design parameter combination; initializing a search feasible region of the design point according to the circuit knowledge graph and the simulation data lookup table, and performing multi-point exploration Bayesian optimization to obtain a candidate design point set of the current circuit; according to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, combining a model predictive control framework, performing a reinforcement learning method to obtain an optimal design point of the current circuit, and providing an optimal configuration of the current circuit. The present application effectively reduces the consumption of simulation computing resources, improves the optimization efficiency, and at the same time ensures that the design meets the multi-objective performance requirements such as gain, power consumption and bandwidth, overcomes the limitations of traditional methods in processing complex high-dimensional design space, and provides a more flexible, accurate and robust solution. The present application also provides corresponding devices, systems and media, and the beneficial effects of the devices, systems and media are similar to those of the method, which will not be described here.

[0035] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or can be learned by practice of the present application. The objects and other advantages of the present application can be achieved and obtained by the structure particularly pointed out in the specification, claims and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0036] The accompanying drawings are used to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification, and are used to explain the technical solutions of the present application together with the embodiments of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0037] Figure 1 is a flowchart of the circuit optimization method based on model predictive control provided by the present application;

[0038] Figure 2is a flow chart of determining a candidate design point set of a current circuit provided by the present application;

[0039] Figure 3 is a flow chart of determining an optimal design point of a current circuit provided by the present application;

[0040] Figure 4 is a structure diagram of a circuit optimization system based on model predictive control provided by the present application;

[0041] Figure 5 is a structure diagram of a circuit optimization device based on model predictive control provided by the present application. DETAILED DESCRIPTION

[0042] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0043] The present application is further described below in combination with the drawings and specific embodiments. The described embodiments should not be regarded as limiting the present application, and all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of the present application.

[0044] In the following description, "some embodiments" are related to a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0046] With the increasing complexity and performance requirements of electronic devices, parameter optimization in analog circuit design has become a research hotspot. In analog circuit design, the parameter space is high-dimensional and complex, and traditional methods rely on engineers' experience or large-scale trial-and-error simulation processes, which are time-consuming and inefficient, making it difficult to quickly and efficiently explore the global optimal solution, especially when balancing contradictory objectives such as gain, power consumption, bandwidth, etc. In addition, the cost of evaluating the performance of simulation devices and circuits is relatively high, especially in high-dimensional optimization parameter space, and multiple calls to SPICE and other simulation tools bring significant computational burden. Analog circuit design also faces the problem of insufficient artificial experience and data, and engineers' experience is difficult to systematize and embed into data-driven processes, while relying entirely on experience is limited by the diversity and non-linear dynamic characteristics of circuit performance models, resulting in low knowledge transfer efficiency and high dependence on historical data accumulation.

[0047] In the prior art, a large-scale multi-objective analog chip circuit evolutionary optimization design method is disclosed in patent CN117910410A, which proposes an optimization method combining a differential grouping module and an adaptive cooperative co-evolution strategy. By intelligently grouping decision variables and iteratively adjusting parameters in each group using different optimization strategies, the high-dimensional problem is efficiently decomposed into low-dimensional sub-problems, and the confidence adaptive strategy is used to enhance the credibility and rigor of the grouping results.

[0048] Patent CN118940705A discloses a circuit optimization method based on pre-post simulation strategy and multi-objective optimization. First, the multi-objective heuristic strategy is used to adjust the circuit component parameters through the pre-simulation process, and the simulator is used to evaluate the objective function and constraint function. Then, in the post-simulation process, the adaptive reference vector method is used to select elite solutions for layout optimization, and the simulator is also used to calculate the target value and constraint value. If the constraint condition is not met, the optimization process is adaptively adjusted according to the specific situation until a satisfactory solution set is obtained.

[0049] Although the above two methods have achieved certain optimization effect, the former relies too much on the differential grouping module to affect the cooperative evolution strategy, and performs poorly in real simulation environment and does not consider design knowledge rules. The latter needs to call the simulator multiple times to calculate the index values of a large number of solutions in the pre-post simulation process, resulting in long simulation time, high computational resource demand, and limited task complexity.

[0050] Other common optimization methods such as genetic algorithm (GA), particle swarm optimization (PSO), traditional Bayesian optimization, and gradient-based methods also have their own limitations, for example, GA has high computational cost when dealing with high-dimensional parameter space, PSO may face long convergence time and local optimal solution problems, traditional Bayesian optimization has large computational overhead in high-dimensional and noisy design space, and gradient-based methods are prone to local optimal solution and are not suitable for non-differentiable design parameter adjustment.

[0051] To solve the problems in the related art, the embodiments of the present application provide a circuit optimization method, system, device and medium based on model predictive control. The embodiments of the present application combine multi-point exploration Bayesian optimization, reinforcement learning and model predictive control, use simulation data lookup table to reduce the number of simulation calls to reduce the consumption of computing resources, and dynamically adjust the optimization strategy to cope with changing design requirements. This method not only can quickly and efficiently explore the design space, avoid invalid exploration and fall into local optimal solution, but also can intelligently adjust the optimization direction according to multi-objective and constraint requirements, greatly improve the optimization efficiency and precision, so that the circuit design meets the performance index while effectively reducing the design time and computational cost. Compared with the prior art, the embodiments of the present application introduce a knowledge graph to guide the selection of the initial design space, and combine historical data and design rules to enhance the optimization process, ensuring design flexibility, robustness and adaptability to complex and changing design environments.

[0052] First, the circuit optimization method based on model predictive control provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0053] With reference to Figure 1 The implementation process of the circuit optimization method based on model predictive control provided by the embodiments of the present application includes but is not limited to the following steps.

[0054] Step 101, according to the circuit design experience document and the circuit simulation data, a circuit knowledge graph and a simulation data lookup table are constructed.

[0055] The circuit knowledge graph is used to define entities, entity relationships and design experience rules in analog circuit design. The circuit simulation data includes simulation data of the current circuit and simulation data of the historical circuit; the simulation data lookup table is used to store the circuit performance indicators corresponding to different design points. Each design point corresponds to a combination of circuit design parameters.

[0056] Step 101 establishes a comprehensive knowledge base to support the subsequent circuit design optimization process. By integrating circuit design experience documents and circuit simulation data, this step constructs a circuit knowledge graph and a simulation data lookup table (LUT). The circuit knowledge graph defines key entities in analog circuit design (such as transistors, resistors, etc.), the relationships between these entities, and the experience rules accumulated during the design process. This not only helps to understand the internal working mechanism of the circuit, but also provides valuable prior knowledge for optimization algorithms. On the other hand, the LUT stores the performance indicators of the circuit corresponding to different design points, so that it can be quickly queried during the optimization process without having to perform time-consuming circuit simulation every time. Each design point corresponds to a specific combination of circuit design parameters, ensuring that the LUT data can be directly applied to actual design decisions.

[0057] The purpose of building a knowledge graph is to structure the circuit design experience documents, including theoretical rules, engineering experience, and design constraints in the field of circuit design, to provide prior constraints and dynamic updating capabilities for multi-objective optimization. First, define entities and relationships, where entity classification includes circuit elements (such as transistors, resistors), circuit parameters (such as gain, power consumption), design specifications (such as lower limit of gain), and environmental factors (such as temperature). These entities are connected through triples (entity 1, relationship, entity 2), for example, "transistor affects gain". Then, the construction of the knowledge graph is completed through four steps: collecting domain knowledge, establishing entities and relationships, integrating rules and constraints, and integrating dynamic data sources.

[0058] Specifically, this includes obtaining knowledge from circuit design experience documents, using a graph database to store entities and relationships, encoding physical rules and design constraints as edges in the graph, and updating performance data in real time in combination with simulation tools; then use TransE, RotatE and other technologies to vectorize entities and relationships in the knowledge graph as input features for the optimization model. At the same time, the rules in the knowledge graph are converted into optimization constraints or objective function penalty terms, so that design specifications and performance limitations are considered during the optimization process.

[0059] LUT generation aims to reduce real-time computation costs through pre-simulation, which is achieved by using the SPICE tool to perform large-scale simulation of circuit performance under different process parameters, and storing the results in table form for quick query.

[0060] Step 102, according to the circuit knowledge graph and the simulation data lookup table, initialize the search feasible region of the design point, and perform multi-point exploration Bayesian optimization to obtain the candidate design point set of the current circuit.

[0061] The goal of step 102 is to initialize the design space based on the circuit knowledge graph and simulation data lookup table, and to determine a set of initial high-quality design points using Multi-Point Exploration Bayesian Optimization (MPE-BO). First, based on the information provided by the circuit knowledge graph, this step can limit the search of the feasible region, avoiding blind search of unrealistic or unreasonable design parameter space. Then, through the MPE-BO method to evaluate multiple design points in parallel, this method can efficiently find a set of design points close to the optimal solution in a complex high-dimensional design space. Compared with traditional single-point exploration, this method increases the breadth of exploration, thereby speeding up the process of finding the global optimal solution, while reducing the risk of falling into local optimum. The result of this is a set of candidate design points that are preliminarily screened, which represent the potential excellent circuit configuration of the current circuit.

[0062] Step 103, according to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, combined with the model predictive control framework, the reinforcement learning method is executed to obtain the optimal design point of the current circuit, and the optimal configuration of the current circuit is provided.

[0063] Step 103 aims to use the Model Predictive Control (MPC) framework combined with reinforcement learning methods to further optimize the candidate design point set obtained in step 102 to determine the final optimal design point. This process first relies on the real-time performance feedback provided by the simulation data lookup table, allowing the reinforcement learning algorithm to quickly evaluate the actual effect of each design point without the need for complete circuit simulation. Then, by incorporating the design rules and constraints in the circuit knowledge graph into the MPC framework, it is ensured that each adjustment meets the preset technical specifications and performance requirements. Reinforcement learning iteratively optimizes on this basis, selects the optimal action (i.e. adjusts the design parameters) according to the current state, and gradually approaches the optimal design scheme through the reward mechanism. Ultimately, this series of operations collectively outputs a set of best circuit configuration parameters that meet all design objectives, achieving efficient, accurate and robust circuit design optimization.

[0064] In some embodiments of the present application, during the process of constructing the circuit knowledge graph, key entities in circuit design are first defined. These entities include specific circuit elements such as operational amplifiers (Op-Amp), N-type transistors (NPN), P-type transistors (PNP), resistors (Resistor), and capacitors (Capacitor). In addition, circuit parameters such as transistor width (W), current (I), gain (Gain), bandwidth (Bandwidth), and power (Power) are also included. Design specifications cover specific design goals or constraints such as gain, phase margin, power consumption, etc. Environmental factors such as temperature (Temperature), voltage (Voltage), and process variation (PVT) are also considered to reflect their impact on circuit performance.

[0065] The inter-entity association is described by the form of triplets to describe the interaction or dependency between entities. For example, "transistor width affects gain" indicates that the physical size of the transistor has a direct impact on its gain; "gain is inversely proportional to power consumption" indicates that increasing gain usually leads to an increase in power consumption; and "voltage variation may affect current and power consumption" emphasizes the impact of voltage changes on circuit performance indicators. This way of defining inter-entity associations provides a basic framework for subsequent circuit knowledge graph construction.

[0066] For the construction of design experience rules, first, the design rules are extracted from the circuit design experience documents and coded as edges in the knowledge graph, such as the inverse relationship between gain and power consumption or the impact of PVT variation on design targets. Finally, by integrating data sources from simulation tools, circuit design parameters and their performance can be compared and optimized with the rules in the knowledge graph, thereby realizing dynamic adjustment based on feedback. This process ensures the accuracy and flexibility of the design, while supporting continuous knowledge updating and optimization.

[0067] In some embodiments of the present application, taking a two-stage operational amplifier as an example, the circuit knowledge graph corresponding to the two-stage operational amplifier contains entities such as circuit elements (e.g. operational amplifier, transistor, resistor, capacitor), design parameters (transistor width, gain, power consumption, bandwidth), performance specifications (lower limit of gain, upper limit of power consumption, phase margin), and environmental factors (temperature, voltage, process variation PVT), and defines the physical rules and constraints between entities through triples, such as “transistor width affects gain”, “gain and power consumption are inversely related”, and “temperature change reduces bandwidth stability”. In addition, the knowledge graph also integrates circuit design experience (such as the trade-off criteria for gain and bandwidth), the influence of process variation on performance, and hard constraint conditions (such as power consumption ≤ 5mW). The relationship between entities is managed and updated using a graph database (such as Neo4j), and the LUT is obtained by integrating precomputed data generated by SPICE simulation, and the iterative upgrade of the knowledge graph is realized through an optimization result dynamic feedback mechanism (such as successful case expansion and over-limit parameter constraint reinforcement). This provides solid prior knowledge support for Bayesian optimization and reinforcement learning, ensuring the accuracy and efficiency of the multi-objective parameter tuning process.

[0068] In some embodiments of the present application, with reference to Figure 2 In step 102, the search feasible region of the design point is initialized according to the circuit knowledge graph and the simulation data lookup table, and multi-point exploration Bayesian optimization is performed to obtain the implementation process of the candidate design point set of the current circuit, which includes but is not limited to the following steps.

[0069] Step 201: Sample data from the simulation data lookup table to train a proxy model.

[0070] The proxy model fits the nonlinear simulation results of the analog circuit design by constructing an objective function.

[0071] In step 201, data is sampled from the simulation data lookup table LUT to train a proxy model. The proxy model aims to fit the nonlinear simulation results in analog circuit design by constructing an objective function. The key to this step is to effectively train the model using existing simulation data so that it can accurately predict the performance of the circuit under different combinations of design parameters. In this way, the number of actual simulations can be greatly reduced in the subsequent optimization process, saving computing resources and time. The selection and training of the proxy model are crucial to improving the efficiency of the entire optimization process, as it directly determines the accuracy of the performance prediction of the unexplored design space.

[0072] Step 202: Initialize the search feasible region of the design point according to the circuit knowledge graph and the simulation data lookup table.

[0073] In step 202, the search feasible region of the design point is initialized according to the circuit knowledge graph and the simulation data lookup table. This means not only considering the existing simulation data, but also combining the professional knowledge, rules and experience in the field to define the possible range of design parameters. The circuit knowledge graph provides important information about circuit elements, design parameters and their mutual relationships, which helps to determine which combination of design parameters is reasonable and worth exploring. The process of initializing the search feasible region ensures that the optimization algorithm will not waste time on unrealistic or ineffective design points, improving the effectiveness and pertinence of the search, and laying the foundation for subsequent multi-point exploration.

[0074] In step 203, multi-point acquisition function is used to combine the surrogate model to perform multi-point exploration Bayesian optimization in the search feasible region, and to screen out the candidate design point set of the current circuit.

[0075] In step 203, multi-point acquisition function is used to combine the previously trained surrogate model to perform multi-point exploration Bayesian optimization in the search feasible region, and to screen out the candidate design point set. The core of this step is to evaluate multiple design points simultaneously to accelerate the discovery of potential high-quality design schemes. The multi-point exploration method not only increases the chance of finding better solutions in each iteration, but also avoids the problem of traditional single-point exploration easily falling into local optimum. By intelligently selecting the next design point to be evaluated, this process can efficiently narrow down the range of the best design point. Finally, the candidate design point set screened out after this round of optimization represents the most promising circuit configuration after preliminary optimization, providing a solid foundation for further refinement optimization.

[0076] In some embodiments of the present application, during each round of iteration of multi-point exploration Bayesian optimization, the simulation data lookup table (LUT) is used to quickly evaluate the actual performance indicators of each round of optimization results (i.e. candidate design point set), avoiding time-consuming circuit simulation process, ensuring the accuracy and efficiency of the evaluation results. Subsequently, according to these evaluation results, the surrogate model is updated by incorporating the actual performance data into the training set, adjusting or optimizing the model parameters to improve the accuracy of future design space prediction. This dynamic updating mechanism not only enhances the ability of the surrogate model to predict the performance of unexplored areas, but also enables each round of optimization to make decisions based on the latest and most accurate information, effectively improving the accuracy and efficiency of the overall optimization process. In this way, the entire process not only guarantees the effectiveness of preliminary screening, but also provides a solid foundation for subsequent optimization steps.

[0077] In the field of circuit optimization design, traditional Bayesian optimization provides an efficient and systematic method to explore complex high-dimensional parameter space. Its main role is to reduce the number of expensive simulations while improving the probability of finding the global optimal solution. Circuit design usually involves multiple interrelated design parameters (such as transistor size, bias current, etc.), which have complex and nonlinear relationships with circuit performance indicators (such as gain, power consumption, bandwidth, etc.). Bayesian optimization builds a proxy model (usually Gaussian process regression GP) to approximate the true objective function, and uses acquisition functions (such as expected improvement EI) to intelligently select the next most promising point for evaluation.

[0078] Compared with traditional Bayesian optimization, the multi-point exploration Bayesian optimization MPE-BO proposed in the embodiments of the present application accelerates the optimization process by evaluating multiple design points simultaneously, which is particularly suitable for complex and high-dimensional circuit design problems. This method not only increases the chance of finding better solutions in each iteration, but also avoids the problem of easily falling into local optima in traditional single-point exploration. In addition, MPE-BO combines the prior information provided by the circuit knowledge graph and the precomputed data in the simulation data lookup table (LUT) to further improve the optimization efficiency and accuracy, ensuring that the optimization results meet the design targets and meet the needs of practical applications.

[0079] In some embodiments of the present application, the multi-point acquisition function of the MPE-BO proposed in the embodiments of the present application satisfies the following formula (1):

[0080] (1),

[0081] In formula (1), denotes the multi-point acquisition function, denotes the number of design points in the candidate design point set, denotes the th design point. denotes the th design point corresponding to the weighted multi-objective expected improvement function.

[0082] The multi-point acquisition function MPEBO plays a core role in the MPE-BO method proposed in the embodiments of the present application, and its main purpose is to accelerate the optimization process by evaluating multiple design points simultaneously, which is particularly suitable for complex and high-dimensional design spaces.

[0083] Unlike traditional Bayesian optimization, which only selects one most promising design point for the next exploration, the multi-point acquisition function selects design points at a time through the definition of formula (1), which enables simultaneous exploration of multiple potential high-quality solutions in each iteration, effectively increasing the likelihood of finding the global optimal solution and accelerating the convergence speed.

[0084] For each selected design point , represents the expected improvement of this point in meeting multiple optimization objectives, and reflects the importance difference or priority between different objectives through weighting, ensuring the comprehensive consideration of each objective in the optimization process. By maximizing the sum of MOEI of all selected design points, MPEBO not only pursues the best value of a single objective, but also seeks the best balance among multiple objectives in the entire design space.

[0085] By considering the total expected improvement of multiple design points, MPE-BO can better balance the exploration of unknown regions and the utilization of known good regions. This means that it can not only delve into areas that show good performance but have not been fully explored, but also further optimize design schemes that have already performed well based on existing information.

[0086] Therefore, formula (1) not only provides an effective mechanism for MPE-BO to guide multi-point parallel exploration, but also ensures effective search for global optimal solutions in multi-objective optimization scenarios by introducing MOEI, effectively improving optimization efficiency and the quality of results. This method is particularly suitable for solving complex circuit design problems, where multiple conflicting objectives such as gain, power consumption, bandwidth, etc. need to be optimized simultaneously.

[0087] In some embodiments of the present application, the weighted multi-objective expected improvement function satisfies the following formula (2):

[0088] (2);

[0089] In formula (2), denotes the number of objective functions of the surrogate model, denotes the th objective function, denotes the th objective function value corresponding to the th design point, denotes the th weight coefficient, denotes the current optimal value, denotes the mathematical expectation function.

[0090] The weighted multi-objective expected improvement function MOEI plays a crucial role in the optimization framework proposed in the embodiments of the present application. It is mainly used to evaluate and select design points with potential improvement value, especially when dealing with multi-objective optimization problems.

[0091] The core task of the MOEI function is to quantify the expected improvement of the th design point Improvement potential in meeting multiple objective functions. By calculating the expected improvement value of each design point relative to the current optimal solution, those design points that may bring effective performance improvement can be effectively identified.

[0092] In practical applications, circuit design often needs to consider multiple conflicting objectives (such as gain, power consumption, bandwidth, etc.) at the same time. The number of objective functions represented by the agent model, each objective function reflects the requirements of the circuit in different aspects. By introducing weight coefficients weighted sum of each target, MOEI can flexibly adjust the relative importance between each target, so as to realize the balanced optimization between multiple targets.

[0093] Mathematical expectation function , used to calculate the given design point The weighted average value of the improvement. Specifically, the mathematical expectation function calculates the improvement of the design point relative to the current optimal solution . If the improvement is negative, it is taken as 0, ensuring that only those design points with potential for positive improvement are focused on. By maximizing this expectation value, MOEI ensures that each iteration moves in the direction of overall performance improvement.

[0094] By comprehensively considering the improvement potential of each objective function, MOEI provides an effective mechanism to guide the search direction of the optimization algorithm. This not only helps to quickly find the global optimal solution, but also avoids falling into local optimal solution, especially in complex, high-dimensional design space. It is particularly prominent.

[0095] In summary, formula (2) quantifies the expected improvement of each design point relative to the current optimal solution, and combines the weight distribution between multiple objectives to achieve effective exploration of the design space. This method not only improves the efficiency and effectiveness of the optimization process, but also ensures that the final design scheme can achieve the best balance between multiple key indicators, especially suitable for solving complex circuit design problems.

[0096] In some embodiments of the present application, the weighted multi-objective expected improvement function further includes a constraint penalty term, which is obtained according to design experience rules. The weighted multi-objective expected improvement function satisfies the following formula (3):

[0097] (3);

[0098] In formula (3), represents the number of constraint conditions, represents the th design point for the a violation penalty of the i-th constraint, a weight coefficient of the i-th constraint. a weight coefficient of the i-th constraint.

[0099] The embodiments of the present application introduce a constraint penalty term in the weighted multi-objective expected improvement function (MOEI) to ensure that the design points not only bring performance improvement, but also must meet a series of preset design constraints. This mechanism is crucial for realizing efficient and practical application-demand-compliant circuit optimization design.

[0100] The MOEI function first quantifies the potential value of each design point by calculating its expected improvement value on multiple objective functions relative to the current optimal solution. This part maintains attention to the balance between multiple objectives, while encouraging the exploration of design points that have the potential to bring effective performance improvement. Then, the constraint penalty term is introduced to evaluate whether the design point meets all the preset design rules and limit conditions.

[0101] The constraint penalty term is mainly used to handle design points that do not meet the constraints. Among them, a violation penalty of the i-th constraint, a violation penalty of the i-th constraint, If a design point meets a certain constraint, the corresponding is negative or zero, and the penalty term does not work; otherwise, if the design point violates a constraint, it is punished according to the degree of violation. The weight coefficient is used to adjust the importance of different constraints, ensuring that key constraints are given priority.

[0102] By introducing the constraint penalty term, the MOEI function effectively incorporates design experience rules into the optimization process, ensuring that the final selected design scheme not only performs well in performance indicators, but also strictly adheres to various limit conditions in engineering practice (such as power consumption upper limit, physical size, etc.). This helps to avoid generating design schemes that are theoretically superior in performance but cannot be implemented in practice.

[0103] Combining the comprehensive consideration of multi-objective improvement amount and constraint penalty amount, the optimization algorithm can more accurately locate those high-quality design points that can bring performance breakthroughs and meet all design requirements. This method improves the practical feasibility of the optimization result, making the final design scheme more practical and reliable in real-world application environments.

[0104] In summary, the MOEI function further enhances the capability of the weighted multi-objective expected improvement function by introducing a constraint penalty term, enabling it to not only identify design points with high potential but also ensure that these design points strictly adhere to pre-set design specifications. This is particularly important for solving complex circuit design problems, as it guarantees that the optimization process can both pursue superior performance and ensure the practical feasibility and compliance of the design scheme.

[0105] In some embodiments of the present application, in the entity extraction and rule encoding phase, first, relevant entities such as circuit elements, design parameters, and their relationships, such as the inverse relationship between gain and power, are extracted from the circuit knowledge graph. Through graph embedding technology (such as Graph Embeddings), these relationships and rules are converted into numerical information, facilitating subsequent processing and calculation. The next step is the rule formatting process, which defines logical rules or formulas based on the extracted rules, expressing these rules in mathematical form, such as converting the rule "gain and power consumption are inversely proportional" into the formula , and incorporating it into the objective function to achieve quantitative evaluation and optimization. This series of steps enables the professional knowledge in the knowledge graph to be effectively utilized in the automated design process, improving design efficiency and performance.

[0106] In some embodiments of the present application, the strategy of the multi-point exploration Bayesian optimization MPE-BO in selecting the next design point in each iteration satisfies the following formula (4):

[0107] (4);

[0108] In formula (4), is the th design point selected in each iteration.

[0109] This strategy allows MPE-BO to explore the design space more extensively by simultaneously selecting and evaluating multiple design points. This is in contrast to traditional Bayesian optimization, which only selects a single most promising design point for exploration. Multi-point exploration allows the algorithm to search for potential high-quality solutions in different local regions, increasing the likelihood of finding the global optimal solution.

[0110] In each round of iteration, the algorithm will select those design points with the largest expected improvement sum as the objects of the next round of evaluation. This approach ensures that each iteration is based on the latest information to make the most intelligent choices, gradually guiding the search towards the optimal solution.

[0111] By maximizing the sum of expected improvements across all design points, MPE-BO not only considers the value of exploring unknown regions but also utilizes existing simulation results and model predictions to guide the search direction, enabling the algorithm to quickly approach the optimal solution with fewer iterations.

[0112] As MPE-BO explores multiple design points simultaneously, it reduces the risk of falling into local optima due to premature concentration on a specific region. Even if certain regions appear to have higher potential for improvement, through extensive parallel exploration, the algorithm still has the opportunity to discover other potentially better solutions.

[0113] In summary, by systematically selecting multiple high-potential design points for parallel evaluation, MPE-BO effectively combines the advantages of exploration and exploitation, not only speeding up the process of finding the optimal solution but also improving the quality of the final design. This method is particularly suitable for handling complex, high-dimensional, and multi-local optimal circuit design problems.

[0114] In some embodiments of the present application, the surrogate model of MPE-BO is a machine learning model, including a Support Vector Regression (SVR) model.

[0115] By using a machine learning model, especially an SVR model, MPE-BO can efficiently approximate complex objective functions during the simulation of circuit design optimization processes. Compared with traditional methods, this approach can better handle nonlinear relationships and provide more accurate predictions of objective functions, thereby improving optimization efficiency and result accuracy.

[0116] SVR, as a powerful non-parametric regression technique, is particularly suitable for handling nonlinear problems in high-dimensional space. In the MPE-BO framework, SVR is used to fit an objective function model based on existing simulation data (such as circuit performance data under different process parameters). This allows the optimization algorithm to quickly evaluate different circuit design schemes without the need for time-consuming SPICE simulations, effectively reducing computational costs.

[0117] SVR models use kernel functions to handle nonlinear relationships in the input space. This means that even in the face of very complex relationships between circuit design parameters and performance, SVR can effectively model and predict. This ability is crucial for achieving accurate circuit optimization, as it allows the algorithm to consider all possible combinations of design variables and their interactions, rather than just linear or simple relationships.

[0118] In each iteration of the MPE-BO, the SVR model needs to be trained using the current available dataset, with the goal of finding the model parameters that minimize the loss function. This process involves adjusting the model's weights and bias terms to ensure that its output is as close as possible to the true target values. A well-trained SVR model can provide a reliable foundation for the subsequent acquisition function optimization step, guiding the selection of the most promising design points for further exploration.

[0119] To further improve optimization efficiency, the present application also proposes to incorporate domain knowledge from the knowledge graph into the initialization phase of the SVR model. This can help to set a reasonable initial parameter range, avoiding unnecessary search areas, and thus speeding up the process of converging to the global optimal solution. The knowledge graph not only provides valuable information about the relationships between circuit components, but also helps to identify design parameter combinations that are considered more likely to produce excellent results based on historical data and engineering experience.

[0120] In some embodiments of the present application, the objective function of the SVR model satisfies the following formula (5):

[0121] (5);

[0122] In formula (5), is the weight vector, denotes the bias term, denotes the number of slack variables, denotes the th slack variable; is a regularization parameter used to control the complexity of the model.

[0123] In some embodiments of the present application, the kernel function of the SVR model adopts the Gaussian radial basis function (RBF), which satisfies the following formula (6):

[0124] (6);

[0125] In formula (6), is the width parameter of the kernel function; is the output value of the kernel function, representing the similarity between the input samples and . In high-dimensional space, it can be regarded as mapping the original input space to a higher-dimensional space and calculating the inner product of two points in this new space. The RBF kernel can map the original input space to a higher-dimensional space, making it easier to find a linear separating hyperplane in this new space, thus effectively solving the non-linear problem in the original space.

[0126] In some embodiments of the present application, referenceFigure 3 In step 103, according to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, combined with the model predictive control framework, the reinforcement learning method is executed to obtain the optimal design point of the current circuit, and the implementation process of the optimal configuration of the current circuit includes but is not limited to the following steps.

[0127] In step 301, according to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, the state space and the action space of the reinforcement learning method are initialized.

[0128] The state space is used to describe the state of the current circuit, including the candidate design point set and the corresponding performance indicators. The action space is used to describe the adjustable action range and the step limit of the candidate design point set, and the boundary is constrained by the simulation data lookup table and the circuit knowledge graph.

[0129] The reinforcement learning method can further fine-tune the circuit design parameters based on the multi-point exploration Bayesian optimization MPE-BO. Through the dynamic interaction between state, action and reward, reinforcement learning can continuously explore and optimize the design space, especially suitable for handling complex multi-objective optimization problems. In the field of circuit design, the state can represent the current design configuration and its performance indicators, the action involves adjustable design parameter changes, and the reward evaluates the effect of each action according to the preset target (such as improving gain, reducing power loss, etc.). This way makes reinforcement learning not only able to find the optimal solution of a single performance indicator, but also effectively balances multiple conflicting design goals, so as to find the best comprehensive performance circuit design scheme. Therefore, the method combining MPE-BO and reinforcement learning provides a powerful new way to solve complex circuit design problems.

[0130] In step 301, the state space and the action space of the reinforcement learning method are initialized according to the simulation data lookup table, the circuit knowledge graph and the candidate design point set. The setting of the state space aims to comprehensively describe the current design state of the circuit, including but not limited to the considered candidate design point set and the corresponding performance indicators, which provides a basis for evaluating different design schemes. The action space defines the action range and step limit that can be adjusted on these candidate design points, ensuring that the exploration process is flexible and meets the actual operation specifications. By combining the boundary conditions provided by the simulation data lookup table and the circuit knowledge graph, the range of the action space can be effectively limited, ensuring the effectiveness and rationality of the search.

[0131] In step 302, the state space and the action space are input into the policy network of the reinforcement learning method, and the reward function of the reinforcement learning method is combined to output the optimized parameter set, which is used as the initial parameter search domain of the model predictive control framework.

[0132] The set of optimized parameters refers to a set of circuit design parameters that are most likely to improve the performance of the circuit after optimization.

[0133] In step 302, the initialized state space and action space are input into the policy network of the reinforcement learning method, and a reward function is used to guide the output of the set of optimized parameters. The core of this step is to identify those action combinations that are most likely to improve the performance of the circuit. The policy network predicts the best action direction that may bring performance improvement based on the given state and action space, and the output set of optimized parameters serves as the initial parameter search domain for the subsequent optimization phase. This process not only helps to narrow the search range and improve efficiency, but also ensures the directionality of the search, i.e., moving towards the goal of performance optimization.

[0134] In step 303, a multi-step optimization problem model is constructed using the model predictive control framework, and exploration and optimization are performed within the initial parameter search domain to obtain the optimal design point, providing the optimal configuration of the current circuit.

[0135] In step 303, a multi-step optimization problem model is constructed using the model predictive control framework, and detailed exploration and optimization are performed within the initial parameter search domain. By predicting the circuit state at multiple future time steps, long-term performance and constraint conditions are balanced to ensure that the solution that maximizes long-term performance is found while satisfying system constraints, thereby obtaining the optimal design point set and providing the best parameter combination for the current circuit configuration. This step emphasizes the importance of making decisions based on future predictions, so that the circuit design not only focuses on immediate performance improvement, but also aims to maximize overall stability and long-term benefits, providing strong support for achieving high-performance and stable circuit design.

[0136] The significance of model predictive control (MPC) in circuit optimization design lies in its ability to provide a powerful framework for handling dynamic optimization problems in complex, multi-variable systems. By utilizing MPC, the circuit design process can make decisions based on predictions of future time steps, allowing for solutions that maximize long-term performance while considering system constraints. Specifically, in circuit design, MPC can help engineers effectively balance different design objectives (such as gain, power consumption, bandwidth, etc.) while ensuring compliance with various design limitations (such as voltage range, power consumption upper limit, etc.). Additionally, by combining simulation data and domain knowledge, MPC can quickly iterate and find the optimal or near-optimal design configuration while ensuring circuit stability and performance, thereby effectively improving design efficiency and quality. Therefore, MPC provides a flexible and efficient method for solving complex circuit design problems, especially in application scenarios that require precise control and optimization.

[0137] In some embodiments of the present application, the current time step in the state space The state vector can be represented as ,in Indicates circuit design parameters, This indicates the corresponding performance metrics, such as gain and power consumption.

[0138] In some embodiments of this application, design experience rules from a circuit knowledge graph are incorporated into a reward function, which is used to evaluate the quality of an action based on the circuit's performance. For multi-objective optimization, the reward function may be a weighted sum of multiple objectives (such as gain, power consumption, bandwidth, etc.). When an agent selects parameters that do not conform to the design rules, its reward value can be reduced or penalized.

[0139] In some embodiments of this application, the current time step reward function The following formula (7) must be satisfied:

[0140] (7);

[0141] In formula (7), Indicates the current time step Gain, Indicates the current time step Power consumption; yes The weighting coefficients, yes Weighting coefficients; This represents a constraint penalty term, used to measure the penalty for violating design rules of experience (such as power consumption limits, voltage ranges, etc.), ensuring that the circuit design meets all constraints. yes The weighting coefficients.

[0142] This reward function comprehensively considers the requirements of maximizing gain, minimizing power consumption, and adhering to design rules. By assigning different weight coefficients to different factors, the priority of each objective can be flexibly adjusted according to actual needs. This mechanism enables reinforcement learning algorithms to effectively identify the optimal circuit configuration that both significantly improves performance and meets all design requirements during the exploration process. Furthermore, such a reward function can also encourage the algorithm to discover design schemes that, while slightly inferior in some aspects, are more balanced and practical overall, thereby improving the overall quality and applicability of the final circuit design.

[0143] In some embodiments of the present application, the policy network of the reinforcement learning method adopts a deep neural network (DNN). This measure effectively enhances the ability of the algorithm to process complex, high-dimensional data, enabling the system to more accurately identify the optimal design parameters. By utilizing the powerful nonlinear fitting ability of the DNN, the policy network can learn the complex mapping relationship between input features and output performance from a large amount of historical data and simulation results, thereby effectively guiding the exploration and optimization in the circuit design process. In addition, the hierarchical structure of the DNN helps to automatically extract and understand key features in the data, reducing the dependence on manual feature engineering and further improving the search efficiency and the quality of the solution. Therefore, the use of DNN as the policy network not only enhances the expression ability and generalization performance of the reinforcement learning model, but also provides strong support for solving complex multi-objective circuit design problems.

[0144] In some embodiments of the present application, the neural network structure of the policy network DNN is as follows.

[0145] First, the input layer of the policy network DNN receives the state vector in the state space at the current time step , where represents the resistance at the current time step , represents the capacitance at the current time step , represents the gain at the current time step , represents the power consumption at the current time step .

[0146] Second, the hidden layer of the policy network DNN is composed of multiple fully connected layers, each applying a ReLU activation function to introduce a nonlinear transformation. Each hidden layer converts the output of the previous layer into the input of the next layer through a weight matrix and a bias term. The calculation of the first hidden layer satisfies the following formula (8):

[0147] (8);

[0148] In formula (8), represents the output of the first hidden layer, is the weight matrix of the first hidden layer, is the corresponding bias term; the calculation of the second hidden layer satisfies the following formula (9):

[0149] (9);

[0150] In formula (9), represents the output of the second hidden layer, is the weight matrix of the second hidden layer, is the corresponding bias term.

[0151] Finally, the output layer of the policy network DNN is typically a linear layer, either without an activation function or with a problem-specific activation function (as commonly used in regression tasks). The computation of the output layer satisfies Equation (10) as follows:

[0152] (10).

[0153] In Equation (10), is the set of optimized parameters output by the policy network DNN, and the goal of the policy network is to map the state vector to the set of optimized parameters .

[0154] In some embodiments of the present application, the training of the policy network is to optimize the network parameters by maximizing the expected cumulative reward, so the deterministic gradient policy gradient is used for training. In the deterministic gradient policy gradient method, the policy gradient updates the parameters of the policy network by optimizing the expectation of the reward function. Given the policy and the reward function , the policy gradient update satisfies Equation (11) as follows:

[0155] (11).

[0156] In Equation (11), represents the gradient of the parameters of the policy function , represents the action probability distribution output by the policy network according to the current state , which means that for each possible action, the policy network will give a probability of executing that action, and the goal is to find the optimal probability distribution that maximizes the expected return; represents the expected total return under the policy , i.e., the objective function, which is maximized by adjusting the parameters ; is the action value function under the given state and action , which measures the expected long-term return that can be obtained after taking a certain action in a particular state. By evaluating the value of different actions, we can understand which actions are more helpful to improve overall performance; represents the average over all possible states , which emphasizes that the calculation of the policy gradient needs to consider all possible states of the environment, and this processing ensures that the resulting gradient can effectively guide the improvement of the policy under various conditions.

[0157] In summary, equation (11) provides a systematic approach to directly optimize the parameters of the policy network in order to find the optimal behavior policy in an unknown environment. This approach avoids directly solving the complex dynamic programming problem and instead learns the best policy through empirical data from interacting with the environment, which is particularly suitable for application in complex and nonlinear decision-making processes such as circuit design optimization and other multi-objective optimization scenarios.

[0158] In some embodiments of the present application, the multi-step optimization problem model satisfies the following equation (12):

[0159] (12);

[0160] In equation (12), represents the set of optimization parameters from the current time step to the future time steps; represents the multi-step optimization problem model, and represents the minimum cumulative cost of the candidate actions for the future time steps of the current time step ; represents the state vector at time step in the state space, , represents a state prediction model constructed based on a simulation data lookup table; represents the set of optimization parameters at time step ; represents the objective function at the current time step ; represents the number of constraint conditions, represents the constraint penalty amount corresponding to the th constraint condition when the state vector and the set of optimization parameters at time step violate the th constraint condition, represents the weight coefficient of the th constraint condition.

[0161] wherein, represents the set of optimization parameters from the current time step to the future time steps. By optimizing these parameters, the design goal can be approached or achieved as closely as possible while satisfying all constraint conditions. The optimization parameters here can be understood as different actions or adjustment measures taken at different time points.

[0162] In addition, represents the state vector at time step This means that MPC utilizes existing simulation data to predict future states, allowing it to consider possible future scenarios when making decisions at each step, rather than simply reacting based on the current state. This makes the method well-suited for handling complex systems that require consideration of long-term impacts.

[0163] The core idea of MPC is "rolling optimization" or "moving window optimization". At each iteration, MPC recalculates the optimal parameter set for a future time period based on the current system state However, only the first one in this sequence is applied to the actual system. This mechanism allows MPC to adjust in real-time based on the latest system information, adapting to changes in the environment and uncertainties.

[0164] In summary, the core goal of the multi-step optimization problem model is to find the optimal control policy by minimizing the cumulative cost over future time steps. The cumulative cost consists of two parts: one is the objective function at the current time step , which evaluates the performance after taking a specific action in a particular state. For example, in circuit design, it could be the difference between key performance indicators such as gain, power consumption, etc., and their expected target values. The other part is the constraint penalty , which ensures that the solution satisfies all given design constraints.

[0165] In some embodiments of the present application, the objective function is usually a weighted sum of circuit design objectives (such as gain, power consumption, etc.). For example, the objective function for maximizing gain and minimizing power consumption satisfies the following formula (13):

[0166] (13);

[0167] In formula (13), represents the gain at time step , and represents the power consumption at time step .

[0168] In some embodiments of the present application, the constraint penalty is used to ensure that the design does not violate constraints. For example, when gain and can be the first constraint condition, the constraint penalty satisfies the following formula (14):

[0169] (14);

[0170] In formula (14), is the maximum limit of gain, To maximize the power consumption.

[0171] In some embodiments of the present application, after each iteration of the collaborative optimization of reinforcement learning and MPC, the optimized parameters are verified by calling a circuit simulation tool to ensure that the optimization objectives (such as gain, bandwidth, power consumption, etc.) are met. If the results meet expectations, the optimization process ends; if the results do not meet the design goals, optimization continues until the maximum number of iterations is reached or the optimal solution is reached. Finally, when all optimization objectives are met, the optimized circuit design parameters are output, providing the optimal circuit configuration.

[0172] The policy network of reinforcement learning selects actions based on the current circuit design parameters and performance, i.e., adjusts certain parameters to optimize circuit performance. With the help of real-time performance evaluation data provided by the simulation data lookup table LUT, the policy network can more accurately predict the results of each action and optimize its decision-making strategy through training. The data in the LUT as part of the input helps the policy network identify which parameter adjustments can bring higher rewards. At the same time, model predictive control MPC aims to maximize or minimize specific design indicators such as gain, power consumption, etc., which often requires multiple calculations with the help of simulation tools. However, by utilizing the LUT, the present technology can avoid relying on simulation calculations at each iteration and instead directly obtain partial circuit performance data from the LUT, thereby speeding up the calculation process of the objective function. Specifically, in each optimization step of MPC, when a set of design parameters needs to be evaluated for their impact on circuit performance, the LUT provides pre-computed performance data that can be directly obtained by looking up the corresponding circuit parameter combinations (such as resistance, capacitance, transistor size, etc.) to obtain the target function values (such as gain, power consumption, etc.). This method reduces the need for complex simulation and lowers the computational cost, especially in cases where the target function needs to be evaluated multiple times at each control step, the application of LUT effectively improves the efficiency of the entire optimization process.

[0173] In some embodiments of the present application, the circuit knowledge graph is updated according to the collaborative optimization results of reinforcement learning and MPC.

[0174] In summary, the embodiments of the present application provide a circuit optimization method based on model predictive control, which has the following technical effects.

[0175] The circuit optimization method based on model predictive control provided by the embodiment of the application realizes efficient and robust circuit design optimization through deep integration of knowledge driving and data driving. First, a knowledge graph including circuit design experience documents and simulation data is constructed, entities and their associations and design experience rules are defined, and simulation data lookup tables (LUTs) are combined. The SPICE tool is used to pre-generate circuit performance data under different process parameters and store them in table form, thereby providing prior constraints for the optimization process and avoiding frequent calls to high-time-consuming simulation tools, effectively reducing the computational cost.

[0176] In the efficient global exploration and preliminary optimization phase, multi-point exploration Bayesian optimization (MPE-BO) is adopted, the search feasible region is initialized based on the knowledge graph, and the unreasonable parameter range is narrowed down; a support vector regression (SVR) surrogate model is used to fit the nonlinear objective function, and multiple design points are evaluated in parallel by combining multi-point collection functions, thereby breaking through the single-point limitation of traditional Bayesian optimization. In addition, the dynamic weighted multi-objective expected improvement function (MOEI) and the constraint penalty term are used to balance the conflicts of multiple objectives such as gain and power consumption, reduce the risk of local optimum, and screen out a candidate design point set. Further, with the help of the model predictive control (MPC) framework, a multi-step optimization model is constructed to predict the circuit state at multiple time steps in the future, the long-term performance and constraint conditions are balanced, and the reinforcement learning strategy network is combined to dynamically adjust the parameters through the reward function, thereby realizing multi-objective collaborative optimization.

[0177] Finally, the method iteratively updates the knowledge graph and the LUT and the SVR model according to the optimization results through a dynamic updating mechanism, ensures that the design rules and simulation data are iterated synchronously, adapts to complex process variations and dynamic environments, and guarantees that the optimization decision is based on the latest information. The LUT reduces the number of simulation calls, the MPE-BO accelerates the convergence speed, and the overall optimization efficiency is improved. The knowledge graph constraint and the MPE-BO combination avoid the local optimal trap, the MOEI function quantifies the multi-objective improvement potential, the MPC framework dynamically balances the conflict indicators such as gain, power consumption, and bandwidth, is suitable for high-complexity analog circuit design, quickly generates the optimal parameter combination under strict constraints, and effectively improves the design quality and robustness.

[0178] Secondly, with reference to Figure 4 The embodiment of the application provides a circuit optimization system based on model predictive control, which includes a knowledge driving module, a preliminary Bayesian optimization module, and an advanced collaborative optimization module.

[0179] The knowledge-driven module is configured to construct a circuit knowledge graph and a simulation data lookup table according to circuit design experience documents and circuit simulation data. The circuit simulation data includes simulation data of a current circuit and simulation data of historical circuits. The circuit knowledge graph is configured to define entities, entity correlations and design experience rules in analog circuit design. The simulation data lookup table is configured to store circuit performance indicators corresponding to different design points. Each design point corresponds to a circuit design parameter combination.

[0180] The preliminary Bayesian optimization module is configured to initialize a search feasible region of a design point according to the circuit knowledge graph and the simulation data lookup table, and perform multi-point exploration Bayesian optimization to obtain a candidate design point set of the current circuit.

[0181] The advanced collaborative optimization module is configured to obtain an optimal design point of the current circuit by performing a reinforcement learning method in combination with a model predictive control framework according to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, and provide an optimal configuration of the current circuit.

[0182] Secondly, referring to Figure 5 The circuit optimization apparatus based on the model predictive control is provided, which comprises a processor and a memory. The memory is configured to store a program. When the program is executed by the processor, the processor implements the circuit optimization method based on the model predictive control.

[0183] In addition, the circuit optimization apparatus based on the model predictive control is provided, which comprises a processor and a memory. The memory is configured to store a program. When the program is executed by the processor, the processor implements the circuit optimization method based on the model predictive control.

[0184] Similarly, the contents in the method embodiments are applicable to the system embodiments, the apparatus embodiments and the medium embodiments. The system embodiments, the apparatus embodiments and the medium embodiments achieve the same functions and the same beneficial effects as the method embodiments.

[0185] In some alternative embodiments, the functions / operations mentioned in the block diagram can not occur in the order mentioned in the operation schematic diagram. For example, two blocks shown in succession can actually be executed substantially simultaneously or the blocks can sometimes be executed in reverse order, depending on the functions / operations involved. In addition, the embodiments presented and described in the flowcharts of the present application are provided by way of example, and the purpose is to provide a more comprehensive understanding of the technology. The disclosed method is not limited to the operations and logical flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and in which sub-operations described as part of larger operations are independently executed.

[0186] Furthermore, although the present application is described in the context of functional modules, it is understood that one or more of the functions and / or features can be integrated in a single physical device and / or software module, or one or more functions and / or features can be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary to an understanding of the present application. Rather, the properties, functions and internal relationships of the various functional modules disclosed in the devices shown herein are deemed to be illustrative of the principles of the present application. Therefore, the present application is not limited to the illustrative implementations shown and discussed herein, but rather, the scope of the present application is limited only by the claims and the full breadth of equivalents thereof.

[0187] If the functions are implemented in software, the functions can be stored in or implemented as one or more software modules on a computer-readable storage medium. In terms of this understanding, the technical solutions of the present application, in essence, or the parts of the technical solutions that make contributions to the prior art, or the parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of programs for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the various embodiments of the method of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0188] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a list of executable program instructions for implementing logical functions, and can be specifically embodied in any computer-readable medium for use by a program execution system, device or equipment (such as a computer-based system, a system including a processor, or other system that can take programs from a program execution system, device or equipment and execute the programs) or in conjunction with these program execution systems, devices or equipment. For the purpose of the present specification, the "computer-readable medium" can be any device that can contain, store, communicate, propagate or transport programs for use by a program execution system, device or equipment or in conjunction with these program execution systems, devices or equipment.

[0189] More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can also be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, for example, via optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and stored in a computer memory.

[0190] It should be understood that aspects of the application can be implemented in hardware, software, firmware or combinations thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable

[0191] In the above description of the present application, reference has been made to descriptive terms such as "one embodiment / scheme", "another embodiment / scheme" or "some embodiments / schemes" etc. which can mean that a particular feature, structure, material or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. The illustrative examples described above do not necessarily all refer to the same embodiment or example of the application. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0192] While the embodiments of the present application have been shown and described, it is to be understood that various modifications, substitutions, combinations, and variations can be made therein without departing from the spirit and scope of the present application, which is defined by the appended claims and their equivalents.

[0193] The above is a specific description of the preferred embodiments of the present application, but the present application is not limited to the embodiments, and those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the present application, and these equivalent modifications or replacements are included in the scope defined by the claims of the present application.

Claims

1. A method for circuit optimization based on model predictive control, characterized in that, The method comprises the following steps: According to the circuit design experience document and the circuit simulation data, a circuit knowledge graph and a simulation data lookup table are constructed; the circuit simulation data includes simulation data of a current circuit and simulation data of a historical circuit; The circuit knowledge graph is used to define entities, entity correlations and design experience rules in analog circuit design; the simulation data lookup table is used to store circuit performance indicators corresponding to different design points; each design point corresponds to a circuit design parameter combination; According to the circuit knowledge graph and the simulation data lookup table, a search feasible region of the design point is initialized, and multi-point exploration Bayesian optimization is performed to obtain a candidate design point set of the current circuit, comprising: A proxy model is trained by sampling data from the simulation data lookup table; the proxy model fits the nonlinear simulation results of analog circuit design by constructing an objective function; the search feasible region of the design point is initialized according to the circuit knowledge graph and the simulation data lookup table; a multi-point collection function is used to perform multi-point exploration Bayesian optimization in the search feasible region in combination with the proxy model, and a candidate design point set of the current circuit is screened out; According to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, a model predictive control framework is combined to execute a reinforcement learning method to obtain an optimal design point of the current circuit and provide an optimal configuration of the current circuit.

2. The model predictive control based circuit optimization method of claim 1, wherein, The multi-point collection function satisfies the following formula: ； in, This represents the multi-point acquisition function. This indicates the number of design points in the candidate design point set. Indicates the first One design point; Indicates the first The weighted multi-objective expectation improvement function corresponds to each design point; the weighted multi-objective expectation improvement function satisfies the following formula: ； wherein, a number of objective functions representing the proxy model, represents the i-th objective function, represents the i-th objective function, represents the i-th objective function value corresponding to the i-th design point, represents the i-th objective function value corresponding to the i-th design point, represents the i-th objective function value corresponding to the i-th design point, represents the i-th objective function value corresponding to the i-th design point, represents the i-th objective function value corresponding to the i-th design point, represents the i-th objective function value corresponding to the i-th design point, represents the i-th objective function value corresponding to the i-th design point, represents the i-th objective function value corresponding to the i-th design point.

3. The model predictive control based circuit optimization method of claim 2, wherein, The weighted multi-objective expected improvement function further includes a constraint penalty term obtained according to the design experience rules; the weighted multi-objective expected improvement function satisfies the following formula: ； wherein, denotes the number of constraints, denotes the violation penalty of the th design point for the th constraint, denotes the weight coefficient of the th constraint.

4. The model predictive control based circuit optimization method of claim 1, wherein, According to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, a model predictive control framework is combined to execute a reinforcement learning method to obtain an optimal design point of the current circuit and provide an optimal configuration of the current circuit, comprising: According to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, a state space and an action space of the reinforcement learning method are initialized; the state space is used to describe the state of the current circuit, including the candidate design point set and its corresponding performance indicators; the action space is used to describe the adjustable action range and its step limit corresponding to the candidate design point set, and the boundary is constrained by the simulation data lookup table and the circuit knowledge graph; The state space and the action space are input into a policy network of the reinforcement learning method, and an optimized parameter set is output in combination with a reward function of the reinforcement learning method; the optimized parameter set refers to a circuit design parameter set that is most likely to improve the performance of the circuit after optimization; the optimized parameter set is used as an initial parameter search domain of the model predictive control framework; A multi-step optimization problem model is constructed by using the model predictive control framework to explore and optimize in the initial parameter search domain to obtain the optimal design point and provide the optimal configuration of the current circuit.

5. The model predictive control based circuit optimization method of claim 4, wherein, The multi-step optimization problem model satisfies the following formula: ； wherein, denotes an optimized parameter set for future time steps starting from the current time step ; denotes the multi-step optimization problem model, denotes the minimum value of the cumulative cost of the candidate actions for future time steps starting from the current time step ; denotes a state vector at time step in the state space, , denotes a state prediction model constructed based on the simulation data lookup table; denotes an optimized parameter set at time step ; denotes an objective function for the current time step ; denotes the number of constraint conditions, denotes a constraint penalty amount corresponding to the th constraint condition for a state vector and an optimized parameter set at time step , denotes a weight coefficient of the th constraint condition.

6. The model predictive control based circuit optimization method of claim 1, wherein, The proxy model is a machine learning model.

7. A model predictive control based circuit optimization system, characterized in that, The method comprises a knowledge-driven module, a preliminary Bayesian optimization module, and an advanced collaborative optimization module. The knowledge-driven module is configured to construct a circuit knowledge graph and a simulation data lookup table according to circuit design experience documents and circuit simulation data. The circuit simulation data comprises simulation data of a current circuit and simulation data of historical circuits. The circuit knowledge graph is configured to define entities, entity correlations, and design experience rules in analog circuit design. The simulation data lookup table is configured to store circuit performance indicators corresponding to different design points. Each design point corresponds to a combination of circuit design parameters. The preliminary Bayesian optimization module is configured to initialize a search feasible region of the design points according to the circuit knowledge graph and the simulation data lookup table, and perform multi-point exploration Bayesian optimization to obtain a candidate design point set of the current circuit.

8. A circuit optimization apparatus based on model predictive control, characterized by The method comprises the following steps: sampling data from the simulation data lookup table to train a proxy model; the proxy model is configured to construct an objective function to fit nonlinear simulation results of analog circuit design; 9. A computer medium having stored therein a program executable by a processor, characterized by, the search feasible region of the design points is initialized according to the circuit knowledge graph and the simulation data lookup table; a multi-point collection function is used to perform multi-point exploration Bayesian optimization in the search feasible region in combination with the proxy model, and a candidate design point set of the current circuit is screened out. The advanced collaborative optimization module is configured to execute a reinforcement learning method in combination with a model predictive control framework to obtain an optimal design point of the current circuit according to the simulation data lookup table, the circuit knowledge graph, and the candidate design point set, and provide an optimal configuration of the current circuit. The method comprises the following steps: a processor and a memory; the memory is configured to store a program; when the program is executed by the processor, the processor is configured to implement the model predictive control-based circuit optimization method according to any one of claims 1 to 6. The program executable by the processor is configured to implement the model predictive control-based circuit optimization method according to any one of claims 1 to 6 when executed by the processor.

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