Inner spacer for gate all around devices

Abstract

Semiconductor devices, such as gate all around (GAA) devices, process tools and methods of making GAA devices, and inner spacer pads and inner spacers for GAA devices are described herein. The methods include performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of layers of semiconductor material (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)). The amorphous silicon liner is conformally formed along the GAA device, including conformally formed along the recessed semiconductor material layer and the respective plurality of channel layers, and the inner spacer is formed directly on the amorphous silicon liner. One or more operations of the methods described herein are performed in situ in an integrated machining tool system.

Description

Technical Field

[0001] Detailed description of the present disclosure relates generally to semiconductor devices. More particularly, embodiments of the present disclosure are directed to gate-all-around (GAA) devices and methods of forming GAA devices with inner spacer liners. Background Art

[0002] Transistors are key components in most integrated circuits. Because a transistor's drive current and speed are proportional to its gate width, faster transistors typically require larger gate widths. Consequently, there's a trade-off between transistor size and speed. FinFETs (fin field-effect transistors) were developed to address the conflicting goals of maximizing transistor drive current and minimizing transistor size. FinFETs, characterized by a fin-shaped channel region, can significantly increase transistor size without significantly increasing the transistor's footprint, and are currently used in many integrated circuits. However, finFETs also have their drawbacks.

[0003] As the feature size of transistor devices continues to shrink to achieve greater circuit density and higher performance, it is necessary to improve the transistor device structure to improve electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and horizontal all-around gate (hGAA) structures. The hGAA device structure includes multiple lattice-matched channels suspended in a stacked configuration and connected through source / drain regions. The hGAA structure has good electrostatic control capabilities and can be widely used in complementary metal oxide semiconductor (CMOS) chip manufacturing.

[0004] One of the challenges of CMOS wafer manufacturing (and GAA formation) is reducing parasitic capacitance. The selective etching process used to form the indentations / grooves of the inner spacers is extremely challenging. Due to the selective etching process, silicon (Si) loss is inevitable at the corners of the indentations / grooves in the semiconductor material layer. Silicon (Si) loss reduces the current path and can even lead to current crowding if the silicon (Si) loss angle is not designed properly. In addition, silicon (Si) loss can significantly degrade DC performance. The thinner the channel layer, the worse the DC performance.

[0005] Therefore, there is a need for methods to reduce the amount of silicon (Si) loss in gate-all-around (GAA) devices. Summary of the Invention

[0006] One or more embodiments of the present disclosure relate to a method for manufacturing an electronic device. In some embodiments, the method includes forming a superlattice structure on a top surface of a semiconductor substrate, the superlattice structure including a plurality of semiconductor material layers and corresponding plurality of channel layers arranged alternately in a plurality of stacked pairs; recessing a portion of the plurality of semiconductor material layers to form a recessed semiconductor material layer; conformally forming an amorphous silicon liner along the electronic device, including along the recessed semiconductor material layer and the corresponding plurality of channel layers; and forming an inner spacer directly on the amorphous silicon liner, wherein the inner spacer is adjacent to a source region and a drain region.

[0007] Additional embodiments of the present disclosure are directed to a method for manufacturing a gate-all-around (GAA) device. In some embodiments, the method includes: pre-cleaning a semiconductor substrate having a superlattice structure formed on a top surface thereof. The superlattice structure includes a plurality of recessed semiconductor material layers and a corresponding plurality of channel layers arranged alternately in a plurality of stacked pairs. The plurality of semiconductor material layers include silicon germanium (SiGe), and the corresponding plurality of channel layers include silicon (Si). The method further includes performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within the superlattice structure. In some embodiments, the amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layers and the corresponding plurality of channel layers, the inner spacer is directly formed on the amorphous silicon liner, and the inner spacer is adjacent to the source region and the drain region. The method further includes etching a portion of the inner spacer; and removing the replacement metal gate and the recessed semiconductor layer from the semiconductor substrate, followed by etching an inner sidewall portion of the amorphous silicon liner.

[0008] Further embodiments of the present disclosure relate to a processing tool. In some embodiments, the processing tool includes: a central transfer station, the central transfer station including a robot, the robot configured to move a semiconductor substrate; a plurality of processing stations, each processing station connected to the central transfer station and providing a processing area, the processing area being separated from the processing area of ​​an adjacent processing station, the plurality of processing stations including a pre-cleaning chamber and a chemical vapor deposition (CVD) chamber; and a controller connected to the central transfer station and the plurality of processing stations, the controller configured to activate the robot to move the semiconductor substrate between the processing stations and control amorphous silicon substrates for forming a gate-all-around (GAA) device. A processing cycle for a liner, the processing cycle comprising: pre-cleaning a semiconductor substrate, the semiconductor substrate having a superlattice structure formed on a top surface of the semiconductor substrate, the superlattice structure comprising a plurality of recessed semiconductor material layers and corresponding plurality of channel layers alternately arranged in a plurality of stacked pairs; and performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within the superlattice structure, the amorphous silicon liner being conformally formed along a GAA device, including along the recessed semiconductor material layers and the corresponding plurality of channel layers, the inner spacer being directly formed on the amorphous silicon liner, the inner spacer being adjacent to a source region and a drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to understand the above-mentioned features of the present disclosure in detail, reference may be made to the detailed description of the present disclosure, which is briefly summarized above, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only specific embodiments of the present disclosure and are not to be construed as limiting the scope thereof, as the present disclosure admits to other equally effective embodiments.

[0010] Figure 1 A flowchart illustrating a method of forming an electronic device according to one or more embodiments is provided;

[0011] Figure 2A shows a schematic cross-sectional view of an electronic device according to one or more specific embodiments;

[0012] Figure 2B shows a schematic cross-sectional view of an electronic device according to one or more specific embodiments;

[0013] Figure 2C shows a schematic cross-sectional view of an electronic device according to one or more specific embodiments;

[0014] Figure 2D shows a schematic cross-sectional view of an electronic device according to one or more specific embodiments;

[0015] Figure 2Eshows a schematic cross-sectional view of an electronic device according to one or more specific embodiments;

[0016] Figure 2F shows a schematic cross-sectional view of an electronic device according to one or more specific embodiments;

[0017] Figure 2G shows a schematic cross-sectional view of an electronic device according to one or more specific embodiments;

[0018] Figure 2H shows a schematic cross-sectional view of an electronic device according to one or more specific embodiments;

[0019] Figure 2I shows a schematic cross-sectional view of an electronic device according to one or more specific embodiments;

[0020] Figure 2J A schematic cross-sectional view illustrating an electronic device according to one or more specific embodiments; and

[0021] Figure 3 A schematic top view of an example multi-chamber processing system for forming electronic devices is shown in accordance with one or more embodiments.

[0022] For ease of understanding, the same reference numerals are used to mark the same elements common to the various figures as much as possible. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further description. DETAILED DESCRIPTION

[0023] Before describing several specific embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the structural details or process steps set forth in the following description. The present disclosure is capable of other specific embodiments and can be practiced or carried out in various ways.

[0024] Throughout this specification and the appended claims, the term "substrate" refers to a surface or portion of a surface upon which a process is performed. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, reference to a substrate may also refer to only a portion of a substrate. Furthermore, reference to depositing onto a substrate may refer to either a bare substrate or a substrate upon which one or more films or features are deposited or formed.

[0025] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during the manufacturing process. For example, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers, which may be referred to as "semiconductor substrates." The substrate may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise generate or graft target chemical molecules to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may also be performed on underlying layers formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context dictates. Thus, for example, where a film / layer or portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface consists of will depend on the film being deposited and the specific chemistry being used.

[0026] Throughout this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gaseous species that can react with a substrate surface.

[0027] As used herein, the term "in situ" refers to processes that are all performed in the same process chamber or in separate process chambers connected online as part of an integrated processing system, such that each process is performed without breaking vacuum. As used herein, the term "ex situ" refers to processes that are performed in at least two different process chambers, such that one or more of the processes are performed with a break in vacuum. In some embodiments, processes are performed without breaking vacuum or exposure to ambient air.

[0028] A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, a transistor may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other components. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source region and the drain region comprise doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric layer interposed between a gate electrode and the channel region in the substrate.

[0029] As used herein, the term "field-effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement-mode field-effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field in the device, which is generated by the voltage difference between the body of the device and the gate terminal. The three terminals of a field-effect transistor are the source (S), through which carriers enter the channel; the drain (D), through which carriers leave the channel; and the gate (G), which is the terminal that modulates the conductivity of the channel. Traditionally, the current entering the channel at the source (S) is labeled I S , the current entering the channel at the drain (D) is marked as I D The drain-to-source voltage is labeled V DS By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D ).

[0030] A metal oxide semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulating gate, and the gate voltage determines the device's conductivity. This ability to change conductivity with an applied voltage can be used to amplify or switch electronic signals. A MOSFET is based on the modulation of charge concentration by a metal oxide semiconductor (MOS) capacitor between a body electrode and a gate electrode located above the body, insulated from all other device regions by a gate electrode dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a single highly doped region separated by a body region. These regions can be p-type or n-type, but they are all of the same type, opposite to the type of the body region. The source and drain (unlike the body) are highly doped, indicated by a "+" sign after the doping type.

[0031] If the MOSFET is an n-channel, or nMOS FET, then the source and drain are n+ regions, and the bulk is the p-region. If the MOSFET is a p-channel, or pMOS FET, then the source and drain are p+ regions, and the bulk is the n-region. The source is so named because it is the source of charge carriers (electrons for n-channels and holes for p-channels) flowing through the channel; similarly, the drain is where the charge carriers leave the channel.

[0032] The term "Fin Field Effect Transistor (FinFET)" as used herein refers to a MOSFET transistor constructed on a substrate, in which the gates are placed on two or three sides of the channel, forming a dual-gate or triple-gate structure. Because the channel region forms a "fin" on the substrate, FinFET devices are collectively referred to as FinFETs. FinFET devices have fast switching times and high current density.

[0033] As used herein, the term "gate-all-around (GAA)" refers to an electronic device, such as a transistor, in which gate material surrounds a channel region on all sides. The channel region of a GAA transistor may include nanowires or nanoplates, or nanosheets, strip-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device comprises a plurality of vertically spaced horizontal nanowires or horizontal strips, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0034] The term "nanowire" as used herein refers to a nanostructure with a diameter of nanometers (10 -9 A nanowire can also be defined as a structure with a length to width ratio greater than 1000. In addition, a nanowire can also be defined as a structure with a thickness or diameter limited to tens of nanometers or less and an unlimited length. Nanowires are used in transistors and some laser applications. In one or more specific embodiments, the nanowires are made of semiconductor materials, metal materials, insulator materials, superconducting materials or molecular materials. In one or more specific embodiments, nanowires are used in transistors of logic CPUs, GPUs, MPUs, and volatile (such as DRAM) and non-volatile (such as NAND) devices. The term "nanosheet" as used herein refers to a two-dimensional nanostructure with a thickness ranging from about 0.1 nanometers to about 1000 nanometers.

[0035] The present disclosure is described with reference to the accompanying drawings, which illustrate devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The processes shown in the drawings are merely illustrative of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0036] Figure 1 A process flow diagram of a method 100 for forming an electronic device (eg, a gate-all-around (GAA) device) according to some embodiments of the present disclosure is shown. Figures 2A-2J The method 100 is described. Figures 2A-2J Stages of fabrication of semiconductor structures according to some specific embodiments of the present disclosure are described. Figures 2A-2J A cross-sectional view of a GAA device according to one or more specific embodiments is shown. The method 100 can be part of a multi-step manufacturing process for a semiconductor device. Accordingly, the method 100 can be performed in any suitable processing chamber coupled to a cluster tool, such as Figure 3The processing system 400 is shown. The processing system 400 may include a processing chamber for fabricating semiconductor devices, such as a chamber configured for pre-cleaning, etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), such as thermal CVD, epitaxial growth, oxidation, or any other suitable chamber for fabricating semiconductor devices.

[0037] Figure 2A A semiconductor substrate 200 having a top surface 202 is shown. As used herein, the terms "semiconductor substrate 200" and "substrate 200" may be used interchangeably. The method 100 may optionally include one or more etching processes (operation 102), described further below, to form Figure 2A . In some embodiments, the substrate 200 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate that is entirely composed of semiconductor material. The bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may include one or more materials, such as crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or non-patterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 200 includes a semiconductor material such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 200 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although several examples of materials from which a substrate may be formed are described herein, any material that can serve as a basis for passive and active electronic devices (such as transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be constructed within the spirit and scope of the present disclosure.

[0038] In some embodiments, the semiconductor material can be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate can be doped using any suitable process, such as an ion implantation process. The term "n-type," as used herein, refers to a semiconductor created during the manufacturing process by doping an intrinsic semiconductor with an electron donor element. The term n-type derives from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of wells (or holes). Compared to n-type semiconductors, p-type semiconductors have a greater concentration of holes than electrons. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or a combination thereof. In some embodiments, substrate 200 can be doped to provide a high dose of dopant at a first location on the surface of substrate 200 to prevent parasitic bottom devices from turning on.

[0039] At least one superlattice structure 204 is formed atop the top surface 202 of the substrate 200. The superlattice structure 204 includes a plurality of semiconductor material layers 226 and a corresponding plurality of channel layers 224 arranged in a plurality of stacked pairs. As used herein, the terms "semiconductor material layers 226" and "dummy semiconductor layers 226" are used interchangeably. In some embodiments, the plurality of stacked layers include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In some embodiments, the silicon-germanium (SiGe) may include germanium (Ge) with a molar fraction ranging from 0% to 50%. In some embodiments, the plurality of semiconductor material layers 226 include silicon-germanium (SiGe), and the plurality of channel layers 224 include silicon (Si). In some embodiments, the plurality of semiconductor material layers 226 and the corresponding plurality of channel layers 224 include any number of lattice-matched material pairs suitable for forming the superlattice structure 204. In some embodiments, the plurality of semiconductor material layers 226 and the corresponding plurality of channel layers 224 include from about 2 to about 50 pairs of lattice-matched materials. In some embodiments, the plurality of channel layers 224 can be doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

[0040] In one or more specific embodiments, the thickness of the plurality of semiconductor material layers 226 and the plurality of channel layers 224 is in a range from about 2 nanometers to about 50 nanometers, including any subranges and values ​​therebetween, such as in a range from about 3 nanometers to about 20 nanometers, or in a range from about 2 nanometers to about 15 nanometers.

[0041] Figure 2AAlso illustrated is a replacement gate structure (e.g., dummy gate structure 209) formed and patterned on the superlattice structure 204. The dummy gate structure 209 defines a channel region of the transistor device. The dummy gate structure 209 can be formed using any suitable conventional deposition and patterning process known in the art. The dummy gate structure 209 may include any suitable material known to those skilled in the art. In some embodiments, the dummy gate structure 209 includes one or more of a sacrificial oxide layer 210 and a dummy gate polysilicon layer 212. In some embodiments, sidewall spacers 214 are formed along the outer sidewalls of the dummy gate structure 209. In some embodiments, the sidewall spacers 214 include a suitable insulator material known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or the like. In some embodiments, the sidewall spacers 214 are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0042] Reference Figure 2B At operation 104, in some embodiments, a source trench 232 and a drain trench 234 are formed adjacent to the superlattice structure 204 on both sides of the superlattice structure 204. In some embodiments, the source trench 232 is formed adjacent to a first end of the superlattice structure 204, and the drain trench 234 is formed adjacent to a second, opposite end of the superlattice structure 204. Figure 2B In the illustrated embodiment, one of the source trench 232 or the drain trench 234 is not shown at the front face of the superlattice structure 204. The other end of the superlattice structure 204 has the other of the source trench 232 or the drain trench 234. In some embodiments, the source trench 232 and the drain trench 234 include a source region and a drain region formed therein, respectively. In other words, in some embodiments, the source region is formed in the source trench 232, and the drain region is formed in the drain trench 234. In some embodiments, the source region and / or the drain region are formed from any suitable semiconductor material, such as, but not limited to, silicon, germanium, silicon germanium, silicon phosphorus, silicon arsenic, or the like. In one or more embodiments, the source region and the drain region can be independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga). In some embodiments, the source region and the drain region can be formed using any suitable deposition process, such as an epitaxial deposition process.

[0043] Reference Figure 2CAt operation 106, a portion of the semiconductor material layer 226 is isotropically etched to form a recessed semiconductor material layer 226'. In one or more embodiments, an opening can be formed by isotropically etching under the superlattice structure 204. In some embodiments, the superlattice structure 204 includes alternating layers of silicon (Si) layers (e.g., the plurality of channel layers 224) and silicon germanium (SiGe) layers (e.g., the plurality of semiconductor material layers 226), which are isotropically etched to form a cavity opening under the superlattice structure 204 using, for example, a dry etching process, a wet etching process, an RIE process, or a combination thereof. In some embodiments, the dry etching process includes using a fluorine-based etchant, such as HF, CF4, SF6, CH2F2, CHF3, C2F6, other fluorine-containing etchants, or combinations thereof. In some embodiments, the wet etching process includes using an etchant including nitric acid (HNO3), ammonium hydroxide (NH3OH), ammonium fluoride (NH4F), hydrogen peroxide (H2O2), other suitable etchants, or combinations thereof. In some embodiments, the etching process is controlled by factors such as duration, temperature, pressure, power supply, bias voltage, bias power, etchant flow rate, and / or other suitable parameters to remove a desired amount of the semiconductor material layer 226. In some embodiments, the amount of the semiconductor material layer 226 removed at operation 106 is controlled by the duration of the etching process to ensure that a sufficient channel length L is maintained to form a metal gate stack in subsequent processing steps.

[0044] In some embodiments, after the semiconductor material layer cavity etching of operation 106, a pre-cleaning process may be performed before the inner liner and inner spacer formation of operation 108. The pre-cleaning process may include any suitable pre-cleaning process known to those skilled in the art. In some embodiments, the pre-cleaning process includes etching a portion of the plurality of semiconductor material layers 226 with dilute hydrofluoric acid (diluted HF), including dilute HF greater than 100:1, such as 130:1, to etch away native oxide on the substrate to form a hydrophobic surface. In some embodiments, the pre-cleaning process may include conventional plasma etching, or remote plasma assisted dry etching processes, such as SiCoNi etchant produced by Applied Materials, Inc., Santa Clara, California, USA. TM Etching process, which is commercially available. TM During the etching process, the device is exposed to H2, NF3 and / or NH3 plasma species, such as plasma-excited hydrogen and fluorine species. For example, in some embodiments, the device may be exposed to H2, NF3 and NH3 plasma simultaneously. TM Etching process can be used on SiCoNi TMThe process is performed in a pre-clean chamber that can be integrated into one of a variety of multi-processing platforms, including Dual ACP, GT and platforms, which are commercially available from Applied Materials.

[0045] The wet etching process may include a hydrofluoric acid (HF) last process, a so-called "HF last" process, in which the surface is HF etched to hydrogen terminate the surface. Alternatively, any other liquid-based epitaxial pre-cleaning process may be used. In some embodiments, the process includes a sublimate etch for removing native oxide. The etching process may be plasma or thermal based. The plasma process may be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0046] In operation 110, as Figure 2D As shown, method 100 includes performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner 250 and an inner spacer 260. In one or more specific embodiments, the CVD process is a thermal CVD process. The inner spacer liner 250 is particularly useful in nMOS FET structures, pMOS FET structures, and GAA devices and will be described in this context, although the inner spacer liner 250 is not limited to these applications.

[0047] Embodiments of the present disclosure are directed to inner spacers that improve overall GAA device performance. Some embodiments are directed to forming the inner spacer prior to forming the inner spacer to compensate for silicon (Si) corner losses during indentation / cavity etching. Some embodiments advantageously provide fully restored ion / current losses by forming the inner spacer prior to inner spacer formation.

[0048] Specific embodiments of the present disclosure are directed to an inner spacer pad configuration that advantageously has an overall lower effective capacitance (C eff ), and has high resist performance for both dry and wet etching processes. Some embodiments are directed to an inner spacer configuration at a 3nm GAA device size, which advantageously has an overall lower effective capacitance (C) than a conventional inner spacer without an inner spacer in a comparative GAA device. eff It is believed that the presence of the inner spacer liner along the sidewall improves the wire-release process window, thereby improving the yield of static random access memory (SRAM).

[0049] In some embodiments, the amorphous silicon liner 250 is formed before the inner spacer 260 is deposited. The amorphous silicon liner 250 and the inner spacer 260 are formed in a single step using the same deposition process. As used herein, "amorphous silicon" or "a-Si" refers to a silicon-containing layer / film that lacks a crystalline structure when deposited. In one or more embodiments, the amorphous silicon liner 250 and the inner spacer 260 are formed by flowing any suitable silicon precursor. During the deposition of the amorphous silicon liner 250, the flow of a second precursor source, such as a carbon source, an oxygen source, and / or a nitrogen source, is turned off. During the deposition of the inner spacer 260, the flow of the second precursor source (such as a carbon source, an oxygen source, and / or a nitrogen source) is turned on to form the inner spacer comprising a low-k dielectric material, such as one or more of silicon oxycarbide (SiOC) or silicon oxynitride (SiON). In one or more embodiments, the chemical vapor deposition (CVD) process is performed at a temperature ranging from 400°C to 650°C. In one or more specific embodiments, the amorphous silicon liner 250 and the inner spacer 260 are formed at different temperatures ranging from 400°C to 650°C.

[0050] In some embodiments, the amorphous silicon liner 250 is formed along the GAA device, including along the recessed semiconductor material layer 226′ and the corresponding plurality of channel layers 224. In some embodiments, the inner spacer 260 is formed directly on the amorphous silicon liner 250. In some embodiments, the amorphous silicon liner 250 is conformally formed along the recessed semiconductor material layer 226′ and the corresponding plurality of channel layers 224, as well as along the sidewall spacers 214. In some embodiments, the inner spacer 260 is adjacent to the source trench 232 and the drain trench 234.

[0051] The thermal chemical vapor deposition process of operation 108 may be performed until the amorphous silicon liner 250 and the inner spacer 260 are formed to a desired thickness. In some embodiments, the thickness of the amorphous silicon liner 250 is in the range of 0.5 nanometers to 3 nanometers, including all subranges and values ​​therebetween. In some embodiments, the thickness of the amorphous silicon liner 250 varies depending on the amount of silicon (Si) loss, as further described below.

[0052] The inner spacer 260 may comprise any suitable insulator material known in the art, such as a low-k dielectric material. In one or more embodiments, the low-k dielectric material has an k value in the range of 3 to 5. In some embodiments, the low-k dielectric material of the inner spacer 260 comprises one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or a spin-on dielectric. In some embodiments, the low-k dielectric material of the inner spacer 260 comprises one or more of silicon oxycarbide (SiOC) or silicon oxynitride (SiON). In some embodiments, the thickness of the inner spacer 260 is in the range of 2 nm to 5 nm, including all subranges and values ​​therebetween.

[0053] In some embodiments, the amorphous silicon liner 250 has a thickness in a range of 0.5 nm to 3 nm, and the inner spacer 260 has a thickness in a range of 2 nm to 5 nm, including all subranges and values ​​therebetween. In some embodiments, the amorphous silicon liner 250 and the inner spacer 260 are formed in situ in an integrated processing tool. In some embodiments, the amorphous silicon liner 250 is formed before depositing the inner spacer 260, and the amorphous silicon liner 250 and the inner spacer 260 are formed in a single step using the same deposition process (e.g., the CVD process of operation 110 of method 100).

[0054] In some embodiments, the amorphous silicon liner 250 is conformally formed along the recessed semiconductor material layer 226' and the corresponding plurality of channel layers 224 and sidewall spacers 214. As used herein, the term "conformality" refers to the conformality of a layer to the contours of a feature or layer. The conformality of a layer is typically quantified by the ratio of the average thickness of the layer deposited on the feature sidewalls to the average thickness of the same deposited layer on the field or upper surface of the substrate. In some embodiments, one or more of the amorphous silicon liner 250 and the inner spacers 260 have a conformality in the range of 70% to 90%. As used in this context, "conformality in the range of 70% to 90%" means that the ratio of the average thickness of the layer deposited on the feature sidewalls to the average thickness of the same deposited layer deposited on the field or upper surface of the substrate is in the range of 70% to 90%.

[0055] The amorphous silicon liner 250 and the inner spacers 260 may define any suitable shape, including but not limited to a circle, a square, a rectangle, or any other polygon.

[0056] In some embodiments, each of the amorphous silicon liner 250 and the inner spacer 260 is substantially free of seams and / or voids. As used in this context, "substantially free" means less than about 5% (including less than about 4%, less than about 3%, less than about 2%, less than about 1%, less than about 0.5%, and less than about 0.1%) of seams and / or voids based on an atomic basis of the total composition of each of the amorphous silicon liner 250 and the inner spacer 260.

[0057] Reference Figure 2E At operation 112, method 100 includes etching a portion of inner spacer 260 to form etched inner spacer 260'. The etching process of operation 112 may include any suitable etching process, including but not limited to a pre-clean process, a wet etching process, or a dry etching process as described herein. In one or more specific embodiments, inner spacer 260 is etched from sidewall liner 214 to form etched inner spacer 260' and an amorphous silicon liner.

[0058] refer to Figure 2F , method 100 includes source / drain epitaxial growth and interlayer dielectric formation processes (operation 114) and replacement metal gate formation and polysilicon removal (operation 116). Figure 2F In the embodiment, the GAA device includes a highly doped epitaxial source / drain junction 270, a protective dielectric layer 272 on the highly doped epitaxial source / drain junction 270, such as silicon nitride (SiN), silicon oxynitride (SiON) or a combination thereof, and an interlayer dielectric 274 formed on the protective dielectric layer 272. Figure 2F Such processes and layers as shown are well known to those skilled in the art.

[0059] In some embodiments, during operation 116, the dummy gate structure 209 is removed to expose the channel region of the superlattice structure 204. During the removal of the dummy gate structure 209, the layers 270, 272, and 274 may protect the source / drain trenches 232 / 234. The dummy gate structure 209 may be removed using any conventional etching process, such as a pre-clean process, a wet etching process, or a dry etching process as described herein. In some embodiments, the dummy gate structure 209 includes one or more of a sacrificial oxide layer 210 and a dummy gate polysilicon layer 212, and the entire dummy gate structure 209 is removed by a selective etching process. In some embodiments, when the dummy gate structure 209 includes sidewall spacers, such as sidewall spacers 214, the sidewall spacers 214 are not removed during operation 112.

[0060] Reference Figure 2GAt operation 118, the method 100 includes removing the recessed semiconductor material layer 226' in the superlattice structure 204. At operation 118, the recessed semiconductor material layer 226' is selectively etched between the plurality of channel layers 224 in the superlattice structure 204. For example, in the case where the superlattice structure 204 is composed of a silicon (Si) layer and a silicon germanium (SiGe) layer, the silicon germanium (SiGe) is selectively etched to form the channel nanowires. For example, the recessed semiconductor material layer 226' composed of silicon germanium (SiGe) can be removed using any known etchant that is selective to the plurality of channel layers 224 (e.g., silicon (Si)), wherein the etchant etches the recessed semiconductor material layer 226' at a significantly higher rate than the plurality of channel layers 224. In some embodiments, a pre-cleaning process, a selective dry etching process, or a wet etching process as described herein can be used. In some embodiments, when the plurality of channel layers 224 are silicon (Si) and the recessed semiconductor material layer 226 ′ is silicon germanium (SiGe), a wet etchant, such as but not limited to a carboxylic acid / nitric acid / HF aqueous solution and a citric acid / nitric acid / HF aqueous solution, may be used to selectively remove the SiGe layer.

[0061] In one or more specific embodiments, Figure 2G As shown, the removal of the plurality of semiconductor material layers 226 (and / or the recessed semiconductor material layer 226 ′) leaves gaps between the plurality of channel layers 224 . The gaps between the plurality of channel layers 224 have a thickness of about 3 nanometers to about 20 nanometers, including any subranges and values ​​therebetween. The remaining channel layers 224 form a vertical array of channel nanowires that are coupled to the source / drain regions in the source trench 232 / drain trench 234 . The channel nanowires are parallel to the top surface 202 of the substrate 200 and aligned with each other to form a single column of channel nanowires.

[0062] refer to Figure 2H At operation 120, the method 100 includes etching a portion of the amorphous silicon liner 250 to form an etched amorphous silicon liner 250'. In one or more embodiments, the portion of the amorphous silicon liner 250 etched at operation 120 is a portion previously formed along the recessed semiconductor material layer 226'. Figure 2G In one or more embodiments, the portion of the amorphous silicon liner 250 formed along the recessed semiconductor material layer 226' (at Figure 2G The portions of the amorphous silicon liner 250 formed along the plurality of channel layers 224 are not etched.

[0063] It has been advantageously found that etching a portion of the amorphous silicon liner 250 formed along the inner sidewalls in operation 120 to form an etched amorphous silicon liner 250' reduces the effective capacitance (C eff ), measured in femtofarads per micron (fF / μm).

[0064] For example, in some embodiments, the amorphous silicon liner 250 has a thickness of approximately 1 nm, and the inner spacer 260 includes a low-k dielectric material having a k value of 4 when there is a silicon (Si) loss of approximately 1 nm. In a specific embodiment, wherein the amorphous silicon liner 250 has a thickness of approximately 1 nm, and the inner spacer 260 includes a low-k dielectric material having a k value of 4 when there is a silicon (Si) loss of approximately 1 nm, and a portion of the amorphous silicon liner 250 formed along the inner sidewall is etched in operation 116 to form an etched amorphous silicon liner 250′, the GAA device has a reduced effective capacitance (C ) compared to a GAA device without the inner spacer liner. eff ), the effective capacitance is measured in femtofarads per micron (fF / μm).

[0065] In other embodiments, the amorphous silicon liner 250 has a thickness of approximately 2 nm, and the inner spacer 260 includes a low-k dielectric material having a k value of 4, where the k value is 4 when there is a silicon (Si) loss of approximately 1 nm. In embodiments where the amorphous silicon liner 250 has a thickness of approximately 2 nm, the inner spacer 260 includes a low-k dielectric material having a k value of 4 when there is a silicon (Si) loss of approximately 1 nm, and a portion of the amorphous silicon liner 250 formed along the inner sidewall is etched at operation 116 to form an etched amorphous silicon liner 250 ′, the GAA device has a DC performance gain compared to a GAA device without the inner spacer liner.

[0066] It is advantageously found that the GAA device with the etched amorphous silicon liner 250' has a lower effective capacitance (C) than the GAA device without the inner spacer liner. eff ) (measured in femtofarads per micron (fF / μm)), the DC performance of the GAA device with the amorphous silicon liner 250 is improved by about 40%.

[0067] In some embodiments, the thickness of the amorphous silicon liner 250 is in the range of 0.5 nm to 3 nm, including all subranges and values ​​therebetween. It has been found that an amorphous silicon liner having a thickness greater than 3 nm has an overall greater effective capacitance (C eff ).

[0068] Reference Figure 2IAt operation 122, method 100 includes forming an interlayer dielectric (ILD) 276 on each remaining channel layer 224. In some embodiments, the ILD 276 encapsulates the remaining channel layer 224 and covers all portions of the channel layer 224 except for portions covered by the etched amorphous silicon liner 250'. The ILD 276 can be deposited using conventional chemical vapor deposition methods (e.g., plasma-enhanced chemical vapor deposition and low-pressure chemical vapor deposition). In one or more embodiments, the ILD 276 is formed of any suitable dielectric material described herein, such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride.

[0069] Reference Figure 2J At operation 124, method 100 includes one or more processes known to those skilled in the art for completing an hGAA device, such as replacement metal gate formation. For example, in one or more embodiments, a high-k dielectric 278 is formed on the ILD 276. The high-k dielectric 278 can be any suitable high-dielectric material deposited by any suitable deposition technique known to those skilled in the art. In some embodiments, the high-k dielectric 278 includes hafnium oxide. In some embodiments, a conductive material, such as titanium nitride (Tin), tungsten (W), cobalt (Co), aluminum (Al), or the like, is deposited on the high-k dielectric. The conductive material can be formed using any suitable deposition process, such as, but not limited to, atomic layer deposition (ALD), to ensure that a layer having a uniform thickness is formed around each of the plurality of channel layers 224.

[0070] Additional embodiments of the present disclosure are directed to a processing system 400 and method for forming the amorphous silicon liner 250 and inner spacer 260 of the electronic device (eg, GAA device), as described herein. Figure 3 Examples of processing systems that may be appropriately modified according to the teachings provided herein include Dual ACP, GT and The ® platform, commercially available from Applied Materials, Inc., Santa Clara, California, USA, can also utilize other processing systems. Other processing systems, including systems from other manufacturers, can also benefit from the aspects described herein.

[0071] The processing system 400 may include any dielectric deposition product (DDP) available from Applied Materials, Inc., Santa Clara, California, USA. In some embodiments, the processing system 400 includes a low-k silicon carbide (SiOC) dielectric chemical vapor deposition (CVD) chamber. In some embodiments, the processing system 400 includes a low-k silicon carbide (SiOC) dielectric chemical vapor deposition (CVD) chamber by connecting the low-k silicon carbide (SiOC) dielectric chemical vapor deposition (CVD) chamber to the The company's etch systems (available from Applied Materials, Inc., Santa Clara, CA, USA) combine advanced unit process solutions to provide integrated tool solutions (e.g., integrated cyclic-CVD deposition-etch processing systems).

[0072] In some embodiments, one or more operations of the methods of the present disclosure are performed in situ, as described herein. In some embodiments, one or more operations of the methods of the present disclosure are performed ex situ, as described herein. In some embodiments, one or more operations of method 100 are performed in situ in an integrated processing tool (e.g., processing system 400). As used herein, unless otherwise indicated, the terms "integrated processing tool," "integrated tool system," "cluster tool," "processing tool," and "processing system 400" are used interchangeably to refer to a process that is a process that is a collection of processing tools, such as a processing system 400. Figure 3 Processing system 400 is shown.

[0073] One or more operations of method 100 are performed by an integrated module in-situ within an integrated process tool system, such as processing system 400. Unless otherwise indicated, the integrated modules described herein are performed in-situ within an integrated process tool system, such as processing system 400.

[0074] In some embodiments, the processing system 400 includes an integrated module for performing a pre-cleaning process before forming the interspacer liner and the interspacer (operation 108 of method 100 ), and performing a thermal chemical vapor deposition process to form the amorphous silicon liner and the interspacer within the superlattice structure (operation 110 of method 100 ).

[0075] In some embodiments, the processing system 400 includes an integrated module for performing a pre-cleaning process prior to forming the inner spacer liner and the inner spacer (operation 108 of method 100), performing a thermal chemical vapor deposition process to form an amorphous silicon liner and the inner spacer within the superlattice structure (operation 110 of method 100), and etching a portion of the inner spacer (operation 112 of method 100).

[0076] In some embodiments, the processing system 400 is also particularly well-suited for 3D memory horizontal wordline applications and forming contact / sidewall spacers.

[0077] In some embodiments, each operation of the methods described herein is performed in the same processing chamber. In some embodiments, the operations of the methods described herein are performed in separate processing chambers. In some embodiments, the separate processing chambers are connected together as part of a processing system. In some embodiments, the operations of the methods described herein are performed without breaking vacuum.

[0078] Figure 3 A schematic top view of an example of a multi-chamber processing system 400 according to a specific embodiment of the present disclosure is shown. The processing system 400 generally includes a factory interface 402, load lock chambers 404, 406, transfer chambers 408, 410 with respective transfer robots 412, 414, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430. As described in detail herein, wafers in the processing system 400 can be processed in each chamber and transferred between each chamber without exposing the wafers to an environment external to the processing system 400 (e.g., the atmospheric environment that may exist in a wafer fab). For example, wafers can be processed in each chamber and transferred between each chamber in a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without disrupting the low pressure or vacuum environment between various processes performed on the wafers in the processing system 400. Accordingly, the processing system 400 can provide an integrated solution for a number of wafer processing operations.

[0079] exist Figure 3 In some examples, the factory interface 402 includes a docking station 440 and a factory interface robot 442 to facilitate wafer transfer. The docking station 440 is configured to receive one or more front opening unified pods (FOUPs) 444. In some examples, each factory interface robot 442 generally includes a blade 448 disposed at one end of the respective factory interface robot 442, which is configured to transfer wafers from the factory interface 402 to the load lock chambers 404, 406.

[0080] The load lock chambers 404, 406 have respective ports 450, 452 coupled to the factory interface 402 and respective ports 454, 456 coupled to the transfer chamber 408. The transfer chamber 408 further has respective ports 458, 460 coupled to the holding chambers 416, 418 and respective ports 462, 464 coupled to the processing chambers 420, 422. Similarly, the transfer chamber 410 has respective ports 466, 468 coupled to the holding chambers 416, 418 and respective ports 470, 472, 474, 476 coupled to the processing chambers 424, 426, 428, 430. Ports 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, and 476 may be, for example, openings with slit valves for wafers to be passed through by transfer robots 412 and 414 and for providing a seal between the respective chambers to prevent gas from passing between the respective chambers. Generally, any port is open to allow wafers to be transferred therethrough. Otherwise, the port is closed.

[0081] The load lock chambers 404, 406, transfer chambers 408, 410, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430 may be fluidly coupled to a gas and pressure control system (not specifically illustrated). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. During operation, the factory interface robot 442 transfers wafers from the FOUP 444 to the load lock chamber 404 or 406 via port 450 or 452. The gas and pressure control system pump then depressurizes the load lock chamber 404 or 406. The gas and pressure control system further maintains a low pressure or vacuum environment (which may include an inert gas) within the transfer chambers 408, 410 and holding chambers 416, 418. Thus, pumping down the load lock chamber 404 or 406 facilitates transferring wafers between, for example, the atmospheric environment of the factory interface 402 and the low pressure or vacuum environment of the transfer chamber 408 .

[0082] After the wafer pump in the load lock chamber 404 or 406 is depressurized, the transfer robot 412 transfers the wafer from the load lock chamber 404 or 406 to the transfer chamber 408 via port 454 or 456. The transfer robot 412 can then transfer the wafer to either of the processing chambers 420 or 422 for processing via ports 462 or 464, respectively, and transfer the wafer to either of the holding chambers 416 or 418 for holding via ports 458 or 460, respectively, pending further transfer. Similarly, the transfer robot 414 can access the wafer in the holding chamber 416 or 418 via ports 466 or 468, and can transfer the wafer to any of the processing chambers 424, 426, 428, 430 and / or between the processing chambers and the holding chambers 416 or 418 via ports 470, 472, 474, 476, respectively, holding the wafer for further transfer via ports 466 or 468. Transfer and holding of wafers within and between the various chambers can be performed in a low pressure or vacuum environment provided by the gas and pressure control system.

[0083] The processing chambers 420, 422, 424, 426, 428, 430 may be any suitable chamber for processing wafers. In some embodiments, the processing chambers 420, 422, 424, 426, 428, 430 include a pre-clean chamber, a chemical vapor deposition (CVD) chamber, and an etching chamber. In some embodiments, the processing chamber 420 may be capable of performing an annealing process, the processing chamber 422 may be capable of performing a cleaning process, and the processing chambers 424, 426, 428, 430 may be capable of performing an epitaxial growth process. In some examples, the processing chamber 422 may be capable of performing a cleaning process, the processing chamber 420 may be capable of performing an etching process, and the processing chambers 424, 426, 428, 430 may be capable of performing their respective epitaxial growth processes. The processing chamber 422 may be a SiCoNi wafer manufactured by Applied Materials, Inc., Santa Clara, California, USA. TM Pre-clean chamber. The processing chamber 420 may be a Selectra available from Applied Materials, Inc., Santa Clara, CA, USA. TM Etching chamber.

[0084] A system controller 490 is coupled to the processing system 400 for controlling the processing system 400 or components thereof. For example, the system controller 490 can control the execution of the processing system 400 by directly controlling the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430 of the processing system 400 or by controlling controllers associated with the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430. During execution, the system controller 490 can enable data collection and feedback from the various chambers to coordinate the performance of the processing system 400.

[0085] System controller 490 generally includes a central processing unit (CPU) 492, memory 494, and support circuits 496. CPU 492 can be any general-purpose processor suitable for use in industrial environments. Memory 494, or non-transitory computer-readable media, is accessible by CPU 492 and can include one or more of random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage. Support circuits 496 are coupled to CPU 492 and can include cache memory, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein can generally be implemented, for example, as software routines, by CPU 492 executing computer instruction program code stored in memory 494 (or the memory of a particular processing chamber) under the control of CPU 492. As CPU 492 executes the computer instruction program code, CPU 492 controls the chamber to perform processing according to the various methods.

[0086] Other processing systems may also employ other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 408 and 410 and holding chambers 416 and 418. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chamber) may be implemented as the transfer device in the processing system.

[0087] The process may generally be stored as a software routine in the memory of the system controller 490, which, when executed by the processor, causes the processing chamber to perform the process of the present disclosure. The software routine may also be stored and / or executed by a second processor (not shown), which is remote from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the process may be implemented in software and executed using a computer system, or in hardware as, for example, an application-specific integrated circuit or other type of hardware, or as a combination of software and hardware. When executed by the processor, the software routine converts a general-purpose computer into a special-purpose computer (controller) that controls the execution of the chamber, thereby enabling the process to be performed.

[0088] One or more embodiments of the present disclosure are directed to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform a method described herein, such as method 100 .

[0089] The terms "a", "an" and "the" and similar referents used when describing the materials and methods discussed herein (particularly in the context of the following claims) should be interpreted as including the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, the recitation of numerical ranges herein is merely a shorthand method for individually referring to each individual numerical value within the range. Unless otherwise indicated herein or clearly contradicted by the context, all methods described herein can be performed in any suitable order. The use of any and all examples provided herein, or exemplary language (such as "such as"), is solely for the purpose of better illustrating the materials and methods and does not constitute a limitation on the scope unless otherwise claimed. No language in the specification should be interpreted as indicating that any non-claimed element is essential to the practice of the disclosed materials and methods.

[0090] References throughout this specification to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that particular features, structures, materials, or characteristics associated with an embodiment are included in at least one embodiment of the present disclosure. Thus, phrases such as "in one or more embodiments," "in some embodiments," "in an embodiment," or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0091] Although the disclosure herein has been described with reference to specific embodiments, it will be understood by those skilled in the art that the described embodiments are merely illustrative of the principles and applicators of the disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to encompass modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for manufacturing an electronic device, the method comprising: forming a superlattice structure on a top surface of the semiconductor substrate, the superlattice structure comprising a plurality of semiconductor material layers and corresponding plurality of channel layers arranged alternately in a plurality of stacked pairs; recessing a portion of the plurality of semiconductor material layers to form a recessed semiconductor material layer; conformally forming an amorphous silicon liner along the electronic device, including along the recessed semiconductor material layer and the corresponding plurality of channel layers; as well as An inner spacer is formed directly on the amorphous silicon liner, wherein the inner spacer is adjacent to the source region and the drain region.

2. The method of claim 1, further comprising: The semiconductor substrate is pre-cleaned before forming the amorphous silicon liner and the inner spacer. 3 . The method of claim 2 , wherein pre-cleaning the semiconductor substrate, forming the amorphous silicon liner, and forming the inner spacer are performed in an integrated tool system without breaking vacuum. 4 . The method of claim 1 , wherein the amorphous silicon liner has a thickness in a range of 0.5 nm to 3 nm. 5 . The method of claim 1 , wherein the amorphous silicon liner and the inner spacer are formed through a chemical vapor deposition (CVD) process at a temperature in a range of 400° C. to 650° C. The method of claim 1 , wherein the inner spacer comprises a low-k dielectric material. The method of claim 6 , wherein the low-k dielectric material has an k value between 3 and 5.

8. The method of claim 6, wherein the low-k dielectric material comprises one or more of silicon oxycarbide (SiOC) or silicon oxynitride (SiON).

9. The method of claim 1, wherein the amorphous silicon liner and the inner spacer are each substantially free of seams and / or voids.

10. The method of claim 1, wherein the plurality of semiconductor material layers comprise silicon germanium (SiGe), and the corresponding plurality of channel layers comprise silicon (Si).

11. The method of claim 1 , further comprising: A portion of the inner spacer is etched.

12. A method of manufacturing a gate-all-around (GAA) device, the method comprising: pre-cleaning a semiconductor substrate having a superlattice structure formed on a top surface of the semiconductor substrate, the superlattice structure comprising a plurality of recessed semiconductor material layers and a corresponding plurality of channel layers arranged alternately in a plurality of stacked pairs; performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within the superlattice structure, wherein the amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layer and the corresponding plurality of channel layers, the inner spacer is directly formed on the amorphous silicon liner, and the inner spacer is adjacent to the source region and the drain region; etching a portion of the inner spacer; as well as The replacement metal gate and the recessed semiconductor material layer are removed from the semiconductor substrate, and then the inner sidewall portion of the amorphous silicon liner is etched. 13 . The method of claim 12 , wherein pre-cleaning the semiconductor substrate, forming the amorphous silicon liner, and forming the inner spacer are performed in an integrated tool system without breaking vacuum.

14. The method of claim 12, wherein the amorphous silicon liner and the inner spacer are formed at a temperature in a range of 400°C to 650°C.

15. The method of claim 12, wherein the amorphous silicon liner and the inner spacer are each substantially free of seams and / or voids.

16. The method of claim 12, wherein the amorphous silicon liner has a thickness in a range of 0.5 nm to 3 nm. 17 . The method of claim 12 , wherein the inner spacer comprises a low-k dielectric material having an k value between 3 and 5.

18. The method of claim 17, wherein the low-k dielectric material comprises one or more of silicon oxycarbide (SiOC) or silicon oxynitride (SiON).

19. A processing tool, comprising: a central transfer station comprising a robot configured to move a semiconductor substrate; a plurality of processing stations, each processing station being connected to the central transfer station and providing a processing area that is separate from a processing area of ​​an adjacent processing station, the plurality of processing stations including a pre-clean chamber and a chemical vapor deposition (CVD) chamber; as well as a controller connected to the central transfer station and the plurality of processing stations, the controller being configured to activate the robot to move the semiconductor substrate between the processing stations and control a processing cycle for forming an amorphous silicon liner for a gate-all-around (GAA) device, the processing cycle comprising: pre-cleaning the semiconductor substrate, the semiconductor substrate having a superlattice structure formed on a top surface of the semiconductor substrate, the superlattice structure comprising a plurality of recessed semiconductor material layers and corresponding plurality of channel layers arranged alternately in a plurality of stacked pairs; and performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within the superlattice structure, wherein the amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layer and the corresponding multiple channel layers, and the inner spacer is directly formed on the amorphous silicon liner, and the inner spacer is adjacent to the source region and the drain region.

20. The processing tool of claim 19, wherein the plurality of processing stations further comprises an etching chamber for etching a portion of the inner spacer.

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