Low-power-consumption chip power supply management system suitable for extremely wide power supply voltage range

Abstract

The low-power-consumption chip power supply management system adapts to an extremely wide power supply voltage range, can be started under extremely low to ultrahigh power supply voltage and can tolerate high power supply voltage, and meanwhile has extremely low dormancy power consumption. The system comprises a constant electric domain control circuit, a reference voltage and current generator and a voltage stabilizer, high enough power supply voltage is provided for a post-stage circuit through a first-stage PUMP and a second-stage PUMP, external power supply noise is isolated, the voltage stabilizer controls source electrode voltage of an NMOS pass transistor NPASS through loop feedback so as to generate a stable on-chip main power supply VDD, and the on-chip main power supply VDD is connected with the voltage stabilizer. And most of circuit power supplies are cut off in a low-power-consumption mode, so that ultra-low standby power consumption is ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit power management, and in particular relates to a low-power chip power management system that is adaptable to an extremely wide power supply voltage range. Background Art

[0002] In modern electronic systems, integrated circuits (ICs) often face the challenge of large fluctuations in external power supply voltages. This is particularly true in mobile devices, sensors, and renewable energy systems, where external power supply voltages can range from extremely low to extremely high. Furthermore, a single IC chip must be compatible with a variety of supply voltages to meet diverse market demands. This places stringent demands on the chip's internal power management. Traditional power management systems, when faced with this complex power supply environment, face challenges such as difficulty starting from low voltage, poor voltage stability, and high standby power consumption.

[0003] Traditional power systems, such as Figure 1 As shown, a simple power switch is typically used to directly transfer external power to an on-chip intermediate power supply without any on-chip voltage boosting. While this approach is simple, it increases the design difficulty of the low-voltage reference voltage and current generator when the power supply voltage varies widely, and it is also susceptible to interference at high power supply voltages. Furthermore, to ensure proper operation of the voltage regulator at low power supply voltages, conventional voltage regulators typically use negative-threshold NMOS devices. Even when the gate is connected to ground in sleep mode, these devices cannot be fully shut down, resulting in significant leakage current. Therefore, conventional solutions typically require shutting down the power switch to control leakage power, but this increases system complexity and area costs. Summary of the Invention

[0004] The present invention aims to provide a low-power chip power management system that can adapt to an extremely wide power supply voltage range. It can operate stably under extremely low to high power supply voltages and has extremely low sleep power consumption, so as to solve the technical problems of instability and high power consumption of traditional power management systems when the external power supply voltage fluctuates greatly.

[0005] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0006] A low-power chip power management system adaptable to an extremely wide power supply voltage range includes a normal power domain control circuit, a reference voltage and current generator, and a voltage regulator, wherein:

[0007] The normal power domain control circuit has a first input terminal connected to an external wake-up signal Wakeup; a second input terminal connected to a power supply VCC; and an output terminal for an intermediate power supply VM. The normal power domain control circuit detects whether the power supply VCC is powered on. When the power supply VCC is detected, the circuit outputs the intermediate power supply VM through a logic judgment function to provide power for the reference voltage and current generator.

[0008] The normal power domain control circuit is responsible for checking whether the external wake-up signal Wakeup is valid when the system is in sleep mode. If Wakeup is valid, it outputs the intermediate power supply VM through a logic judgment function to provide power supply for the reference voltage and current generator;

[0009] The reference voltage and current generator has a first input terminal connected to the intermediate power supply VM, an output terminal of the normal power domain control circuit, and a second input terminal connected to the power supply VCC; a first output terminal is a clock CLK, connected to the first input terminal of the voltage regulator; a second output terminal is a pre-reference voltage PREVREF, connected to the second input terminal of the voltage regulator; a third output terminal is a pre-reference current PREIREF3, connected to the third input terminal of the voltage regulator; a fourth output terminal is a high-precision reference current IREF, connected to the fourth input terminal of the voltage regulator; and a fifth output terminal is a high-precision reference voltage VREF, connected to the fifth input terminal of the voltage regulator. The reference voltage and current generator provides the pre-reference voltage, pre-reference current, high-precision reference voltage, high-precision reference current, and clock to the voltage regulator in the subsequent stage;

[0010] The voltage regulator has a sixth input terminal connected to the power supply VCC; the output terminal is the output power supply VDD, which provides a stable power supply for other IPs or digital logic on the chip.

[0011] Furthermore, the normal power domain control circuit includes an ultra-low power consumption power-on reset circuit, a normal power domain logic control circuit, and a power switch tube PSW, wherein:

[0012] The input terminal of the ultra-low power power-on reset circuit is connected to the power supply VCC, and the output terminal PORE_ULP is connected to the first input terminal of the normal power domain logic control circuit. It is used to detect the power-on status of the external power supply VCC and generate a power-on reset signal PORE_ULP to ensure the stability of the system at power-on;

[0013] The second input terminal of the normal power domain logic control circuit is connected to the sleep state enable signal SLEEP_EN from the chip digital circuit system, the third input terminal is connected to the wakeup source Wakeup signal, and the output terminal power-on enable signal PMU_AON_EN is connected to the gate of the power switch tube PSW to control the conduction and shutdown of the power switch tube PSW to achieve a low-power sleep mode;

[0014] The source of the power switch tube PSW is connected to the external power supply VCC, and the drain outputs the intermediate power supply VM, which is connected to the first input terminal of the reference voltage and current generator as a power supply.

[0015] Furthermore, the reference voltage and current generator includes a low-voltage and low-precision bandgap circuit, a low-power OSC, a first-level PUMP, a high-precision bandgap circuit, a buffer, and a reference current generator, wherein:

[0016] The low-voltage, low-precision bandgap circuit has an input end connected to the power supply VCC; the output end PREIREF1 and the output end PREVREF are respectively connected to the first input end and the second input end of the first-level PUMP, the output end PREIREF2 is connected to the first input end of the low-power OSC, the output end PREIREF3 is connected to the third input end of the voltage regulator, and the output end PREIREF4 is connected to the first input end of the high-precision bandgap circuit; the low-voltage, low-precision bandgap circuit provides a pre-reference current and a pre-reference voltage for the low-power OSC, the first-level PUMP, and the high-precision bandgap circuit;

[0017] The second input end of the low-power OSC is connected to the power supply VCC; the output end is connected to the third input end of the first-level PUMP and the first input end of the voltage regulator to provide the clock signal CLK for the voltage regulator; the first-level PUMP provides a sufficiently high normal operating power supply voltage for the high-precision bandgap circuit, Buffer and reference current generator, and isolates external power supply noise. The low-voltage and low-precision bandgap circuit provides low-precision reference current and voltage for the basic bias requirements of the system. The low-power OSC provides a stable clock signal to ensure the normal operation of the PUMP. The high-precision bandgap circuit, Buffer and reference current generator provide high-precision reference voltage and current for precise control and stable operation of the system.

[0018] The first-level PUMP has a fourth input terminal connected to the power supply VCC; the output terminal is the on-chip power supply PVDD1, the on-chip power supply PVDD1 is connected to the first terminal of the capacitor CL1, the second terminal of the capacitor CL1 is grounded, and the on-chip power supply PVDD1 is also connected to the power supply terminal of the high-precision bandgap circuit, the buffer, and the reference current generator;

[0019] The high-precision bandgap circuit, the output terminal VREF_CORE is connected to the input terminal of the Buffer and the reference current generator to provide a core high-precision reference voltage;

[0020] The buffer and reference current generator have an output terminal IREF connected to the fourth input terminal of the voltage regulator, and an output terminal VREF connected to the fifth input terminal of the voltage regulator; to provide a high-precision reference voltage VREF and a high-precision reference current IREF.

[0021] Furthermore, the voltage regulator includes a two-stage pump, an op amp (AMP), an NMOS pass transistor (NPASS), feedback resistors R1 and R2, and a voltage-stabilizing capacitor (CL2). The two-stage pump provides sufficient power supply voltage for the op amp (AMP) to operate normally. The op amp (AMP) controls the source voltage of the NMOS pass transistor (NPASS) through loop feedback to generate a stable on-chip main power supply (VDD). Adjustment of feedback resistors R1 and R2 ensures output voltage stability and accuracy.

[0022] The two-stage PUMP has a first input end connected to the first output end clock CLK of the reference voltage and current generator, a second input end connected to the second output end pre-reference voltage PREVREF of the reference voltage and current generator, a third input end connected to the third output end pre-reference current PREIREF3 of the reference voltage and current generator, and a fourth input end connected to the power supply VCC; the output end is the on-chip power supply PVDD2, which is connected to the first end of the capacitor CL2, and the second end of the capacitor CL2 is grounded. The on-chip power supply PVDD2 is also connected to the power supply end of the operational amplifier AMP, serving as the power supply for the operational amplifier AMP;

[0023] The operational amplifier AMP has a first input terminal which is a bias current terminal of the operational amplifier AMP and is connected to the fourth output terminal of the reference voltage and current generator, the high-precision reference current IREF; a second input terminal which is a positive input terminal of the operational amplifier AMP and is connected to the fourth output terminal of the reference voltage and current generator, the high-precision reference voltage VREF; and an output terminal which is connected to the gate of the NMOS pass transistor NPASS;

[0024] The second end of the feedback resistor R1 is connected to the first end of the feedback resistor R2, the second end of the feedback resistor R2 is grounded, and the second end of the feedback resistor R1 and the first end of the feedback resistor R2 are commonly connected to the third inverting input terminal of the operational amplifier AMP;

[0025] The NMOS pass transistor NPASS has a drain connected to an external power supply VCC, a source connected to a first end of the feedback resistor R1, and a source outputting a power supply VDD. The power supply VDD is connected to a first end of a voltage stabilizing capacitor CL, and a second end of the voltage stabilizing capacitor CL is grounded.

[0026] The present invention provides a low-power chip power management system that is adaptable to an extremely wide power supply voltage range and has the following advantages:

[0027] 1. Power supply architecture: Compared with traditional solutions, this invention uses on-chip boost processing, through a single-stage and two-stage pump, to provide a higher power supply voltage, ensuring the system's operating stability under different power supply voltage ranges. This solves the design difficulties of reference voltage and current generators and voltage regulators in traditional solutions when facing extremely low power supplies and large power supply interference.

[0028] 2. Low power consumption: This invention achieves extremely low standby power consumption by controlling the shutdown of the power switch PSW and the NMOS pass transistor NPASS in sleep mode. In contrast, the negative-threshold NMOS device in traditional solutions cannot be completely shut down in sleep mode, resulting in high leakage current power consumption.

[0029] 3. Drive Capability: The present invention uses an NMOS pass transistor (NPASS), which has higher drive capability and smaller area overhead. Traditional solutions require larger PMOS devices and negative threshold NMOS devices, increasing area and design complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is the schematic diagram of the traditional power supply system.

[0031] Figure 2 A diagram showing the composition of a low-power chip power management system that adapts to an extremely wide power supply voltage range according to an embodiment of the present invention. Figure 3 Schematic diagram of a low-power chip power management system that adapts to an extremely wide power supply voltage range according to the present invention; DETAILED DESCRIPTION

[0032] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0033] In this embodiment, a low-power chip power management system that adapts to an extremely wide power supply voltage range is provided. Figure 2 As shown in the system composition diagram, it includes a normal power domain control circuit, a reference voltage and current generator, and a voltage regulator.

[0034] The normal power domain control circuit includes an ultra-low power power-on reset circuit, a normal power domain logic control circuit, and a power switch PSW. Its first input is connected to an external wake-up signal (Wakeup); its second input is connected to power supply VCC; and its output is an intermediate power supply (VM). The normal power domain control circuit detects whether power supply VCC is powered on. Upon detecting power supply VCC, it uses a logic determination function to output intermediate power supply VM, providing power to the reference voltage and current generator.

[0035] In addition, when the system is in sleep mode, the normal power domain control circuit is also responsible for checking whether the external wake-up signal Wakeup is valid. If Wakeup is valid, the intermediate power supply VM is output through the logic judgment function to provide power supply for the reference voltage and current generator.

[0036] The reference voltage and current generator has a first input connected to the intermediate power supply VM, the output terminal of the normal power domain control circuit, and a second input connected to the power supply VCC. The first output is a clock CLK, connected to the first input of the voltage regulator. The second output is a pre-reference voltage PREVREF, connected to the second input of the voltage regulator. The third output is a pre-reference current PREIREF3, connected to the third input of the voltage regulator. The fourth output is a high-precision reference current IREF, connected to the fourth input of the voltage regulator. The fifth output is a high-precision reference voltage VREF, connected to the fifth input of the voltage regulator. The reference voltage and current generator provides the pre-reference voltage, pre-reference current, high-precision reference voltage, high-precision reference current, and clock for the subsequent voltage regulator.

[0037] Among them, the sixth input terminal of the voltage regulator is connected to the power supply VCC; the output terminal is the output power supply VDD, which provides a stable power supply for other IP or digital logic on the chip.

[0038] Specifically, if Figure 3 As shown, the normal power domain control circuit includes an ultra-low power consumption power-on reset circuit, a normal power domain logic control circuit and a power switch tube PSW.

[0039] The input of the ultra-low power power-on reset circuit is connected to the power supply VCC, and the output PORE_ULP is connected to the first input of the normal power domain logic control circuit, which is used to detect the power-on status of the external power supply VCC and generate a power-on reset signal PORE_ULP. When VCC is powered on, the power-on reset signal PORE_ULP is valid. After receiving the valid power-on reset signal PORE_ULP, the normal power domain logic control circuit outputs the power-on enable signal PMU_AON_EN as a valid low level, driving the power switch tube PSW to conduct, thereby introducing the external power supply VCC into the system.

[0040] The second input of the normal power domain logic control circuit is connected to the sleep state enable signal SLEEP_EN from the chip's digital circuit system, the third input is connected to the wakeup source Wakeup signal, and the output power-on enable signal PMU_AON_EN is connected to the gate of the power switch tube PSW, which is used to control the conduction and shutdown of the power switch tube PSW. When the chip enters sleep mode, the SLEEP_EN signal is valid, the normal power domain logic control circuit turns PMU_AON_EN invalid, the power switch tube PSW is turned off, and the system enters low-power mode. When the Wakeup signal is valid, the normal power domain logic control circuit reactivates PMU_AON_EN, the power switch tube PSW is turned on, the system exits low-power mode, and resumes normal operation.

[0041] The source of the power switch tube PSW is connected to the external power supply VCC, and the drain outputs the intermediate power supply VM, which is connected to the first input terminal of the reference voltage and current generator as a power supply.

[0042] Specifically, if Figure 3 As shown, the reference voltage and current generator includes a low-voltage and low-precision bandgap circuit, a low-power OSC, a first-level PUMP, a high-precision bandgap circuit, a buffer and a reference current generator.

[0043] Among them, the low-voltage, low-precision bandgap circuit has an input connected to the power supply VCC; the output terminals PREIREF1 and PREVREF are respectively connected to the first input terminal and the second input terminal of the first-stage PUMP, the output terminal PREIREF2 is connected to the first input terminal of the low-power OSC, the output terminal PREIREF3 is connected to the third input terminal of the voltage regulator, and the output terminal PREIREF4 is connected to the first input terminal of the high-precision bandgap circuit. It provides pre-reference current and pre-reference voltage for the low-power OSC, the first-stage PUMP, and the high-precision bandgap circuit;

[0044] Among them, the low-power OSC has a second input terminal connected to the power supply VCC; the output terminal is connected to the third input terminal of the first-level PUMP and the first input terminal of the voltage regulator to provide a clock signal CLK for the voltage regulator;

[0045] Among them, the first-stage PUMP has a fourth input terminal connected to the power supply VCC; the output terminal is the on-chip power supply PVDD1, which is connected to the first terminal of the capacitor CL1, and the second terminal of the capacitor CL1 is grounded. The on-chip power supply PVDD1 is also connected to the power supply terminal of the high-precision bandgap circuit, buffer, and reference current generator. The first-stage PUMP uses the boost function to maintain the output on-chip power supply PVDD1 sufficient to maintain the subsequent high-precision bandgap circuit, buffer, and reference current generator within the normal operating voltage range even when the power supply VCC is low. At the same time, when there is noise interference in the power supply VCC, the first-stage PUMP plays a voltage stabilization role to resist the interference of the power supply VCC.

[0046] The high-precision bandgap circuit has an output terminal VREF_CORE connected to the input terminals of the buffer and the reference current generator to provide a high-precision core reference voltage.

[0047] The output terminal IREF of the buffer and the reference current generator is connected to the fourth input terminal of the voltage regulator, and the output terminal VREF is connected to the fifth input terminal of the voltage regulator to provide a high-precision reference voltage VREF and a high-precision reference current IREF.

[0048] Specifically, if Figure 3 As shown, the voltage regulator includes two-stage PUMP, an operational amplifier AMP, an NMOS pass transistor NPASS, a feedback resistor R1, a feedback resistor R2, and a voltage stabilizing capacitor CL2.

[0049] The two-stage PUMP has a first input connected to the first output clock CLK of the reference voltage and current generator, a second input connected to the pre-reference voltage PREVREF, a second output of the reference voltage and current generator, a third input connected to the pre-reference current PREIREF3, a third output of the reference voltage and current generator, and a fourth input connected to the power supply VCC. The output is the on-chip power supply PVDD2, connected to the first end of the capacitor CL2, the second end of the capacitor CL2 is grounded, and the on-chip power supply PVDD2 is also connected to the power supply end of the operational amplifier AMP, serving as the power supply for the operational amplifier AMP.

[0050] Among them, the operational amplifier AMP has a first input terminal which is the bias current terminal of the operational amplifier AMP, connected to the fourth output terminal of the reference voltage and current generator, the high-precision reference current IREF; the second input terminal is the positive input terminal of the operational amplifier AMP, connected to the fourth output terminal of the reference voltage and current generator, the high-precision reference voltage VREF; and the output terminal is connected to the gate of the NMOS pass tube NPASS.

[0051] The second end of the feedback resistor R1 is connected to the first end of the feedback resistor R2, the second end of the feedback resistor R2 is grounded, and the second end of the feedback resistor R1 and the first end of the feedback resistor R2 are commonly connected to the third inverting input terminal of the operational amplifier AMP;

[0052] Among them, the NMOS pass transistor NPASS has a drain connected to the external power supply VCC, a source connected to the first end of the feedback resistor R1, and the source also outputs the power supply VDD. The power supply VDD is connected to the first end of the voltage-stabilizing capacitor CL, and the second end of the voltage-stabilizing capacitor CL is grounded.

[0053] The on-chip power supply PVDD2, output from the two-stage pump, serves as the power supply for the op amp AMP. Even when the power supply VCC is low, it can still provide sufficient drive voltage for the gate of the NMOS pass transistor NPASS. Compared to traditional structures, the two-stage pump plus the NMOS pass transistor NPASS structure has stronger drive capability and can achieve a smaller device area under the same load capacity.

[0054] When the system is in sleep mode, the NMOS pass transistor NPASS can be turned off by setting the gate voltage to a low level, effectively controlling the low power consumption level in sleep mode.

[0055] It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be protected by the present invention.

Claims

1. A low-power chip power management system that adapts to an extremely wide power supply voltage range, characterized in that: It includes a normal power domain control circuit, a reference voltage and current generator, and a voltage regulator, wherein: The normal power domain control circuit has a first input terminal connected to an external wake-up signal Wakeup; a second input terminal connected to a power supply VCC; and an output terminal for an intermediate power supply VM. The normal power domain control circuit detects whether the power supply VCC is powered on. When the power supply VCC is detected, the circuit outputs the intermediate power supply VM through a logic judgment function to provide power for the reference voltage and current generator. The normal power domain control circuit is responsible for checking whether the external wake-up signal Wakeup is valid when the system is in sleep mode. If Wakeup is valid, it outputs the intermediate power supply VM through a logic judgment function to provide power supply for the reference voltage and current generator; The reference voltage and current generator has a first input terminal connected to the intermediate power supply VM, an output terminal of the normal power domain control circuit, and a second input terminal connected to the power supply VCC; a first output terminal is a clock CLK, connected to the first input terminal of the voltage regulator; a second output terminal is a pre-reference voltage PREVREF, connected to the second input terminal of the voltage regulator; a third output terminal is a pre-reference current PREIREF3, connected to the third input terminal of the voltage regulator; a fourth output terminal is a high-precision reference current IREF, connected to the fourth input terminal of the voltage regulator; and a fifth output terminal is a high-precision reference voltage VREF, connected to the fifth input terminal of the voltage regulator. The reference voltage and current generator provides the pre-reference voltage, pre-reference current, high-precision reference voltage, high-precision reference current, and clock to the voltage regulator in the subsequent stage; The voltage regulator has a sixth input terminal connected to the power supply VCC; and an output terminal is the output power supply VDD.

2. The low-power chip power management system that adapts to an extremely wide power supply voltage range according to claim 1, characterized in that: The normal power domain control circuit includes an ultra-low power consumption power-on reset circuit, a normal power domain logic control circuit, and a power switch tube PSW, wherein: The input terminal of the ultra-low power power-on reset circuit is connected to the power supply VCC, and the output terminal PORE_ULP is connected to the first input terminal of the normal power domain logic control circuit, for detecting the power-on state of the external power supply VCC and generating a power-on reset signal PORE_ULP; The second input terminal of the normal power domain logic control circuit is the sleep state enable signal SLEEP_EN, the third input terminal is connected to the wakeup source Wakeup signal, and the output terminal power-on enable signal PMU_AON_EN is connected to the gate of the power switch tube PSW, which is used to control the conduction and shutdown of the power switch tube PSW; The source of the power switch tube PSW is connected to the external power supply VCC, and the drain outputs the intermediate power supply VM, which is connected to the first input terminal of the reference voltage and current generator as a power supply.

3. The low-power chip power management system adaptable to an extremely wide power supply voltage range according to claim 1, characterized in that: The reference voltage and current generator includes a low-voltage and low-precision bandgap circuit, a low-power OSC, a first-level PUMP, a high-precision bandgap circuit, a buffer, and a reference current generator, wherein: The low-voltage and low-precision bandgap circuit has an input end connected to the power supply VCC; the output end PREIREF1 and the output end PREVREF are respectively connected to the first input end and the second input end of the first-level PUMP, the output end PREIREF2 is connected to the first input end of the low-power OSC, the output end PREIREF3 is connected to the third input end of the voltage regulator, and the output end PREIREF4 is connected to the first input end of the high-precision bandgap circuit; the low-voltage and low-precision bandgap circuit provides a pre-reference current and a pre-reference voltage for the low-power OSC, the first-level PUMP, and the high-precision bandgap circuit; The low-power OSC has a second input terminal connected to the power supply VCC; an output terminal connected to the third input terminal of the first-level PUMP and the first input terminal of the voltage regulator to provide a clock signal CLK for the voltage regulator; The first-level PUMP has a fourth input terminal connected to the power supply VCC; the output terminal is the on-chip power supply PVDD1, the on-chip power supply PVDD1 is connected to the first terminal of the capacitor CL1, the second terminal of the capacitor CL1 is grounded, and the on-chip power supply PVDD1 is also connected to the power supply terminal of the high-precision bandgap circuit, the buffer, and the reference current generator; The high-precision bandgap circuit, the output terminal VREF_CORE is connected to the input terminal of the Buffer and the reference current generator to provide a core high-precision reference voltage; The buffer and reference current generator have an output terminal IREF connected to the fourth input terminal of the voltage regulator, and an output terminal VREF connected to the fifth input terminal of the voltage regulator; to provide a high-precision reference voltage VREF and a high-precision reference current IREF.

4. The low-power chip power management system adaptable to an extremely wide power supply voltage range according to claim 1, characterized in that: The voltage regulator includes two-stage PUMP, operational amplifier AMP, NMOS pass transistor NPASS, feedback resistor R1, feedback resistor R2, and voltage stabilizing capacitor CL2, wherein: The two-stage PUMP has a first input end connected to the first output end clock CLK of the reference voltage and current generator, a second input end connected to the second output end pre-reference voltage PREVREF of the reference voltage and current generator, a third input end connected to the third output end pre-reference current PREIREF3 of the reference voltage and current generator, and a fourth input end connected to the power supply VCC; the output end is the on-chip power supply PVDD2, which is connected to the first end of the capacitor CL2, and the second end of the capacitor CL2 is grounded. The on-chip power supply PVDD2 is also connected to the power supply end of the operational amplifier AMP, serving as the power supply for the operational amplifier AMP; The operational amplifier AMP has a first input terminal which is a bias current terminal of the operational amplifier AMP and is connected to the fourth output terminal of the reference voltage and current generator, the high-precision reference current IREF; a second input terminal which is a positive input terminal of the operational amplifier AMP and is connected to the fourth output terminal of the reference voltage and current generator, the high-precision reference voltage VREF; and an output terminal which is connected to the gate of the NMOS pass transistor NPASS; The second end of the feedback resistor R1 is connected to the first end of the feedback resistor R2, the second end of the feedback resistor R2 is grounded, and the second end of the feedback resistor R1 and the first end of the feedback resistor R2 are commonly connected to the third inverting input terminal of the operational amplifier AMP; The NMOS pass transistor NPASS has a drain connected to an external power supply VCC, a source connected to a first end of the feedback resistor R1, and a source outputting a power supply VDD. The power supply VDD is connected to a first end of a voltage stabilizing capacitor CL, and a second end of the voltage stabilizing capacitor CL is grounded.

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