Memory access dependence prediction method, system and storage medium for a processor

Abstract

The application is suitable for the technical field of processors, and particularly relates to a memory access dependence prediction method and system for a processor and a storage medium. The memory access dependence prediction system comprises a load and store dependence predictor configured to predict whether there is address dependence between a load instruction and a store instruction. The load and store dependence predictor comprises a load instruction reorder buffer, a store instruction reorder buffer, an index generator, a load and store dependence history table, and a store execution record table. The store execution record table is configured to record a store instruction reorder buffer index value and a reorder buffer age value of the store instruction. Compared with the prior art, the address dependence prediction accuracy and efficiency of the load instruction and the store instruction are higher, and the performance of the processor is better.

Description

TECHNICAL FIELD

[0001] The present application is suitable for the field of processor technology, and particularly relates to a memory access dependence prediction method and system for a processor and a storage medium. BACKGROUND

[0002] There are many dependences between different instructions of a program. Dependence refers to that the execution of an instruction depends on the result of another instruction, which can be classified into the following categories:

[0003] (1) Data dependence, which refers to the correlation between the operands of instructions;

[0004] (2) Address dependence, which refers to the correlation between the memory access addresses of instructions accessing memory (load instructions and store instructions);

[0005] (3) Control dependence, which refers to the correlation caused by branch instructions;

[0006] (4) Structural dependence, which refers to the correlation caused by insufficient hardware resources. In modern high-performance processors, the strategy of out-of-order execution and in-order submission is used to "relieve" or "solve" the dependence between instructions to improve the parallelism of instructions while ensuring that the processor can implement precise exceptions.

[0007] Compared with ordinary instructions (such as arithmetic instructions), memory access instructions need to consider address dependence in addition to data dependence. For the inference processing of address dependence, there are three strategies:

[0008] (1) Conservative, that is, when a load instruction load0 performs address dependence checking, if there is a store instruction store0 older than load0 whose memory access address is not ready, it is always considered that there is address dependence between load0 and store0, so load0 will always access memory later than store0.

[0009] (2) Aggressive, that is, when a load instruction load0 performs address dependence checking, if there is a store instruction store0 older than load0 whose memory access address is not ready, it is always considered that there is no address dependence between load0 and store0, and if load0 does not have address dependence with storeX older than load0 at this time, load0 can access memory earlier than store0.

[0010] (3) Predictive: a predictor is established to predict the address dependency between the load instruction and the store instruction. When the load instruction load0 is checking the address dependency, if there is a memory access address of the store instruction store0 older than load0 that is not ready, the prediction result of the predictor is used to determine whether there is an address dependency between the load instruction load0 and the store instruction store0.

[0011] However, in the speculative processing of the address dependency, the conservative strategy has the advantage of simple processing, but when the load instruction and the store instruction actually have no address dependency, unnecessary waiting of the load instruction memory access is increased.

[0012] The advantage of the aggressive strategy is simple processing, but sometimes it is too aggressive, resulting in a misjudgment of the address dependency between the load instruction and the store instruction, so that the load instruction retrieves incorrect data from the memory, and finally a pipeline flush mechanism needs to be started and the instruction fetching and execution are restarted from the load instruction.

[0013] The predictive strategy is a compromise between the conservative strategy and the aggressive strategy, which consumes some hardware resources but provides more accurate address dependency prediction, thereby improving the performance of the processor.

[0014] Therefore, there is an urgent need for a new memory access dependency prediction method, system and storage medium for a processor to solve the above technical problems. SUMMARY

[0015] The present application provides a memory access dependency prediction method, system and storage medium for a processor, aiming to improve the accuracy and efficiency of address dependency prediction of load instructions and store instructions and improve the performance of the processor.

[0016] In a first aspect, the present application provides a memory access dependency prediction system for a processor, the memory access dependency prediction system comprising:

[0017] a load and store dependency predictor configured to predict whether there is an address dependency between the load instruction and the store instruction;

[0018] The load and store dependency predictor comprises a load instruction reorder buffer, a store instruction reorder buffer, an index generator, a load and store dependency history table and a store execution record table.

[0019] The load instruction reorder buffer is configured to store the load instruction.

[0020] The store instruction reorder buffer is configured to store the store instruction.

[0021] The index generator is configured to process a program counter of the load instruction or a program counter of the store instruction to obtain a load table entry index or a store table entry index of the load and store dependency history table, and store the load table entry index into a corresponding table entry of the load instruction reorder buffer or store the store table entry index into a corresponding table entry of the store instruction reorder buffer.

[0022] The load and store dependency history table is configured to record dependency relationships between the load instruction and the store instruction.

[0023] The store execution record table is configured to record a store instruction reorder buffer index value and a reorder buffer age value of the store instruction.

[0024] Preferably, the load and store dependency history table comprises a request arbitrator, a plurality of static storage modules, a plurality of in-line table entry selectors, and a port output selector.

[0025] The request arbitrator is configured to arbitrate read and write requests of the load instruction and the store instruction to the static storage modules according to a preset priority.

[0026] The static storage module is configured to store the store execution record table index value.

[0027] The in-line table entry selector is configured to select a single static storage table entry in the static storage module to send to the port output selector.

[0028] The port output selector is configured to select a final table entry from the received plurality of static storage table entries to output.

[0029] Preferably, the store instruction reorder buffer is further configured to read, according to the store table entry index, an execution record table entry index of the corresponding store execution record table from the load and store dependency history table, and store, according to the execution record table entry index, the store instruction reorder buffer index value and the reorder buffer age value corresponding to the store instruction into the store execution record table.

[0030] Preferably, the load instruction reorder buffer is further configured to read, according to the load table entry index, an execution record table entry index of the corresponding store execution record table from the load and store dependency history table, read, according to the execution record table entry index, the reorder buffer age value and the store instruction reorder buffer index value of the corresponding table entry in the store execution record table, compare the reorder buffer age value with the load instruction to obtain a prediction result, and write the prediction result and the store instruction reorder buffer index value into the corresponding table entry of the load instruction reorder buffer.

[0031] Preferably, when the load instruction and the store instruction are executed out of order, an address dependency check is performed according to the address information of the load instruction to determine whether there is a store instruction prior to the current load instruction in program order that is not ready; if so, the prediction result is used to determine whether the load instruction has an address dependency with the store instruction;

[0032] If the prediction result is that there is a store-after-load flag, the current load instruction is in a dormant state until the store instruction corresponding to the store instruction reordering cache index value wakes up the current load instruction, and the current load instruction reinitiates memory access and performs a write-back operation.

[0033] Preferably, when the load instruction and the store instruction are executed out of order, an address dependency check is performed according to the address information of the store instruction to determine whether the memory access address of the store instruction overlaps with the memory access address of the load instruction; if so, the store instruction reordering cache writes the store instruction reordering cache index value corresponding to the store instruction into the table item corresponding to the load instruction reordering cache of the load instruction, and marks a store-after-load violation;

[0034] When the load instruction performs the address check, if there is a store-after-load violation marked and satisfying the submission condition, the load instruction reordering cache updates the table item of the load and store dependency history record table according to the load table index and the store instruction reordering cache index value.

[0035] Preferably, the memory access dependency prediction system further comprises a performance monitoring module.

[0036] The performance monitoring module is configured to count the total number of predictions and the number of prediction errors of the load and store dependency predictor; when the ratio between the total number of predictions and the number of prediction errors reaches a preset ratio, all table items in the load and store dependency predictor are emptied.

[0037] In a second aspect, the present application further provides a memory access dependency prediction method for a processor, which is based on the memory access dependency prediction system for a processor according to any one of the above embodiments, and the memory access dependency prediction method comprises the following steps:

[0038] S1, the index generator processes the program counter of the store instruction to obtain a store table item index of the load and store dependency history record table, and stores the store table item index into the table item corresponding to the store instruction reordering cache;

[0039] S2, reading a corresponding execution record table entry index of the storage execution record table from the load and storage dependency history record table according to the storage table entry index, and storing a storage instruction reorder buffer index value and a reorder buffer age value of the storage instruction into a corresponding entry of the storage execution record table according to the execution record table entry index;

[0040] S3, the index generator processes a program counter of the load instruction to obtain a load table entry index of the load and storage dependency history record table, and stores the load table entry index into a corresponding entry of the load instruction reorder buffer;

[0041] S4, the load instruction reads a corresponding execution record table entry index from the load and storage dependency history record table according to the load table entry index, reads the reorder buffer age value and the storage instruction reorder buffer index value of a corresponding entry of the storage execution record table according to the execution record table entry index, and obtains a prediction result by comparing the reorder buffer age value with the load instruction;

[0042] S5, when the load instruction and the storage instruction are executed in a reordering manner, address dependency checking is performed according to address information of the load instruction to determine whether there is a storage instruction prior to the load instruction in a program order and not ready; if yes, it is determined whether the load instruction has address dependency with the storage instruction according to the prediction result.

[0043] If the prediction result is a storage-after-load flag, the load instruction is in a sleep state until the storage instruction corresponding to the storage instruction reorder buffer index value wakes up the load instruction, and the load instruction reinitiates memory access and executes a write-back operation.

[0044] In a third aspect, the present application also provides a computer device, comprising a memory, a processor, and a memory access dependency prediction program for the processor stored in the memory and executable on the processor, wherein the processor executes the memory access dependency prediction program to implement the steps of the memory access dependency prediction method for the processor.

[0045] In a fourth aspect, the present application also provides a computer readable storage medium, wherein the computer readable storage medium stores a memory access dependency prediction program for the processor, and the memory access dependency prediction program is executed by the processor to implement the steps of the memory access dependency prediction method for the processor.

[0046] Compared with the prior art, the application stores, records and predicts the load instruction and the store instruction by loading and storing dependency predictor, and when the address dependency check of the load instruction is performed, whether there is address dependency between the load instruction and the store instruction can be determined according to the prediction result of the load and store dependency predictor, so that the address dependency prediction of the memory access instruction is effectively performed, the unnecessary memory access waiting is reduced, and the situation of the store-after-load (LAW) violation is reduced. Meanwhile, the load and store dependency history record table of the application uses the static storage module of the bank instead of the register stack, so that the area of the physical implementation is saved, the read-write port conflict is reduced, and the application to the high-frequency processor is realized. BRIEF DESCRIPTION OF DRAWINGS

[0047] The application will be described in detail below with reference to the accompanying drawings. The above or other aspects of the application will become more apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0048] Figure 1 is a structural schematic diagram of a memory access dependency prediction system for a processor provided by an embodiment of the application;

[0049] Figure 2 is a table entry part field schematic diagram of the load instruction reordering cache of the memory access dependency prediction system for a processor provided by an embodiment of the application;

[0050] Figure 3 is a table entry part field schematic diagram of the store instruction reordering cache of the memory access dependency prediction system for a processor provided by an embodiment of the application;

[0051] Figure 4 is a structural schematic diagram of a load and store dependency history record table of the memory access dependency prediction system for a processor provided by an embodiment of the application;

[0052] Figure 5 is a structural schematic diagram of a static storage module of the memory access dependency prediction system for a processor provided by an embodiment of the application;

[0053] Figure 6 is a table entry part field schematic diagram of the load and store dependency history record table of the memory access dependency prediction system for a processor provided by an embodiment of the application;

[0054] Figure 7 is a structural schematic diagram of a store execution record table of the memory access dependency prediction system for a processor provided by an embodiment of the application;

[0055] Figure 8 is a structural schematic diagram of an index generator of the memory access dependency prediction system for a processor provided by an embodiment of the application;

[0056] Figure 9 is a flow chart of a memory access dependency prediction method for a processor provided by an embodiment of the present application;

[0057] Figure 10 is a structural schematic diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0059] Embodiment One

[0060] Referring to Figure 1 The present application provides a memory access dependency prediction system 100 for a processor, which comprises a load and store dependency predictor 2.

[0061] The load and store dependency predictor 2 is used to predict whether there is an address dependency between the load instruction and the store instruction, and can perform prediction, update and emptying on the load instruction / store instruction.

[0062] The load and store dependency predictor 2 comprises a load instruction reorder buffer 21 (LOB), a store instruction reorder buffer 22 (SOB), an index generator 23, a load-store dependency history table 24 (LSDHT) and a store execution profile table 25 (SPT).

[0063] The load instruction reorder buffer 21 is used to store the load instruction in program order, which adopts a first-in first-out (FIFO) queue, loads the load instruction that has been emitted but not completed, and ensures that the result is submitted in program order to maintain the correctness of memory operation. The related fields in the table entry of the load instruction reorder buffer 21 can refer to Figure 2 which comprises a valid flag, a load table entry index (load and store dependency history table index value), a store instruction reorder buffer index value and a prediction result (store-after-load prediction flag).

[0064] The storage instruction reordering cache 22 is used to store the storage instructions in program order, adopts a first-in first-out queue, manages the emitted storage instructions, tracks their addresses, data and execution status, and guarantees that the storage operations update the memory in program order. The related fields in the table entries of the storage instruction reordering cache 22 can refer to Figure 3 , which include a valid flag bit and a storage table entry index.

[0065] Specifically, the load instruction reordering cache 21 and the storage instruction reordering cache 22 belong to a data load and storage unit (LSU) in actual application, and the load instructions and the storage instructions can be executed out of order by the data load and storage unit. The data load and storage unit further includes a data cache, a page table cache, an interface with an external storage subsystem and the like.

[0066] The load and storage dependency history table 24 is used to record the dependency relationship between the load instructions and the storage instructions, thereby providing a reference for dependency prediction of a current instruction and optimizing the pipeline execution efficiency.

[0067] In the embodiment of the present application, please refer to Figure 4 , Figure 4 Fig. 4 is a structural schematic diagram of a load and storage dependency history table 24 of a memory access dependency prediction system for a processor provided by the embodiment of the present application; the load and storage dependency history table 24 includes a request arbitrator 241, a plurality of static storage modules 242 (SRAM), a plurality of in-line table entry selectors 243 and a port output selector 244.

[0068] The request arbitrator 241 is used to arbitrate the read and write requests of the load instructions and the storage instructions to the static storage modules 242 according to a preset priority. For example, when there are multiple load instructions / storage instructions needing to read and write the static storage modules 242 at the same time, these requests are arbitrated according to a certain priority, so that a static storage module 242 is accessed at most once in the same clock cycle.

[0069] The static storage module 242 is used to store the storage execution record table 25 index value. The table entries of the load and storage dependency history table 24 are stored in 2 b SRAM blocks, each SRAM block has 2 h rows, and each row stores 2 w load and storage dependency history table 24 table entries. Please refer to Figures 5-6 , Figure 5 Fig. 5 is a structural schematic diagram of a static storage module 242 of a memory access dependency prediction system for a processor provided by the embodiment of the present application,Figure 6 is a schematic diagram of a table entry part field of a load and store dependency history table 24 of a memory access dependency prediction system for a processor provided by embodiments of the present application. The table entry content of the load and store dependency history table 24 stored by a single static storage module 242 includes a 1-bit valid bit, an m-bit saturation counter, and an n-bit storage execution record table 25 index value.

[0070] The in-row table entry selector 243 is configured to select a single table entry from the single static storage table in the static storage module 242 to send to the port output selector 244. For example, when a row is read from a certain static storage module 242, a single table entry is selected from the 2 w table entries in the row.

[0071] The port output selector 244 is configured to select a final table entry from the multiple received static storage table entries for output. For example, a final table entry is selected from the single table entries selected by the multiple in-row table entry selectors 243 in the 2 b static storage modules 242.

[0072] The storage execution record table 25 is configured to record a storage instruction reorder buffer index value and a reorder buffer age value of the storage instruction, to assist in processing storage conflicts and ensuring that storage operations are completed in the correct order. Please refer to Figure 7 , Figure 7 is a structural schematic diagram of a storage execution record table 25 of a memory access dependency prediction system for a processor provided by embodiments of the present application, which includes a valid bit, a storage instruction reorder buffer index value, and a reorder buffer age value.

[0073] The index generator 23 is configured to process the program counter of the load instruction or the program counter of the storage instruction to obtain a load table entry index or a storage table entry index of the load and store dependency history table 24, and store the load table entry index into a corresponding table entry of the load instruction reorder buffer 21 or store the storage table entry index into a corresponding table entry of the storage instruction reorder buffer 22, so as to quickly query the dependency history or the related record in the cache. Please refer to Figure 8 , Figure 8Figure 1 is a structural schematic diagram of an index generator 23 of a memory access dependence prediction system for a processor provided by an embodiment of the present application. It generates a load table entry index / storing table entry index of a load and storing dependence history record table 24 by processing (e.g. hash operation) an instruction program counter (PC) of a 32-bit load instruction / storing instruction, wherein b bits are used for a static storing module 242 index, h bits are used for a static storing module 242 inner row index, and w bits are used for a static storing module 242 inner row table entry index. In addition, an execution record table entry index of a storing execution record table 25 of n bits is also generated by the index generator 23.

[0074] In an embodiment of the present application, the storing instruction reordering cache 22 is further configured to read a corresponding execution record table entry index of the storing execution record table 25 from the load and storing dependence history record table 24 according to the storing table entry index, and store the storing instruction reordering cache index value and the reordering cache age value corresponding to the storing instruction into the storing execution record table 25 according to the execution record table entry index.

[0075] In an embodiment of the present application, the storing instruction reordering cache 22 is further configured to read a corresponding execution record table entry index of the storing execution record table 25 from the load and storing dependence history record table 24 according to the storing table entry index, and store the storing instruction reordering cache index value and the reordering cache age value corresponding to the storing instruction into the storing execution record table 25 according to the execution record table entry index.

[0076] In an embodiment of the present application, when the load instruction and the storing instruction are executed out of order, an address dependence check is performed according to address information of the load instruction to determine whether there is a storing instruction prior to the current load instruction in program order that is not ready; if so, it is determined according to the prediction result whether the load instruction has address dependence with the storing instruction.

[0077] If the prediction result is a load-after-store (LAW) flag, the current load instruction is in a sleep state until the storing instruction corresponding to the storing instruction reordering cache index value wakes up the current load instruction, and the current load instruction reinitiates memory access and executes a write-back operation. Thus, pipeline flush caused by LAW violation is avoided.

[0078] In the embodiment of the present application, when the load instruction and the store instruction are executed out of order, address dependency check is performed according to the address information of the store instruction to determine whether the memory access address of the store instruction and the memory access address of the load instruction overlap (address overlap refers to the case that the memory address range involved in two or more memory access operations (such as load instruction / store instruction) partially or totally overlaps): if yes, the store instruction reorder buffer 22 writes the store instruction reorder buffer index value corresponding to the store instruction into the table item corresponding to the load instruction in the load instruction reorder buffer 21, and marks the store-after-load violation.

[0079] When the load instruction performs address check, if there is one satisfying the submission condition and marked with the store-after-load violation, the load instruction reorder buffer 21 updates the table item of the load and store dependency history record table 24 according to the load table item index and the store instruction reorder buffer index value.

[0080] Specifically, in the out-of-order execution process, the store instruction a and the load instruction b are included, the address information of the load instruction b is first sent to the data load and store processing unit (LSU), and when the address dependency check is performed, it is found that the memory access address of the older store instruction a (the program order is earlier) is not ready, and the valid prediction information is not stored in the table item of the load instruction reorder buffer 21 (because the table item index of the load and store dependency history record table 24 is not indexed to the valid table item), so it is speculatively considered that the store instruction a does not have the store-after-load (LAW) violation, and the memory access is continued and the load result is written back.

[0081] When the address of the store instruction a is sent to the data load and store processing unit (LSU) later, it is found that the memory access address of the store instruction a overlaps with the memory access address of the load instruction b, that is, the store-after-load (LAW) violation occurs at this time, and the store instruction a stores the store instruction reorder buffer index value (sob_idx) of itself into the table item of the load and store dependency history record table 24 corresponding to the load instruction b.

[0082] When the load instruction b checks that it meets the commit condition and the storage LAW is violated, the load table index (ld_idx) stored in the table entry of the load and storage dependency history record table 24 is read, and the storage instruction reorder buffer index value (sob_idx) recorded in the table entry of the load instruction reorder buffer 21 is indexed according to the load instruction of the load instruction reorder buffer 21, to obtain the storage table index (st_idx) recorded in the table entry of the load instruction reorder buffer 21. Then, the corresponding two table entries in the load and storage dependency history record table 24 are read in sequence in two continuous ticks according to the load table index (ld_idx) and the storage table index (st_idx) respectively, the corresponding valid update counter values are increased, the valid bits are modified (in another optional way, the valid bits can be always equal to the value of the highest bit of the valid update counter), and the execution record table entry index (spt_idx) of the storage execution record table 25 for updating is generated by using the PC of the load instruction b through the index generator 23, to combine the three into the new table entry values of the load and storage dependency history record table 24. The two new table entry values generated are sequentially stored in the two table entries of the load and storage dependency history record table 24 indexed by the load table index (ld_idx) and the storage table index (st_idx), and the updating process of the load and storage dependency history record table 24 is completed.

[0083] When the storage instruction a is committed from the load instruction reorder buffer 21, the corresponding table entry of the load and storage dependency history record table 24 is read again according to the load table index (ld_idx) stored in the table entry of the load instruction reorder buffer 21, the storage execution record table 25 is indexed according to the execution record table entry index (spt_idx) recorded in the table entry of the load and storage dependency history record table 24, and if the storage instruction reorder buffer index value (sob_idx) and the reorder buffer age value (rob_ptr) of the read table entry of the storage execution record table 25 are respectively equal to the storage instruction reorder buffer index value (sob_idx) and the reorder buffer age value (rob_ptr) of the table entry index of the load instruction reorder buffer 21 of the storage instruction a, the table entry of the storage execution record table 25 is invalidated.

[0084] In the embodiment of the present application, the memory access dependency prediction system 100 further comprises a performance monitoring module 1.

[0085] The performance monitoring module 1 is used to count the total prediction times and the prediction error times (the prediction error refers to that when the storage instruction is renamed, it is found that there is no address dependency when the load instruction address is checked) of the load and storage dependency predictor 2; when the ratio between the total prediction times and the prediction error times reaches a preset ratio, all the table entries in the load and storage dependency predictor 2 are emptied.

[0086] Compared with the prior art, the application stores, records and predicts the load instruction and the store instruction by loading and storing dependency predictors, and when the address dependency check of the load instruction is performed, whether there is address dependency between the load instruction and the store instruction can be determined according to the prediction result of the load and store dependency predictor, so that the address dependency prediction of the memory access instruction is effectively performed, the unnecessary memory access waiting is reduced, and the situation of the store-after-load (LAW) violation is reduced. Meanwhile, the load and store dependency history record table of the application uses the static storage module of the bank instead of the register stack, so that the area of the physical implementation is saved, the read-write port conflict is reduced, and the application to the high-frequency processor is realized.

[0087] Embodiment two

[0088] Please refer to Figure 9 The application provides a memory access dependency prediction method for a processor, which is based on the memory access dependency prediction system 100 for the processor as described in Embodiment one, and comprises the following steps:

[0089] S1, the index generator 23 processes the program counter of the store instruction to obtain the store table item index (st_idx) of the load and store dependency history record table 24, and stores the store table item index (st_idx) into the corresponding table item of the store instruction reorder buffer 22;

[0090] S2, the execution record table item index of the store execution record table 25 is read from the load and store dependency history record table 24 according to the store table item index (st_idx), and the store instruction reorder buffer index value (sob_idx) and the reorder buffer age value (rob_ptr) of the store instruction are stored into the corresponding table item of the store execution record table 25 according to the execution record table item index;

[0091] S3, the index generator 23 processes the program counter of the load instruction to obtain the load table item index (ld_idx) of the load and store dependency history record table 24, and stores the load table item index (ld_idx) into the corresponding table item of the load instruction reorder buffer 21;

[0092] S4, the loading instruction reads a corresponding execution record table item index from the loading and storing dependence history record table 24 according to the loading table item index (ld_idx); reads the reordering buffer age value (rob_ptr) and the storing instruction reordering buffer index value (sob_idx) of a corresponding table item in the storing execution record table 25 according to the execution record table item index; and makes a comparison prediction between the reordering buffer age value (rob_ptr) and the loading instruction, to obtain a prediction result;

[0093] S5, when the loading instruction and the storing instruction are executed in a reordering manner, address dependence checking is performed according to address information of the loading instruction, to determine whether there is a storing instruction prior to the loading instruction in program order and not ready yet; if yes, it is determined whether the loading instruction has address dependence with the storing instruction according to the prediction result;

[0094] If the prediction result is that there is a store-after-load mark, the loading instruction is in a dormant state until the storing instruction reordering buffer index value (sob_idx) corresponds to the storing instruction, which wakes up the loading instruction; and the loading instruction reinitiates memory access and executes a write-back operation.

[0095] In the embodiment of the application, the loading and storing dependence predictor 2 is also updated, and in the reordering execution process, there are a storing instruction a and a loading instruction b; address information of the loading instruction b is first sent to a data loading and storing processing unit (LSU) to perform address dependence checking, and it is found that a memory access address of the storing instruction a older than the loading instruction b (in program order) is not ready, and valid prediction information is not stored in a table item of a loading instruction reordering buffer 21 (because a table item index of a loading and storing dependence history record table 24 is not indexed to a valid table item); therefore, it is presumed that the storing instruction a does not have a store-after-load (LAW) violation, and the memory access and write-back of the loading result are continued.

[0096] When address information of the storing instruction a is sent to the data loading and storing processing unit (LSU) later, it is found that the memory access address of the storing instruction a overlaps with the memory access address of the loading instruction b, that is, a store-after-load (LAW) violation occurs at this time, and the storing instruction a stores a storing instruction reordering buffer index value (sob_idx) of the storing instruction a in a table item of the loading and storing dependence history record table 24 corresponding to the loading instruction b.

[0097] When the load instruction b checks that it meets the commit condition and the store LAW violation, the load table index (ld_idx) stored in the table entry of the load and store dependency history table 24 is read, and the store instruction reorder buffer index value (sob_idx) recorded in the table entry of the load instruction reorder buffer 21 is indexed according to the load instruction of the load instruction reorder buffer 21, to obtain the store table index (st_idx) recorded in the table entry of the load instruction reorder buffer 21. Then, the corresponding two table entries in the load and store dependency history table 24 are read in sequence in two continuous ticks according to the load table index (ld_idx) and the store table index (st_idx) respectively, the corresponding valid update counter values are increased, the valid bits are modified (in another optional way, the valid bits can be always equal to the value of the highest bit of the valid update counter), and the execution record table entry index (spt_idx) of the store execution record table 25 for updating is generated by the index generator 23 using the PC of the load instruction b, to combine the three into the new table entry values of the load and store dependency history table 24. The two new table entry values generated are sequentially stored in the two table entries of the load and store dependency history table 24 indexed by the load table index (ld_idx) and the store table index (st_idx), and the updating process of the load and store dependency history table 24 is completed.

[0098] When the store instruction a is committed from the load instruction reorder buffer 21, the corresponding table entry of the load and store dependency history table 24 is read again using the load table index (ld_idx) stored in the table entry of the load instruction reorder buffer 21, the store execution record table 25 is indexed according to the execution record table entry index (spt_idx) recorded in the table entry of the load and store dependency history table 24, and if the store instruction reorder buffer index value (sob_idx) and the reorder buffer age value (rob_ptr) of the read table entry of the store execution record table 25 are respectively equal to the store instruction reorder buffer index value (sob_idx) and the reorder buffer age value (rob_ptr) of the table entry index of the load instruction reorder buffer 21 of the store instruction a, the table entry of the store execution record table 25 is invalidated.

[0099] In the embodiment of the present application, the total prediction number and the prediction error number (the prediction error refers to the address dependency found to be non-existent when the load instruction address is checked during the store instruction renaming) of the load and store dependency predictor 2 are counted, and when the ratio between the total prediction number and the prediction error number reaches a preset ratio, all the table entries in the load and store dependency predictor 2 are emptied.

[0100] The memory access dependence prediction method for a processor is based on the memory access dependence prediction system 100 for a processor in the above embodiment, and can achieve the same technical effects. For details, refer to the description in the above embodiment, which will not be repeated here.

[0101] Embodiment three

[0102] The embodiment of the present application further provides a computer device, which refers to Figure 10 , Figure 10 is a structural schematic diagram of the computer device provided by the embodiment of the present application. The computer device 300 comprises a memory 302, a processor 301 and a memory access dependence prediction program for a processor stored in the memory 302 and capable of running on the processor 301.

[0103] The processor 301 invokes the memory access dependence prediction program for a processor stored in the memory 302 to execute the steps in the memory access dependence prediction method for a processor provided by the embodiment of the present application. For details, refer to Figure 9 , which specifically comprises the following steps:

[0104] S1, the index generator 23 processes the program counter of a storage instruction to obtain a storage table entry index (st_idx) of the load and storage dependence history record table 24, and stores the storage table entry index (st_idx) into the corresponding table entry of the storage instruction reorder buffer 22;

[0105] S2, the storage table entry index (st_idx) is used to read the corresponding execution record table entry index of the storage execution record table 25 from the load and storage dependence history record table 24, and the storage instruction reorder buffer index value (sob_idx) and the reorder buffer age value (rob_ptr) of the storage instruction are stored into the corresponding table entry of the storage execution record table 25 according to the execution record table entry index;

[0106] S3, the index generator 23 processes the program counter of a load instruction to obtain a load table entry index (ld_idx) of the load and storage dependence history record table 24, and stores the load table entry index (ld_idx) into the corresponding table entry of the load instruction reorder buffer 21;

[0107] S4, the loading instruction reads a corresponding execution record table item index from the loading and storing dependence history record table 24 according to the loading table item index (ld_idx); reads the reordering buffer age value (rob_ptr) and the storing instruction reordering buffer index value (sob_idx) of a corresponding table item in the storing execution record table 25 according to the execution record table item index; and makes a comparison prediction between the reordering buffer age value (rob_ptr) and the loading instruction, to obtain a prediction result;

[0108] S5, when the loading instruction and the storing instruction are executed in a reordering manner, address dependence checking is performed according to address information of the loading instruction, to determine whether there is a storing instruction prior to the loading instruction in program order and not ready; if yes, it is determined whether the loading instruction has address dependence with the storing instruction according to the prediction result;

[0109] If the prediction result is that there is a storing-after-loading mark, the loading instruction is in a dormant state until the storing instruction reordering buffer index value (sob_idx) corresponds to the storing instruction, which wakes up the loading instruction; and the loading instruction reinitiates memory access and executes a write-back operation.

[0110] In the embodiment of the application, the loading and storing dependence predictor 2 is also updated, and in the reordering execution process, there are a storing instruction a and a loading instruction b; address information of the loading instruction b is first sent to a data loading and storing processing unit (LSU) to perform address dependence checking, and it is found that a memory access address of the storing instruction a older than the loading instruction b (in program order) is not ready, and valid prediction information is not stored in a table item of a loading instruction reordering buffer 21 (because a table item index of a loading and storing dependence history record table 24 is not indexed to a valid table item); therefore, it is presumed that the storing instruction a does not have a storing-after-loading (LAW) violation, and the memory access and write-back of the loading result are continued.

[0111] When address information of the storing instruction a is sent to the data loading and storing processing unit (LSU) later, it is found that the memory access address of the storing instruction a overlaps with the memory access address of the loading instruction b, that is, a storing-after-loading (LAW) violation occurs at this time; and the storing instruction a stores a storing instruction reordering buffer index value (sob_idx) of the storing instruction a in a table item of the loading and storing dependence history record table 24 corresponding to the loading instruction b.

[0112] When the load instruction b checks that it meets the commit condition and a storage LAW violation occurs, the load table item index (ld_idx) stored in the table item of the load and storage dependency history record table 24 is read, and the storage instruction reorder buffer index value (sob_idx) recorded in the table item of the load instruction reorder buffer 21 is indexed according to the load instruction of the load instruction reorder buffer 21, to obtain the storage table item index (st_idx) recorded in the table item of the load instruction reorder buffer 21. Then, the corresponding two table items in the load and storage dependency history record table 24 are read in sequence in two continuous ticks according to the load table item index (ld_idx) and the storage table item index (st_idx) respectively, the corresponding valid update counter value is increased, the valid bit is modified (in another optional way, it can be made to always equal to the value of the highest bit of the valid update counter), and the execution record table item index (spt_idx) of the storage execution record table 25 for updating is generated by the index generator 23 using the PC of the load instruction b, to combine the three into the new table item value of the load and storage dependency history record table 24. The two new table item values generated are sequentially stored in the two table items of the load and storage dependency history record table 24 indexed by the load table item index (ld_idx) and the storage table item index (st_idx), and the updating process of the load and storage dependency history record table 24 is completed.

[0113] When the storage instruction a is committed from the load instruction reorder buffer 21, the corresponding table item of the load and storage dependency history record table 24 is read again using the load table item index (ld_idx) stored in the table item of the load instruction reorder buffer 21, the storage execution record table 25 is indexed according to the execution record table item index (spt_idx) recorded in the table item of the load and storage dependency history record table 24, and if the storage instruction reorder buffer index value (sob_idx) and the reorder buffer age value (rob_ptr) of the table item of the storage execution record table 25 read are respectively equal to the storage instruction reorder buffer index value (sob_idx) and the reorder buffer age value (rob_ptr) of the table item index of the load instruction reorder buffer 21 of the storage instruction a, the table item of the storage execution record table 25 is invalidated.

[0114] In the embodiment of the present application, the total prediction number and the prediction error number (the prediction error refers to the case that when the load instruction address is checked, it is found that there is no address dependency) of the load and storage dependency predictor 2 are counted, and when the ratio between the total prediction number and the prediction error number reaches a preset ratio, all the table items in the load and storage dependency predictor 2 are emptied.

[0115] The computer device 300 provided by the embodiment of the present application can realize the steps in the memory access dependence prediction method for a processor in the above embodiment, and can realize the same technical effects. Details are described in the above embodiment, and will not be described here again.

[0116] Embodiment four

[0117] The embodiment of the present application also provides a computer readable storage medium, which stores a memory access dependence prediction program for a processor. The memory access dependence prediction program for a processor, when executed by the processor, realizes each process and step in the memory access dependence prediction method for a processor provided by the embodiment of the present application, and can realize the same technical effects. To avoid repetition, details will not be described here again.

[0118] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The program can be stored in a computer readable storage medium. When the program is executed, the processes of the above-mentioned embodiment methods can be included. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM) or a random access memory (RAM).

[0119] It should be noted that in this document, the term "comprising" or "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0120] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be realized by means of software and necessary general hardware platforms. Of course, they can also be realized by hardware, but in many cases, the former is a better embodiment. Based on this understanding, the technical solutions of the present application or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disc, optical disc), and includes a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, air conditioner or network device) execute the method described in each embodiment of the present application.

[0121] The embodiments of the present application are described above with reference to the accompanying drawings, and the disclosed are only the preferred embodiments of the present application, but the present application is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, but not restrictive, and the ordinary skilled in the art can make many equivalent changes without departing from the spirit of the present application and the scope of protection of the claims, and all the equivalent changes are within the protection scope of the present application.

Claims

1. A memory access dependence prediction system for a processor, the system comprising: The memory access dependency prediction system comprises: a load and store dependency predictor configured to predict whether there is an address dependency between a load instruction and a store instruction; the load and store dependency predictor comprises a load instruction reorder buffer, a store instruction reorder buffer, an index generator, a load and store dependency history table, and a store execution record table; the load instruction reorder buffer is configured to store the load instruction; the store instruction reorder buffer is configured to store the store instruction; the index generator is configured to process a program counter of the load instruction or a program counter of the store instruction to obtain a load entry index or a store entry index of the load and store dependency history table, and store the load entry index into a corresponding entry of the load instruction reorder buffer or store the store entry index into a corresponding entry of the store instruction reorder buffer; the load and store dependency history table is configured to record a dependency relationship between the load instruction and the store instruction; the store execution record table is configured to record a store instruction reorder buffer index value and a reorder buffer age value of the store instruction.

2. The memory access dependence prediction system for a processor of claim 1, wherein, the load and store dependency history table comprises a request arbitrator, a plurality of static storage modules, a plurality of in-line entry selectors, and a port output selector; the request arbitrator is configured to arbitrate read and write requests of the load instruction and the store instruction to the static storage modules according to a preset priority; the static storage module is configured to store the store execution record table index value; the in-line entry selector is configured to select a single static storage entry from the static storage module and send the single static storage entry to the port output selector; the port output selector is configured to select a final entry from a plurality of received static storage entries and output the final entry.

3. The memory access dependence prediction system for a processor of claim 1, wherein, the store instruction reorder buffer is further configured to read an execution record entry index of the store execution record table corresponding to the store entry index from the load and store dependency history table, and store a store instruction reorder buffer index value and a reorder buffer age value corresponding to the store instruction into the store execution record table according to the execution record entry index.

4. The memory access dependence prediction system for a processor of claim 3, wherein, the load instruction reorder buffer is further configured to read an execution record entry index of the store execution record table corresponding to the load entry index from the load and store dependency history table, and read a reorder buffer age value and a store instruction reorder buffer index value of a corresponding entry in the store execution record table according to the execution record entry index; the reorder buffer age value is compared with the load instruction to obtain a prediction result, and the prediction result and the store instruction reorder buffer index value are written into a corresponding entry of the load instruction reorder buffer.

5. The memory access dependence prediction system for a processor of claim 4, wherein, When the load instruction and the store instruction are executed out of order, address dependency checking is performed according to address information of the load instruction to determine whether there is a store instruction prior to the current load instruction in program order that is not ready; if so, it is determined according to the prediction result whether the load instruction has address dependency with the store instruction; If the prediction result is that there is a store-after-load flag, the current load instruction is in a dormant state until the store instruction corresponding to the store instruction reordering cache index value wakes up the current load instruction, and the current load instruction reinitiates memory access and performs a write-back operation.

6. The memory access dependence prediction system for a processor of claim 4, wherein, When the load instruction and the store instruction are executed out of order, address dependency checking is performed according to address information of the load instruction to determine whether there is a store instruction prior to the current load instruction in program order that is not ready; if so, it is determined according to the prediction result whether the load instruction has address dependency with the store instruction; When the load instruction performs address checking, if there is a store-after-load violation flag and it meets the submission condition, the load instruction reordering cache updates the table entry of the load and store dependency history record table according to the load table index and the store instruction reordering cache index value.

7. The memory access dependence prediction system for a processor of claim 1, wherein, The memory access dependency prediction system further comprises a performance monitoring module. The performance monitoring module is configured to count the total number of predictions and the number of prediction errors of the load and store dependency predictor; when the ratio between the total number of predictions and the number of prediction errors reaches a preset ratio, all table entries in the load and store dependency predictor are emptied.

8. A method for memory access dependence prediction for a processor, the method comprising: The memory access dependency prediction method is based on the memory access dependency prediction system for a processor according to claims 1-7, and the memory access dependency prediction method comprises the following steps: S1, the index generator processes the program counter of the store instruction to obtain the store table entry index of the load and store dependency history record table; and stores the store table entry index into the table entry corresponding to the store instruction reordering cache; S2, the execution record table entry index of the corresponding store execution record table is read from the load and store dependency history record table according to the store table entry index, and the store instruction reordering cache index value and the reordering cache age value of the store instruction are stored into the table entry corresponding to the store execution record table according to the execution record table entry index; S3, the index generator processes the program counter of the load instruction to obtain the load table entry index of the load and store dependency history record table; and stores the load table entry index into the table entry corresponding to the load instruction reordering cache; S3, the index generator processes the program counter of the load instruction to obtain the load table entry index of the load and store dependency history record table; and stores the load table entry index into the table entry corresponding to the load instruction reordering cache; S4, the loading instruction reads a corresponding execution record table item index from the loading and storage dependency history record table according to the loading table item index; reads the reordering cache age value and the storage instruction reordering cache index value of a corresponding table item in the storage execution record table according to the execution record table item index; and compares the reordering cache age value with the loading instruction to obtain a prediction result; S5, when the loading instruction and the storage instruction are executed in a reordering manner, address dependency checking is performed according to address information of the loading instruction to determine whether there is a storage instruction prior to the loading instruction in a program sequence and not ready: if yes, it is determined whether the loading instruction has address dependency with the storage instruction according to the prediction result; If the prediction result is that there is a store-after-load mark, the loading instruction is in a dormant state until the storage instruction corresponding to the storage instruction reordering cache index value wakes up the loading instruction, and the loading instruction reinitiates memory access and executes a write-back operation.

9. A computer device, comprising: Comprise: a memory, a processor, and a memory access dependency prediction program for a processor stored on the memory and executable on the processor, wherein the processor executes the memory access dependency prediction program to implement the steps of the memory access dependency prediction method for a processor as claimed in claim 8.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a memory access dependency prediction program for a processor, and the memory access dependency prediction program for a processor is executed by a processor to implement the steps of the memory access dependency prediction method for a processor as claimed in claim 8.

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