Test clock control-based QCA fault detection circuit and detection method

Abstract

The invention discloses a QCA fault detection circuit and detection method based on test clock control, and belongs to the technical field of quantum cellular automaton circuit detection. According to the invention, the arrangement of the programmable clock generation circuit layer, the metal sheet layer, the five clock signal lines, the five clock metal lines and the clock signal source is equivalent to the introduction of a test clock to the to-be-tested QCA circuit, and the test clock can send a test clock signal to a to-be-tested area in the to-be-tested QCA circuit when the to-be-tested QCA circuit is detected. According to the method and the device, fixed faults in the to-be-tested QCA circuit can be effectively detected, non-fixed faults in the to-be-tested QCA circuit can be effectively detected, and the detection success rate is relatively high from the aspect of the test effect.

Description

Technical Field

[0001] The present invention belongs to the technical field of quantum cellular automaton circuit detection, and in particular relates to a QCA fault detection circuit and a detection method based on test clock control. Background Art

[0002] As CMOS circuit technology approaches its physical limits, issues such as short-channel effects, high leakage currents, and high lithography costs severely constrain its further development. Against this backdrop, researchers are increasingly focusing on a new nanoscale device: quantum cellular automata (QCAs). These devices offer advantages such as ultra-low power consumption, high integration, and terahertz-level computing speeds.

[0003] Quantum cellular automaton (QCA) circuits differ fundamentally from traditional CMOS circuits in their information transmission mechanisms: CMOS circuits rely on carrier transport to implement logical operations, while QCA circuits encode information through the polarization states of quantum cells. This fundamental difference in physical implementation makes existing traditional CMOS circuit testing methods (such as IDDQ testing) difficult to directly apply to QCA circuit testing. However, stuck-at-fault modes exhibit significant testing value in both types of circuits (QCA and traditional CMOS). For QCA circuits, abnormal locking of the cell polarization state also meets the basic characteristics of a stuck-at-fault mode. However, the unique quantum properties of QCA circuits place new demands on fault detection in QCA circuits. Specifically, the four-phase clock signal control mechanism in QCA circuits can introduce non-stuck-at-fault modes such as clock failures. Therefore, this application designs a QCA fault detection circuit and method based on test clock control. Summary of the Invention

[0004] In view of the above-mentioned defects and deficiencies in the prior art, the present application proposes a QCA fault detection circuit and detection method based on test clock control.

[0005] In order to achieve the above-mentioned object, the present invention adopts the following technical solutions: A QCA fault detection circuit based on test clock control is disclosed. The QCA fault detection circuit based on test clock control described in this application is used to detect an existing QCA circuit constructed based on a clock scheme with an arbitrary square clock region. In this application, the existing QCA circuit constructed based on a clock scheme with an arbitrary square clock region is referred to as a QCA circuit to be tested. The QCA fault detection circuit based on test clock control is improved based on an existing nanometer quantum cellular automaton circuit with a programmable clock. The improvement of the QCA fault detection circuit based on test clock control over the existing nanometer quantum cellular automaton circuit with a programmable clock is as follows: (1) The present application sets the position of the QCA circuit to be tested to be the same as the position of the quantum cellular automaton in the existing nano-quantum cellular automaton circuit with a programmable clock, that is, the QCA circuit to be tested is also located between the programmable clock generation circuit layer and the metal sheet layer; (2) The QCA fault detection circuit based on test clock control described in the present application includes a polarization signal line, and the polarization signal line in the present application replaces the special clock signal line in the existing nano-quantum cellular automaton circuit with a programmable clock; in the present application, the setting of the programmable clock generation circuit layer, the metal sheet layer, the five clock signal lines, the five clock metal lines and the clock signal source is equivalent to introducing a test clock to the QCA circuit to be tested, and the above-mentioned test clock can send a test clock signal to the area to be tested in the QCA circuit to be tested when the QCA circuit to be tested is tested, and the test clock signal is a polarization clock signal.

[0006] A QCA fault detection method based on test clock control is implemented using a QCA fault detection circuit based on test clock control. The QCA fault detection method based on test clock control includes the following steps: S1. Divide the QCA circuit to be tested into n logic functions with three input variables. Based on an existing clock scheme based on arbitrary square clock regions and n logic functions, construct n corresponding simulated QCA circuits, where n is greater than or equal to 1. Then, construct a normal circuit truth table, a faulty circuit truth table, and an SSF fault list based on the simulated QCA circuits. Obtain test vectors based on the normal circuit truth table, the faulty circuit truth table, and the SSF fault list. S2. Performing fault detection on the QCA circuit to be tested using the QCA fault detection circuit based on test clock control, the fault truth table, and the SSF fault list, including the following steps: S2-1, dividing the QCA circuit to be tested into regions corresponding to n logic functions with three input variables; S2-2. Determine whether a sensitization path needs to be designed. For an area including the output end of the QCA circuit to be tested, no sensitization path needs to be designed. For an area not including the output end of the QCA circuit to be tested, a sensitization path needs to be designed. S2-3. Starting from the output end of the QCA circuit to be tested, a reverse test method is used for each divided area.

[0007] Preferably, in step S1, constructing truth tables for all fault-free circuits includes the following steps: dividing the QCA circuit to be tested into n regions represented by three-input variable logic functions, constructing n corresponding analog QCA circuits according to an existing clock scheme based on arbitrary square clock regions and the n three-input variable logic functions, where n is greater than or equal to 1, and constructing corresponding fault-free circuit truth tables for all analog QCA circuits; Preferably, in step S1, constructing truth tables for all fault circuits includes the following steps: injecting all possible single stuck-at fault SSF models in all simulated QCA circuits into all simulated QCA circuits to obtain all faulty simulated QCA circuits; then, simulating all faulty simulated QCA circuits using the simulation tool QCADesigner with 2ⁿ binary input combinations to obtain steady-state output responses for all binary input combinations corresponding to all faulty simulated QCA circuits; and constructing fault circuit truth tables based on simulated waveforms of the steady-state output responses. Preferably, in step S1, constructing a list of all SSF faults includes the following steps: all SSF fault lists are obtained in the same manner, and taking one of the SSF fault list obtaining methods as an example, the following steps are included: an SSF fault column is listed in a table, and the SSF fault column lists all possible single stuck-at faults SSF in a simulated QCA circuit, wherein a single stuck-at fault includes a fault that is stuck at 1 (sa1) and a fault that is stuck at 0 (sa0) at each node; by analyzing the equivalence of single stuck-at faults in the circuit, single stuck-at faults with the same output impact are grouped into equivalent fault classes, thereby eliminating redundant faults; then, all faults included in each equivalent fault class are completely recorded in the SSF fault column in the form of a single row, completing the construction of the SSF fault list and obtaining the SSF fault list; Preferably, in step S1, obtaining a test vector includes the following steps: for one single fixed-type fault SSF mode in each equivalent fault class in an SSF fault list, comparing the fault-free circuit truth table and the faulty circuit truth table, finding all binary input combinations corresponding to the above-mentioned single fixed-type fault SSF mode and capable of causing the fault-free simulation QCA circuit and the faulty simulation QCA circuit to output different values ​​as test vectors; for all single fixed-type fault SSF modes in the SSF fault list that do not belong to all equivalent fault classes, by comparing the fault-free circuit truth table and the faulty circuit truth table, finding all binary input combinations corresponding to the above-mentioned single fixed-type fault SSF mode and capable of causing the fault-free simulation QCA circuit and the faulty simulation QCA circuit to output different values ​​as test vectors; recording all test vectors in the SSF fault list in the form of a test vector column, and the test vectors in the test vector column correspond to the single fixed-type fault SSF mode in the SSF fault column; the fault-free truth table, the faulty truth table and the SSF fault list constitute a database.

[0008] Preferably, in step S2, the method for designing a sensitization path comprises the following steps: A path that passes through a tested and fault-free area is preferentially selected as the sensitized path, and the non-sensitized inputs of the majority gate in the tested and fault-free area are fixed to 0 and 1 respectively. This ensures that the fault effect of the tested area can be propagated along the sensitized path to the output end of the QCA circuit under test for output. When no path that passes through the tested, fault-free region exists as a sensitizing path, only a path passing through the tested, faulty region can be selected as the sensitizing path. In this case, a list of SSF faults associated with the three-input logic function corresponding to the tested, faulty region is found in the database. A complement set is obtained based on the fault location, the logic value of the stuck-at fault introduced by the test clock in the tested, faulty region, and the corresponding test vector in the SSF fault list. Then, the vectors in the complement set are observed, and two logic values ​​of a specific vector are selected as the two inputs to the region under test, excluding the sensitizing path input. Let this specific vector be vector M. Vector M must satisfy the condition that two logic values ​​in vector M are consistent with two logic values ​​of corresponding positions in another vector in the complement set. This ensures that the output value of the sensitizing path (the path passing through the tested, faulty region), whether 0 or 1, does not activate the fault in the tested, faulty region, thereby ensuring that the fault effect in the tested region can propagate along the sensitizing path to the output of the QCA circuit under test.

[0009] Preferably, in step S2-3, when any area is tested, the above detection process is performed twice, and the positions of the stuck-at fault introduced by the test clock in the two detection processes are different.

[0010] Preferably, in step S2-3, when the output results of the output terminal of the QCA circuit to be tested are consistent with the output results of the simulated QCA circuit corresponding to the logic function in the fault truth table corresponding to the fault injection location during the two detection processes, it indicates that there is no fault in the area; In step S2-3, during the two detection processes, the output result of the output terminal of the QCA circuit to be tested is inconsistent with the output result of the analog QCA circuit corresponding to the logic function in the fault truth table corresponding to the fault injection position, which indicates that there is a fault in the area. Then, the detection process of the above area is repeated until the output result of the output terminal cout of the QCA circuit to be tested is consistent with the output result of the analog QCA circuit corresponding to the logic function in the fault truth table result corresponding to the fault injection position, and the location of the fault can be obtained; among which, in the repeated detection process of area 1, only the location of the fixed-type fault introduced by the test clock is changed.

[0011] Compared with the prior art, the present invention has the following beneficial effects: The present application can effectively detect both fixed-type faults and non-fixed-type faults in the QCA circuit to be tested. Moreover, from the perspective of test results, the detection success rate is relatively good. Specifically, the test shows that: the fault detection success rate obtained by test group 1 (testing all QCA circuits based on the existing USE clock scheme that contain one fixed-type fault and one clock fault, and the fixed-type fault and the clock fault occur in different regions) reached 98%, the fault detection success rate obtained by test group 2 (testing all QCA circuits based on the existing USE clock scheme that contain two fixed-type faults and the two fixed-type faults occur in different regions) reached 100%, and the fault detection success rate obtained by test group 3 (testing all QCA circuits based on the existing USE clock scheme that contain one fixed-type fault and one QCA device manufacturing defect, and the fixed-type fault and the QCA device manufacturing defect occur in different regions) reached 100%. The fault detection success rate achieved in test group one (testing all QCA circuits built based on the existing USE clock scheme with two clock faults occurring in different regions) reached 96%. The fault detection success rate achieved in test group four (testing all QCA circuits built based on the existing USE clock scheme with two clock faults occurring in different regions) reached 96%. The fault detection success rate achieved in test group five (testing all QCA circuits built based on the existing USE clock scheme with one clock fault and one QCA device manufacturing defect occurring in different regions) reached 94%. The fault detection success rate achieved in test group six (testing all QCA circuits built based on the existing USE clock scheme with two QCA device manufacturing defects occurring in different regions) reached 92%. The average fault detection success rate for all test groups (i.e., test groups one to six) reached 96%. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is the circuit diagram corresponding to the three-input variable logic function F=A+ B·C; Figure 2 The analog QCA circuit corresponding to the three-input variable logic function F=A+B·C constructed for the existing USE clock scheme; Figure 3 To simulate the steady-state output response of all binary input combinations obtained by simulating the QCA circuit using the QCADesigner simulation platform, and to obtain simulation waveforms based on the steady-state output response; Figure 4 The truth table of the fault-free circuit includes test vectors represented by binary input combinations and simulated QCA circuit output results represented by steady-state output responses corresponding to the binary input combinations; Figure 5It is the SSF fault list; Figure 6 A QCA circuit of one of the test cases in test group 1, which is also the QCA circuit to be tested described in the embodiment; Figure 7 The fault locations detected in area 4 and area 1 of the QCA circuit to be tested in this embodiment; Figure 8 This is the QCA circuit of one of the test cases in test group 2; Figure 9 This is the QCA circuit for one of the test cases in test group three; Figure 10 This is the QCA circuit for one of the test cases in test group 4; Figure 11 This is the QCA circuit for one of the test cases in test group five; Figure 12 This is the QCA circuit of one of the test cases in test group six. DETAILED DESCRIPTION

[0013] Example 1: A QCA fault detection circuit based on test clock control is disclosed herein. The QCA fault detection circuit based on test clock control is used to detect an existing QCA circuit constructed based on a clock scheme with arbitrary square clock regions. In this embodiment, the existing QCA circuit constructed based on a clock scheme with arbitrary square clock regions adopts an existing QCA circuit constructed based on an existing USE clock scheme. In this application, the existing QCA circuit constructed based on a clock scheme with arbitrary square clock regions is referred to as the QCA circuit to be tested. The existing USE clock scheme is consistent with the technical content disclosed in Section IV. PROPOSED CLOCKING SCHEME of the paper "USE: A Universal, Scalable and Efficient Clocking Scheme for QCA." The QCA fault detection circuit based on test clock control described in this application is improved based on the existing nanometer quantum cellular automaton circuit with a programmable clock. The improvement of the QCA fault detection circuit based on test clock control over the existing nanometer quantum cellular automaton circuit with a programmable clock is that: (1) The position of the QCA circuit to be tested is set to be the same as the position of the quantum cellular automaton in the existing nano-quantum cellular automaton circuit with a programmable clock, that is, the QCA circuit to be tested is also located between the programmable clock generation circuit layer and the metal sheet layer; in this application, the existing nano-quantum cellular automaton circuit with a programmable clock is the nano-quantum cellular automaton circuit with a programmable clock disclosed in CN 119167856 A; (2) The QCA fault detection circuit based on test clock control described in this application includes a polarization signal line, and the polarization signal line in this application replaces the special clock signal line in the existing nano-quantum cellular automaton circuit with a programmable clock; The QCA fault detection circuit based on test clock control in the present application also includes five clock signal lines and five clock metal lines. The five clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line and a polarization signal line. The five clock metal lines include a first clock metal line, a second clock metal line, a third clock metal line, a fourth clock metal line and a polarization clock metal line; all first clock signal lines are connected to the first clock metal line, all second clock signal lines are connected to the second clock metal line, all third clock signal lines are connected to the third clock metal line, all fourth clock signal lines are connected to the fourth clock metal line, all polarization clock signal lines are connected to the polarization clock metal line, and the five clock metal lines are all connected to the clock signal source. In this application, the first clock metal line is connected to the clock signal source for transmitting the first clock signal, the second clock metal line is connected to the clock signal source for transmitting the second clock signal, the third clock metal line is connected to the clock signal source for transmitting the third clock signal, the fourth clock metal line is connected to the clock signal source for transmitting the fourth clock signal, and the polarized clock metal line is connected to the clock signal source for transmitting the polarized clock signal, which is the test clock signal.

[0014] In the present application, the arrangement of the programmable clock generation circuit layer, the metal sheet layer, the five clock signal lines, the five clock metal lines, and the clock signal source is equivalent to introducing a test clock into the QCA circuit to be tested. The above-mentioned test clock (i.e., the arrangement of the programmable clock generation circuit layer, the metal sheet layer, the five clock signal lines, the five clock metal lines, and the clock signal source in the present application) can send a test clock signal (i.e., a polarized clock signal) to the area to be tested in the QCA circuit to be tested when the QCA circuit to be tested is tested. The method of generating the test clock signal in the present application is the same as that in CN 119167856. The polarization clock signal generation method disclosed in A is consistent. The test clock signal uses a clock signal with a long Hold phase to lock the electrons in the cell in a fixed position for a long time, so that the polarization state of the cell is fixed to 1 or 0, and will not affect the cells in other areas outside the test area in the QCA circuit to be tested, so as to facilitate fault detection in the test area; that is, the present application controls the local electric field between the metal plate and the upper metal sheet layer through the setting of a clock signal source, five clock signal lines, five clock metal lines and a programmable clock generation circuit layer to ensure that for the test of the QCA circuit to be tested, the test clock signal (i.e., the polarization clock signal) only acts on the test area, while the cells in other areas of the QCA circuit to be tested except the test area are still driven by the conventional clock signal (i.e., the first clock signal, the second clock signal, the third clock signal and the fourth clock signal), thereby realizing fault detection of the test area in the QCA circuit to be tested.

[0015] A QCA fault detection method based on test clock control includes the following steps: S1. Divide the QCA circuit to be tested into n logic functions with three input variables. Based on the existing clock scheme based on arbitrary square clock regions and n logic functions, construct n corresponding analog QCA circuits, where n is greater than or equal to 1. In this embodiment, the existing clock scheme based on arbitrary square clock regions adopts the existing USE clock scheme. Then, based on the analog QCA circuits, construct a normal circuit truth table, a faulty circuit truth table, and an SSF fault list. Then, obtain test vectors based on the normal circuit truth table, the faulty circuit truth table, and the SSF fault list. In step S1, constructing all fault-free circuit truth tables includes the following steps: dividing the QCA circuit to be tested into n regions represented by three-input variable logic functions, constructing n corresponding analog QCA circuits according to the existing USE clock scheme and n three-input variable logic functions, where n is greater than or equal to 1, and constructing corresponding fault-free circuit truth tables for all analog QCA circuits; in this embodiment, Figure 6Taking the QCA circuit to be tested as an example, in this embodiment, the QCA circuit to be tested is divided into four regions represented by three-input variable logic functions. The four three-input variable logic functions are F=A+B·C, F=(A+B)·C, F=(A·B + A·C + B·C)' with C=0, and F=(A+B)·C'. Take the three-input variable logic function F=A+ B·C ( Figure 1 Taking the logic function shown in the figure as an example, an analog QCA circuit with three input variables is constructed according to the existing USE clock scheme, as shown in Figure 2 As shown, the analog QCA circuit is a fault-free analog QCA circuit; then, 2 3 Binary input combinations (2 3 The above analog QCA circuit is simulated using the QCADesigner simulation platform to obtain the steady-state output responses of all binary input combinations, and the simulation waveform is obtained based on the steady-state output response. The simulation waveform is as follows: Figure 3 As shown in FIG, a fault-free circuit truth table is established based on the simulation waveform. The fault-free circuit truth table includes the test vectors represented by the binary input combination and the simulated QCA circuit output results represented by the steady-state output responses corresponding to the binary input combination, as shown in FIG. Figure 4 As shown, Figure 4 Where input represents the test vector represented by the binary input combination, and output represents the output result of the simulated QCA circuit represented by the steady-state output response corresponding to the binary input combination; In step S1, constructing truth tables for all fault circuits includes the following steps: injecting all possible single stuck-at fault SSF models into all simulated QCA circuits to obtain all faulty simulated QCA circuits; then, using the simulation tool QCADesigner to simulate all faulty simulated QCA circuits with 2ⁿ binary input combinations to obtain steady-state output responses for all binary input combinations corresponding to all faulty simulated QCA circuits; and constructing fault circuit truth tables based on the simulated waveforms of the steady-state output responses. In step S1, a list of all SSF faults is constructed, including the following steps: All SSF fault lists are obtained in the same manner. Taking one of the SSF fault list acquisition methods as an example, the following steps are included: an SSF fault column is listed in a table, and the SSF fault column lists all possible single stuck-at faults (SSFs) in a simulated QCA circuit. Single stuck-at faults include faults that are stuck at 1 (sa1) and faults that are stuck at 0 (sa0) at each node. By analyzing the equivalence of single stuck-at faults in the circuit, single stuck-at faults with the same output impact are grouped into equivalent fault classes, thereby eliminating redundant faults. Then, all faults contained in each equivalent fault class are completely recorded in the SSF fault column in the form of a single row, completing the construction of the SSF fault list and obtaining the SSF fault list. In step S1, all test vectors are obtained, including the following steps: including the following steps: for one single fixed fault SSF mode in each equivalent fault class in an SSF fault list, compare the fault-free circuit truth table and the faulty circuit truth table, and find all binary input combinations corresponding to the above single fixed fault SSF mode and that can make the fault-free simulation QCA circuit and the faulty simulation QCA circuit output different as test vectors; for all single fixed fault SSF modes in the SSF fault list that do not belong to all equivalent fault classes, by comparing the fault-free circuit truth table and the faulty circuit truth table, find all binary input combinations corresponding to the above single fixed fault SSF mode and that can make the fault-free simulation QCA circuit and the faulty simulation QCA circuit output different as test vectors; record all test vectors in the SSF fault list in the form of a test vector column, and the test vectors in the test vector column correspond to the single fixed fault SSF mode in the SSF fault column, the SSF fault list is as follows: Figure 5 As shown; the no-fault truth table, the fault truth table and the SSF fault list constitute the database.

[0016] S2. Perform fault detection on the QCA circuit to be tested using the QCA fault detection circuit controlled by the test clock, the fault truth table, and the SSF fault list. This specifically includes the following steps: S2-1, dividing the QCA circuit to be tested into regions corresponding to n logic functions with three input variables; In this embodiment, the QCA circuit to be tested is divided into four regions, namely region 1, region 2, region 3 and region 4. Figure 6 As shown in the figure, starting from the output end of the QCA circuit to be tested, the test is conducted in reverse order, testing area 3, area 4, area 1 and area 2 in turn; S2-2. Determine whether a sensitization path needs to be designed. For the area containing the output terminal of the QCA circuit to be tested, a sensitization path does not need to be designed. For the area not containing the output terminal of the QCA circuit to be tested, a sensitization path needs to be designed. In other words, before testing, it is necessary to first determine whether a sensitization path needs to be designed. The purpose of setting a sensitization path is to achieve effective propagation of fault effects. Specifically, for the area containing the output terminal of the QCA circuit to be tested, a sensitization path does not need to be designed and testing can be performed directly in that area. For the area not containing the output terminal of the QCA circuit to be tested, a sensitization path needs to be designed first and then tested. In this application, the method for designing a sensitization path includes the following steps: A path that passes through a tested and fault-free area is preferentially selected as the sensitized path, and the non-sensitized inputs of the majority gate in the tested and fault-free area are fixed to 0 and 1 respectively. This ensures that the fault effect of the tested area can be propagated along the sensitized path to the output end of the QCA circuit under test for output. When there is no path that can pass through the detected and fault-free area as the sensitized path, only a path that passes through the detected and faulty area can be selected as the sensitized path. At this time, the SSF fault list related to the three-input variable logic function corresponding to the above-mentioned detected and faulty area should be found from the database, and the complement set should be obtained based on the fault location, the logic value (logical value 0 or 1) of the fixed-type fault introduced by the test clock in the detected and faulty area, and the corresponding test vector in the SSF fault list. For example, Figure 5 The corresponding test vectors for the stuck-at-0 fault at position a, represented by row 4, are 100, 101, and 110. Since the three-input logic function has eight binary input combinations, namely 000, 001, 010, 011, 100, 101, 110, and 111, the vectors 000, 001, 010, 011, and 111 constitute a complement set. Then, observing the vectors in the complement set, two logic values ​​of a specific vector are selected as the two inputs of the region under test, excluding the input of the sensitized path. Let this specific vector be vector M. The condition that vector M must satisfy is that two logic values ​​in vector M are consistent with two logic values ​​of corresponding positions in another vector in the complement set. This ensures that the output value of the sensitized path (the sensitized path is the path passing through the region under test with the fault) is 0 or 1, and does not activate the fault in the region under test with the fault. This ensures that the fault effect of the region under test can propagate along the sensitized path to the output of the QCA circuit under test. S2-3, starting from the output end of the QCA circuit to be tested, a reverse test is performed on each divided area. Specifically in this embodiment, the following steps are included: (1) Test for area 3: Since region 3 includes the output terminal cout of the QCA circuit to be tested, that is, the output of region 3 is an output of the output terminal of the QCA circuit to be tested, there is no need to design a sensitization path for region 3, and region 3 can be directly tested; Testing region 3 specifically includes the following steps: performing a first testing process on region 3, including the following steps: introducing a stuck-at fault (logical value 0 in this embodiment) at any location in region 3 using a test clock, then obtaining an SSF fault list with a logic function of F=A+B·C from a database, then obtaining all corresponding test vectors from the SSF fault list based on the location where the stuck-at fault is introduced, the number of test vectors being 3, namely 100, 101, and 110, and applying the three test vectors to the input terminals of region 3 (there are three input terminals, namely input terminal A, input terminal B, and input terminal C) three times using the test clock. When the test vectors are applied to the input terminals of region 3 using the test clock, the 0 or 1 in the test vectors are all applied to the input terminals of region 3 by the test clock, and then observing the output result of the output terminal cout of the QCA circuit to be tested; Then, a second detection process is performed on region 3, wherein the second detection process on region 3 differs from the first detection process on region 3 only in that the position where the stuck-at fault is introduced by using the test clock is different; It was observed that the output results of the output terminal cout of the QCA circuit to be tested obtained in the first detection process of region 3 and the second detection process of region 3 were consistent with the output results of the simulated QCA circuit corresponding to the logic function F=A+B·C in the fault truth table corresponding to the fault injection position, which indicates that there is no fault in region 3; the present application performs two detection processes on region 3 (i.e., the first detection process of region 3 and the second detection process of region 3), and the positions of the stuck-at fault introduced by the test clock in the two detection processes are different; the above-mentioned setting can effectively prevent the position where the stuck-at fault is first introduced by the test clock in the first detection process of region 3 is exactly the position where the fault exists in region 3 of the QCA circuit to be tested. At this time, the output result of the output terminal cout of the QCA circuit to be tested is consistent with the output result of the simulated QCA circuit corresponding to the logic function F=A+B·C in the fault truth table corresponding to the fault injection position. At this time, if only the first detection process of region 3 is performed, it will be concluded that there is no fault in region 3, which is inconsistent with the fact that there is a fault in region 3 of the QCA circuit to be tested, resulting in a misjudgment; (2) Test area 4: Since region 4 includes the output terminal sum of the QCA circuit under test, that is, the output of region 4 is another output of the output terminal of the QCA circuit under test, there is no need to design a sensitization path for region 4 under test, and region 4 can be directly tested; Testing area 4 includes the following steps: The first detection process for area 4 is different from the first detection process for area 3 in that: 1) the first detection process for area 4 obtains the SSF fault list with the logic function F = (A + B) · C' from the database; 2) the first detection process for area 4 introduces a stuck-at fault at any position in area 4 using the test clock; A second detection process is performed on region 4. The difference between the second detection process and the first detection process is that the location of the stuck-at fault introduced by the test clock is different. It was observed that during both the first and second tests of region 4, the output results of the QCA circuit output terminal sum under test were inconsistent with the simulated QCA circuit output results corresponding to the logic function F = (A + B) · C' in the fault truth table corresponding to the fault injection location, indicating that a fault exists in region 4. The testing process for region 4 is then repeated until the output of the QCA circuit output terminal sum under test matches the output of the simulated QCA circuit corresponding to the logic function F = (A + B) · C' in the fault truth table corresponding to the fault injection location. This allows the fault location to be determined. During the repeated testing of region 4, only the location of the stuck-at fault introduced by the test clock is changed. (3) Test area 1: In this embodiment, the logic function of region 1 is F = (A + B) · C. In this step, a sensitized path must be selected before testing region 1. In this embodiment, the selected sensitized path is the path from test region 1 to test region 3. Because this sensitized path passes through a previously tested and fault-free region (i.e., test region 3), when testing region 1, the test clock configuration must first be used to set the non-sensitized input wire A3 of one of the majority gates in test region 3 to 0 and the non-sensitized input wire C3 of the other majority gate to 1. Then, the detection of area 1 includes the following steps: The first detection process for area 1 is different from the first detection process for area 3 in that: 1) the first detection process for area 1 obtains the SSF fault list with the logic function F = (A + B) C from the database; 2) the first detection process for area 1 introduces a stuck-at fault at any location in area 1 using the test clock; A second detection process is performed on region 1. The difference between the second detection process and the first detection process is that the location of the stuck-at fault introduced by the test clock is different. Observations revealed that during both the first and second tests of region 1, the output of the QCA circuit output terminal cout under test was inconsistent with the simulated QCA circuit output corresponding to the logic function F = (A + B)·C in the fault truth table corresponding to the fault injection location, indicating a fault in region 1. The test process for region 1 is then repeated until the output of the QCA circuit under test, cout, matches the simulated QCA circuit output corresponding to the logic function F = (A + B)·C in the fault truth table corresponding to the fault injection location. This allows the fault location to be determined. During the repeated test of region 1, only the location where the stuck-at fault is introduced by the test clock is changed. In this embodiment, a clock fault exists in region 1. The clock fault is a non-stuck-in type fault. During the test of region 1, since the test clock can simulate the polarization state of the stuck-in type fault (i.e., force the logical state of the cell to be locked to 0 or 1), when the test clock applies the test vector to a specific position in region 1 (i.e., the position where the non-stuck-in type fault exists), the output result of the output terminal cout of the QCA circuit to be tested can be consistent with the simulated QCA circuit output result in the fault truth table result corresponding to the fault injection position. In other words, the method described in the present application can also effectively detect non-stuck-in type faults.

[0017] (4) Test area 2: In this embodiment, the logic function of area 2 is F = (A•B + A•C + B•C)' and C = 0. In this step, a sensitization path needs to be selected before testing area 2. In this embodiment, the sensitization path selected is: the path from the test area 2 to the test area 1 to the test area 3. Since this sensitization path passes through the area that has been tested and has a fault (i.e., the test area 1), It is necessary to find the SSF fault list related to the three-input variable logic function corresponding to the above-mentioned detected and faulty area 1 from the database, and obtain the complement according to the fault location, the logic value of the fixed fault introduced by the test clock in the detected and faulty area (the logic value is 0 in this embodiment) and the corresponding test vector in the SSF fault list. In this embodiment, the complement is {000, 001, 010, 100, 110}. Then, observe the vectors in the complement, select two logic values ​​of one specific vector as the two inputs other than the sensitized path input in the test area; let the above-mentioned specific vector be vector M, and the condition that vector M should satisfy is that two logic values ​​in vector M are respectively consistent with the two logic values ​​of the corresponding positions in another vector in the complement. Specifically in this embodiment, the specific vector can be 000, and the first logic value and the second logic value of the specific vector 000 are respectively consistent with the two logic values ​​of the corresponding positions in the other vector in the complement. The first logic value and the second logic value in vector 001 are consistent, wherein the first logic value in a specific vector 000 corresponds to the first logic value in another vector 001, the second logic value in a specific vector 000 corresponds to the second logic value in another vector 001, and the third logic value in a specific vector 000 corresponds to the third logic value in another vector 001. Therefore, the first two logic values ​​0 and 0 in vector 000 are respectively used as the two inputs (i.e., input wireA1 and input wireB1) in the test area 1 except for the sensitized path input. Obviously, when the input wireA1=0 and wireB1=0 of the test area 1, no matter whether the input C of the test area 1 is 0 or 1 (here C is one of the three inputs of area 1 and also the output of area 2), the fault in area 1 will not be activated. Therefore, let the input wireA1 and input wire B1 is 0, which ensures that the output value of the sensitized path (the path passing through the detected faulty region as the sensitized path) will not activate the fault in the detected faulty region 1, regardless of whether it is 0 or 1. This ensures that the fault effect of the region to be tested can be propagated along the sensitized path to the output of the QCA circuit to be tested. For the detected fault-free region, that is, region 3 to be tested, the non-sensitized inputs of the majority gate in region 3 to be tested, wires A3 and C3, are fixed to 0 and 1, respectively, using the test clock. Then, the detection of area 2 includes the following steps: The first detection process for area 2 is different from the first detection process for area 3 in that: 1) the first detection process for area 2 obtains a list of SSF faults with a logic function of F=(A•B + A•C + B•C)' and C=0 from the database; 2) the first detection process for area 2 introduces a stuck-at fault at any position in area 2 using a test clock; A second detection process is performed on area 2. The difference between the second detection process and the first detection process is that the location of the stuck-at fault introduced by the test clock is different. It is observed that the output results of the output terminal cout of the QCA circuit under test obtained in the first detection process of area 2 and the second detection process of area 2 are consistent with the output results of the simulated QCA circuit corresponding to the fault truth table corresponding to the fault injection position and the logic function F=(A•B+ A•C+B•C)' and C=0, which indicates that there is no fault in area 2. The fault locations detected in areas 4 and 1 of the QCA circuit under test in this embodiment are as follows: Figure 7 shown.

[0018] test: Test Group 1: All QCA circuits built based on the existing USE clock scheme are tested, including one stuck-at fault and one clock fault, where the stuck-at fault and the clock fault occur in different regions. The test results of Test Group 1 are shown in Table 1. One of the test cases in Test Group 1 is Figure 6 The QCA circuit shown, Figure 6 The QCA circuit shown contains a stuck-at fault and a clock fault, and the stuck-at fault and the clock fault occur in different regions. In this test group 1, the other QCA circuits under test containing a stuck-at fault and a clock fault are relatively Figure 6 The difference between the QCA circuits shown is that the regions and / or locations of the stuck-at fault and the clock fault in the other QCA circuits under test containing a stuck-at fault and a clock fault are different from those in the QCA circuits under test containing a stuck-at fault and a clock fault. Figure 6 In the illustrated QCA circuit, the stuck-at fault and the clock fault exist in different regions and / or locations within the region; Test Group 2: All QCA circuits built on the existing USE clock scheme with two stuck-at faults in different regions are tested. The test results of Test Group 2 are shown in Table 1. One of the test cases in Test Group 2 is Figure 8 The QCA circuit shown, Figure 8 The QCA circuit shown contains two stuck-at faults. In this test group 2, the other QCA circuits under test that contain two stuck-at faults are relatively Figure 8The difference between the QCA circuits shown is that the regions where the two stuck-at faults exist and / or the positions of the regions in the other QCA circuits under test containing two stuck-at faults are different from those in the other QCA circuits under test containing two stuck-at faults. Figure 8 The regions where two stuck-at faults exist in the QCA circuit shown and / or their locations in the regions are different; Test Group 3: All QCA circuits built based on the existing USE clock scheme are tested, including a stuck-at fault and a QCA device manufacturing defect, where the stuck-at fault and the QCA device manufacturing defect occur in different regions. The test results of Test Group 3 are shown in Table 1. One of the test cases in Test Group 3 is Figure 9 The QCA circuit shown, Figure 9 The QCA circuit shown contains a stuck-at fault and a QCA device manufacturing defect. In this test group 3, the other QCA circuits under test containing a stuck-at fault and a QCA device manufacturing defect are relatively Figure 9 The difference between the QCA circuits shown is that the regions and / or locations of the stuck-at fault and the QCA device manufacturing defect in the other QCA circuits under test that contain a stuck-at fault and a QCA device manufacturing defect are different from those in the other QCA circuits under test that contain a stuck-at fault and a QCA device manufacturing defect. Figure 9 The stuck-at faults in the QCA circuit and the QCA device manufacturing defects are shown to exist in different regions and / or locations within the regions; Test Group 4: All QCA circuits built on the existing USE clock scheme with two clock faults and two clock faults in different regions are tested. The test results of Test Group 4 are shown in Table 1. One of the test cases in Test Group 4 is Figure 10 The QCA circuit shown, Figure 10 The QCA circuit shown contains two clock faults; in this test group 4, the other QCA circuits under test containing two clock faults are relatively Figure 10 The difference between the QCA circuit shown is that the region where the two clock faults exist and / or the position of the region in the other QCA circuit under test containing two clock faults is different from that in the QCA circuit under test containing two clock faults. Figure 10 The regions where two clock faults exist in the QCA circuit shown and / or the locations in the regions are different; Test Group 5: All QCA circuits built based on the existing USE clock scheme are tested, including a clock fault and a QCA device manufacturing defect, and the clock fault and QCA device manufacturing defect occur in different regions. The test results of Test Group 5 are shown in Table 1; one of the test cases in Test Group 5 is Figure 11 The QCA circuit shown, Figure 11The QCA circuit shown contains a clock fault and a QCA device manufacturing defect; in this test group 5, the other QCA circuits under test containing a clock fault and a QCA device manufacturing defect are relatively Figure 11 The difference between the QCA circuit shown is that the region and / or location of the clock fault and the QCA device manufacturing defect in the other QCA circuit under test containing a clock fault and a QCA device manufacturing defect is different from that in the QCA circuit under test. Figure 11 The regions and / or locations within the regions where clock faults and QCA device manufacturing defects exist in the QCA circuit are shown to be different; Test Group 6: All QCA circuits built based on the existing USE clock scheme are tested, including two QCA device manufacturing defects and the two QCA device manufacturing defects occur in different areas. The test results of Test Group 6 are shown in Table 1; one of the test cases in Test Group 6 is Figure 12 The QCA circuit shown, Figure 12 The QCA circuit shown contains two QCA device manufacturing defects; in this test group six, the other QCA circuits under test containing two QCA device manufacturing defects are relatively Figure 12 The difference between the QCA circuits shown is that the regions and / or locations of the two QCA device manufacturing defects in the other QCA circuits under test that contain two QCA device manufacturing defects are different from those in the other QCA circuits under test that contain two QCA device manufacturing defects. Figure 12 The regions and / or locations within the regions where the manufacturing defects exist are different for the two QCA devices in the illustrated QCA circuit.

[0019] Table 1 Test results of each test group In Table 1, the success rate of fault detection in the test group is the average of the success rates of fault detection in all QCA circuits to be tested in the test group, and the success rate of fault detection in the QCA circuit to be tested is the ratio of the number of faults in the QCA circuit to be tested detected using the method described in the present application to the number of faults contained in the QCA circuit to be tested.

[0020] It can be seen from Table 1 that: The success rate of fault detection in test group one reached 98%, the success rate of fault detection in test group two reached 100%, the success rate of fault detection in test group three reached 96%, the success rate of fault detection in test group four reached 96%, the success rate of fault detection in test group five reached 94%, and the success rate of fault detection in test group six reached 92%. The average success rate of fault detection in all test groups (i.e., test groups one to six) reached 96%. The above-mentioned beneficial effects of this application are mainly due to the following technical innovations: In the present application, when testing a QCA circuit to be tested, the QCA circuit to be tested is first divided into multiple independent test areas. For each test area, a test clock signal can be sent to the test area in the QCA circuit to be tested using a test clock. The test clock signal uses a clock signal with a long hold phase to lock the electrons in the cell in a fixed position for a long time, so that the polarization state of the cell is fixed to 1 or 0, without affecting the cells in other areas outside the test area in the QCA circuit to be tested. The present application has the function of detecting faults in different areas; in addition, the present application also incorporates the design of a sensitization path, especially when the sensitization path is a path that passes through a tested area with a fault. Based on the application of complement vectors, this application innovatively uses a test clock to desensitize the relevant areas through which the sensitized path passes, effectively ensuring that no matter whether the sensitized path value is 0 or 1, the fault in the detected and faulty area will not be activated, thereby achieving accurate shielding of the fault effect in the detected and faulty area, and then effectively ensuring that the fault effect is propagated to the output end of the QCA circuit to be tested without being interfered with by the fault signal in the detected and faulty area; in addition, the optimization of the detection order of this application also has an important impact on the overall performance. A reverse detection strategy starting from the output end is adopted to give priority to processing the fault area close to the output, effectively shortening the propagation path of the fault signal.

Claims

1. A QCA fault detection circuit based on test clock control, characterized by: The QCA fault detection circuit based on test clock control is used to detect the existing QCA circuit constructed based on the clock scheme with arbitrary square clock regions; An existing QCA circuit constructed based on a clock scheme with an arbitrary square clock region is referred to as a QCA circuit under test; The QCA fault detection circuit based on test clock control is improved based on the existing nano quantum cellular automaton circuit with programmable clock. The improvement is as follows: (1) Setting the position of the QCA circuit to be tested to be the same as the position of the quantum cellular automaton in the existing nano-quantum cellular automaton circuit with a programmable clock; (2) The QCA fault detection circuit based on test clock control includes a polarization signal line, and the polarization signal line replaces the special clock signal line in the existing nano quantum cellular automaton circuit with a programmable clock; In the QCA fault detection circuit based on test clock control, the setting of the programmable clock generation circuit layer, the metal foil layer, five clock signal lines, five clock metal lines and the clock signal source is equivalent to introducing a test clock into the QCA circuit to be tested. The test clock can send a test clock signal to the area to be tested in the QCA circuit to be tested when the QCA circuit to be tested is tested. The test clock signal is a polarized clock signal.

2. A QCA fault detection method based on test clock control, characterized by: The QCA fault detection method based on test clock control is implemented using the QCA fault detection circuit based on test clock control according to claim 1. The QCA fault detection method based on test clock control includes the following steps: S1. Divide the QCA circuit to be tested into n logic functions with three input variables. Based on an existing clock scheme based on arbitrary square clock regions and n logic functions, construct n corresponding simulated QCA circuits, where n is greater than or equal to 1. Then, construct a truth table for the fault-free circuit, a truth table for the faulty circuit, and an SSF fault list based on the simulated QCA circuits to obtain test vectors. S2. Performing fault detection on the QCA circuit to be tested using the QCA fault detection circuit based on test clock control, the fault truth table, and the SSF fault list, including the following steps: S2-1, dividing the QCA circuit to be tested into regions corresponding to n logic functions with three input variables; S2-2. Determine whether a sensitization path needs to be designed. For an area including the output end of the QCA circuit to be tested, no sensitization path needs to be designed. For an area not including the output end of the QCA circuit to be tested, a sensitization path needs to be designed. S2-3. Starting from the output end of the QCA circuit to be tested, a reverse test method is used for each divided area.

3. The QCA fault detection method based on test clock control according to claim 2, characterized in that: In step S1, constructing all fault-free circuit truth tables includes the following steps: dividing the QCA circuit to be tested into n areas represented by three-input variable logic functions, and constructing n corresponding analog QCA circuits according to the existing clock scheme based on arbitrary square clock areas and n three-input variable logic functions, where n is greater than or equal to 1, and corresponding fault-free circuit truth tables are constructed for all analog QCA circuits.

4. The QCA fault detection method based on test clock control according to claim 2, characterized in that: In step S1, constructing the truth table of all fault circuits includes the following steps: injecting all possible single stuck-at fault SSF models in all simulated QCA circuits to obtain all faulty simulated QCA circuits, and then simulating all faulty simulated QCA circuits with the simulation tool QCADesigner using 2ⁿ binary input combinations to obtain the steady-state output responses of all binary input combinations corresponding to all faulty simulated QCA circuits, and establishing the fault circuit truth table based on the steady-state output response simulation waveforms.

5. The QCA fault detection method based on test clock control according to claim 2, characterized in that: In step S1, all SSF fault lists are constructed, including the following steps: all SSF fault lists are obtained in the same way. Taking one of the SSF fault list acquisition methods as an example, the following steps are included: the SSF fault column is listed in a table, and the SSF fault column lists all possible single stuck-at faults SSF in a simulated QCA circuit, where single stuck-at faults include faults that are stuck at 1 and faults that are stuck at 0 at each node. By analyzing the equivalence of single stuck-at faults in the circuit, single stuck-at faults with the same output impact are merged into equivalent fault classes, thereby eliminating redundant faults; then, all faults contained in each equivalent fault class are fully recorded in the SSF fault column in the form of a single row to complete the construction of the SSF fault list and obtain the SSF fault list.

6. The QCA fault detection method based on test clock control according to claim 2, characterized in that: In step S1, a test vector is obtained, which includes the following steps: for a single fixed-type fault SSF mode in each equivalent fault class in an SSF fault list, the truth table of the fault-free circuit and the truth table of the faulty circuit are compared to find out all binary input combinations corresponding to the above single fixed-type fault SSF mode and which can make the fault-free simulation QCA circuit and the faulty simulation QCA circuit output different values ​​as test vectors; for all single fixed-type fault SSF modes in the SSF fault list that do not belong to all equivalent fault classes, the truth table of the fault-free circuit and the truth table of the faulty circuit are compared to find out all binary input combinations corresponding to the above single fixed-type fault SSF mode and which can make the fault-free simulation QCA circuit and the faulty simulation QCA circuit output different values ​​as test vectors; all test vectors are recorded in the SSF fault list in the form of a test vector column, and the test vectors in the test vector column correspond to the single fixed-type fault SSF mode in the SSF fault column; the fault-free truth table, the fault truth table and the SSF fault list constitute a database.

7. The QCA fault detection method based on test clock control according to claim 2, characterized in that: In step S2, the method for designing a sensitization path includes the following steps: A path that passes through a tested and fault-free area is preferentially selected as the sensitized path, and the non-sensitized inputs of the majority gate in the tested and fault-free area are fixed to 0 and 1 respectively. This ensures that the fault effect of the tested area can be propagated along the sensitized path to the output end of the QCA circuit under test for output. When there is no path that can pass through the tested and fault-free region as a sensitizing path, only a path that passes through the tested and faulty region can be selected as the sensitizing path. In this case, a list of SSF faults related to the three-input variable logic function corresponding to the tested and faulty region is found in the database. A complement set is obtained based on the fault location, the logic value of the stuck-at fault introduced by the test clock in the tested and faulty region, and the corresponding test vector in the SSF fault list. Then, the vectors in the complement set are observed and two logic values ​​of a specific vector are selected as the two inputs of the region under test, excluding the input of the sensitizing path. Let the specific vector be vector M. The condition that vector M must satisfy is that two logic values ​​in vector M are consistent with two logic values ​​of corresponding positions in another vector in the complement set, so that the output value of the sensitizing path, whether 0 or 1, will not activate the fault in the tested and faulty region, thereby ensuring that the fault effect of the tested region can be propagated along the sensitizing path to the output of the QCA circuit under test.

8. The QCA fault detection method based on test clock control according to claim 2, characterized in that: In step S2-3, when any area is tested, the above detection process is performed twice, and the positions of the stuck-at faults introduced by the test clock in the two detection processes are different.

9. The QCA fault detection method based on test clock control according to claim 2, characterized in that: In step S2-3, when the output results of the output terminal of the QCA circuit under test are consistent with the output results of the simulated QCA circuit corresponding to the logic function in the fault truth table corresponding to the fault injection location during the two detection processes, it indicates that there is no fault in this area; In step S2-3, during the two detection processes, the output result of the output terminal of the QCA circuit to be tested is inconsistent with the output result of the analog QCA circuit corresponding to the logic function in the fault truth table corresponding to the fault injection position, which indicates that there is a fault in the area. Then, the detection process of the above area is repeated until the output result of the output terminal cout of the QCA circuit to be tested is consistent with the output result of the analog QCA circuit corresponding to the logic function in the fault truth table result corresponding to the fault injection position, and the location of the fault can be obtained; among which, in the repeated detection process of area 1, only the location of the fixed-type fault introduced by the test clock is changed.

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