Formation method of semiconductor structure
By forming a protective layer in the opening of the hard mask layer and performing flattening, the line edge roughness problem of semiconductor devices is solved, substrate loss is reduced, device performance and patterning quality are improved.
Patent Information
- Application Number
- CN202410195077.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-21
- Publication Date
- 2025-08-26
AI Technical Summary
In the prior art, the linear edge roughness (LER) problem of semiconductor devices leads to degradation of device performance, and the switching characteristics of transistors cannot be effectively controlled, affecting the manufacturing of highly integrated devices.
The protective layer is formed in the opening of the hard mask layer. The top surface of the protective layer is lower than the top surface of the hard mask layer and covers the substrate surface. By flattening the side walls of the hard mask layer exposed by the protective layer, the linear edge roughness of the hard mask layer is reduced, and the substrate is etched after the protective layer is removed.
Through the protection effect of the protective layer, the loss of the substrate is reduced, the flatness of the hard mask layer is improved, the quality of the patterned graphic structure is improved, the line edge roughness of the hard mask layer is reduced, and the device performance is improved.
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Figure CN120545183A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art
[0002] With the development of technology, the integration level of integrated circuits is increasing day by day. To achieve this high integration level, the feature size of the device is getting smaller and smaller. Such feature size includes the connection lines and functional areas formed in the semiconductor device.
[0003] To achieve such small feature sizes, high-resolution photolithography processes are required. However, as feature sizes (such as line widths) decrease, line edge roughness (LER) becomes a problem. LER refers to irregular or wavy features that appear at the edges or sidewalls of pattern definitions in semiconductor devices.
[0004] LER is increasingly impacting device performance as the proportion of roughness to the overall feature size increases. In device manufacturing with nanometer-scale features, significant roughness at the edges of photoresist lines can negatively impact transistor performance, preventing transistors from switching on and off as planned. Therefore, improving LER is a crucial issue in improving device performance. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which improves the line edge roughness of a hard mask layer of the semiconductor structure and reduces the loss of the substrate.
[0006] To solve the above problems, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a hard mask layer located on the top of the substrate, the hard mask layer having an opening exposing the substrate; forming a protective layer in the opening, the top surface of the protective layer being lower than the top surface of the hard mask layer, and the protective layer covering the top surface of the substrate; performing a planarization process on the sidewalls of the hard mask layer exposed by the protective layer to reduce the line edge roughness of the hard mask layer; and removing the protective layer.
[0007] Optionally, the hard mask layer includes a first hard mask layer located on top of the substrate; a second hard mask layer located on top of the first hard mask layer, and the hardness of the second hard mask layer is less than the hardness of the first hard mask layer; in the step of forming a protective layer in the opening, the protective layer covers the sidewalls of the first hard mask layer and the protective layer exposes the second hard mask layer.
[0008] Optionally, the material of the first hard mask layer includes silicon nitride, and the material of the second hard mask layer includes silicon oxide.
[0009] Optionally, in the step of forming the protective layer, the material of the protective layer includes amorphous carbon or amorphous silicon.
[0010] Optionally, in the step of forming the protective layer, the thickness of the protective layer is to
[0011]
[0012] Optionally, before forming the protective layer, the method further includes: filling the opening with a protective material layer, wherein the protective material layer covers the sidewalls of the hard mask layer; and performing a planarization process on the top surfaces of the protective material layer and the hard mask layer.
[0013] Optionally, the step of forming a protective layer in the opening includes: removing a portion of the thickness of the protective material layer to form a protective layer located at the bottom of the opening and covering the top surface of the substrate.
[0014] Optionally, in the step of filling the protective material layer, the thickness of the protective material layer is to
[0015] Optionally, the process of filling the protective material layer includes a spin coating process or a vapor deposition process.
[0016] Optionally, in the step of performing a planarization process on the top surface of the protective material layer and the top surface of the hard mask layer, the planarization process includes an ion beam etching process.
[0017] Optionally, the parameters of the ion beam etching process include: the etching gas includes a mixture of carbon fluorine gas and inert gas; the volume ratio of the carbon fluorine gas to the inert gas is 1:5 to 1:30; the total flow rate of the etching gas is 10 sccm to 100 sccm; the gas pressure in the chamber is 5 mtorr to 200 mtorr; the incident angle of the plasma is 0 degrees to 60 degrees; the rotation speed is 0 rpm to 60 rpm; and the stage temperature is set to 40°C to 70°C.
[0018] Optionally, the process of removing a portion of the protective material layer includes an inductively coupled plasma etching process or a capacitively coupled plasma etching process.
[0019] Optionally, the parameters of the inductively coupled plasma etching process include: the etching gas includes one or more of carbon fluorine gas, sulfur hexafluoride gas, sulfur dioxide gas and inert gas; the total flow rate of the etching gas is 10 sccm to 400 sccm; the process pressure is 5 mtorr to 200 mtorr; and the process temperature is 40°C to 70°C.
[0020] Optionally, the step of removing a portion of the thickness of the protective material layer includes: etching the protective material layer.
[0021] Optionally, the process of planarizing the sidewalls of the hard mask layer exposed by the protection layer includes an ion beam etching process.
[0022] Optionally, the parameters of the ion beam etching process include: the etching gas includes a mixture of carbon fluorine gas and inert gas; the volume ratio of the carbon fluorine gas to the inert gas is 1:5 to 1:30; the total flow rate of the etching gas is 10 sccm to 100 sccm; the gas pressure in the chamber is 5 mtorr to 200 mtorr; the incident angle of the plasma is 0 degrees to 60 degrees; the rotation speed is 0 rpm to 60 rpm; and the stage temperature is set to 40°C to 70°C.
[0023] Optionally, the process of removing the protective layer includes one or both of a wet etching process and a vapor phase etching process.
[0024] Optionally, the process of removing the protective layer includes a wet etching process, and etching parameters of the wet etching process include: an etching solution including a sulfuric acid solution or a diluted hydrofluoric acid solution, a process temperature of 30° C. to 80° C., and a process time of 5 min to 30 min.
[0025] Optionally, after removing the protective layer, the method further includes: using the hard mask layer as a mask to etch the substrate along the opening in the hard mask layer.
[0026] Optionally, the base includes a substrate; in the step of etching the base, the substrate is etched using the hard mask layer as a mask to form a fin located on the remaining substrate.
[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0028] An embodiment of the present invention provides a method for forming a semiconductor structure. The method comprises forming a hard mask layer having an opening on a substrate, forming a protective layer in the opening, wherein the top surface of the protective layer is lower than the top surface of the hard mask layer and covers the top surface of the substrate; performing a planarization process on the sidewalls of the hard mask layer exposed by the protective layer to reduce the line edge roughness of the hard mask layer; and removing the protective layer. When the sidewalls of the hard mask layer exposed by the protective layer are planarized, the protective layer can protect the substrate, thereby reducing substrate loss.
[0029] In an optional embodiment, before forming the protective layer, the method further includes: filling the opening with a protective material layer, wherein the protective material layer covers the sidewalls of the hard mask layer; and performing a planarization process on the top surfaces of the protective material layer and the hard mask layer. By performing the planarization process on the top surfaces of the protective material layer and the hard mask layer, the flatness of the top surface of the hard mask layer is improved, thereby improving the parity effect (fin pitch walking) of the pattern structure formed after patterning using the hard mask layer as a mask. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figures 1 to 2 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;
[0031] Figures 3 to 10 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0032] Current photolithography processes can result in high line-edge roughness in semiconductor devices, making reducing this roughness a challenge. This article analyzes the reasons why improving line-edge roughness is so difficult, using a schematic diagram of a semiconductor structure.
[0033] Figures 1 to 2 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.
[0034] refer to Figure 1 , providing a substrate 10; forming a hard mask layer 11 located on the top of the substrate 10, wherein an opening 13 is formed in the hard mask layer 11 that penetrates the hard mask layer 11 and exposes the substrate.
[0035] The hard mask layer 11 includes: a first hard mask layer 11B located on the top of the substrate 10; and a second hard mask layer 11A located on the top of the first hard mask layer 11B.
[0036] The opening 13 is formed by etching the hard mask layer 11 , and thus, due to the influence of the etching process, the line edge roughness of the sidewall of the hard mask layer 11 is relatively high.
[0037] As can be seen from FIG. 1 , the line edge roughness of the sidewall of the hard mask layer 11 is relatively high.
[0038] refer to Figure 2 , the sidewalls of the hard mask layer 11 are planarized.
[0039] The research found that Figure 1As shown, after the opening 13 of the hard mask layer 11 is formed, the opening 13 exposes the top surface of the substrate 10. Since the substrate 10 is exposed to the flattening process environment when the sidewall of the hard mask layer 11 is flattened, it is easy to cause damage to the substrate 10. For example, when an ion beam etching process is required for flattening, the ion beam etching process is easy to cause damage to the substrate 10 exposed by the opening 13 (such as Figure 2 As shown in FIG, the semiconductor structure performance may be affected in subsequent processes.
[0040] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a hard mask layer located on the top of the substrate, the hard mask layer having an opening exposing the substrate; forming a protective layer in the opening, the top surface of the protective layer being lower than the top surface of the hard mask layer, and the protective layer covering the top surface of the substrate; performing planarization on the side walls of the hard mask layer exposed by the protective layer to reduce the line edge roughness of the hard mask layer; and removing the protective layer.
[0041] In the solution disclosed in the embodiment of the present invention, a protective layer covering the substrate is formed at the bottom of the opening penetrating the hard mask layer. When the sidewalls of the hard mask layer of the semiconductor structure are planarized, the protective layer can protect the substrate, thereby reducing the loss of the substrate.
[0042] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0043] Figures 3 to 10 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0044] refer to Figure 3 , providing a substrate 20.
[0045] The substrate 20 is used to provide a process platform for subsequent process steps.
[0046] In this embodiment, the substrate 20 is used to form a field effect transistor. As an example, the substrate 20 is used to form a fin field effect transistor.
[0047] The substrate 20 includes a layer to be etched (not shown). When etching is subsequently performed using the hard mask layer on the top of the substrate 20 as a mask, the layer to be etched becomes the etched object.
[0048] In this embodiment, the base 20 includes a substrate, and the substrate serves as a layer to be etched.
[0049] The substrate is made of silicon. In other embodiments, the substrate may be made of one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.
[0050] In other embodiments, the base may also include a substrate and a layer to be etched located on the substrate.
[0051] refer to Figure 4 , forming a hard mask layer 21 located on the top of the substrate 20 , wherein the hard mask layer 21 has an opening 23 exposing the substrate 20 .
[0052] The hard mask layer 21 is used as an etching mask for subsequent patterning of the substrate 20 to form the fin 25. Specifically, the hard mask layer 21 is used as an etching mask for subsequent patterning of the layer to be etched.
[0053] In this embodiment, the opening 23 penetrates the hard mask layer 21 and is used for subsequent filling of a protective material layer and forming a protective layer.
[0054] Specifically, the hard mask layer 21 includes: a first hard mask layer 21B located on top of the substrate 20; and a second hard mask layer 21A located on top of the first hard mask layer 21B. The hardness of the second hard mask layer 21A is less than that of the first hard mask layer 21B.
[0055] Specifically, the first hard mask layer 21B is obtained by patterning a first hard mask material layer (not shown); and the second hard mask layer 21A is obtained by patterning a second hard mask material layer (not shown).
[0056] It should be noted that the hardness of the second hard mask layer 21A is less than the hardness of the first hard mask layer 21B, which means that the hardness of the first hard mask material layer is larger. After the first hard mask material layer is subsequently patterned to form the first hard mask layer 21B, the roughness of the side wall of the first hard mask layer 21B is smaller, which is conducive to the subsequent formation of the fin 25 with smaller side wall roughness; the hardness of the second hard mask layer 21A is smaller, which is conducive to accurately transferring the pattern to the first hard mask layer 21B. Moreover, the patterning of the first hard mask material layer and the second hard mask material layer usually adopts an organic pattern layer (for example, photoresist) for defining the pattern. Then, an organic pattern layer is formed on the second hard mask layer 21A with smaller hardness, which is conducive to improving the adhesion between the second hard mask layer 21A and the organic pattern layer.
[0057] In this embodiment, the steps of forming the first hard mask layer 21B and the second hard mask layer 21A include: depositing a first hard mask material layer on top of the substrate 20; forming a second hard mask material layer on top of the first hard mask material layer; forming a patterned photoresist layer (not shown) on top of the second hard mask layer; using the patterned photoresist layer as a mask, patterning the second hard mask material layer to form the second hard mask layer 21A; using the second hard mask layer 21A as a mask, patterning the first hard mask material layer to form the first hard mask layer 21B.
[0058] The first hard mask layer 21B is made of silicon nitride, and the second hard mask layer 21A is made of silicon oxide.
[0059] The silicon nitride has a greater hardness, which is beneficial for forming a first hard mask layer 21B with smaller surface roughness on the sidewalls after the first hard mask material layer is subsequently patterned, thereby facilitating the formation of fins with smaller surface roughness in subsequent processes; the silicon oxide has a lower hardness, which is beneficial for transferring the photoresist pattern to the first hard mask layer 21B.
[0060] Combined with reference Figures 5 to 7 A protection layer 24 is formed in the opening 23 , wherein a top surface of the protection layer 24 is lower than a top surface of the hard mask layer 21 , and the protection layer 24 covers the top surface of the substrate 20 .
[0061] The protection layer 24 covers the top surface of the substrate 20 . When the exposed sidewalls of the hard mask layer 21 are subsequently planarized, the protection layer 24 is used to protect the substrate 20 , thereby reducing the loss of the substrate 20 .
[0062] In this embodiment, the material of the protection layer 24 includes amorphous carbon or amorphous silicon.
[0063] The amorphous carbon or amorphous silicon has good filling properties and can better cover the top of the substrate 20 located at the bottom of the opening 23. When the sidewall of the hard mask layer 21 of the semiconductor structure is planarized, the protective layer 24 can protect the substrate 20, thereby reducing the loss of the substrate 20.
[0064] refer to Figure 7 In the step of forming the protection layer 24 in the opening 23 , the protection layer 24 covers the sidewalls of the first hard mask layer 21B and exposes the second hard mask layer 21A.
[0065] Specifically, the hardness of the first hard mask layer 21B is greater than that of the second hard mask layer 21B, and the line edge roughness of the side wall of the first hard mask layer 21B is less than that of the second hard mask layer 21A. When the side wall of the hard mask layer 21 of the semiconductor structure is subsequently planarized, since the protective layer 24 covers the side wall of the first hard mask layer 21B and the protective layer 24 exposes the second hard mask layer 21A, that is, the second hard mask layer 21A is exposed to the etching environment for a longer time than the first hard mask layer 21B, the line edge roughness of the side wall of the first hard mask layer 21B can be consistent with the line edge roughness of the side wall of the second hard mask layer 21A.
[0066] It should be noted that, in this embodiment, the thickness h of the protective layer 24 should not be too large or too small. If the thickness h of the protective layer 24 is too large, it is easy to cause insufficient exposure of the sidewalls of the hard mask layer 21, resulting in insufficient flattening of the sidewalls of the hard mask layer 21 during the subsequent flattening of the sidewalls of the hard mask layer 21 of the semiconductor structure, and thus the line edge roughness of the sidewalls of the hard mask layer 21 cannot be reduced; if the thickness h of the protective layer 24 is too small, when the sidewalls of the hard mask layer 21 of the semiconductor structure are subsequently flattened, it is easy to cause the protective layer 24 to be removed in advance, which is easy to cause regular or irregular substrate height differences at different positions of the substrate 20, and at the same time, the probability of the substrate 20 being damaged due to exposure is also higher, which in turn affects the subsequent process. Therefore, in this embodiment, the thickness h of the protective layer 24 is to
[0067] refer to Figure 5 Before forming the protection layer 24 , the method further includes: filling a protection material layer 24A in the opening 23 , wherein the protection material layer 24A covers the sidewall of the hard mask layer 21 .
[0068] In the subsequent planarization process of the top surface of the protection material layer 24A and the top surface of the hard mask layer 21 , the protection material layer 24A covers the sidewalls of the hard mask layer 21 and can protect the sidewalls of the hard mask layer 21 .
[0069] Moreover, the protective material layer 24A is used to form the protective layer 24 later.
[0070] In this embodiment, the process of filling the protective material layer 24A includes a spin coating process or a vapor deposition process.
[0071] The spin coating process can evenly coat a liquid or thin film material on a substrate, ensuring a consistent coating thickness. Large substrate areas can be coated in a short time, improving productivity. Furthermore, the thickness of the resulting coating can be controlled by adjusting spin coating process parameters. Thus, a protective material layer 24A having a uniform thickness can be obtained.
[0072] The vapor deposition process has good uniformity and controllability. Due to the uniformity of the vapor deposition, a uniform protective material layer 24A can be grown on the substrate 20. At the same time, due to the controllability of the vapor deposition, the thickness of the protective material layer 24A grown on the substrate 20 can be precisely controlled.
[0073] It should be noted that the thickness H of the protective material layer 24A should not be too large or too small. If the thickness H of the protective material layer 24A is too large, the process time will be prolonged during the subsequent removal of a portion of the protective material layer 24A (for example, during the planarization process of the top surface of the protective material layer 24A and the top surface of the hard mask layer 21, a portion of the protective material layer 24A needs to be removed to expose the top surface of the hard mask layer 21). This will cause excessive loss of the top surface of the hard mask layer 21 (for example, the top surface of the second hard mask layer 21A), thereby affecting subsequent process steps. If the thickness H of the protective material layer 24A is too small, a portion of the sidewall of the hard mask layer 21 will be easily exposed. During the subsequent planarization process of the top surface of the protective material layer 24A and the top surface of the hard mask layer 21, the exposed sidewall of the hard mask layer 21 will be easily lost, which is not conducive to improving the flatness of the top surface of the hard mask layer 21. Therefore, in this embodiment, the thickness H of the protective material layer 24A is to
[0074] refer to Figure 6 Before forming the protection layer 24 , the method further includes: performing a planarization process on the top surface of the protection material layer 24A and the top surface of the hard mask layer 21 .
[0075] Specifically, by performing a planarization process on the top surface of the protective material layer 24A and the top surface of the hard mask layer 21, the flatness of the top surface of the hard mask layer 21 is improved, thereby improving the odd-even effect of the pattern structure formed after patterning using the hard mask layer 21 as a mask.
[0076] In the step of performing a planarization process on the top surface of the protection material layer 24A and the top surface of the hard mask layer 21 , the planarization process includes an ion beam etching (IBE) process.
[0077] The ion beam etching process can achieve a relatively uniform etching rate distribution, thereby obtaining a relatively flat surface, which is composed of the top surface of the protective material layer 24A and the top surface of the hard mask layer 21, thereby improving the odd-even effect of the graphic structure formed after patterning using the hard mask layer 21 as a mask.
[0078] The parameters of the ion beam etching process include: the etching gas includes a mixture of carbon fluorine gas and an inert gas; the volume ratio of the carbon fluorine gas to the inert gas is 1:5 to 1:30; the total flow rate of the etching gas is 10 sccm to 100 sccm; the gas pressure in the chamber is 5 mtorr to 200 mtorr; the incident angle of the plasma is 0 degrees to 60 degrees; the rotation speed is 0 rpm to 60 rpm; and the stage temperature is set to 40°C to 70°C.
[0079] The parameters of the ion beam etching process include: the etching gas comprises a mixture of a carbon fluorine gas and an inert gas; and the volume ratio of the carbon fluorine gas to the inert gas is 1:5 to 1:30. By setting the volume ratio of the carbon fluorine gas to the inert gas within the above range, the etching gas can significantly improve the flatness of the top surface of the hard mask layer 21.
[0080] Continue to refer Figure 7 The step of forming the protection layer 24 in the opening 23 includes: removing a portion of the thickness of the protection material layer 24A to form the protection layer 24 located at the bottom of the opening 23 and covering the top surface of the substrate 20.
[0081] Specifically, a portion of the protective material layer 24A is removed to expose the sidewalls of the hard mask layer 21 . The exposed sidewalls of the hard mask layer 21 may be planarized to reduce the line edge roughness of the hard mask layer 21 .
[0082] At the same time, the protective material layer 24A is directly used to form the protective layer 24, thereby simplifying the process steps and saving materials.
[0083] The step of removing a portion of the protective material layer 24A includes etching the protective material layer 24A until the entire second hard mask layer 21A is exposed.
[0084] Specifically, when the sidewalls of the hard mask layer 21 of the semiconductor structure are subsequently smoothed, the sidewalls of the second hard mask layer 21A are completely exposed, so that the sidewalls of the second hard mask layer 21A can be smoothed by an ion beam etching process. Since the ion beam etching process has a collimating characteristic, the line edge roughness of the sidewalls of the second hard mask layer 21A can be reduced.
[0085] The process of removing a portion of the protective material layer 24A includes an inductively coupled plasma etching process or a capacitively coupled plasma etching process.
[0086] The inductively coupled plasma etching process has good controllability and low damage, so it can accurately remove a portion of the protective material layer 24A. At the same time, it can reduce surface damage to the hard mask layer 21, facilitating subsequent process steps.
[0087] The parameters of the inductively coupled plasma etching process include: the etching gas includes one or more of carbon fluorine gas, sulfur hexafluoride gas, sulfur dioxide gas and inert gas; the total flow rate of the etching gas is 10 sccm to 400 sccm; the process pressure is 5 mtorr to 200 mtorr; and the process temperature is 40°C to 70°C.
[0088] It should be noted that, in other embodiments, after the top surfaces of the protective material layer and the hard mask layer are planarized, the protective material layer may be removed and an additional protective layer may be formed.
[0089] refer to Figure 8 , the sidewalls of the hard mask layer 21 exposed by the protection layer 24 are planarized to reduce the line edge roughness of the hard mask layer 21 .
[0090] Specifically, the line edge roughness of the hard mask layer 21 is reduced, and subsequent patterning using the hard mask layer 21 as a mask is beneficial to improving pattern transfer quality.
[0091] The process of planarizing the sidewalls of the hard mask layer 21 exposed by the protection layer 24 includes an ion beam etching process.
[0092] The ion beam etching process is a physical sputtering process. During the process, the side walls of the hard mask layer 21 are smoothed only by physical impact, so that no solution residues or chemical contamination are introduced, thereby avoiding affecting the material properties of the hard mask layer 21. At the same time, since the ion beam generated during the ion beam etching process passes through the ion aperture, the size and shape of the ion beam are limited, which correspondingly makes the ion beam highly collimated, that is, the ion beam etching process has a high degree of collimation. Therefore, when the ion beam etching process is used to smooth the side walls of the hard mask layer 21, based on the collimation characteristics of the ion beam etching process, the line edge roughness of the side walls of the hard mask layer 21 is improved.
[0093] The parameters of the ion beam etching process include: the etching gas includes a mixture of carbon fluorine gas and an inert gas; the volume ratio of the etching gas is 1:5 to 1:30; the total flow rate of the etching gas is 10 sccm to 100 sccm; the gas pressure in the chamber is 5 mtorr to 200 mtorr; the incident angle of the plasma is 0 degrees to 60 degrees; the rotation speed is 0 rpm to 60 rpm; and the stage temperature is set to 40°C to 70°C.
[0094] The parameters of the ion beam etching process include: an etching gas comprising a mixture of a carbon fluoride gas and an inert gas; and a volume ratio of the etching gas of 1:5 to 1:30. By setting the volume ratio of the carbon fluoride gas to the inert gas within the above range, the etching gas can significantly reduce the line edge roughness of the sidewall of the hard mask layer 21.
[0095] refer to Figure 9 , remove the protective layer 24.
[0096] The protective layer 24 is removed to facilitate subsequent etching along the opening 23 in the hard mask layer 21 and the bottom of the opening 23 .
[0097] In order to improve the etching selectivity when removing the protective layer 24 , the process of removing the protective layer 24 includes one or both of a wet etching process and a vapor phase etching process.
[0098] In this embodiment, the process of removing the protective layer 24 includes a wet etching process.
[0099] The wet etching process has the characteristic of isotropic etching, which is conducive to completely removing the protective layer 24. Moreover, the wet etching process is easy to obtain a large etching selectivity, which is conducive to reducing damage to other film layers during the process of removing the protective layer 24.
[0100] In this embodiment, the etching parameters of the wet etching process include: the etching solution includes a sulfuric acid solution or a diluted hydrofluoric acid solution, the process temperature is 30° C. to 80° C., and the process time is 5 min to 30 min.
[0101] The temperature of the wet etching process should not be too high or too low. If the process temperature is too high, the probability of damage to other film layers (e.g., the hard mask layer 21) is increased. If the process temperature is too low, the protective layer 24 may remain, which in turn may affect the quality of subsequent patterning of the substrate 20. Therefore, in this embodiment, the process temperature is 30°C to 80°C.
[0102] The wet etching process should be performed neither too long nor too short. If the wet etching process is performed too long, the probability of damage to other film layers (e.g., the hard mask layer 21) may increase. If the wet etching process is performed too short, the protective layer 24 may remain, which may affect the quality of the subsequent formation of the fin 25. Therefore, in this embodiment, the process time is 5 to 30 minutes.
[0103] It should be noted that, in other embodiments, the protective layer may be removed by using a vapor phase etching process, or by combining a wet etching process with a vapor phase etching process.
[0104] refer to Figure 10 After removing the protective layer 24 , the method further includes: using the hard mask layer 21 as a mask to etch the substrate 20 along the opening 23 in the hard mask layer 21 .
[0105] Specifically, the layer to be etched is etched to form a desired target pattern.
[0106] In this embodiment, the base 20 includes a substrate. Therefore, in the step of etching the base 20 , the substrate is etched using the hard mask layer 21 as a mask to form the fin 25 located on the remaining substrate.
[0107] In this embodiment, the discrete fins 25 on the substrate are used to provide channels of the FinFET.
[0108] Therefore, in this embodiment, the material of the fin 25 is the same as that of the substrate, that is, silicon. In other embodiments, the material of the fin 25 may be one or more semiconductor materials suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The material of the fin may also be different from that of the substrate.
[0109] By adopting the above processing method, the quality of the fin 25 is improved while the loss to the substrate is reduced.
[0110] As an example, the substrate is etched using an anisotropic etching process with the hard mask layer 21 as a mask.
[0111] It is understood that the embodiments of the present invention are not limited to forming the fin 25. In other embodiments, the hard mask layer formed by the above steps can also be used to etch other types of layers to be etched, such as a gate material layer or an interlayer dielectric material layer.
[0112] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a hard mask layer on top of the substrate, the hard mask layer having an opening exposing the substrate; forming a protection layer in the opening, wherein a top surface of the protection layer is lower than a top surface of the hard mask layer, and the protection layer covers a top surface of the substrate; performing a planarization process on the sidewalls of the hard mask layer exposed by the protective layer to reduce the line edge roughness of the hard mask layer; The protective layer is removed.
2. The method for forming a semiconductor structure according to claim 1, wherein: The hard mask layer includes: a first hard mask layer located on top of the substrate; a second hard mask layer located on top of the first hard mask layer, wherein the hardness of the second hard mask layer is less than that of the first hard mask layer; In the step of forming a protection layer in the opening, the protection layer covers the sidewalls of the first hard mask layer and exposes the second hard mask layer.
3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the first hard mask layer includes silicon nitride, and the material of the second hard mask layer includes silicon oxide.
4. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the protective layer, the material of the protective layer includes amorphous carbon or amorphous silicon.
5. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the protective layer, the thickness of the protective layer is to 6. The method for forming a semiconductor structure according to any one of claims 1 to 5, wherein: Before forming the protection layer, the method further includes: filling the opening with a protection material layer, wherein the protection material layer covers the sidewall of the hard mask layer; A planarization process is performed on the top surfaces of the protective material layer and the hard mask layer.
7. The method for forming a semiconductor structure according to claim 6, wherein: The step of forming the protection layer in the opening includes: removing a portion of the thickness of the protection material layer to form a protection layer located at the bottom of the opening and covering the top surface of the substrate.
8. The method for forming a semiconductor structure according to claim 6, wherein: In the step of filling the protective material layer, the thickness of the protective material layer is to 9. The method for forming a semiconductor structure according to claim 6, wherein: The process of filling the protective material layer includes a spin coating process or a vapor deposition process.
10. The method for forming a semiconductor structure according to claim 6, wherein: In the step of performing a planarization process on the top surface of the protective material layer and the top surface of the hard mask layer, the planarization process includes an ion beam etching process.
11. The method for forming a semiconductor structure according to claim 10, wherein: The parameters of the ion beam etching process include: the etching gas includes a mixture of carbon fluorine gas and an inert gas; the volume ratio of the carbon fluorine gas to the inert gas is 1:5 to 1:30; the total flow rate of the etching gas is 10 sccm to 100 sccm; the gas pressure in the chamber is 5 mtorr to 200 mtorr; the incident angle of the plasma is 0 degrees to 60 degrees; the rotation speed is 0 rpm to 60 rpm; and the stage temperature is set to 40°C to 70°C.
12. The method for forming a semiconductor structure according to claim 7, wherein: The process of removing a portion of the protective material layer includes an inductively coupled plasma etching process or a capacitively coupled plasma etching process.
13. The method for forming a semiconductor structure according to claim 12, wherein: The parameters of the inductively coupled plasma etching process include: the etching gas includes one or more of carbon fluorine gas, sulfur hexafluoride gas, sulfur dioxide gas and inert gas; the total flow rate of the etching gas is 10 sccm to 400 sccm; the process pressure is 5 mtorr to 200 mtorr; and the process temperature is 40°C to 70°C.
14. The method for forming a semiconductor structure according to claim 7, wherein: The step of removing a portion of the thickness of the protective material layer includes: etching the protective material layer.
15. The method for forming a semiconductor structure according to any one of claims 1 to 5, wherein: The process of planarizing the sidewall of the hard mask layer exposed by the protection layer includes an ion beam etching process.
16. The method for forming a semiconductor structure according to claim 15, wherein: The parameters of the ion beam etching process include: the etching gas includes a mixture of carbon fluorine gas and an inert gas; the volume ratio of the carbon fluorine gas to the inert gas is 1:5 to 1:30; the total flow rate of the etching gas is 10 sccm to 100 sccm; the gas pressure in the chamber is 5 mtorr to 200 mtorr; the incident angle of the plasma is 0 degrees to 60 degrees; the rotation speed is 0 rpm to 60 rpm; and the stage temperature is set to 40°C to 70°C.
17. The method for forming a semiconductor structure according to any one of claims 1 to 5, wherein: The process of removing the protective layer includes one or both of a wet etching process and a vapor phase etching process.
18. The method for forming a semiconductor structure according to claim 17, wherein: The process of removing the protective layer includes a wet etching process, and the etching parameters of the wet etching process include: the etching solution includes a sulfuric acid solution or a diluted hydrofluoric acid solution, the process temperature is 30° C. to 80° C., and the process time is 5 min to 30 min.
19. The method for forming a semiconductor structure according to any one of claims 1 to 5, wherein: After removing the protective layer, the method further includes: using the hard mask layer as a mask to etch the substrate along the opening in the hard mask layer.
20. The method for forming a semiconductor structure according to claim 19, wherein: The base includes a substrate; in the step of etching the base, the hard mask layer is used as a mask to etch the substrate to form a fin located on the remaining substrate.