Timing trigger circuit, bias voltage adjusting device, power amplifier and equipment

Abstract

The invention provides a timing trigger circuit, a bias voltage adjusting device, a power amplifier and electronic equipment. The timing trigger circuit comprises at least two cascaded monostable trigger modules, the input end of the first-stage monostable trigger module receives an input signal, and the first output end of the adjacent previous-stage monostable trigger module is coupled with the input end of the next-stage monostable trigger module; the monostable trigger module comprises a monostable trigger body and a reset unit. And when the first-stage monostable trigger module is triggered by an input signal, the first-stage monostable trigger module outputs a first high level with the duration of T1, and the second-stage monostable trigger module is triggered to output a second high level with the duration of T2, so that the triggering is performed in sequence until the last-stage monostable trigger module outputs an Nth high level with the duration of Tn. According to the method, the problems that the PVT rising speed is low and the long packet power declines along with time can be solved, the dynamic EVM is optimized, and the design difficulty of the power amplifier can be remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to a timing trigger circuit, a bias voltage adjustment device, a power amplifier and an electronic device. Background Art

[0002] With the continuous development of WiFi technology, the modulation methods used are becoming increasingly complex. WiFi 6 uses 1024QAM, and WiFi 7 uses 4096QAM. The EVM (Error Vector Magnitude) demodulation threshold has also been improved from -35dBm to -38dBm. Different platforms use WiFi data packets of varying lengths, with some using short packets and others using long packets. When designing WiFi power amplifiers (PAs), the inherent characteristics of the amplifier tube make it difficult to simultaneously address the PVT (power vs. time) performance of both long and short packets, resulting in poor dynamic EVM results.

[0003] Currently, WiFi modules integrate both TX (transmit) and RX (receive) functions. Power amplifiers are typically implemented using GaAs or SiGe processes, while the power amplifier bias circuit is implemented using CMOS (Complementary Metal Oxide Semiconductor) or SOI (Silicon-On-Insulator). Existing technologies for designing WiFi power amplifiers typically tend to prioritize either long or short packets, such as sacrificing long packets in favor of short packets. This can lead to power shortages on platforms that frequently use long packets. For more information, see [Note: The following appears to be unrelated and should likely be omitted:] Figure 1 , Figure 1 FIG. 1 is a block diagram of a specific example of a power amplifier in the prior art. Figure 1As shown, a conventional power amplifier includes an input matching circuit 110, a power amplifier 120, an output matching circuit 130, and a bias circuit 140. Bias circuit 140 is typically implemented by a bandgap reference voltage circuit and an LDO (low dropout regulator) module. Adjusting the bias voltage waveform can significantly improve the power amplifier's PVT waveform. Typically, after the LDO module is enabled, the output voltage stabilizes after a short settling time, and the power amplifier 120 maintains a stable bias for a relatively long period of time. Its PVT characteristics are entirely dependent on the characteristics of the power amplifier 120 itself. When the power amplifier 120 outputs high power, the current is typically high, and its thermal characteristics are significant. As operating time increases, the power amplifier 120 becomes increasingly hotter, and its gain decreases, resulting in poor PVT over long periods of time and difficulty meeting EVM requirements.

[0004] In order to solve the above problems, there are two main methods for adjusting the bias voltage in the related art:

[0005] (1) Using an oscillator and a counter to set the timing, in order to change the bias voltage at the required time point. This method has the problem of the oscillator contaminating the power supply. This is because the power supply will also power the LNA (Low Noise Amplifier), which will deteriorate the LNA's NF (Noise Figure). Furthermore, the bias voltage output waveform also has obvious periodic glitches, which affects the performance of the power amplifier.

[0006] (2) The bias voltage is adjusted by switching the reference voltage of the LDO module, that is, the reference voltage given by the bandgap reference voltage circuit is shaped by a shaping circuit (such as a filter circuit), and then amplified by the LDO module to obtain the desired waveform. The limitation of this method is that the current mobile phone WiFi FEM (Front-End Modules) has lower and lower requirements for leakage, and the shaping circuit is likely to interfere with the voltage of the bandgap reference voltage circuit itself. Since the power consumption of the bandgap reference voltage circuit itself is too low, its output voltage cannot be immediately restored after being interfered with by external factors, which may cause the output voltage of the LDO module to be inaccurate. In addition, this method also has the limitation that it is usually only applicable to short packets and not long packets.

[0007] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0008] The present invention aims to provide a timing trigger circuit, a bias voltage adjustment device, a power amplifier, and an electronic device. The present invention can improve the problems of slow PVT rise and time-dependent power drop in long packets. The present invention is applicable to different types of power amplifiers, compensates for long and short packets without affecting LNA performance, optimizes its dynamic EVM, and significantly reduces the design difficulty of the power amplifier.

[0009] To achieve the above objectives, the present invention is implemented through the following technical solutions: a timing trigger circuit, comprising at least two cascaded monostable trigger modules, wherein the input terminal of the monostable trigger module of a first stage is used to receive an input signal, and the first output terminal of the monostable trigger module of the adjacent previous stage is coupled to the input terminal of the monostable trigger module of the next stage;

[0010] The monostable trigger module includes a monostable trigger body and a reset unit electrically connected to the monostable trigger body and configured to implement a low-level reset. The monostable trigger body and the reset unit are coupled between a first supply voltage and a reference ground. A common point between an input terminal of the monostable trigger body and a first terminal of the reset unit serves as an input terminal of the monostable trigger module. A first output terminal of the monostable trigger body serves as a first output terminal of the monostable trigger module. A second output terminal of the monostable trigger body serves as a second output terminal of the monostable trigger module to provide an output voltage. The first output terminal and the second output terminal of the monostable trigger module output signals of opposite levels.

[0011] The timing trigger circuit is configured such that when the first-stage monostable trigger module is triggered by the input signal, the second output terminal of the first-stage monostable trigger module outputs a first high level for a duration of T1, and when the first high level ends, the second output terminal of the second-stage monostable trigger module is triggered to output a second high level for a duration of T2, and so on, until the second output terminal of the last-stage monostable trigger module outputs a second high level for a duration of T n The nth high level of , where n is the number of the monostable trigger modules.

[0012] Optionally, the monostable trigger body includes a delay unit and a logic trigger unit; the common point of the first end of the delay unit and the first end of the reset unit forms the input end of the monostable trigger module, the second end of the delay unit, the first end of the logic trigger unit and the second end of the reset unit are coupled, the second end of the logic trigger unit is coupled to the third end of the reset unit, the third end and the fourth end of the logic trigger unit serve as the first output end and the second output end of the monostable trigger body respectively; the fifth end of the logic trigger unit is coupled to the fourth end of the reset unit for receiving the first power supply voltage, and the third end of the delay unit and the fifth end of the reset unit are coupled to the reference ground.

[0013] Optionally, the reset unit includes a first inverter, a second inverter, a first MOS transistor and a second MOS transistor; the input end of the first inverter is used to receive the input signal, the output end of the first inverter, the input end of the second inverter and the gate of the first MOS transistor are coupled, the output end of the second inverter is coupled to the gate of the second MOS transistor, the second end of the delay unit, the first end of the first MOS transistor and the first end of the logic trigger unit are coupled, the first end of the second MOS transistor is coupled to the second end of the logic trigger unit, the second end of the second MOS transistor is used to receive the first power supply voltage, and the second end of the first MOS transistor is coupled to the reference ground.

[0014] Optionally, the delay unit includes a first capacitor and a first resistor, the first end of the first capacitor is used to receive the input signal, the second end of the first capacitor and the first end of the first resistor are coupled to the second end of the reset unit and the first end of the logic trigger unit, and the second end of the first resistor is coupled to the reference ground.

[0015] Optionally, the logic trigger unit includes a NOR gate, a second capacitor, a second resistor, a third inverter, a fourth inverter and a fifth inverter, the first input end of the NOR gate is coupled to the second end of the reset unit, the second input end of the NOR gate, the output end of the third inverter and the input end of the fourth inverter are coupled, the output end of the NOR gate is coupled to the first end of the second capacitor, the second end of the second capacitor, the first end of the second resistor, the input end of the third inverter and the third end of the reset unit are coupled, the common node of the output end of the fourth inverter and the input end of the fifth inverter serves as the third end of the logic trigger unit, and the output end of the fifth inverter serves as the fourth end of the logic trigger unit; the second end of the second resistor is used to receive the first supply voltage.

[0016] To achieve the above objectives, the present invention further provides a bias voltage adjustment device, comprising a timing trigger circuit, a bandgap reference voltage circuit, and an LDO module as described above; the timing trigger circuit is coupled between a negative input terminal of the LDO module and an output terminal of the LDO module and / or the timing trigger circuit is coupled between the output terminal of the bandgap reference voltage circuit and a positive input terminal of the LDO module to adjust the output voltage of the LDO module.

[0017] Optionally, the LDO module includes an LDO body and an adjustable resistor sub-module, the output end of the bandgap reference voltage circuit is coupled to the positive phase input end of the LDO body, the first end of the adjustable resistor sub-module is coupled to the negative phase input end of the LDO body, the second end of the adjustable resistor sub-module is coupled to the output end of the LDO body, and the timing trigger circuit is coupled to the control end of the adjustable resistor sub-module to adjust the output voltage of the LDO module.

[0018] Optionally, the adjustable resistor submodule includes a first voltage divider circuit and a second voltage divider circuit, wherein a first end of the first voltage divider circuit is coupled to the output end of the LDO body, a second end of the first voltage divider circuit, a first end of the second voltage divider circuit, and a negative input end of the LDO body are coupled, and a second end of the second voltage divider circuit is connected to a reference ground;

[0019] The first voltage-dividing circuit and the second voltage-dividing circuit have the same structure, and both include first voltage-dividing units, the same number as the monostable trigger modules of the timing trigger circuit, connected in series; the first voltage-dividing unit includes a first control switch and a third resistor connected in parallel; the second output end of the monostable trigger module of the timing trigger circuit is coupled one-to-one with the control end of the first control switch of the first voltage-dividing unit of the first voltage-dividing circuit or the second voltage-dividing circuit.

[0020] Optionally, the bandgap reference voltage circuit includes an electrically connected bandgap reference voltage generating body and an adjustable voltage output module, wherein the bandgap reference voltage generating body and the adjustable voltage output module are coupled between the second power supply voltage and a reference ground;

[0021] The input end of the adjustable voltage output module is coupled to the output end of the bandgap reference voltage generating body, the output end of the adjustable voltage output module is coupled to the positive input end of the LDO module, the negative input end of the LDO module is coupled to its output end, and the timing trigger circuit is coupled to the control end of the adjustable voltage output module to adjust the output voltage of the bandgap reference voltage circuit.

[0022] Optionally, the adjustable voltage output module includes the same number of second voltage dividing units as the monostable trigger modules of the timing trigger circuit, and each of the second voltage dividing units includes a fourth resistor and a second control switch;

[0023] The first end of the fourth resistor of the first second voltage divider unit is coupled to the output end of the bandgap reference voltage generating body, the second end of the fourth resistor of the adjacent previous second voltage divider unit is coupled to the first end of the fourth resistor of the next second voltage divider unit, and the second end of the fourth resistor of the last second voltage divider unit is coupled to the reference ground. The first end and the second end of the second control switch of each second voltage divider unit are respectively coupled to the first end / second end of its fourth resistor and the non-inverting input end of the LDO module. The control end of the second control switch of each second voltage divider unit is coupled one-to-one with the second output end of the monostable trigger module of the timing trigger circuit.

[0024] Optionally, the bias voltage adjustment device further includes a filter circuit, a first end of the filter circuit is coupled to the output end of the bandgap reference voltage circuit, a second end of the filter circuit is coupled to the positive phase input end of the LDO module, and a third end of the filter circuit is grounded.

[0025] Optionally, the filtering circuit includes a fifth resistor and a third capacitor, the first end of the fifth resistor is coupled to the output end of the bandgap reference voltage circuit, the second end of the fifth resistor, the first end of the third capacitor and the positive phase input end of the LDO module are coupled, and the second end of the third capacitor is coupled to the reference ground.

[0026] Optionally, the timing trigger circuit further includes a signal receiving trigger module, a counter module and a first AND gate, wherein the number of the first AND gates is less than or equal to the number of the monostable trigger modules; the first input terminal of the signal receiving trigger module is used to receive the input signal, the output terminal of the signal receiving trigger module is coupled to the input terminal of the first-stage monostable trigger module, the first input terminal of the first AND gate is used to receive the input signal, the second input terminal of the first AND gate is coupled to the first output terminal of the adjacent previous-stage monostable trigger module, and the output terminal of the first AND gate is coupled to the input terminal of the next-stage monostable trigger module; the first output terminal of the last-stage monostable trigger module is coupled to the first terminal of the counter module and the second input terminal of the signal receiving trigger module, so as to realize cyclic triggering of the first-stage monostable trigger module and the subsequent-stage monostable trigger modules through the signal receiving trigger module; the second terminal of the counter module is coupled between the negative phase input terminal of the LDO module and the output terminal of the LDO module and / or between the output terminal of the bandgap reference voltage circuit and the positive phase input terminal of the LDO module, so as to adjust the output voltage of the LDO module.

[0027] Optionally, the signal receiving trigger module includes a signal trigger, a second AND gate and an OR gate, the input end of the signal trigger and the first input end of the second AND gate are used to receive the input signal, the output end of the signal trigger is coupled to the first input end of the OR gate, the second input end of the second AND gate is coupled to the second end of the counter module, the output end of the second AND gate is coupled to the second input end of the OR gate, and the output end of the OR gate is coupled to the input end of the first-stage monostable trigger module.

[0028] In order to achieve the above object, the present invention further provides a power amplifier, which includes the bias voltage adjustment device described in any one of the above items and a power amplifier tube, and the bias voltage adjustment device is used to adjust the bias voltage of the power amplifier tube.

[0029] In order to achieve the above object, the present invention further provides an electronic device, which includes any of the above-mentioned timing trigger circuits, any of the above-mentioned bias voltage adjustment devices, or the above-mentioned power amplifier.

[0030] Compared with the prior art, the timing trigger circuit, bias voltage adjustment device, power amplifier and electronic equipment provided by the present invention have the following advantages:

[0031] The timing trigger circuit provided by the present invention includes multiple cascaded monostable trigger modules. With such configuration, the timing trigger circuit provided by the present invention can achieve fine control of multiple output voltages and the output duration of each output voltage by setting the parameters of each monostable trigger module, so as to meet various requirements such as pulse width adjustment, timing, shaping and delay, thereby improving control accuracy and system stability; further, the monostable trigger module of the timing trigger circuit provided by the present invention includes a monostable trigger body and a reset unit, and the reset unit can realize a low-level reset function, thereby ensuring stable reset while also improving anti-interference performance; further, the timing trigger circuit provided by the present invention, when the first-stage monostable trigger module is triggered by the input signal, the second output end of the first-stage monostable trigger module outputs a first high level with a duration of T1, and when the first high level ends, the second output end of the second-stage monostable trigger module is triggered to output a second high level with a duration of T2, and so on, and so on, until the second output end of the last-stage monostable trigger module outputs a duration of T n Thus, the timing trigger circuit provided by the present invention can improve the problems of slow PVT rise speed and power drop over time in long packets. It can be applied to different types of power amplifiers, compensate for long and short packets without affecting LNA performance, optimize its dynamic EVM, and significantly reduce the design difficulty of power amplifiers.

[0032] Furthermore, since the bias voltage adjustment device, power amplifier and electronic device provided by the present invention belong to the same inventive concept as the timing trigger circuit provided by the present invention, the bias voltage adjustment device, power amplifier and electronic device provided by the present invention have at least all the advantages of the timing trigger circuit provided by the present invention. For details about the beneficial effects of the bias voltage adjustment device, power amplifier and electronic device provided by the present invention, please refer to the above description of the beneficial effects of the timing trigger circuit provided by the present invention, and no further details will be given here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A structural block diagram of a specific example of a power amplifier in the prior art;

[0034] Figure 2a A schematic diagram of the overall structure of the timing trigger circuit provided in the first embodiment of the present invention;

[0035] Figure 2b A schematic diagram of the circuit structure of a monostable trigger module of the timing trigger circuit provided in the first embodiment of the present invention;

[0036] Figure 2c A schematic diagram of the simulation results of the output voltage waveform of the timing trigger circuit provided in the first embodiment of the present invention;

[0037] Figure 3a A schematic diagram of a bias voltage adjustment device according to a second embodiment of the present invention;

[0038] Figure 3b A schematic structural diagram of a bias voltage adjustment device provided in a second embodiment of the present invention;

[0039] Figure 3c Schematic diagram of waveform simulation results of the output voltage of the bias voltage adjustment device and the output voltage of the timing trigger circuit provided in the second embodiment of the present invention;

[0040] Figure 4 A schematic structural diagram of a bias voltage adjustment device provided in a third embodiment of the present invention;

[0041] Figure 5 A schematic structural diagram of a bias voltage adjustment device provided in a fourth embodiment of the present invention;

[0042] Figure 6a A schematic structural diagram of a specific example of a timing trigger circuit of a bias voltage adjustment device provided in a fifth embodiment of the present invention;

[0043] Figure 6b A schematic structural diagram of a bias voltage adjustment device provided in a fifth embodiment of the present invention;

[0044] Figure 6c Schematic diagram of waveform simulation results of the output voltage of the bias voltage adjustment device and the output voltage of the timing trigger circuit provided in the fifth embodiment of the present invention;

[0045] Figure 7 A structural block diagram of a power amplifier provided in Embodiment 6 of the present invention;

[0046] The accompanying drawings are numerals as follows:

[0047] Input matching circuit 110, power amplifier tube 120, output matching circuit 130, bias circuit 140;

[0048] Timing trigger circuit-200; Monostable trigger module-M1, M2, M n-1 、M n ;

[0049] Reset unit 211, first inverter INV1, second inverter INV2, first MOS transistor N1, second MOS transistor N2;

[0050] Monostable trigger body 212, delay unit 2121, first capacitor C1, first resistor R1, logic trigger unit 2122, NOR gate NOR, second capacitor C2, second resistor R2, third inverter INV3, fourth inverter INV4, fifth inverter INV5;

[0051] Signal receiving trigger module 213, signal trigger M0, second AND gate 2131, OR gate 2132; counter module 214, first AND gate 215;

[0052] Input signal-PA_EN, first power supply voltage-VCC1, second power supply voltage-VCC2;

[0053] LDO module-300, LDO body-310, adjustable resistor submodule-320, first voltage divider circuit-321, second voltage divider circuit-322, first voltage divider units-3211, 3221, first control switches-A1, A2, A n , B1, B2, B n , the third resistor - R A1 、R A2 , R An 、R B1 、R B2 , R Bn ;

[0054] Bandgap reference voltage circuit-400, bandgap reference voltage generating body-410;

[0055] Adjustable voltage output module-420, second voltage divider unit-421, fourth resistor-R bg1 , Rbg2, Rbgn, second control switch-N bg1 、N bg2 、N bgn ;

[0056] Filter circuit - RC, fifth resistor - Rf, third capacitor - Cf;

[0057] Bias voltage adjustment device -Bias. DETAILED DESCRIPTION

[0058] The following, in conjunction with the accompanying drawings, further details the timed trigger circuit, bias voltage adjustment device, power amplifier, and electronic device proposed by the present invention. The following description will further clarify the advantages and features of the present invention. It should be noted that the drawings are simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of the embodiments of the present invention. To make the purposes, features, and advantages of the present invention more readily apparent, please refer to the drawings. It should be noted that the structures, proportions, and sizes illustrated in the drawings herein are intended solely to facilitate understanding and reading by those skilled in the art, and are not intended to limit the implementation of the present invention. Any structural modifications, changes in proportions, or adjustments in size, provided they produce the same or similar effects and achieve the same objectives, are still within the scope of the technical content disclosed herein. The specific design features of the present invention disclosed herein, including, for example, specific dimensions, directions, positions, and shapes, will be determined in part by the specific application and environment in which they are intended. Furthermore, in the embodiments described below, the same reference numerals may be used across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions may be omitted. In this specification, similar reference numerals and letters are used to refer to similar items, so once an item is defined in one figure, it need not be further discussed in subsequent figures. In addition, if the method described herein includes a series of steps, the order in which the steps are presented herein is not necessarily the only order in which the steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0059] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element. The singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features.

[0060] It should be understood that when an element is referred to as being "connected," "connected to," or "coupled to" another element, it can be directly connected to the other element or there can be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly connected to" another element, there are no intervening elements.

[0061] The core concept of the present invention is to provide a timing trigger circuit, bias voltage adjustment device, power amplifier, and electronic equipment. The present invention can improve the problems of slow PVT rise speed and long packet power drop over time. It is applicable to different types of power amplifiers, compensates for long and short packets without affecting LNA performance, optimizes its dynamic EVM, and can significantly reduce the design difficulty of the power amplifier.

[0062] It should be noted that the timing trigger circuit provided by the present invention can be used in the bias voltage adjustment device, power amplifier and electronic device provided by the present invention, and the bias voltage adjustment device and power amplifier provided by the present invention can be used in the electronic device provided by the present invention. By way of example, the electronic devices include but are not limited to video products such as televisions, video recorders and digital cameras, communication products such as mobile phones, communication switching equipment and communication transmission equipment, and learning assistance products such as translators, learning machines and electronic dictionaries, etc., without giving a full list of examples. Those skilled in the art should understand that the present invention does not impose any limitation on the electronic devices.

[0063] Furthermore, to facilitate understanding of the present invention, unless otherwise specified, this document uses the timing trigger circuit provided by the present invention applied to a bias voltage adjustment device, and the bias voltage adjustment device applied to a power amplifier as an example. However, this is clearly not a limitation of the present invention. The timing trigger circuit provided by the present invention can be applied to any scenario where a voltage waveform needs to change over time, including but not limited to bias voltage adjustment devices and segmented switches. The bias voltage adjustment device provided by the present invention can be used in, including but not limited to, power amplifiers, oscillators, and modulators.

[0064] Example 1

[0065] This embodiment provides a timing trigger circuit. For example, see Figure 2a and Figure 2b ,in, Figure 2a This is a schematic diagram of the overall structure of the timing trigger circuit provided in this embodiment, Figure 2b This is a schematic diagram of the circuit structure of a monostable trigger module of the timing trigger circuit provided in this embodiment. Figure 2a and Figure 2b It can be seen that the timing trigger circuit provided in this embodiment includes at least two cascaded monostable trigger modules (( Figure 2a In the figure, n monostable trigger modules M1, M2, M n-1 、M n , n≥2), the input terminal IN of the first-stage monostable trigger module M1 is used to receive the input signal PA_EN, and the adjacent previous-stage monostable trigger modules M1, M2, ..., M n-1 The first output terminal is coupled to the monostable trigger module M2, ..., M n Further, if Figure 2b ( Figure 2b The first monostable trigger module M i As shown in an example, 1≤i≤n), each monostable trigger module includes a monostable trigger body 212 and a reset unit 211 electrically connected to the monostable trigger body 212 and used to implement a low-level reset. The monostable trigger body 212 and the reset unit 211 are coupled between a first power supply voltage VCC1 and a reference ground; a common point between an input terminal of the monostable trigger body 212 and a first terminal of the reset unit 211 serves as the monostable trigger module M. i The input terminal IN of the monostable trigger body 212 serves as the first output terminal of the monostable trigger module M i The first output terminal OUT of the monostable trigger body 212 as the second output terminal of the monostable trigger module M i The second output terminal A i / Bi To provide output voltage, and the monostable trigger module M i The first output terminal OUT and the second output terminal A i / B i The output level signal is opposite. For further information, see Figure 2c , Figure 2c This is a schematic diagram of the simulation results of the output voltage waveform of the timing trigger circuit provided in this embodiment. Figure 2c As shown, the timing trigger circuit is configured such that when the first-stage monostable trigger module M1 is triggered by the input signal PA_EN, the second output terminal A1 / B1 of the first-stage monostable trigger module M1 outputs a first high level with a duration of T1, and when the first high level ends, the second output terminal A2 / B2 of the second-stage monostable trigger module M2 is triggered to output a second high level with a duration of T2, and so on, until the last-stage monostable trigger module M n The second output terminal output duration is T n The nth high level of , where n is the number of the monostable trigger modules.

[0066] The timing trigger circuit provided by the present invention includes a plurality of cascaded monostable trigger modules. With such a configuration, the timing trigger circuit provided by the present invention can be configured to generate a plurality of cascaded monostable trigger modules. i The parameters of the monostable trigger body 212 (specifically, the monostable trigger body 212) realize fine control of each output voltage and the output duration of each output voltage to meet various requirements such as pulse width adjustment, timing, shaping and delay, thereby improving control accuracy and system stability; further, the monostable trigger module of the timing trigger circuit provided by the present invention includes the monostable trigger body 212 and the reset unit 211, and the reset unit 211 can realize a low-level reset function, thereby ensuring stable reset while also improving anti-interference performance; further, the timing trigger circuit provided by the present invention, when the first-stage monostable trigger module M i Triggered by the input signal PA_EN, the second output terminal A1 / B1 of the first-stage monostable trigger module M1 outputs a first high level with a duration of T1. When the first high level ends, the second output terminal A2 / B2 of the second-stage monostable trigger module M2 is triggered to output a second high level with a duration of T2. In this way, the second output terminal A3 / B3 of the third-stage monostable trigger module M3, the second output terminal A4 / B4 of the fourth-stage monostable trigger module M4, etc. are triggered in sequence to output the third high level, the fourth high level, etc. with a duration of T3, T4, etc., until the last-stage monostable trigger module M n The second output terminal A n / B nThe output duration is nth high level Tn. Thus, the timing trigger circuit provided by the present invention can improve the problems of slow PVT rise and power drop over time for long packets. It is applicable to different types of power amplifiers, compensating for long and short packets without affecting LNA performance, optimizing its dynamic EVM, and significantly reducing the design difficulty of power amplifiers.

[0067] For example, please see Figure 2c , Figure 2c In the middle, T1, T2, T3, T4, ..., T n Respectively represent the monostable trigger modules M1, M2, M3, M4, ..., M n The timing time of A1 / B1, A2 / B2, A3 / B3, A4 / B4, ..., An / Bn corresponds to the waveforms of the first, second, third, fourth, ..., monostable trigger modules M1, M2, M3, M4, ..., M n The voltage waveform output from the second output terminal is Figure 2c It can be seen that when the input signal PA_EN of the power amplifier changes from low to high, the first-stage monostable trigger module M1 is triggered, and the second output terminal A1 / B1 of the first-stage monostable trigger module M1 outputs the first high level for a duration of T1. When the first high level ends, a rising edge will appear at the first output terminal of the first-stage monostable trigger module M1 (the level signals output by the first output terminal and the second output terminal are opposite), and the second-stage monostable trigger module M2 is triggered, and the second output terminal A2 / B2 of the monostable trigger module M2 outputs the second high level for a duration of T2. And so on, to the n-th stage monostable trigger module M n The output time of the second output terminal An / Bn is T n The n-th high level of A1 / B1, A2 / B2, ..., An / Bn can be used to control the voltage required at the corresponding time point.

[0068] It should be noted that those skilled in the art should be able to understand that the present invention does not impose too many restrictions on the specific number of the monostable trigger modules and the output voltage value and output duration of each monostable trigger module. When applying the present invention, reasonable selection should be made according to actual needs.

[0069] For example, in some exemplary embodiments, please continue to refer to Figure 2b ,like Figure 2b As shown, the monostable trigger body 212 includes a delay unit 2121 and a logic trigger unit 2122; the common point of the first end of the delay unit 2121 and the first end of the reset unit 211 forms the monostable trigger module M iThe first end of the logic trigger unit 2122 and the second end of the reset unit 211 are coupled to the input end of the monostable trigger body 212, the second end of the delay unit 2121, the first end of the logic trigger unit 2122 and the second end of the reset unit 211 are coupled, the second end of the logic trigger unit 2122 is coupled to the third end of the reset unit 211, the third end and the fourth end of the logic trigger unit 2122 serve as the first output end and the second output end of the monostable trigger body 212, respectively; the fifth end of the logic trigger unit 2122 is coupled to the fourth end of the reset unit 211 for receiving the first power supply voltage VCC1, the third end of the delay unit 2121 and the fifth end of the reset unit 211 are coupled to the reference ground.

[0070] The monostable trigger body 212 of the monostable trigger module of the timing trigger circuit provided by the present invention includes a delay unit 2121 and a logic trigger unit 2122. Therefore, the parameters of the delay unit 2121 can be designed as needed to control the output duration of the output voltage, and the parameters of the logic trigger unit 2122 can be designed to achieve fine control of the output voltage.

[0071] It should be noted that those skilled in the art will appreciate that the design of the monostable trigger body 212, including the delay unit 2121 and the logic trigger unit 2122, is merely an exemplary description of a preferred embodiment and does not limit the present invention. For example, in other embodiments, the monostable trigger body 212 may also employ, but is not limited to, a differential monostable trigger and an integrated monostable trigger. For more detailed information about the monostable trigger body 212, please refer to the relevant information on monostable triggers known to those skilled in the art. Due to space limitations, this article does not elaborate on this in detail.

[0072] For example, in some exemplary embodiments, please continue to refer to Figure 2b ,like Figure 2bAs shown, the reset unit 211 includes a first inverter INV1, a second inverter INV2, a first MOS transistor N1, and a second MOS transistor N2; the input end of the first inverter INV1 is used to receive an input signal (the input signal 212 of the monostable trigger body of the first-stage monostable trigger module M1 is PA_EN, and the input signal 212 of the monostable trigger body of the other-stage monostable trigger module M1 is the output signal of the first output end of the previous stage), the output end of the first inverter INV1, the input end of the second inverter INV2, and the gate of the first MOS transistor N1 are coupled, the output end of the second inverter INV2 is coupled to the gate of the second MOS transistor N2, the second end of the delay unit 2121, the first end of the first MOS transistor N1, and the first end of the logic trigger unit 2122 are coupled, the first end of the second MOS transistor N2 is coupled to the second end of the logic trigger unit 2122, the second end of the second MOS transistor N2 is used to receive the first supply voltage VCC1, and the second end of the first MOS transistor N1 is coupled to the reference ground.

[0073] Therefore, the monostable trigger module reset unit 211 of the timing trigger circuit provided by the present invention adopts the design of the first inverter INV1, the second inverter INV2, the first MOS transistor N1 and the second MOS transistor N2, which is simple in logic and easy to implement.

[0074] It should be understood that the present invention does not impose excessive restrictions on the first MOS transistor N1 and the second MOS transistor N2. For example, the first MOS transistor N1 and the second MOS transistor N2 can be, but are not limited to, NMOS transistors and PMOS transistors. It should also be noted that those skilled in the art should understand that the design of the reset unit 211 implemented herein using the first inverter INV1, the second inverter INV2, the first MOS transistor N1, and the second MOS transistor N2 is merely an exemplary description of a preferred embodiment and is not a limitation of the present invention. For example, in other embodiments, a reset circuit or reset chip composed of a resistor, a capacitor, and a diode may also be used.

[0075] For example, in some exemplary embodiments, please continue to refer to Figure 2b ,like Figure 2b As shown, the delay unit 2121 includes a first capacitor C1 and a first resistor R1. The first end of the first capacitor C1 is used to receive an input signal (the input signal 212 of the monostable trigger body of the first-stage monostable trigger module M1 is PA_EN, and the input signal of the other-stage monostable trigger modules M i+1 The 212 input signal of the monostable trigger body is the previous level monostable trigger module M iThe output signal of the first output terminal, 1≤i≤n-1), the second terminal of the first capacitor C1 and the first terminal of the first resistor R1 are coupled to the second terminal of the reset unit 211 and the first terminal of the logic trigger unit 2122, and the second terminal of the first resistor R1 is coupled to the reference ground.

[0076] Therefore, the delay unit 2121 of the monostable trigger body 212 of the monostable trigger module of the timing trigger circuit provided by the present invention adopts a design method of the first capacitor C1 and the first resistor R1, which is simple in logic, easy to implement and has low cost; the output duration of the output voltage corresponding to the monostable trigger body 212 can be set by reasonably selecting the parameters of the first capacitor C1 and the first resistor R1.

[0077] It should be noted that, as those skilled in the art can understand, the design of the delay unit 2121 using the first capacitor C1 and the first resistor R1 is only an illustrative description of a preferred embodiment, and is not a limitation of the present invention. For example, in other embodiments, the delay unit 2121 can also be implemented using methods including but not limited to a 555 timer.

[0078] For example, in some exemplary embodiments, please continue to refer to Figure 2b ,like Figure 2b As shown, the logic trigger unit 2122 includes a NOR gate NOR, a second capacitor C2, a second resistor R2, a third inverter INV3, a fourth inverter INV4, and a fifth inverter INV5. The first input terminal of the NOR gate NOR is coupled to the second terminal of the reset unit 211, the second input terminal of the NOR gate NOR, the output terminal of the third inverter INV3, and the input terminal of the fourth inverter INV4 are coupled, the output terminal of the NOR gate NOR is coupled to the first terminal of the second capacitor C2, the second terminal of the second capacitor C2, the first terminal of the second resistor R2, the input terminal of the third inverter INV3, and the third terminal of the reset unit 211 are coupled, a common node of the output terminal of the fourth inverter INV4 and the input terminal of the fifth inverter INV5 serves as the third terminal of the logic trigger unit 2122, and the output terminal of the fifth inverter INV5 serves as the fourth terminal of the logic trigger unit 2122; the second terminal of the second resistor R2 is used to receive the first supply voltage VCC1.

[0079] Therefore, the logic trigger unit 2122 of the monostable trigger body 212 of the monostable trigger module of the timing trigger circuit provided by the present invention adopts a design method of a NOR gate NOR, a second capacitor C2, a second resistor R2, a third inverter INV3, a fourth inverter INV4 and a fifth inverter INV5. The output voltage corresponding to the monostable trigger body 212 can be set by reasonably selecting the parameters of the second resistor R2, and the logic is clear and easy to implement.

[0080] Example 2

[0081] This embodiment provides a bias voltage adjustment device. For example, see Figure 3a , Figure 3a This is a schematic diagram of the bias voltage adjustment device provided in this embodiment. Figure 3a As shown, the bias voltage adjustment device provided in this embodiment includes the timing trigger circuit 200, the bandgap reference voltage circuit 400 and the LDO module 300 described in the above embodiment; the timing trigger circuit 200 is coupled between the negative phase input terminal of the LDO module 300 and the output terminal of the LDO module 300 to adjust the output voltage of the LDO module 300.

[0082] The bias voltage circuit provided by the present invention includes a circuit coupled between the negative phase input terminal of the LDO module 300 and the output terminal of the LDO module 300. In this configuration, the bias voltage circuit can be adjusted by adjusting the monostable trigger modules M1, M2, ..., M n The output voltage and the output duration corresponding to each output voltage are adjusted to achieve the purpose of adjusting the output voltage of the LDO module 300, thereby obtaining the required voltage output waveform. It can be seen that the bias voltage adjustment device provided by the present invention is applicable to various power amplifiers.

[0083] For example, please combine Figure 2a See also Figure 3b , Figure 3b This is a schematic diagram of the structure of the bias voltage adjustment device provided in this embodiment. Figure 3b It can be seen that the LDO module 300 includes an LDO body 310 and an adjustable resistance submodule 320. The output end of the bandgap reference voltage circuit 400 is coupled to the positive phase input end of the LDO body 310. The first end of the adjustable resistance submodule 320 is coupled to the negative phase input end of the LDO body 310. The second end of the adjustable resistance submodule 320 is coupled to the output end of the LDO body 310. The timing trigger circuit 200 is coupled to the control end of the adjustable resistance submodule 320 (for example, Figure 2a Each level of the monostable trigger module M1, M2, ..., M nThe second output terminals A1 / B1, A2 / B2, ..., An / Bn are respectively connected to Figure 3b The first control switches A1, A2, ..., A n , B1, B2, ..., B n ) to adjust the output voltage of the LDO module 300.

[0084] In the bias voltage adjustment device provided by the present invention, the LDO module 300 includes an adjustable resistor submodule 320 coupled between the negative input terminal of the LDO body 310 and the output terminal of the LDO body 310, and the timing trigger circuit 200 is coupled to the control terminal of the adjustable resistor submodule 320. With this configuration, the resistance value of the adjustable resistor submodule 320 can be adjusted by adjusting the output voltage of the timing trigger circuit 200 and the duration corresponding to each output voltage, thereby obtaining the required output voltage of the LDO module 300.

[0085] It should be noted that those skilled in the art should be able to understand that the present invention does not impose too many restrictions on the specific implementation of the LDO body 310. For more detailed information about the LDO body 310, please refer to the relevant technical adaptability understanding of low-dropout linear regulators known to those skilled in the art. Due to space limitations, this article does not elaborate on this.

[0086] For example, in some exemplary embodiments, please continue to refer to Figure 3b ,like Figure 3b As shown, the adjustable resistance submodule 320 includes a first voltage divider circuit 321 and a second voltage divider circuit 322. The first end of the first voltage divider circuit 321 is coupled to the output end of the LDO body 310, the second end of the first voltage divider circuit 321, the first end of the second voltage divider circuit 322, and the negative input end of the LDO body 310 are coupled, and the second end of the second voltage divider circuit 322 is connected to the reference ground. Furthermore, the first voltage divider circuit 321 and the second voltage divider circuit 322 have the same structure and both include the same number of first voltage divider units (such as ) connected in series as the monostable trigger modules of the timing trigger circuit 200. Figure 3b As shown, the first voltage divider circuit 321 includes n first voltage divider units 3211, and the second voltage divider circuit 322 includes n second voltage divider units 3221). Taking the first voltage divider unit 3211 as an example, the first voltage divider unit 3211 includes a first control switch A1 and a third resistor R connected in parallel. A1 The second output terminal of the monostable trigger module of the timing trigger circuit 200 and the first control switch A1, A2, ..., A of the first voltage divider circuit 321 nor the first control switches B1, B2, ..., B1 of the first voltage dividing unit 3211 of the second voltage dividing circuit 322. n The control terminals are coupled one-to-one.

[0087] In the bias voltage adjustment device provided by the present invention, the first voltage divider circuit 321 and the second voltage divider circuit 322 of the adjustable resistor submodule 320 of the LDO module 300 adopt the same circuit structure, with clear logic and easy implementation; further, the first voltage divider circuit 321 / the second voltage divider circuit 322 includes the same number of first voltage divider units 3211 and 3221 as the monostable trigger modules of the timing trigger circuit 200 and connected in series, thereby being able to control the first control switches A1, A2, ..., A2 according to the output voltage of the timing trigger circuit 200 and the duration corresponding to each output voltage. n or B1, B2, ..., B n The on / off of the first voltage divider circuit 321 or the second voltage divider circuit 322 is controlled to control the resistance value, thereby obtaining the required output voltage of the LDO module 300.

[0088] It should be noted that those skilled in the art should be able to understand that the present invention provides the first control switches A1, A2, ..., A n , B1, B2, ..., B n For example, in some exemplary embodiments, the first control switch A1 may be, but is not limited to, an NMOS transistor or a PMOS transistor.

[0089] For example, please see Figure 3b ,according to Figure 3b It can be seen that the output voltage of the LDO module 300 can be calculated by the following formula:

[0090] V reg =(1+R a / R b )*V bg

[0091] In the above formula, Vreg is the output voltage of the LDO module 300 , Ra is the resistance of the first voltage divider circuit 321 , Rb is the resistance of the second voltage divider circuit 322 , and Vbg is the output voltage of the bandgap reference voltage circuit 400 .

[0092] It can be seen from the above formula that when the output voltage of the bandgap reference voltage circuit 400 is fixed, the output voltage of the LDO module 300 can be adjusted by adjusting the resistance value of the first voltage divider circuit 321 or the resistance value of the second voltage divider circuit 322. The monostable trigger modules M1, M2, ..., M n The second output terminals A1 / B1, A2 / B2, ..., A n / B n The output voltage of the LDO module 300 is used to control the first control switches A1, A2, ..., A1 of the first voltage dividing unit 3211 of the first voltage dividing circuit 321 of the adjustable resistance submodule 320 of the LDO module 300. n or the first control switches B1, B2, ..., B1 of the first voltage dividing unit 3221 of the first voltage dividing circuit 322. n On / off: By short-circuiting the third resistor -R of the first voltage divider unit 3211 of the first voltage divider circuit 321 A1 、R A2 ,……,R An The output voltage V of the LDO module 300 can be reduced reg , short-circuit the third resistor R of the first voltage dividing unit 3221 of the first voltage dividing circuit 322 B1 、R B2 ,……,R Bn The output voltage Vreg of the LDO module 300 may be increased.

[0093] It should be noted that the second output terminals A1 / B1, A2 / B2, ..., A n / B n Only one of the first control switches A1, A2, ..., A n , B1, B2, ..., or B n For example, in some embodiments, the first control switches A1, A2, ..., A1 of the first voltage dividing unit 3211 of the first voltage dividing circuit 321 may be connected to the first control switches A1, A2, ..., A1 of the first voltage dividing unit 3211 of the first voltage dividing circuit 321. n The switches are coupled one by one. In other embodiments, the first control switches 1, B2, ..., B1 of the first voltage dividing unit 3221 of the first voltage dividing circuit 322 may also be coupled one by one. n The switches are coupled in a one-to-one correspondence.

[0094] For example, see Figure 3c , Figure 3c Schematic diagram of waveform simulation results of the output voltage of the bias voltage adjustment device and the output voltage of the timing trigger circuit 200 provided in this embodiment. Figure 3c In the example, the waveform indicated by PA_EN is the input signal PA_EN received by the first-stage monostable trigger module M1. Figure 3c The left side of the direction shown shows the monostable trigger module M of each level i The waveform of the output voltage of the second terminal of each monostable trigger module of each stage is coupled to the first control switch of the second output terminal of the first-stage monostable trigger module M1. Specifically, B1 represents the second output terminal A1 / B1 of the first-stage monostable trigger module M1 coupled to the first control switch B1, B2 represents the second output terminal A2 / B2 of the second-stage monostable trigger module M2 coupled to the first control switch B2, A3 represents the second output terminal A3 / B3 of the third-stage monostable trigger module M3 coupled to the first control switch A3, and A4 represents the second output terminal A4 / B4 of the fourth-stage monostable trigger module M4 coupled to the first control switch A4; V reg is the waveform of the output voltage of the LDO module 300. Figure 3c It can be seen that the output of the first control switches A3 and A4 connected to the first voltage divider circuit 321 makes the output voltage V reg The output voltage Vreg of the LDO module 300 is increased, and the first control switch A3 is connected to the first voltage divider circuit 322, and the third resistor R is short-circuited. A3 The resistance value is smaller than the third resistor R corresponding to the first control switch A4 A4 The resistance value of the first control switch B1 corresponds to the short-circuited third resistor R B1 The resistance value is smaller than the third resistor R corresponding to the first control switch B2 B2 Thus, by adjusting the timing of each level of the monostable trigger module and the resistance value of the adjustable resistor submodule 320, the required voltage output waveform can be obtained, and the present invention can be adapted to different power amplifiers.

[0095] Example 3

[0096] This embodiment provides another bias voltage adjustment device. The basic principle of the bias voltage adjustment device provided in this embodiment is similar to that of the bias voltage adjustment device provided in the second embodiment. The basic principle can be found in Figure 3a ,from Figure 3a It can be seen that the bias voltage adjustment device provided in this embodiment also includes the timing trigger circuit 200, the bandgap reference voltage circuit 400, and the LDO module 300 described in the above embodiment. To avoid redundancy, only the differences from the second embodiment are described below. For parts not mentioned in this embodiment, please refer to the relevant description of the second embodiment for an adaptive understanding.

[0097] For example, see Figure 4 , Figure 4 This is a schematic diagram of the structure of the bias voltage adjustment device provided in this embodiment. Figure 4 and Figure 3aAs can be seen, the bias voltage adjustment device provided in this embodiment differs from the second embodiment in that the timing trigger circuit 200 provided in this embodiment is coupled between the output terminal of the bandgap reference voltage circuit 400 and the non-inverting input terminal of the LDO module 300. The bandgap reference voltage circuit 400 includes an electrically connected bandgap reference voltage generator 410 and an adjustable voltage output module 420. The bandgap reference voltage generator 410 and the adjustable voltage output module 420 are coupled between the second supply voltage VCC2 and the reference ground. Furthermore, the input terminal of the adjustable voltage output module 420 is coupled to the output terminal of the bandgap reference voltage generator 410, the output terminal of the adjustable voltage output module 420 is coupled to the non-inverting input terminal of the LDO module 300, and the negative input terminal of the LDO module 300 is coupled to its output terminal. The timing trigger circuit 200 is coupled to the control terminal of the adjustable voltage output module 420 to adjust the output voltage of the bandgap reference voltage circuit 400.

[0098] In the bias voltage adjustment device provided by the present invention, the bandgap reference voltage circuit 400 is coupled to the bandgap reference voltage generating body 410 and the adjustable voltage output module 420 at the non-inverting input terminal of the LDO module 300, and the timing trigger circuit 200 is coupled to the control terminal of the adjustable voltage output module 420. With this configuration, the output voltage of the adjustable voltage output module 420 can be adjusted by adjusting the output voltage of the timing trigger circuit 200 and the duration corresponding to each output voltage, thereby obtaining the desired output voltage of the LDO module 300. Furthermore, this method of adjusting the bandgap reference voltage circuit 400 and thus the output voltage of the LDO module 300 not only increases adjustment flexibility but also allows for dynamic adjustment of the temperature coefficient of the bandgap reference voltage circuit 400.

[0099] It should be noted that those skilled in the art should be able to understand that the present invention does not impose too many restrictions on the specific values ​​of the first power supply voltage VCC1 and the second power supply voltage VCC2, and the values ​​of the first power supply voltage VCC1 and the second power supply voltage VCC2 can be the same or different.

[0100] For example, in some exemplary embodiments, please continue to refer to Figure 4 ,like Figure 4 As shown, the adjustable voltage output module 420 includes the same number of second voltage dividing units 421 as the monostable trigger modules of the timing trigger circuit 200. Taking the nth second voltage dividing unit 421 as an example, the second voltage dividing unit 421 includes a fourth resistor R bgn and the second control switch N bgnFurthermore, the fourth resistor R of the first second voltage dividing unit 421 bg1 The first end of the fourth resistor R is coupled to the output end of the bandgap reference voltage generating body 410, the second end of the fourth resistor of the adjacent previous second voltage dividing unit 421 is coupled to the first end of the fourth resistor of the next second voltage dividing unit 421, and the fourth resistor R of the last second voltage dividing unit 421 is coupled to the output end of the bandgap reference voltage generating body 410. bgn The second end of each second voltage dividing unit 421 is coupled to the reference ground. bg1 The first end and the second end are respectively coupled to the first end / the second end of the fourth resistor Rbg1 and the non-inverting input end of the LDO module 300, and the second control switch N of each second voltage dividing unit 421 bg1 、N bg2 ,……,N bgn The control end of is coupled to the second output ends A1 / B1, A2 / B2, . . . , An / Bn of the monostable trigger module of the timing trigger circuit 200 in a one-to-one correspondence.

[0101] The bias voltage adjustment device provided by the present invention, the adjustable voltage output module 420 of the bandgap reference voltage circuit 400 includes the same number of second voltage dividing units 421 as the monostable trigger modules of the timing trigger circuit 200, and the second control switch N of the second voltage dividing unit 421 bg1 、N bg2 ,……,N bgn The control end of the timing trigger circuit 200 and the monostable trigger modules M1, M2, ..., M n The second output terminals A1 / B1, A2 / B2, ..., An / Bn are coupled one by one, thereby controlling the second control switch N bg1 、N bg2 ,……,N bgn The on-off of the fourth resistor R bg1 , Rbg2, ..., Rbgn to adjust the output voltage V bg , thereby obtaining the output voltage V of the LDO module 300 reg .

[0102] It should be noted that, based on the description herein, those skilled in the art should be able to understand that by coupling the second output terminal of the timing trigger circuit 200 provided by the present invention to the second control switch N corresponding to the adjustable voltage output module 420 of the bandgap reference voltage circuit 400, bg1 、N bg2 ,……,N bgn Different output voltages V can be obtained at different timesbg From the calculation formula (1) of the output voltage of the LDO module 300, it can be seen that by adjusting the output voltage V bg The output voltage V of the LDO module 300 can also be adjusted reg Furthermore, as mentioned above, adopting this approach can not only increase the flexibility of voltage adjustment, but also dynamically adjust the temperature coefficient of the bandgap reference voltage circuit 400, thereby further improving control accuracy.

[0103] It should be noted that those skilled in the art should be able to understand that Figure 4 The specific circuit structure of the bandgap reference voltage generating body 410 given in the specification is only an exemplary description of a preferred embodiment, and is not a limitation of the present invention. The present invention does not impose too many restrictions on the specific implementation method of the bandgap reference voltage generating body 410. For more detailed information about the bandgap reference voltage generating body 410, please refer to the relevant description of the bandgap reference voltage generating circuit known to those skilled in the art for adaptive understanding. No further explanation will be given in this article.

[0104] Example 4

[0105] This embodiment provides another bias voltage adjustment device. The basic principle of the bias voltage adjustment device provided in this embodiment is similar to that of the bias voltage adjustment device provided in the third embodiment. The basic principle can also be found in Figure 3a ,from Figure 3a It can be seen that the bias voltage adjustment device provided in this embodiment also includes the timing trigger circuit 200, the bandgap reference voltage circuit 400, and the LDO module 300 described in the above embodiment. To avoid redundancy, only the differences from the third embodiment are described below. For parts not mentioned in this embodiment, please refer to the relevant description of the third embodiment for an adaptive understanding.

[0106] For example, see Figure 5 , Figure 5 This is a schematic diagram of the structure of the bias voltage adjustment device provided in this embodiment. Figure 5 It can be seen that the bias voltage adjustment device provided in this embodiment further includes a filter circuit RC, a first end of the filter circuit RC is coupled to the output end of the bandgap reference voltage circuit 400, a second end of the filter circuit RC is coupled to the non-inverting input end of the LDO module 300, and a third end of the filter circuit RC is grounded. Thus, the bias voltage adjustment device provided by the present invention, by coupling the filter circuit RC between the output end of the bandgap reference voltage circuit 400 and the non-inverting input end of the LDO module 300, adjusts the output voltage V reg During the switching process, the output voltage V regThe waveform becomes smoother, which can further improve the performance of the power amplifier.

[0107] For example, in some exemplary embodiments, please continue to refer to Figure 5 ,like Figure 5 As shown, the filter circuit RC includes a fifth resistor Rf and a third capacitor Cf. The first end of the fifth resistor Rf is coupled to the output end of the bandgap reference voltage circuit 400. The second end of the fifth resistor Rf, the first end of the third capacitor Cf, and the non-inverting input end of the LDO module 300 are coupled. The second end of the third capacitor Cf is coupled to the reference ground. It should be noted that Figure 5 The design of the filter circuit RC using the fifth resistor Rf and the third capacitor Cf is merely an example of a preferred embodiment and is not intended to limit the present invention. The present invention does not impose any particular limitations on the specific implementation of the filter circuit RC. For example, in other embodiments, an inductor filter circuit RC and an inductor-capacitor filter circuit RC may also be used, including but not limited to.

[0108] Example 5

[0109] This embodiment provides another bias voltage adjustment device. The basic principle of the bias voltage adjustment device provided in this embodiment is similar to that of the bias voltage adjustment device provided in the fourth embodiment. The basic principle can also be found in Figure 3a ,from Figure 3a It can be seen that the bias voltage adjustment device provided in this embodiment also includes the timing trigger circuit 200, bandgap reference voltage circuit 400, and LDO module 300 described in the above embodiment. The timing trigger circuit 200 of the bias voltage adjustment device provided in this embodiment has a different structure. To avoid redundancy, only the differences from the fourth embodiment are described below. For parts not mentioned in this embodiment, please refer to the relevant description of the fourth embodiment for an adaptive understanding.

[0110] For example, see Figure 6a and Figure 6b ,in, Figure 6a This is a structural diagram of a specific example of a timing trigger circuit of the bias voltage adjustment device provided in this embodiment. Figure 6b This is a schematic diagram of the structure of the bias voltage adjustment device provided in this embodiment. Figure 6a and Figure 6bIt can be seen that the timing trigger circuit 200 of the bias voltage adjustment device provided in this embodiment further includes a signal receiving trigger module 213, a counter module 214 and a first AND gate 215. The number of the first AND gates 215 is less than or equal to the number of the monostable trigger modules; the first input end of the signal receiving trigger module 213 is used to receive the input signal PA_EN, the output end of the signal receiving trigger module 213 is coupled to the input end of the first-stage monostable trigger module M1, the first input end of the first AND gate 215 is used to receive the input signal PA_EN, the second input end of the first AND gate 215 is coupled to the first output end of the adjacent previous-stage monostable trigger module, and the output end of the first AND gate 215 is coupled to the input end of the next-stage monostable trigger module; the last-stage monostable trigger module M n The first output terminal of the counter module 214 is coupled to the first terminal of the counter module 214 and the second input terminal of the signal receiving trigger module 213, so as to realize the cyclic triggering of the first-stage monostable trigger module M1 and the subsequent stages of the monostable trigger modules through the signal receiving trigger module 213; the second terminal of the counter module 214 is coupled between the negative phase input terminal of the LDO module 300 and the output terminal of the LDO module 300 and / or between the output terminal of the bandgap reference voltage circuit 400 and the positive phase input terminal of the LDO module 300, so as to adjust the output voltage of the LDO module. For example, Figure 6b The second end of the counter module 214 is coupled to the control end of the first control switch of one of the first voltage dividing units 3211 of the second voltage dividing circuit 322 to short-circuit the third resistor (such as R B1 ) example.

[0111] The bias voltage adjustment device provided by the present invention includes a signal receiving trigger module 213, a counter module 214 and a first AND gate 215, and the last stage monostable trigger module M n The first output terminal of the counter module 214 is coupled to the first terminal of the counter module 214 and the second input terminal of the signal receiving trigger module 213, and the output terminal of the signal receiving trigger module 213 is coupled to the input terminal of the first-stage monostable trigger module M1, thereby making the last-stage monostable trigger module M nThe output of the first-stage monostable trigger module M1 can be fed back to form a cyclic trigger, forming a cyclic oscillator. Furthermore, the inputs of the monostable trigger modules of all stages except the first-stage monostable trigger module M1 (i.e., the output signals of the monostable trigger modules of the previous stage) are ANDed with the input signal PA_EN via the first AND gate 215, thereby implementing a reset function in non-PA (power amplifier) ​​mode. Furthermore, the initial triggering is achieved by the signal receiving trigger module 213, thereby performing an oscillation start-up function and achieving better stability. Furthermore, the cyclic oscillator is implemented based on the existing timing circuit, eliminating the need for additional circuitry and facilitating implementation. It is only enabled in PA mode (i.e., when the input signals PA_EN and PA_EN are high), thus avoiding the degradation of the noise figure in receive mode (RX mode) caused by the signal receiving trigger module 213 (more specifically, the signal trigger M0 of the signal receiving trigger module 213) being constantly open. Furthermore, by reasonably setting the timing time of each cascaded monostable trigger module, the required period of the cyclic oscillator can be obtained, and long-period (N*T, N is the counting multiple of the counter module 214, and T is the period of the cyclic oscillator) timing can be achieved through the counting multiple of the counter module 214.

[0112] For example, in some exemplary embodiments, please continue to refer to Figure 6a ,like Figure 6a As shown, the signal receiving trigger module 213 includes a signal trigger M0, a second AND gate 2131 and an OR gate 2132. The input end of the signal trigger M0 and the first input end of the second AND gate 2131 are used to receive the input signal PA_EN, the output end of the signal trigger M0 is coupled to the first input end of the OR gate 2132, the second input end of the second AND gate 2131 is coupled to the second end of the counter module 214, the output end of the second AND gate 2131 is coupled to the second input end of the OR gate 2132, and the output end of the OR gate 2132 is coupled to the input end of the first-stage monostable trigger module M1.

[0113] For example, please see Figure 6b, taking the bias voltage adjustment device provided by the present invention applied to a power amplifier as an example, according to the description in this article, the bias voltage adjustment device provided in Example 2, Example 3 and Example 4 is preferably for a short time after the power amplifier is started (mainly acting in the first few tens of us). This is because for scenarios where a long packet needs to be supplemented to achieve long-term timing, the delay unit 2121 of the monostable trigger module (such as the first resistor R1 and the first capacitor C1 and other devices) must use a very large value, which may occupy a very large layout area. This implementation method is not cost-effective. Normally, the long packet time of the Wifi modulation waveform is in the millisecond level, and the thermal characteristics of the power amplifier itself cause its gain to show a downward trend after establishment. Therefore, after a period of time, it is necessary to provide the output voltage of the bias voltage adjustment device to compensate for the gain drop of the power amplifier. The bias voltage adjustment device provided in Example 5 of this article is preferred. For example, please continue to refer to Figure 6a 、 6b and 6c, where Figure 6c Schematic diagram of waveform simulation results of the output voltage of the bias voltage adjustment device and the output voltage of the timing trigger circuit 200 provided in this embodiment. , n-th level monostable trigger module M n After the output voltage OUT_N becomes high and flat, a portion of the third resistor (such as R B1 ), can increase the output voltage V reg . Figure 6c Only the scenario of replenishing once is shown. If the output voltage needs to be increased multiple times, the counting times of the N-fold counter can be increased to obtain a longer period of timing.

[0114] Example 6

[0115] This embodiment provides a power amplifier. For example, see Figure 7 , Figure 7 This is a structural block diagram of the power amplifier provided in this embodiment. Figure 7 It can be seen that the power amplifier provided by this embodiment includes the bias voltage adjustment device Bias and the power amplifier tube 120 described in any of the above embodiments, and the bias voltage adjustment device Bias is used to adjust the bias voltage of the power amplifier tube 120. Since the power amplifier provided by the present invention includes the bias voltage adjustment device provided by the present invention, according to the above description, the power amplifier provided by the present invention can improve the problems of slow PVT rise rate and long packet power drop over time. It can be applied to different types of power amplifiers, compensate for long and short packets without affecting LNA performance, optimize its dynamic EVM, and significantly reduce the design difficulty of the power amplifier.

[0116] For more detailed information about the power amplifier, please refer to the relevant technologies known to those skilled in the art. Due to space limitations, this article will not elaborate on this.

[0117] Example 7

[0118] This embodiment provides an electronic device, which includes the timing trigger circuit described in any of the above embodiments, the bias voltage adjustment device described in any of the above embodiments, or the power amplifier described in any of the above embodiments.

[0119] Since the electronic device provided by the present invention belongs to the same inventive concept as the timing trigger circuit, bias voltage adjustment device or power amplifier provided by the present invention, and the bias voltage adjustment device or power amplifier provided by the present invention belongs to the same inventive concept as the timing trigger circuit provided by the present invention, the electronic device provided by the present invention has at least all the advantages of the timing trigger circuit provided by the present invention. For details about the beneficial effects of the electronic device provided by the present invention, please refer to the above description of the beneficial effects of the timing trigger circuit provided by the present invention, and no further details will be given here.

[0120] It should be noted that the devices and methods disclosed in the embodiments of this document may also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of the devices, methods, and computer program products according to the various embodiments of this document. In this regard, each box in the flowchart or block diagram may represent a module, program, or portion of code, wherein the module, program segment, or portion of code contains one or more executable instructions for implementing a specified logical function, and the module, program segment, or portion of code contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the boxes may also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes may actually be executed substantially in parallel, or they may sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified function or action, or may be implemented by a combination of dedicated hardware and computer instructions.

[0121] In addition, the functional modules in the various embodiments of this document may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0122] Compared with the prior art, the timing trigger circuit, bias voltage adjustment device, power amplifier and electronic equipment provided by the present invention have the following advantages:

[0123] The timing trigger circuit provided by the present invention includes multiple cascaded monostable trigger modules. With such configuration, the timing trigger circuit provided by the present invention can achieve fine control of multiple output voltages and the output duration of each output voltage by setting the parameters of each monostable trigger module, so as to meet various requirements such as pulse width adjustment, timing, shaping and delay, thereby improving control accuracy and system stability; further, the monostable trigger module of the timing trigger circuit provided by the present invention includes a monostable trigger body and a reset unit, and the reset unit can realize a low-level reset function, thereby ensuring stable reset while also improving anti-interference performance; further, the timing trigger circuit provided by the present invention, when the first-stage monostable trigger module is triggered by the input signal, the second output end of the first-stage monostable trigger module outputs a first high level with a duration of T1, and when the first high level ends, the second output end of the second-stage monostable trigger module is triggered to output a second high level with a duration of T2, and so on, and so on, until the second output end of the last-stage monostable trigger module outputs a duration of T n Thus, the timing trigger circuit provided by the present invention can improve the problems of slow PVT rise speed and power drop over time in long packets. It can be applied to different types of power amplifiers, compensate for long and short packets without affecting LNA performance, optimize its dynamic EVM, and significantly reduce the design difficulty of power amplifiers.

[0124] The foregoing description is merely a description of preferred embodiments of the timing trigger circuit, bias voltage adjustment device, power amplifier, and electronic device provided by the present invention, and does not limit the scope of the present invention in any way. Any changes or modifications made by a person skilled in the art based on the above disclosure are within the scope of protection of the present invention. Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations fall within the scope of the present invention and its equivalents, the present invention is intended to include such modifications and variations.

Claims

1. A timing trigger circuit, characterized in that: The device comprises at least two cascaded monostable trigger modules, wherein the input terminal of the monostable trigger module of the first stage is used to receive an input signal, and the first output terminal of the monostable trigger module of the adjacent previous stage is coupled to the input terminal of the monostable trigger module of the next stage; The monostable trigger module includes a monostable trigger body and a reset unit electrically connected to the monostable trigger body and configured to implement a low-level reset. The monostable trigger body and the reset unit are coupled between a first supply voltage and a reference ground. A common point between an input terminal of the monostable trigger body and a first terminal of the reset unit serves as an input terminal of the monostable trigger module. A first output terminal of the monostable trigger body serves as a first output terminal of the monostable trigger module. A second output terminal of the monostable trigger body serves as a second output terminal of the monostable trigger module to provide an output voltage. The first output terminal and the second output terminal of the monostable trigger module output signals of opposite levels. The timing trigger circuit is configured such that when the first-stage monostable trigger module is triggered by the input signal, the second output terminal of the first-stage monostable trigger module outputs a first high level for a duration of T1, and when the first high level ends, the second output terminal of the second-stage monostable trigger module is triggered to output a second high level for a duration of T2, and so on, until the second output terminal of the last-stage monostable trigger module outputs a second high level for a duration of T n The nth high level of , where n is the number of the monostable trigger modules.

2. The timing trigger circuit according to claim 1, characterized in that: The monostable trigger body includes a delay unit and a logic trigger unit; the common point of the first end of the delay unit and the first end of the reset unit forms the input end of the monostable trigger module, the second end of the delay unit, the first end of the logic trigger unit, and the second end of the reset unit are coupled, the second end of the logic trigger unit is coupled to the third end of the reset unit, and the third and fourth ends of the logic trigger unit serve as the first and second output ends of the monostable trigger body, respectively; the fifth end of the logic trigger unit is coupled to the fourth end of the reset unit for receiving the first supply voltage, and the third end of the delay unit and the fifth end of the reset unit are coupled to the reference ground.

3. The timing trigger circuit according to claim 2, characterized in that: The reset unit includes a first inverter, a second inverter, a first MOS transistor, and a second MOS transistor; the input end of the first inverter is used to receive the input signal, the output end of the first inverter, the input end of the second inverter, and the gate of the first MOS transistor are coupled, the output end of the second inverter is coupled to the gate of the second MOS transistor, the second end of the delay unit, the first end of the first MOS transistor, and the first end of the logic trigger unit are coupled, the first end of the second MOS transistor is coupled to the second end of the logic trigger unit, the second end of the second MOS transistor is used to receive the first power supply voltage, and the second end of the first MOS transistor is coupled to the reference ground.

4. The timing trigger circuit according to claim 2, characterized in that: The delay unit includes a first capacitor and a first resistor, the first end of the first capacitor is used to receive the input signal, the second end of the first capacitor and the first end of the first resistor are coupled to the second end of the reset unit and the first end of the logic trigger unit, and the second end of the first resistor is coupled to the reference ground.

5. The timing trigger circuit according to claim 2, characterized in that: The logic trigger unit includes a NOR gate, a second capacitor, a second resistor, a third inverter, a fourth inverter, and a fifth inverter. The first input terminal of the NOR gate is coupled to the second terminal of the reset unit, the second input terminal of the NOR gate, the output terminal of the third inverter, and the input terminal of the fourth inverter are coupled. The output terminal of the NOR gate is coupled to the first terminal of the second capacitor, the second terminal of the second capacitor, the first terminal of the second resistor, the input terminal of the third inverter, and the third terminal of the reset unit are coupled. A common node of the output terminal of the fourth inverter and the input terminal of the fifth inverter serves as the third terminal of the logic trigger unit, and the output terminal of the fifth inverter serves as the fourth terminal of the logic trigger unit. The second terminal of the second resistor is used to receive the first supply voltage.

6. A bias voltage adjustment device, characterized in that: The device comprises a timing trigger circuit, a bandgap reference voltage circuit, and an LDO module according to any one of claims 1 to 5; the timing trigger circuit is coupled between the negative phase input terminal of the LDO module and the output terminal of the LDO module and / or the timing trigger circuit is coupled between the output terminal of the bandgap reference voltage circuit and the positive phase input terminal of the LDO module to adjust the output voltage of the LDO module.

7. The bias voltage adjustment device according to claim 6, wherein: The LDO module includes an LDO body and an adjustable resistor sub-module. The output end of the bandgap reference voltage circuit is coupled to the positive phase input end of the LDO body. The first end of the adjustable resistor sub-module is coupled to the negative phase input end of the LDO body. The second end of the adjustable resistor sub-module is coupled to the output end of the LDO body. The timing trigger circuit is coupled to the control end of the adjustable resistor sub-module to adjust the output voltage of the LDO module.

8. The bias voltage adjustment device according to claim 7, wherein: The adjustable resistor submodule includes a first voltage divider circuit and a second voltage divider circuit, wherein a first end of the first voltage divider circuit is coupled to the output end of the LDO body, a second end of the first voltage divider circuit, a first end of the second voltage divider circuit, and a negative phase input end of the LDO body are coupled, and a second end of the second voltage divider circuit is connected to a reference ground; The first voltage-dividing circuit and the second voltage-dividing circuit have the same structure, and both include first voltage-dividing units, the same number as the monostable trigger modules of the timing trigger circuit, connected in series; the first voltage-dividing unit includes a first control switch and a third resistor connected in parallel; the second output end of the monostable trigger module of the timing trigger circuit is coupled one-to-one with the control end of the first control switch of the first voltage-dividing unit of the first voltage-dividing circuit or the second voltage-dividing circuit.

9. The bias voltage adjustment device according to claim 6, wherein: The bandgap reference voltage circuit includes an electrically connected bandgap reference voltage generating body and an adjustable voltage output module, wherein the bandgap reference voltage generating body and the adjustable voltage output module are coupled between a second power supply voltage and a reference ground; The input end of the adjustable voltage output module is coupled to the output end of the bandgap reference voltage generating body, the output end of the adjustable voltage output module is coupled to the positive input end of the LDO module, the negative input end of the LDO module is coupled to its output end, and the timing trigger circuit is coupled to the control end of the adjustable voltage output module to adjust the output voltage of the bandgap reference voltage circuit.

10. The bias voltage adjustment device according to claim 9, wherein: The adjustable voltage output module includes the same number of second voltage dividing units as the monostable trigger modules of the timing trigger circuit, and each of the second voltage dividing units includes a fourth resistor and a second control switch; The first end of the fourth resistor of the first second voltage divider unit is coupled to the output end of the bandgap reference voltage generating body, the second end of the fourth resistor of the adjacent previous second voltage divider unit is coupled to the first end of the fourth resistor of the next second voltage divider unit, and the second end of the fourth resistor of the last second voltage divider unit is coupled to the reference ground. The first end and the second end of the second control switch of each second voltage divider unit are respectively coupled to the first end / second end of its fourth resistor and the non-inverting input end of the LDO module. The control end of the second control switch of each second voltage divider unit is coupled one-to-one with the second output end of the monostable trigger module of the timing trigger circuit.

11. The bias voltage adjustment device according to claim 9, wherein: The bias voltage adjustment device further includes a filter circuit, a first end of the filter circuit is coupled to the output end of the bandgap reference voltage circuit, a second end of the filter circuit is coupled to the non-inverting input end of the LDO module, and a third end of the filter circuit is grounded.

12. The bias voltage adjustment device according to claim 11, wherein: The filtering circuit includes a fifth resistor and a third capacitor. The first end of the fifth resistor is coupled to the output end of the bandgap reference voltage circuit, the second end of the fifth resistor, the first end of the third capacitor, and the non-inverting input end of the LDO module are coupled, and the second end of the third capacitor is coupled to the reference ground.

13. The bias voltage adjustment device according to claim 6, wherein: The timing trigger circuit further includes a signal receiving trigger module, a counter module, and a first AND gate, wherein the number of the first AND gates is less than or equal to the number of the monostable trigger modules; the first input terminal of the signal receiving trigger module is used to receive the input signal, the output terminal of the signal receiving trigger module is coupled to the input terminal of the first-stage monostable trigger module, the first input terminal of the first AND gate is used to receive the input signal, the second input terminal of the first AND gate is coupled to the first output terminal of the monostable trigger module of the adjacent previous stage, and the output terminal of the first AND gate is coupled to the input terminal of the monostable trigger module of the next stage; the first output terminal of the monostable trigger module of the last stage is coupled to the first terminal of the counter module and the second input terminal of the signal receiving trigger module, so as to realize cyclic triggering of the first-stage monostable trigger module and the monostable trigger modules of the subsequent stages through the signal receiving trigger module; The second terminal of the counter module is coupled between the negative phase input terminal of the LDO module and the output terminal of the LDO module and / or between the output terminal of the bandgap reference voltage circuit and the positive phase input terminal of the LDO module to adjust the output voltage of the LDO module.

14. The bias voltage adjustment device according to claim 13, wherein: The signal receiving trigger module includes a signal trigger, a second AND gate and an OR gate. The input end of the signal trigger and the first input end of the second AND gate are used to receive the input signal. The output end of the signal trigger is coupled to the first input end of the OR gate. The second input end of the second AND gate is coupled to the second end of the counter module. The output end of the second AND gate is coupled to the second input end of the OR gate. The output end of the OR gate is coupled to the input end of the first-stage monostable trigger module.

15. A power amplifier, characterized in that: It comprises the bias voltage adjustment device according to any one of claims 6 to 14 and a power amplifier tube, wherein the bias voltage adjustment device is used to adjust the bias voltage of the power amplifier tube.

16. An electronic device, characterized in that: It comprises the timing trigger circuit according to any one of claims 1 to 5, the bias voltage adjustment device according to any one of claims 6 to 14, or the power amplifier according to claim 15.

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