Head switch for stacked transistor structures

Abstract

A head switch architecture for a stacked transistor structure includes a first head switch located in an active path, the first head switch configured to provide a supply voltage to a first cascode path; and a second head switch located in the inactive path, the second head switch configured to provide a reduced supply voltage to the second cascode path.

Description

[0001] Related applications

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 445,599, filed on February 14, 2023, entitled “HEAD SWITCH FOR A STACKED TRANSISTOR STRUCTURE,” the contents of which are hereby incorporated by reference in their entirety as if fully set forth below and for all applicable purposes. Technical Field

[0003] The present disclosure relates generally to electronics and, more particularly, to transistors in transceivers. Background Art

[0004] Wireless communication devices and technologies are becoming increasingly common, including those operating in 5G NR Sub6 FR1 and millimeter wave (mmW) FR2 frequencies. Wireless communication devices typically transmit and / or receive communication signals. In a radio frequency (RF) transceiver, communication signals are typically amplified and transmitted by a transmit section, while received communication signals are amplified and processed by a receive section. Communication devices may include multiple transmitters, receivers, and antennas, and are capable of communicating across multiple communication bands and frequencies.

[0005] In some transceivers, it is desirable to achieve good linearity and good signal bandwidth while minimizing the amount of circuit area. One way to minimize circuit area is to use so-called thin-film (or thin-oxide) transistors in certain applications. A specific circuit arrangement of these thin-oxide transistors is known as a stacked transistor structure. One application of this stacked transistor structure can be in mixers and related circuits. Mixers typically upconvert transmit signals and / or downconvert receive signals. Summary of the Invention

[0006] Various implementations of systems, methods, and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the desirable attributes described herein. Without limiting the scope of the appended claims, certain governing features are described herein.

[0007] Details of one or more specific implementations of the subject matter described in this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. Note that the relative dimensions of the following figures may not be drawn to scale.

[0008] One aspect of the present disclosure provides a head switch architecture for a stacked transistor structure, the head switch architecture including: a first head switch located in an active path, the first head switch configured to provide a supply voltage to a first cascode path; and a second head switch located in an inactive path, the second head switch configured to provide a reduced supply voltage to a second cascode path.

[0009] Another aspect of the present disclosure provides a method for biasing a stacked transistor structure, the method comprising: applying a supply voltage to a first cascode path; applying a reduced supply voltage to a second cascode path; and applying a gate voltage to the gate of a cascode transistor in the first cascode path to transition the cascode transistor in the first cascode path from an off and / or standby state to a mission mode state.

[0010] Another aspect of the present disclosure provides a device comprising: means for applying a supply voltage to a first cascode path; means for applying a reduced supply voltage to a second cascode path; and means for applying a gate voltage to a gate of a cascode transistor in the first cascode path to transition the cascode transistor in the first cascode path from an off and / or standby state to a mission mode state.

[0011] Another aspect of the present disclosure provides an apparatus including a first header switching circuit coupled between a supply voltage and a first cascode transistor coupled to a plurality of stacked transistors, the first header switching circuit including a first path coupled between the supply voltage and the first cascode transistor and configured to provide a first voltage to a first node between the first header switching circuit and a terminal of the first cascode transistor, the first header switching circuit also including a second path coupled between the supply voltage and the first cascode transistor and configured to provide a second voltage, lower than the first voltage, to the first node. The apparatus also includes a second header switching circuit coupled between the supply voltage and a second cascode transistor coupled to the plurality of stacked transistors, the second header switching circuit including a third path coupled between the supply voltage and the second cascode transistor and configured to provide a third voltage to a second node between the second header switching circuit and a terminal of the second cascode transistor, the first header switching circuit also including a fourth path coupled between the supply voltage and the second cascode transistor and configured to provide a fourth voltage, lower than the third voltage, to the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with alphabetic characters, such as "102a" or "102b," the alphabetic characters may distinguish between two similar parts or elements in the same figure. Alphabetic characters may be omitted from a reference numeral when it is intended that all parts having the same reference numeral in all figures be included.

[0013] Figure 1 is a diagram illustrating a wireless device communicating with a wireless communication system.

[0014] Figure 2 An example of a wireless device having a transmitter and a receiver is shown.

[0015] Figure 3 is a block diagram showing a circuit, an example of which can be found in Figure 1 implemented in a base station or wireless device Figure 2 part of the transceiver.

[0016] Figure 4 is a diagram showing a circuit, which illustrates Figure 3 A detailed view of a portion of the circuit.

[0017] Figure 5 is a diagram showing a circuit, which illustrates Figure 3 and Figure 4 An exemplary embodiment of a head switch.

[0018] Figure 6 is a diagram showing a circuit, which illustrates the Figure 5 An exemplary embodiment of a desired voltage associated with a header switch.

[0019] Figure 7 is a diagram showing a circuit, which illustrates Figure 5 and Figure 6 An exemplary embodiment of an inactive path head switch.

[0020] Figure 8 is a diagram showing a circuit, which illustrates Figure 3 part of the circuit and Figure 5 Detailed view of an exemplary embodiment of a circuit.

[0021] Figure 9 is a diagram illustrating a circuit according to an exemplary embodiment of the present disclosure.

[0022] Figure 10 is a flow chart describing an example of the operations of a method for biasing a stacked transistor structure.

[0023] Figure 11 is a functional block diagram of an apparatus for biasing a stacked transistor structure. DETAILED DESCRIPTION

[0024] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0025] In a stacked transistor structure, a cascode transistor may be connected to a supply voltage, and successive transistors are connected to the cascode transistor, with the last transistor connected to system ground. When thin oxide transistors are used in such a stacked structure and the supply voltage is relatively high, the bias voltage and the supply voltage may sometimes cause an overvoltage condition in some transistors in the stacked transistor structure. Therefore, it is desirable to have a way to precisely control the voltage applied to the stacked transistor structure.

[0026] A circuit architecture for several different communication circuits (including, for example, mixers, amplifiers, and the like) uses a so-called stacked transistor structure. As the name implies, a stacked transistor structure couples the drains and sources of several transistors between a supply voltage and a system ground. In an exemplary embodiment, the stacked transistor structure may have a cascode transistor connected to the supply voltage and a so-called tail transistor connected to the system ground. Several additional transistors may be connected drain-to-source between the cascode transistor and the tail transistor.

[0027] For example, in a communications mixer, a first (cascode) transistor may have a drain connected to a supply voltage and a source connected to the drain of a second (mixer) transistor. The source of the second (mixer) transistor may be connected to the drain of a third (gain or Gm stage) transistor. The source of the third (Gm) transistor may be connected to the drain of a fourth (tail current source) transistor. The source of the fourth (tail current source) transistor may be connected to system ground. Other stacked transistor structures may also be used; this is just one example.

[0028] In this arrangement, the first transistor may be a cascode transistor, the second transistor may be part of a mixer, the third transistor may be part of a gain stage, and the fourth transistor may provide degeneration and tail currents to the gain stage.

[0029] To provide an acceptable trade-off between linearity and bandwidth, thin-film (also known as thin-oxide) technology is used in many applications to fabricate transistors in a stacked transistor structure. However, it is difficult to reliably bias a stack of four thin-oxide transistor devices using a relatively high (e.g., 1.98V) supply voltage when the transistors are in the on state, in the off state, and during transitions between the off and on states.

[0030] As used herein, the term “head switch” refers to a switch configured to connect and disconnect a circuit (such as, for example, a mixer circuit having a stacked transistor structure) to and from a supply voltage.

[0031] In an exemplary embodiment, a head switch for a stacked transistor structure includes multiple bias paths.

[0032] In an exemplary embodiment, a head switch for a stacked transistor structure having multiple bias paths includes a bias path for cascode transistors in an active path and a bias path for cascode transistors in an inactive path.

[0033] In an exemplary embodiment, the bias path for the active path provides a supply voltage (in the example, 1.98 V) to the active cascode transistors, and the bias path for the inactive path provides a regulated voltage of, for example, 0.8 V (lower than the exemplary supply voltage of 1.98 V) to the inactive cascode transistors in the inactive path.

[0034] In an exemplary embodiment, the header switch connected to the active path is turned on first, and then the gate voltage of the cascode transistor is transitioned from an "off-state" or "standby-state" voltage to a "mission mode" or "on-state" voltage.

[0035] As used herein, the term "off state" may refer to a fully off state from which a communication device having a head switch for a stacked transistor structure can be powered on and placed in a standby state. As used herein, the term "standby state" may refer to a state in which a communication device having a head switch for a stacked transistor structure can be powered on, but in which the device is not fully powered on or processing communication signals. This standby state may also be referred to as an "off" state. As used herein, the term "mission mode" or "on state" may refer to a state in which a device in a head switch for a stacked transistor structure is active and processing communication signals.

[0036] In an exemplary embodiment, turning on the active path first allows tail current to flow through the stacked transistor structure including the cascode transistor associated with the active path, and prevents any tail current from flowing through the cascode transistor in the inactive path. Preventing any tail current from flowing through the cascode transistor in the inactive path allows the inactive path to provide a stable drain voltage (e.g., approximately 0.8V) to the drain of the cascode transistor in the inactive path. In this way, the off / on and on / off transitions can be accurately achieved and made robust to prevent any excessive or uncontrolled voltage transitions.

[0037] In an exemplary embodiment, a headswitch for a stacked transistor structure allows for high linearity and wide bandwidth operation (eg, particularly when using thin oxide transistors) and relatively high supply voltages while improving long-term reliability.

[0038] In an exemplary embodiment, a head switch for a stacked transistor structure allows four thin oxide transistor devices to be reliably biased using a relatively high (e.g., 1.98 V) supply voltage when the transistors are in an on state, an off state, and during transitions between the on and off states.

[0039] The voltages described herein are exemplary only and may vary from those shown based on specific implementation details.

[0040] Figure 1 1 is a diagram illustrating wireless device 110 communicating with wireless communication system 120. Wireless communication system 120 may be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, a 5G NR (New Radio) system, or some other wireless system. A CDMA system may implement Wideband CDMA (WCDMA), CDMA 1X, Evolution Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, Figure 1 A wireless communication system 120 is shown including two base stations 130 and 132 and one system controller 140. In general, a wireless communication system may include any number of base stations and any set of network entities.

[0041] Wireless device 110 may also be referred to as user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. Wireless device 110 may be a cellular phone, a smartphone, a tablet device, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a tablet computer, a cordless phone, a medical device, an automobile, a device configured to connect to one or more other devices (e.g., via the Internet of Things), a wireless local loop (WLL) station, a Bluetooth device, etc. Wireless device 110 may communicate with wireless communication system 120. Wireless device 110 may also receive signals from broadcast stations (e.g., broadcast station 134) and / or signals from satellites (e.g., satellites 150 in one or more global navigation satellite systems (GNSS)). Wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 802.15, 5G, Sub6 5G, 6G, UWB, etc.

[0042] Wireless device 110 may support carrier aggregation, for example, as described in one or more LTE or 5G (sometimes also referred to as New Radio (NR)) standards. In some embodiments, carrier aggregation is used to transmit a single data stream across multiple carriers, as opposed to separate carriers for the respective data streams. Wireless device 110 is capable of operating in various communication bands, including, for example, those used by LTE, WiFi, 5G, or other communication bands within a wide frequency range. Wireless device 110 is also capable of communicating directly with other wireless devices without communicating through a network.

[0043] Generally speaking, carrier aggregation (CA) can be categorized into two types: intra-band CA and inter-band CA. Intra-band CA refers to the operation of multiple carriers within the same frequency band, while inter-band CA refers to the operation of multiple carriers within different frequency bands.

[0044] Figure 2 An example of a transceiver 220 is shown with a transmitter 230 and a receiver 250. In general, the conditioning of the signals in the transmitter 230 and the receiver 250 may be performed by one or more stages of amplifiers, filters, upconverters, downconverters, etc. These circuit blocks may be connected to Figure 2 The configuration shown is arranged differently. In addition, Figure 2 Other circuit blocks not shown in FIG may also be used to condition the signals in transmitter 230 and receiver 250. Unless otherwise indicated, Figure 2 Any signal in , or any other diagram in the accompanying drawings, may be single-ended or differential. Figure 2 Some circuit blocks in the circuit can also be omitted.

[0045] exist Figure 2 In the example shown, the wireless device 200 generally includes a transceiver 220 and a data processor 210. The data processor 210 may include a processor 296 operatively coupled to a memory 298. The memory 298 may be configured to store data and program code, generally indicated using reference numeral 299, and may generally include analog and / or digital processing components. The transceiver 220 includes a transmitter 230 and a receiver 250 that support bidirectional communication. In general, the wireless device 200 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or a portion of the transceiver 220 may be implemented on one or more analog integrated circuits (ICs), radio frequency integrated circuits (RFICs), mixed-signal ICs, and the like.

[0046] A transmitter or receiver can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multiple stages of frequency conversion between radio frequency (RF) and baseband, for example, in the case of a receiver, from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Figure 2 In the example shown, transmitter 230 and receiver 250 are implemented using a direct conversion architecture.

[0047] In the transmit path, data processor 210 processes the data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to transmitter 230. In an exemplary embodiment, data processor 210 includes digital-to-analog converters (DACs) 214a and 214b for converting the digital signals generated by data processor 210 into I and Q analog output signals (e.g., I and Q analog output signals) for further processing. In other embodiments, DACs 214a and 214b are included in transceiver 220, and data processor 210 provides data (e.g., for I and Q) to transceiver 220 in a digital form.

[0048] Within transmitter 230, lowpass filters 232a and 232b filter the I and Q analog transmit signals, respectively, to remove unwanted image frequencies caused by the preceding digital-to-analog conversion. Amplifiers (Amp) 234a and 234b amplify the signals from lowpass filters 232a and 232b, respectively, and provide I and Q baseband signals. Upconverter 240, including upconverting mixers 241a and 241b, upconverts the I and Q baseband signals using I and Q TX LO signals from a transmit (TX) local oscillator (LO) signal generator 290, and provides the upconverted signals. Filter 242 filters the upconverted signals to remove unwanted image frequencies caused by the frequency upconversion and noise in the receive band. Power amplifier (PA) 244 amplifies the signal from filter 242 to achieve the desired output power level and provide the transmit RF signal. The transmit RF signal is routed through a duplexer or switch 246 and transmitted via an antenna 248, or alternatively, the transmit RF signal may be directed to a separate transmit antenna that is distinct from the separate receive antenna. While the examples discussed herein utilize I and Q signals, those skilled in the art will appreciate that the components of the transceiver may be configured to utilize polar modulation.

[0049] In the receive path, antenna 248 receives the communication signal and provides a received RF signal, which is routed through a duplexer or switch 246 and provided to a low-noise amplifier (LNA) 252. Duplexer 246 is designed to operate with specific RX and TX duplexer frequency separation, isolating the RX signal from the TX signal. Alternatively, there may be separate transmit and receive antennas, as mentioned above. In this case, RX and TX isolation can be achieved through limited coupling between the two antennas. In the case of separate RX and TX antennas, the RX antenna can be directly coupled to LNA 252. The received RF signal is amplified by LNA 252 and filtered by filter 254 to obtain the desired RF input signal. Downconversion mixers 261a and 261b in downconverter 260 mix the output of filter 254 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from receive (RX) LO signal generator 280 to generate I and Q baseband signals. The I baseband signal and the Q baseband signal are amplified by amplifiers 262a and 262b and further filtered by low-pass filters 264a and 264b to obtain I analog input signals and Q analog input signals, which are provided to the data processor 210. In the exemplary embodiment shown, the data processor 210 includes analog-to-digital converters (ADCs) 216a and 216b for converting the analog input signals into digital signals to be further processed by the data processor 210. In some embodiments, the ADCs 216a and 216b are included in the transceiver 220 and provide data to the data processor 210 in a digital form.

[0050] exist Figure 2 In the data processor 210, TX LO signal generator 290 generates I TX LO signal and Q TX LO signal for upconversion, while RX LO signal generator 280 generates I RX LO signal and Q RX LO signal for downconversion. Each LO signal is a periodic signal with a specific fundamental frequency. Phase-locked loop (PLL) 292 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the TX LO signal from LO signal generator 290. Similarly, PLL 282 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the RX LO signal from LO signal generator 280.

[0051] In an exemplary embodiment, RX PLL 282, TX PLL 292, RX LO signal generator 280, and TX LO signal generator 290 may alternatively be combined into a single LO generator circuit 295, which may include a common or shared LO signal generator circuit to provide the TX LO signal and the RX LO signal. Alternatively, separate LO generator circuits may be used to generate the TX LO signal and the RX LO signal.

[0052] The wireless device 200 may support carrier aggregation and may (i) receive multiple downlink signals transmitted by one or more cells at different frequencies on multiple downlink carriers, and / or (ii) send multiple uplink signals to one or more cells on multiple uplink carriers. However, those skilled in the art will appreciate that the various aspects described herein may be implemented in systems, devices, and / or architectures that do not support carrier aggregation.

[0053] Figure 2 2 functionally illustrates certain components of transceiver 220, and the illustrated configurations may or may not represent physical device configurations in certain implementations. For example, as described above, transceiver 220 may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, and the like. In some embodiments, transceiver 220 is implemented on a substrate or board (such as a printed circuit board (PCB)) having various modules, chips, and / or components. For example, power amplifier 244, filter 242, and duplexer 246 may be implemented in separate modules or as discrete components, while the remaining components illustrated in transceiver 220 may be implemented in a single transceiver chip.

[0054] The power amplifier 244 may include one or more stages, including, for example, a driver stage, a power amplifier stage, or other components that may be configured to amplify communication signals at one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, the power amplifier 244 may be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and may be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

[0055] In an exemplary embodiment in a superheterodyne architecture, filter 242, PA 244, LNA 252, and filter 254 may be implemented separately from other components in transmitter 230 and receiver 250 (e.g., such a configuration may implement a millimeter wave integrated circuit (mmW-IC) or other superheterodyne-based architecture).

[0056] Figure 3 is a block diagram showing circuit 300, an example of which may be found in Figure 1implemented in wireless devices or base stations Figure 2 For example, the circuit 300 may include the transceiver 220 ( Figure 2 ) section 301.

[0057] In an exemplary embodiment, circuit 300 may include baseband element 302, digital-to-analog converter (DAC) 304, baseband filter (BBF) 306, mixer 310, cascode path 312 (cascode path A), cascode path 314 (cascode path B), electromagnetic (EM) element 316, EM element 318, output path 322 (output path A), and output path 324 (output path B). In an exemplary embodiment, head switch 330 may be selectively connected to EM element 316, and head switch 340 may be selectively connected to EM element 318.

[0058] Although two cascode paths 312 and 314 are shown for illustration, circuit 300 may include more or fewer cascode paths depending on the specific implementation.

[0059] In some exemplary embodiments, the cascode path 312 and the cascode path 314 may be part of the mixer 310 .

[0060] As used herein, the term “selectively connect” is used to describe the various ways in which headswitch 330 may provide selected voltages to EM element 316 and the transistors in cascode path 312 , and the various ways in which headswitch 340 may provide selected voltages to EM element 318 and the transistors in cascode path 314 .

[0061] In an exemplary embodiment, baseband element 302 may be configured to provide a digital baseband information signal, often referred to as digital data, to DAC 304. DAC 304 may convert the digital signal from baseband element 302 into an analog signal, which may be provided to BBF 306. BBF 306 may provide a filtered analog information signal to mixer 310.

[0062] In an exemplary embodiment, mixer 310 may be configured to operate on single-ended signals or differential signals. In an exemplary embodiment, mixer 310 may be an in-phase / quadrature (I / Q) mixer configured to generate I and Q signals for transmission. In some embodiments, mixer 310 will perform signal frequency conversion between baseband and RF frequencies, such as Figure 3As shown. In other embodiments, mixer 310 will perform signal frequency conversion between baseband and an intermediate frequency (IF), and another mixer will perform signal frequency conversion between IF and RF frequencies. In an exemplary embodiment, the I and Q outputs of mixer 310 can be provided to cascode path 312 and cascode path 314.

[0063] In an exemplary embodiment, cascode path 312 is connected to EM element 322, and cascode path 314 is connected to EM element 318. EM element 316 and EM element 318 can be transformers, baluns, or other EM elements. EM element 316 provides an output signal to output path 322, and EM element 318 provides an output signal to output path 324. Output path 322 and output path 324 can be connected to one or more amplifiers, switches, diplexers, duplexers, and antennas or antenna elements.

[0064] In some exemplary embodiments, at a base station such as Figure 1 It may be particularly useful to implement circuit 300 in a base station 130 or 132 .

[0065] Figure 4 is a diagram showing a circuit 400, which illustrates Figure 3 In an exemplary embodiment, circuit 400 includes Figure 3 In an exemplary embodiment, the circuit 400 includes a portion of the transmit architecture of the circuit 300. Figure 3 3. The circuit 400 is a block diagram of a mixer 310, cascode paths 312 and 314, EM elements 316 and 318, and portions of head switches 330 and 340. In an exemplary embodiment, the circuit 400 includes an active path 410, an inactive path 450, a mixer 420 (e.g., a harmonic rejection mixer (HRM); however, other mixer architectures are possible), and a degeneration gain stage 435.

[0066] In the exemplary embodiment, mixer 420 and degenerate gain stage 435 are connected to cascode path 312 (cascode path A) and cascode path 314 (cascode path B). In the exemplary embodiment, mixer 420 may include mixer transistors 422 and 424. However, although only two mixer transistors 422 and 424 are shown, mixer 420 typically includes many additional transistors. In the exemplary embodiment, mixer transistors 422 and 424 receive local oscillator (LO) signals LO_p and LO_m, respectively, at their gates (in this example, typically from a LO_p). Figure 2 TX LO signal generator 290).

[0067] In an exemplary embodiment, the degeneration gain stage 435 may include gain (Gm) transistors 432 and 434 and degeneration transistors 436 and 438. In an exemplary embodiment, the degeneration transistors 436 and 438 may also be referred to as tail current sources. In an exemplary embodiment, the baseband information signals BB_signal_p and BB_signal_m (e.g., from Figure 3 The baseband filter 306 of the baseband filter 306) can be provided to the gates of transistors 432 and 434 respectively. Transistors 436 and 438 can receive bias signals Vb at their gates from, for example, bias circuit 469, which can be an external circuit and can be provided by data processor 210 ( Figure 2 ) or a control signal from another controller.

[0068] In an exemplary embodiment, the active path 410 includes the head switch 330 ( Figure 3 ), EM element 316 ( Figure 3 ) and cascode path 312 ( Figure 3 ). EM element 316 may include a first winding 415 and a second winding 417. In an exemplary embodiment, the center tap of first winding 415 may be connected to header switch 330. First winding 415 may also be connected to the drains of transistors 401 and 402, thereby connecting the drains of transistors 401 and 402 to header switch 330 via first winding 415. The drains of transistors 403 and 404 are directly connected to header switch 330. Second winding 417 may provide an output, which in this example is an output associated with a new radio (NR) communication signal. Cascode path 312 may include transistors 401, 402, 403, and 404. Transistors 401 and 402 are cascode transistors, and transistors 403 and 404 may include current steering functionality to provide output gain control. Although depicted as part of cascode path 312, transistors 403 and 404 are not cascode transistors, and cascode path 312 may or may not include current steering devices for gain control. For example, determining which of transistors 401, 402, 403, and 404 to turn on depends on the desired amount of gain. In the exemplary embodiment, transistors 401, 402, 403, and 404 are shown with thick solid lines to indicate that, in this example, they are part of active path 410 and process communication signals. In the exemplary embodiment, active path 410 may process communication signals during a particular communication mode (e.g., active path 410 may be used for 5G New Radio (NR) signals).

[0069] In an exemplary embodiment, the inactive path 450 includes the head switch 340 ( Figure 3 ), EM element 318 ( Figure 3 ) and cascode path 314 ( Figure 3 ). EM element 318 may include a first winding 425 and a second winding 427. The center tap of first winding 425 may be connected to header switch 340. First winding 425 may also be connected to the drains of transistors 407 and 408, thereby connecting the drains of transistors 407 and 408 to header switch 340 via first winding 425. The drains of transistors 405 and 406 are directly connected to header switch 340. Second winding 427 may provide an output, which in this example is an output related to low-band, mid-band, and high-band (LMH) communication signals.

[0070] Cascode path 314 may include transistors 405, 406, 407, and 408. Transistors 407 and 408 are cascode transistors, and transistors 405 and 406 may include current steering functionality to provide output gain control. For example, determining which of transistors 405, 406, 407, and 408 to turn on depends on the desired amount of gain. Although depicted as part of cascode path 314, transistors 405 and 406 are not cascode transistors, and cascode path 314 may or may not include current steering for gain control. In an exemplary embodiment, transistors 405, 406, 407, and 408 are shown in dashed lines to indicate that, in this example, they are part of inactive path 450 and do not actively process communication signals. However, even if transistors 405, 406, 407, and 408 do not actively process communication signals, it is desirable to provide selective control and biasing to transistors 405, 406, 407, and 408 in inactive path 314. In an exemplary embodiment, the inactive path 450 may be inactive during certain communication modes (e.g., for 5G NR signals), but active during other modes (e.g., active for certain LTE LB, HB, MB (low band, mid band, high band (LMH)) modes).

[0071] Although described as being applicable to stacked transistors in a mixer architecture, the head switch for a stacked transistor structure described herein is applicable to other stacked transistor structures, such as, for example, a stacked transistor structure in a power amplifier (PA), a driver amplifier (DA), or other stacked transistor structures.

[0072] In addition, although Figure 4 Two cascode paths are shown in FIG and other figures below, but three or more cascode paths can be implemented. For example, a third cascode path would have a third EM element and device.

[0073] Figure 5 is a diagram showing a circuit 500, which illustrates Figure 3 and Figure 4 An exemplary embodiment of a head switch. Figure 5 Similar to Figure 4 The components in the will be referred to using the naming method 5XX, where Figure 5 The components marked 5XX in the Figure 4 Components marked with 4XX.

[0074] Circuit 500 includes an active path 510 and an inactive path 550. Head switch 530 is illustrated in active path 510, and head switch 540 is illustrated in inactive path 550.

[0075] In an exemplary embodiment, the head switch 530 may include transistors 562, 564, and 566, and may include resistors 563 and 565. Resistors 563 and 565 may form a resistor divider. In an exemplary embodiment in which the head switch 530 is in the active path 510, transistor 564 is conductive (shown in solid lines), and transistors 562 and 566 are non-conductive (shown in dashed lines). In an exemplary embodiment, transistor 564 may form a first (or main) bias path 579. Figure 5 In the example shown where transistor 564 is on, node 560 can have a voltage substantially equal to the supply voltage, which, as a non-limiting example, is shown in this example as 1.98 V provided by first bias path 579. In some embodiments, the supply voltage may alternatively be referred to as a system voltage.

[0076] In an exemplary embodiment, header switch 540 may include transistors 572, 574, and 576, and may include resistors 573 and 575. Resistors 573 and 575 may form a resistive voltage divider. In an exemplary embodiment in which header switch 540 is in inactive path 550, transistor 572 is conductive (shown in solid lines), transistor 576 is conductive (shown in solid lines), and transistor 574 is non-conductive (shown in dashed lines). In an exemplary embodiment, when transistors 572 and 576 are conductive and transistor 574 is non-conductive, transistors 576 and 572 and resistors 573 and 575 form an auxiliary bias path 580. In this manner, the supply voltage at node 570 can be reduced to a value lower than the voltage present at node 560 to bias the drains of the transistors in cascode path 514 in inactive path 550.

[0077] In some embodiments, a single header switch (eg, header switch 530 or header switch 540 ) can be configured to provide a primary path 579 (eg, Figure 55) and an auxiliary path 580 configured to provide a reduced supply voltage (e.g., header switch 540). Although shown in this example as using a resistor divider to generate the lower supply voltage at node 570, an external voltage supply of 0.8V could also be used to generate the reduced supply voltage in this example.

[0078] In the exemplary embodiment, the head switch 530 is connected to the EM element 516 at the node 560. The EM element 516 is connected to the cascode transistor in the cascode path 512. Although a single cascode transistor 501 is shown in the cascode path 512 for ease of illustration, the cascode transistor 501 is intended to represent Figure 3 and Figure 4 All cascode transistors in the cascode path 312 are connected. For example, one or more additional cascode transistors will be connected to the other side of the first winding 515. The cascode transistor 501 is connected to the mixer 520. The mixer 520 is connected to the degeneration gain stage 535. Although Figure 5 A single mixer transistor 522 is shown in the mixer 520, and a single transistor is shown as the Gm device 532 and the tail current source 536 in the degeneration gain stage 535, but the mixer 520 and the degeneration gain stage 535 may include the devices described above and Figure 4 In an exemplary embodiment, mixer 520 (mixer transistor 522) receives a local oscillator (LO) signal, Gm device 532 receives a baseband information signal, and tail current source 536 receives a bias signal Vb, as described above in Figure 4 Described in .

[0079] In an exemplary embodiment, the head switch 540 is connected to the EM element 518 at the node 570. The EM element 518 is connected to the cascode path 514. Figure 5 A single transistor 507 is shown in the cascode path 514 in FIG, but the cascode path 514 may include additional transistors as described above.

[0080] Although only the first winding 515 is shown in the EM element 516 and only the first winding 525 is shown in the EM element 518 for ease of illustration, the EM element 516 and the EM element 518 will each include a second winding (such as Figure 4 The second winding 417 and the second winding 427 in the Figure 3 and Figure 4 The output path of the circuit described in .

[0081] In the inactive path 550, when the head switch 540 is Figure 5When configured as shown, it is desirable to prevent random voltages at node 570. In an exemplary embodiment, transistors 572 and 573 and resistors 573 and 575 form a so-called auxiliary bias path 580 for the cascode transistors in cascode path 514. In this way, random voltages are prevented from appearing at node 570. In an exemplary embodiment, due to the voltage division performed by resistors 573 and 575, a voltage of approximately 0.8V (as an example) appears at node 570 and is applied to the drains of the cascode transistors in cascode path 514. In other embodiments, an external voltage source may be used to provide a reduced supply voltage at node 570. In an exemplary embodiment, the gates of the transistors in cascode path 514 also receive a bias signal at their gates of, for example, a bias voltage of 0.6V from a bias circuit 569, which may be an external circuit and may be provided by a source from data processor 210 ( Figure 2 ) or a control signal from another controller.

[0082] In an exemplary embodiment, the voltage at node 560 transitions from approximately 0V-0.8V when the header switch 530 is in the standby or off condition to an exemplary voltage of 1.98V when the header switch 530 is in the mission mode condition.

[0083] In an exemplary embodiment, the voltage at node 570 transitions from approximately 0V-0.8V when the head switch 540 is in the standby or off condition to a voltage of approximately 0.8V when the head switch 540 is in the mission mode condition.

[0084] In an exemplary embodiment, the voltage at the gate of the cascode transistor in cascode path 512 (in active path 510 ) is at an example voltage of 1V in the standby or off condition and transitions to a voltage of approximately 1.35V when in the on condition in mission mode.

[0085] In an exemplary embodiment, the voltage at the gate of the cascode transistor in cascode path 514 (in inactive path 550 ) is at an example voltage of 1V in the standby or off condition and transitions to a voltage of approximately 0.6V when in the on condition in mission mode.

[0086] In mission mode, the voltage at the gate of any on-cascode transistor in cascode path 512 (in active path 510 ) is approximately 1.35 V; the voltage at the gate of any off-cascode transistor in cascode path 512 (in active path 510 ) is approximately 1.05 V; and the voltage at the gate of any off-cascode transistor in cascode path 514 (in inactive path 550 ) is approximately 0.6 V.

[0087] In an exemplary embodiment, the voltage at the gate of any transistor in mixer 520 is approximately 1 V in standby mode and transitions to approximately 1.05 V in mission mode.

[0088] In an exemplary embodiment, placing a voltage of approximately 0.8V at node 570 (the drain of the transistor in cascode path 514) and a gate voltage of approximately 0.6V at the gate of the transistor in cascode path 514 ensures that the transistor in cascode path 514 is turned off, thereby preventing the desired signal from being drawn away from active cascode path 512, and preventing the possibility of an overvoltage condition being passed to the transistor in cascode path 514. Applying approximately 0.6V to the gate of the transistor in cascode path 514 when the drain of the transistor in cascode path 514 is at approximately 0.8V places the source of the transistor in cascode path 514 at approximately 1.1V, so that the transistor in cascode path 514 is not overstressed.

[0089] Figure 6 is a diagram showing a circuit 600, which illustrates the Figure 5 An exemplary embodiment of a desired voltage associated with a header switch. Figure 6 Similar to Figure 4 and Figure 5 The components in the components will be referred to using the naming method 6XX, where Figure 6 The components marked 6XX in the Figure 4 Components marked 4XX in the Figure 5 Components marked with 5XX.

[0090] In an exemplary embodiment, circuit 600 includes an active path 610 having a header switch 630. Head switch 630 is connected to an EM element 616 having a first winding 615 and a second winding 617. In an exemplary embodiment, the center tap of the first winding 615 can be connected to the header switch 630. The first winding 615 can also be connected to the drains of transistors 601 and 602, thereby connecting the drains of transistors 601 and 602 to the header switch 630 through the first winding 615. The second winding 617 can provide an output, which in this example is an output related to a new radio (NR) communication signal. Although for ease of illustration, the output is not shown in FIG. Figure 6 Two cascode transistors 601 and 602 are shown in the cascode path 612 of FIG. 1 , but the cascode path 612 may include more transistors. For ease of illustration, Figure 6 The current steering transistors (e.g., Figure 4 of 403 / 404).

[0091] In an exemplary embodiment, the circuit 600 includes an inactive path 650 having a header switch 640. The header switch 640 is connected to an EM element 618 having a first winding 625 and a second winding 627. In an exemplary embodiment, the center tap of the first winding 625 can be connected to the header switch 640. The first winding 625 can also be connected to the drains of transistors 607 and 608, thereby connecting the drains of transistors 607 and 608 to the header switch 640 through the first winding 625. The second winding 627 can provide an output, which in this example is an output related to low-band, mid-band, and high-band (LMH) communication signals. Although for ease of illustration, the outputs in FIG. Figure 6 Two cascode transistors 607 and 608 are shown in the cascode path 614 in FIG. 1 , but the cascode path 614 may include more transistors. For ease of illustration, Figure 6 The current steering transistors (e.g., Figure 4 In an exemplary embodiment, in this example, the current steering device (not shown) in the inactive path 650 will receive a reduced supply voltage (0.8V) from the auxiliary path of the inactive path head switch 640 .

[0092] Mixer 620 may be connected to the sources of transistors 601, 602, 607, and 608. Although labeled as a specific HRM mixer, other mixer topologies may be possible for mixer 620. In an exemplary embodiment, mixer 620 is similar to Figure 5 The mixer 520, and for ease of illustration, from Figure 6 Omitted Figure 5 The gain transistor 532 and the tail current source 536 in the degenerate gain stage 535 are shown.

[0093] In an exemplary embodiment, the head switch 640 applies a bias voltage of approximately 0.8V to the drains of the cascode transistors 607 and 608 in the inactive path 650. An external bias circuit 669 may apply a bias of approximately 0.6V to the gates of the cascode transistors 607 and 608 to ensure that the cascode transistors 607 and 608 are turned off. The bias signal applied to the gates of the transistors 607 and 608 may be provided by the bias circuit 669, which may be an external circuit and may be provided by the data processor 210 ( Figure 2 ) or another controller.

[0094] In an exemplary embodiment, it is undesirable to have the drains of cascode transistors 607 and 608 at a floating voltage, eg, 0V-0.8V, due to the stress that may be presented to transistors (eg, transistors in cascode path 614) during an off-to-on transient condition.

[0095] In an exemplary embodiment, a voltage of approximately 1.1 V appears at the sources of cascode transistors 601, 602, 607, and 608, and is therefore applied to the transistors in mixer 620 ( Figure 6 not shown).

[0096] In an exemplary embodiment, head switch 630 applies a supply voltage (approximately 1.98V in this example) to the drains of transistors 601 and 602. External bias circuit 669 applies a bias voltage of approximately 1.35V to the gates of transistors 601 and 602.

[0097] In an exemplary embodiment, head switch 640 applies a reduced supply voltage (approximately 0.8V in this example) to the drains of transistors 607 and 608. In an exemplary embodiment, external bias circuit 669 may apply a bias voltage of approximately 0.6V to the gates of transistors 607 and 608 to ensure that transistors 607 and 608 remain non-conductive.

[0098] Figure 7 is a diagram showing a circuit 700, which illustrates Figure 6 An exemplary embodiment of an inactive path head switch. Figure 7 Similar to Figure 4 、 Figure 5 and Figure 6 The components in the will be referred to using the naming format 7XX, where Figure 7 The components marked 7XX in the Figure 4 Components marked with 4XX in Figure 5 Components marked 5XX or Figure 6 Components marked with 6XX.

[0099] In an exemplary embodiment, circuit 700 shows a header switch 740 having an auxiliary bias path 780 having transistors 776 and 772 and resistors 773 and 775 configured to provide a voltage of approximately 0.8V to node 770. The voltage of approximately 0.8V at node 770 can bias the drains of cascode transistors 707 and 708 in cascode path 714 when cascode transistors 707 and 708 are in the off position. The gate voltage of approximately 0.6V provided to cascode transistors 707 and 708 ensures that transistors 707 and 708 remain off. In an exemplary embodiment, the gate voltage is provided by an external bias circuit 769, which can be provided by data processor 2010 ( Figure 2 ) or another controller.

[0100] Figure 8 is a diagram showing a circuit 800, which illustrates Figure 3 part of the circuit and Figure 5 Detailed view of an exemplary embodiment of circuit 500. Figure 8 Similar to Figure 3 and Figure 5 The components in the components will be referred to using the naming method 8XX, where Figure 8 The components marked 8XX in the Figure 3 Components marked 3XX in the Figure 5 Components marked with 5XX.

[0101] In the exemplary embodiment, circuit 800 illustrates several voltages provided by headswitch 830 and headswitch 840. In the exemplary embodiment, from a standby (or off) state, headswitch 830 in active path 810 is activated first, i.e., before headswitch 840 in inactive path 850 is activated. Activating headswitch 830 in active path 810 first ensures that all tail currents flowing through cascode path 812, cascode path 814, mixer 820, and transistors 832 and 836 in degeneration gain stage 835 pass only through cascode path 812 associated with headswitch 830 in active path 810. Because no tail current flows through headswitch 840 in inactive path 850, the resistor divider (resistors 873 and 875) accurately provides the desired 0.8V to the center tap of EM element 818 and the drain of the transistor (e.g., transistor 807) in cascode path 814. In this way, all off-to-on transitions may be done accurately and are robust to voltage anomalies that may stress the transistors in the cascode paths 812 and 814 , the transistors in the mixer 820 , and the transistors in the degeneration gain stage 835 .

[0102] Figure 9 is a diagram illustrating a circuit 900 according to an exemplary embodiment of the present disclosure. Figure 9 Similar to Figure 3 、 Figure 4 and Figure 5 The components in the components will be referred to using the naming method 9XX, where Figure 9 The components marked 9XX in the Figure 3 Components marked with 3XX in Figure 4 Components marked 4XX or Figure 5 Components marked with 5XX.

[0103] In an exemplary embodiment, circuit 900 illustrates gate voltage transitions when switching from off mode to mission mode. For example, active path 910a illustrates the active path voltage in off mode, and active path 910b illustrates the active path voltage in mission mode. Similarly, inactive path 950a illustrates the inactive path voltage in off mode, and inactive path 950b illustrates the inactive path voltage in mission mode.

[0104] In an exemplary embodiment, in the active path 910a in standby mode, a supply voltage of approximately 1.9V (an exemplary 1.98V supply voltage) is provided by the header switch 930 to the node 960. This supply voltage is provided to the center tap of the first winding 915 of the EM element 916 and thereby indirectly to the drains of the cascode transistors 901 and 902. The header switch output is directly provided to the drains of the transistors 903 and 904 in the cascode path 912. By the data processor 210 ( Figure 2 ) or another controller provides a gate voltage of approximately 1V to the gates of transistors 901, 902, 903, and 904 in cascode path 912. For ease of illustration only, external bias circuit 969 is shown in active path 910b. External bias circuit 969 can provide bias signals to any transistor in active path 910a, active path 910b, inactive path 950a, and inactive path 950b.

[0105] In an exemplary embodiment, in the active path 910b in mission mode, a supply voltage of approximately 1.9V (an exemplary 1.98V supply voltage) is provided to node 960 by header switch 930. This supply voltage is provided to the center tap of first winding 915 of EM element 916 and, thereby, indirectly to the drains of cascode transistors 901 and 902; and directly to the drains of transistors 903 and 904 in cascode path 912. A gate voltage of approximately 1.35V is provided to the gates of transistors 901, 902, 903, and 904 in cascode path 912 that are enabled; and a gate voltage of approximately 1.05V is provided to the gates of transistors 901, 902, 903, and 904 in cascode path 912 that are disabled. Determining which of transistors 901, 902, 903, and 904 to enable depends on the desired amount of gain. The gate voltages provided to transistors 901, 902, 903, and 904 may be provided by the data processor 210 ( Figure 2 ) or an external bias circuit 969 controlled by another controller.

[0106] In an exemplary embodiment, in the inactive path 930a in standby mode, a supply voltage of approximately 0.8V is provided to node 970 by the head switch 940. This supply voltage is provided to the center tap of the first winding 925 of the EM element 918, and is indirectly provided to the drains of the cascode transistors 907 and 908, and is directly provided to the drains of the transistors 905 and 906 in the cascode path 914. Figure 2 ) or an external bias circuit 969 controlled by another controller provides a gate voltage of approximately 1V to the gates of transistors 905, 906, 907 and 908 in the cascode path 914.

[0107] In an exemplary embodiment, in the inactive path 930b in mission mode, a supply voltage of approximately 0.8V is provided to node 970 by the header switch 940. This supply voltage is provided to the center tap of the first winding 925 of the EM element 918, and is indirectly provided to the drains of the cascode transistors 907 and 908, and is directly provided to the drains of the transistors 905 and 906 in the cascode path 914. A gate voltage of approximately 0.6V is provided to the gates of the transistors 905, 906, 907, and 908 in the cascode path 914. The gate voltages provided to the transistors 905, 906, 907, and 908 may be provided by the data processor 210 ( Figure 2 ) or an external bias circuit 969 controlled by another controller. This results in a voltage of approximately 1.1 V appearing at the sources of transistors 901, 902, 903, 904, 905, 906, 907, and 908 as a bias to the mixer ( Figure 9 In this way, during the transition from standby mode to mission mode, transistors 905, 906, 907, and 908 in cascode path 914 are protected from overvoltage conditions and other voltage transients.

[0108] In an exemplary embodiment, a header switch having both “mission mode” and “auxiliary” paths (such as header switch 930 or header switch 940, or any of the header switches described herein) may also be implemented in an embodiment having only a single signal path (e.g., only an NR signal path), where, for example, the header switch structure may be used to provide an auxiliary voltage of 0.8V during power-up and then provide the mission mode voltage when the gate of the transistor is biased up from 0.8V to the full 1.9V.

[0109] Figure 10 1000 is a flowchart describing an example of the operations of a method for biasing a stacked transistor structure. The blocks in the method 1000 may or may not be performed in the order shown, and in some embodiments, may be performed at least partially in parallel.

[0110] In block 1001 , the gates of the transistors in the cascode path 912 are biased from a fully off / powered down state during initial power up (where all gates are ~0V) to a standby / off state.

[0111] In block 1002, transistors in the active path are biased. For example, header switch 930 in active path 910 may be activated before header switch 940 in inactive path 950 to bias the drains of transistors 901, 902, 903, and 904 in cascode path 912. External bias circuit 969 may be configured to bias the gates of transistors 901, 902, 903, and 904 in cascode path 912.

[0112] In block 1004, transistors in the inactive path are biased. For example, header switch 940 in inactive path 910 may be activated to bias the drains of transistors 905, 906, 907, and 908 in cascode path 914. External bias circuit 969 may be configured to bias the gates of transistors 905, 906, 907, and 908 in cascode path 914.

[0113] In block 1006, the gates of the transistors may be transitioned from a standby state to a mission mode state. For example, the gates of transistors 901, 902, 903, and 904 in cascode path 912 in active path 910 may be transitioned from standby mode to mission mode, and transistors 905, 906, 907, and 908 in cascode path 914 in active path 910 may be transitioned from standby mode to mission mode. For example, transistors 901, 902, 903, and 904 may have their gate voltages transitioned from approximately 1V to approximately 1.35V (if on) or 1.05V (if off). For example, transistors 905, 906, 907, and 908 may have their gate voltages transitioned from approximately 1V to approximately 0.6V.

[0114] Figure 11 is a functional block diagram of an apparatus 1100 for biasing a stacked transistor structure. The apparatus 1100 includes a component 1101 for biasing a gate of a transistor in a cascode path. In certain embodiments, the component 1101 for biasing a gate of a transistor in a cascode path may be configured to perform the method 1000 ( Figure 10 ) and one or more of the functions described in operation block 1001 of FIG. In an exemplary embodiment, means 1101 for biasing the gates of the transistors in the cascode path may include bias circuit 969 that biases the gates of the transistors in the cascode path 912 from a fully off / powered-down state during initial power-up (where all gates are ~0V) to a standby / off state.

[0115] The apparatus 1100 includes means 1102 for biasing transistors in an active path. In certain embodiments, the means 1102 for biasing transistors in an active path may be configured to perform the method 1000 ( Figure 10 ). In an exemplary embodiment, means 1102 for biasing transistors in the active path may include: activating the header switch 930 in the active path 910 before the header switch 940 in the inactive path 950 to bias the drains of the transistors 901, 902, 902, and 904 in the cascode path; and configuring the external bias circuit 969 to bias the gates of the transistors 901, 902, 903, and 904 in the cascode path 912.

[0116] The apparatus 1100 includes means 1104 for biasing transistors in the inactive path. In some embodiments, the means 1104 for biasing transistors in the inactive path can be configured to perform the method 1000 ( Figure 10 ). In an exemplary embodiment, means 1104 for biasing transistors in the inactive path may include: activating header switch 940 in the inactive path 950 after header switch 930 in the active path 910 to bias the drains of transistors 905, 906, 907, and 908 in the cascode path 914; and configuring external bias circuit 969 to bias the gates of transistors 905, 906, 907, and 908 in the cascode path 914.

[0117] The apparatus 1100 includes a component 1106 for transitioning the gate of the transistor from the standby state to the task mode state. In some embodiments, the component 1106 for transitioning the gate of the transistor from the standby state to the task mode state can be configured to perform the method 1000 ( Figure 10 ). In an exemplary embodiment, the means 1106 for transitioning the gates of the transistors from the standby state to the mission mode state may include: transitioning the gate voltages of the transistors 901, 902, 903, and 904 from approximately 1V to approximately 1.35V (if on) or 1.05V (if off); and transitioning the gate voltages of the transistors 905, 906, 907, and 908 from approximately 1V to approximately 0.6V.

[0118] Specific implementation examples are described in the following numbered clauses:

[0119] 1. A header switch architecture for a stacked transistor structure, the header switch architecture comprising: a first header switch located in an active path, the first header switch configured to provide a supply voltage to a first cascode path; and a second header switch located in an inactive path, the second header switch configured to provide a reduced supply voltage to a second cascode path.

[0120] 2. The headswitch architecture of clause 1 , wherein the reduced supply voltage is provided by an auxiliary bias path comprising a pair of transistors and a resistor divider, the resistor divider configured to provide the reduced supply voltage to the second cascode path.

[0121] 3. A headswitch architecture according to any of clauses 1 or 2, wherein the reduced supply voltage is provided to the drain of the cascode transistor in the second cascode path.

[0122] 4. The headswitch architecture of clause 3, further comprising an external bias circuit configured to provide a gate voltage to a gate of the cascode transistor in the second cascode path to turn off the cascode transistor in the second cascode path.

[0123] 5. The head switch architecture of clause 4, further comprising maintaining the cascode transistor in the second cascode path in an off state when the cascode transistor in the first cascode path in the active path transitions from a standby state to a task mode state.

[0124] 6. The headswitch architecture of any of clauses 2 to 5, wherein the stacked transistor structure comprises at least a cascode transistor, a mixer transistor, a gain transistor, and a tail current source transistor.

[0125] 7. The headswitch architecture of clause 6, wherein the supply voltage is configured to be applied to the first cascode path before the reduced supply voltage is applied to the second cascode path.

[0126] 8. A headswitch architecture according to clause 7, wherein applying the supply voltage to the first cascode path before applying the reduced supply voltage to the second cascode path is configured to ensure that the tail current flows only through the first cascode path, the mixer transistor, the gain transistor and the tail current source transistor in the first cascode path.

[0127] 9. A method for biasing a stacked transistor structure, the method comprising: applying a supply voltage to a first cascode path; applying a reduced supply voltage to a second cascode path; and applying a gate voltage to the gate of a cascode transistor in the first cascode path to transition the cascode transistor in the first cascode path from an off and / or standby state to a mission mode state.

[0128] 10. The method of clause 9, further comprising resistively dividing the supply voltage to obtain the reduced supply voltage.

[0129] 11. The method of any of clauses 9 to 10, further comprising providing the reduced supply voltage to drains of cascode transistors in the second cascode path.

[0130] 12. A method according to any of clauses 9 to 11, wherein the first cascode path and the second cascode path each comprise a stacked transistor structure having at least a cascode transistor, a mixer transistor, a gain transistor and a tail current source transistor.

[0131] 13. The method of clause 12, further comprising applying the supply voltage to the first cascode path before applying the reduced supply voltage to the second cascode path.

[0132] 14. A method according to clause 13, wherein applying the supply voltage to the first cascode path before the reduced supply voltage is applied to the second cascode path ensures that the tail current flows only through the first cascode path, the mixer transistor, the gain transistor and the tail current source transistor in the first cascode path.

[0133] 15. A device comprising: means for applying a supply voltage to a first cascode path; means for applying a reduced supply voltage to a second cascode path; and means for applying a gate voltage to the gate of a cascode transistor in the first cascode path to transition the cascode transistor in the first cascode path from an off and / or standby state to a mission mode state.

[0134] 16. The apparatus of clause 15, further comprising means for resistively dividing the supply voltage to obtain the reduced supply voltage.

[0135] 17. Apparatus according to any of clauses 15 to 16, further comprising means for providing the reduced supply voltage to drains of cascode transistors in the second cascode path.

[0136] 18. Apparatus according to any of clauses 15 to 17, wherein the first cascode path and the second cascode path each comprise a stacked transistor structure having at least a cascode transistor, a mixer transistor, a gain transistor and a tail current source transistor.

[0137] 19. Apparatus according to any of clauses 15 to 18, further comprising means for applying the supply voltage to the first cascode path before applying the reduced supply voltage to the second cascode path.

[0138] 20. An apparatus according to clause 19, wherein the means for applying the supply voltage to the first cascode path before the reduced supply voltage is applied to the second cascode path ensures that tail current flows only through the first cascode path, the mixer transistor, the gain transistor and the tail current source transistor in the first cascode path.

[0139] 21. An apparatus, comprising: a first header switching circuit coupled between a supply voltage and a first cascode transistor, the first cascode transistor coupled to a plurality of stacked transistors, the first header switching circuit comprising a first path coupled between the supply voltage and the first cascode transistor and configured to provide a first voltage to a first node between the first header switching circuit and a terminal of the first cascode transistor, the first header switching circuit further comprising a second path coupled between the supply voltage and the first cascode transistor and configured to provide a voltage lower than the first voltage to the first node. a second voltage of the first header switching circuit; and a second header switching circuit, the second header switching circuit being coupled between the supply voltage and a second cascode transistor, the second cascode transistor being coupled to the plurality of stacked transistors, the second header switching circuit comprising a third path, the third path being coupled between the supply voltage and the second cascode transistor and being configured to provide a third voltage to a second node between the second header switching circuit and a terminal of the second cascode transistor, the first header switching circuit further comprising a fourth path, the fourth path being coupled between the supply voltage and the second cascode transistor and being configured to provide a fourth voltage, which is lower than the third voltage, to the second node.

[0140] 22. The apparatus of clause 21, wherein the first path comprises a transistor and the second path comprises a pair of transistors and a resistor divider.

[0141] 23. The apparatus of clause 22, wherein the third path comprises a transistor and the fourth path comprises a pair of transistors and a resistor divider.

[0142] 24. The apparatus of any of clauses 21 to 23, further comprising a mixer circuit comprising the plurality of stacked transistors.

[0143] 25. The apparatus of any of clauses 21 to 24, wherein the plurality of stacked transistors comprises a mixer transistor, a gain transistor, and a tail current source transistor.

[0144] 26. The apparatus of any of clauses 21 to 25, wherein the second cascode transistor is maintained in an off state when the first cascode transistor transitions from the standby state to the mission mode state.

[0145] The circuit architecture described herein may be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described herein may also be fabricated using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistor (HBT), high electron mobility transistor (HEMT), silicon on insulator (SOI), etc.

[0146] The apparatus implementing the circuits described herein may be a standalone device or may be part of a larger device. The device may be (i) a standalone IC, (ii) a collection of one or more ICs that may include a memory IC for storing data and / or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter / receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded in other devices, (vi) a receiver, a cellular phone, a wireless device, a handset, or a mobile unit, (vii) and the like.

[0147] While selected aspects have been illustrated and described in detail, it should be understood that various substitutions and changes can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A head switch architecture for a stacked transistor structure, the head switch architecture comprising: a first header switch, the first header switch being located in an active path, the first header switch being configured to provide a supply voltage to a first cascode path; and A second header switch is located in the inactive path, and the second header switch is configured to provide a reduced supply voltage to the second cascode path.

2. The headswitch architecture of claim 1 , wherein the reduced supply voltage is provided by an auxiliary bias path comprising a pair of transistors and a resistor divider, the resistor divider being configured to provide the reduced supply voltage to the second cascode path. 3 . The headswitch architecture of claim 1 , wherein the reduced supply voltage is provided to drains of cascode transistors in the second cascode path.

4. The headswitch architecture of claim 3 , further comprising an external bias circuit configured to provide a gate voltage to a gate of the cascode transistor in the second cascode path to turn off the cascode transistor in the second cascode path.

5. The headswitch architecture of claim 4 , further comprising maintaining the cascode transistor in the second cascode path in an off state when the cascode transistor in the first cascode path in the active path transitions from a standby state to a task mode state. 6 . The headswitch architecture of claim 1 , wherein the stacked transistor structure comprises at least a cascode transistor, a mixer transistor, a gain transistor, and a tail current source transistor. 7 . The headswitch architecture of claim 6 , wherein the supply voltage is configured to be applied to the first cascode path before the reduced supply voltage is applied to the second cascode path.

8. The headswitch architecture of claim 7 , wherein applying the supply voltage to the first cascode path before applying the reduced supply voltage to the second cascode path is configured to ensure that a tail current flows only through the first cascode path, the mixer transistor, the gain transistor, and the tail current source transistor in the first cascode path.

9. A method for biasing a stacked transistor structure, the method comprising: applying a supply voltage to the first cascode path; applying a reduced supply voltage to the second cascode path; as well as A gate voltage is applied to a gate of a cascode transistor in the first cascode path to transition the cascode transistor in the first cascode path from an off and / or standby state to a mission mode state. 10 . The method of claim 9 , further comprising resistively dividing the supply voltage to obtain the reduced supply voltage. 11 . The method of claim 9 , further comprising providing the reduced supply voltage to drains of cascode transistors in the second cascode path. 12 . The method of claim 9 , wherein the first cascode path and the second cascode path each comprise a stacked transistor structure having at least a cascode transistor, a mixer transistor, a gain transistor, and a tail current source transistor. 13 . The method of claim 12 , further comprising applying the supply voltage to the first cascode path before applying the reduced supply voltage to the second cascode path.

14. The method of claim 13 , wherein applying the supply voltage to the first cascode path before applying the reduced supply voltage to the second cascode path ensures that tail current flows only through the first cascode path, the mixer transistor, the gain transistor, and the tail current source transistor in the first cascode path.

15. A device comprising: means for applying a supply voltage to the first cascode path; means for applying a reduced supply voltage to the second cascode path; and Means for applying a gate voltage to a gate of a cascode transistor in the first cascode path to transition the cascode transistor in the first cascode path from an off and / or standby state to a mission mode state.

16. The apparatus of claim 15, further comprising means for resistively dividing the supply voltage to obtain the reduced supply voltage.

17. The apparatus of claim 15, further comprising means for providing the reduced supply voltage to drains of cascode transistors in the second cascode path.

18. The apparatus of claim 15, wherein the first cascode path and the second cascode path each comprise a stacked transistor structure having at least a cascode transistor, a mixer transistor, a gain transistor, and a tail current source transistor.

19. The apparatus of claim 18, further comprising means for applying the supply voltage to the first cascode path before applying the reduced supply voltage to the second cascode path.

20. The apparatus of claim 19, wherein the means for applying the supply voltage to the first cascode path before the reduced supply voltage is applied to the second cascode path ensures that a tail current flows only through the first cascode path, the mixer transistor, the gain transistor, and the tail current source transistor in the first cascode path.

21. A device comprising: a first header switching circuit coupled between a supply voltage and a first cascode transistor coupled to a plurality of stacked transistors, the first header switching circuit comprising a first path coupled between the supply voltage and the first cascode transistor and configured to provide a first voltage to a first node between terminals of the first header switching circuit and the first cascode transistor, the first header switching circuit further comprising a second path coupled between the supply voltage and the first cascode transistor and configured to provide a second voltage, lower than the first voltage, to the first node; and a second header switching circuit coupled between the supply voltage and a second cascode transistor, the second cascode transistor being coupled to the plurality of stacked transistors, the second header switching circuit comprising a third path coupled between the supply voltage and the second cascode transistor and configured to provide a third voltage to a second node between the second header switching circuit and a terminal of the second cascode transistor, the first header switching circuit further comprising a fourth path coupled between the supply voltage and the second cascode transistor and configured to provide a fourth voltage, lower than the third voltage, to the second node.

22. The apparatus of claim 21, wherein the first path comprises a transistor and the second path comprises a pair of transistors and a resistor divider.

23. The apparatus of claim 22, wherein the third path comprises a transistor and the fourth path comprises a pair of transistors and a resistor divider.

24. The apparatus of claim 21, further comprising a mixer circuit comprising the plurality of stacked transistors.

25. The apparatus of claim 21, wherein the plurality of stacked transistors comprises a mixer transistor, a gain transistor, and a tail current source transistor. 26 . The apparatus of claim 21 , wherein when the first cascode transistor transitions from a standby state to a mission mode state, the second cascode transistor is maintained in an off state.

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