Complementation method of three paths of PWM signals, computer equipment and readable storage medium

Abstract

The invention discloses a complementary method of three paths of PWM signals, computer equipment and a readable storage medium, and relates to the technical field of illumination, the method comprises the following steps: setting a counting mode of a timer as a central alignment mode, and dividing a counting period of the timer into a first half period and a second half period; initializing a front comparison value of a first half period, a rear comparison value of a second half period and an effective level of the first PWM channel, the second PWM channel and the third PWM channel, so as to enable a first PWM signal of the first PWM channel, a second PWM signal of the second PWM channel and a third PWM signal of the third PWM channel to be complementary; duty ratio set values of the first PWM signal, the second PWM signal and the third PWM signal are obtained in real time; and according to the duty ratio setting values of the first PWM signal, the second PWM signal and the third PWM signal, front comparison values, rear comparison values and effective levels of the first PWM channel, the second PWM channel and the third PWM channel are adjusted in real time, so that the first PWM signal, the second PWM signal and the third PWM signal are complementary. According to the invention, strict alternating and dynamic cooperative control of three paths of PWM signals can be realized.

Description

Technical Field

[0001] The present invention relates to the field of lighting technology, and in particular to a three-way PWM signal complementation method, a computer device, and a readable storage medium. Background Art

[0002] Pulse Width Modulation (PWM) technology, a core control method in the field of power electronics, is widely used in motor drives, power conversion, and lighting systems. In recent years, with the popularization of multi-channel loads (such as RGB LED lighting), the synchronous control of multiple PWM signals has become a key technical requirement. For example, in a mixed RGB lighting scenario, the brightness duty cycle of red, green, and blue lights must be independently adjusted through three PWM channels to ensure a constant total light intensity. This places stringent requirements on the timing synchronization and duty cycle coordination of the multi-channel PWM.

[0003] Traditional multi-channel PWM solutions typically use independent timers or channel time-sharing multiplexing, which has the following significant drawbacks:

[0004] (1) Risk of high-level overlap: When each channel operates independently, there is no mandatory association between the duty cycles, which can easily lead to high-level overlap of multiple PWM signals, causing instantaneous overcurrent in the circuit or color mixing distortion (such as RGB light color shift).

[0005] (2) Limitations of complementary PWM: Existing complementary PWM technology only supports paired channels (such as H-bridge drive) and avoids direct pass-through through dead time, but cannot be extended to strict time-sharing control of three independent channels, resulting in the inability to achieve complete alternation of three-color signals in RGB lighting.

[0006] (3) Insufficient dynamic adjustment capability: Current solutions rely on software to calculate the duty cycle in real time or external logic circuits (such as CPLD, Complex Programmable Logic Device) to coordinate multiple channels, which leads to response delays, high resource usage and increased costs. Especially when dynamically adjusting RGB colors, the total duty cycle is difficult to maintain constant, resulting in brightness fluctuations or color temperature deviations.

[0007] To address these issues, existing technologies attempt to achieve multi-channel coordination through time-sharing multiplexing or complex algorithms. However, due to hardware architecture limitations, these technologies still face bottlenecks such as poor real-time performance and insufficient stability. For example, software solutions require frequent interrupts to update registers, resulting in PWM waveform jitter or limiting the minimum duty cycle. External circuitry increases system complexity and power consumption, making them difficult to adapt to small, low-cost lighting equipment. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a complementary method for three PWM signals, a computer device and a readable storage medium, which can realize strict alternation and dynamic coordinated control of the three PWM signals.

[0009] In order to solve the above technical problems, the present invention provides a method for complementing three PWM signals, comprising: setting a counting mode of a timer to a center-aligned mode, and dividing the counting period of the timer into a first half period and a second half period; initializing a front comparison value of the first half period, a back comparison value of the second half period, and an effective level of a first PWM channel, a second PWM channel, and a third PWM channel, so that a first PWM signal of the first PWM channel, a second PWM signal of the second PWM channel, and a third PWM signal of the third PWM channel are complementary; obtaining duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal in real time; and adjusting the front comparison value, the back comparison value, and the effective level of the first PWM channel, the second PWM signal, and the third PWM signal in real time according to the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal, so that the first PWM signal, the second PWM signal, and the third PWM signal are complementary.

[0010] As an improvement to the above scheme, the step of initializing the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel includes: setting the effective level of the second PWM channel to a first level; setting the effective levels of the first PWM channel and the third PWM channel to a second level; wherein, when the first level is a high level, the second level is a low level, and when the first level is a low level, the second level is a high level.

[0011] As an improvement to the above solution, when the first level is high and the second level is low, the step of initializing the front comparison value of the first half cycle and the back comparison value of the second half cycle of the first PWM channel, the second PWM channel, and the third PWM channel includes: initializing the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal so that the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal are all less than 50%, and the sum of the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal is 100%; according to the formula CCR1=(T / 2-D PWM1 )×E, calculate the first front comparison value CCR1 of the first half cycle of the first PWM channel; according to the formula CCR2=(T / 2-D PWM1)×E, calculate the second front comparison value CCR2 of the first half cycle of the second PWM channel; according to the formula CCR3=(T / 2)×E, calculate the third front comparison value CCR3 of the first half cycle of the third PWM channel; according to the formula CCR1FALL=(T / 2)×E, calculate the first rear comparison value CCR1FALL of the second half cycle of the first PWM channel; according to the formula CCR2FALL=(T / 2-D PWM3 )×E, calculate the second comparison value CCR2FALL of the second half cycle of the second PWM channel; according to the formula CCR3FALL=(T / 2-D PWM3 )×E, calculate the third comparison value CCR3FALL of the second half cycle of the third PWM channel; wherein T is 100%, D PWM1 The duty cycle setting value of the first PWM signal, D PWM3 is the duty cycle setting value of the third PWM signal, and E is the resolution of PWM.

[0012] As an improvement to the above solution, when the first level is a low level and the second level is a high level, the steps of initializing the front comparison value of the first half cycle and the rear comparison value of the second half cycle of the first PWM channel, the second PWM channel, and the third PWM channel include: initializing the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal so that the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal are all less than 50%, and the sum of the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal is 100%; according to the formula CCR1=D PWM1 × E, calculate the first previous comparison value CCR1 of the first half cycle of the first PWM channel; according to the formula CCR2 = D PWM1 ×E, calculate the second front comparison value CCR2 of the first half cycle of the second PWM channel; according to the formula CCR3=0, calculate the third front comparison value CCR3 of the first half cycle of the third PWM channel; according to the formula CCR1FALL=0, calculate the first rear comparison value CCR1FALL of the second half cycle of the first PWM channel; according to the formula CCR2FALL=D PWM3 ×E, calculate the second comparison value CCR2FALL of the second half cycle of the second PWM channel; according to the formula CCR3FALL=D PWM3 ×E, calculate the third comparison value CCR3FALL of the second half cycle of the third PWM channel; where D PWM1 The duty cycle setting value of the first PWM signal, D PWM3 is the duty cycle setting value of the third PWM signal, and E is the resolution of PWM.

[0013] As an improvement to the above solution, the step of adjusting the effective levels of the first, second, and third PWM channels in real time based on the duty cycle settings of the first, second, and third PWM signals includes: when the duty cycle setting value of any one of the first, second, and third PWM signals is greater than 50%, selecting the PWM channel corresponding to the PWM signal with a duty cycle setting value greater than 50% as a first target PWM channel, selecting the PWM channel corresponding to a PWM signal with a duty cycle setting value less than 50% as a second target PWM channel, and selecting the PWM channel corresponding to another PWM signal with a duty cycle setting value less than 50% as a third target PWM channel; adjusting the effective level of the first target PWM channel to a first level; and adjusting the effective levels of the second and third target PWM channels to second levels.

[0014] As an improvement to the above solution, the step of adjusting the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal includes: when the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal are all less than or equal to 50%, maintaining the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel unchanged.

[0015] As an improvement to the above solution, when the first level is high and the second level is low, the step of adjusting the front comparison value and the rear comparison value of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal includes: according to the formula CCRa=(T / 2-D PWM’ )×E, calculate the first pre-target comparison value CCRa of the first half cycle of the first target PWM channel; according to the formula CCRb=(T / 2-D PWM’ )×E, calculate the second previous target comparison value CCRb of the first half cycle of the second target PWM channel; according to the formula CCRc=(T / 2)×E, calculate the third previous target comparison value CCRc of the first half cycle of the third target PWM channel; according to the formula CCRaFALL=(T / 2-D PWM” )×E, calculate the first target comparison value CCRaFALL of the second half cycle of the first target PWM channel; according to the formula CCRbFALL=(T / 2)×E, calculate the second target comparison value CCRbFALL of the second half cycle of the second target PWM channel; according to the formula CCRcFALL=(T / 2-D PWM”)×E, calculate the third target comparison value CCRcFALL of the second half cycle of the third target PWM channel; wherein T is 100%, D PWM’ The duty cycle setting value of a PWM signal with a duty cycle setting value less than 50%, D PWM” is the duty cycle setting value of another PWM signal whose duty cycle setting value is less than 50%, and E is the resolution of PWM.

[0016] As an improvement to the above solution, when the first level is low and the second level is high, the step of adjusting the front comparison value and the rear comparison value of the first PWM channel, the second PWM channel and the third PWM channel in real time according to the duty cycle setting values ​​of the first PWM signal, the second PWM signal and the third PWM signal includes: according to the formula CCRa=D PWM’ × E, calculate the first target comparison value CCRa of the first half cycle of the first target PWM channel; according to the formula CCRb=D PWM’ ×E, calculate the second previous target comparison value CCRb of the first half cycle of the second target PWM channel; according to the formula CCRc=0, calculate the third previous target comparison value CCRc of the first half cycle of the third target PWM channel; according to the formula CCRaFALL=D PWM” ×E, calculate the first target comparison value CCRaFALL of the second half cycle of the first target PWM channel; according to the formula CCRbFALL=0, calculate the second target comparison value CCRbFALL of the second half cycle of the second target PWM channel; according to the formula CCRcFALL=D PWM” ×E, calculate the third target comparison value CCRcFALL of the second half cycle of the third target PWM channel; where D PWM’ The duty cycle setting value of a PWM signal with a duty cycle setting value less than 50%, D PWM” is the duty cycle setting value of another PWM signal whose duty cycle setting value is less than 50%, and E is the resolution of PWM.

[0017] Accordingly, the present invention further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, wherein the processor implements the steps of the above-mentioned three-way PWM signal complementation method when executing the computer program.

[0018] Accordingly, the present invention further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-mentioned method for complementing three PWM signals.

[0019] The present invention can be implemented using a common M0 single-chip microcomputer. Through innovative timer configuration and duty cycle coupling mechanisms, the present invention achieves strict alternating output of three signals and a dynamic constant total duty cycle, fundamentally improving color accuracy and energy efficiency. The implementation of the present invention has the following beneficial effects:

[0020] (1) Zero overlap risk, ensuring circuit safety and color mixing accuracy;

[0021] (2) Simplify system design, reduce MCU resource usage and external circuits, and reduce costs;

[0022] (3) Hardware implementation avoids software jitter risks, and the PWM output frequency is high to ensure stable RGB lighting brightness. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 1 is a flow chart of a first embodiment of a method for complementing three PWM signals according to the present invention;

[0024] Figure 2 This is a waveform diagram of a first embodiment of three-way PWM signals in the present invention;

[0025] Figure 3 is a flow chart of a second embodiment of the three-way PWM signal complementation method of the present invention;

[0026] Figure 4 This is a waveform diagram of a second embodiment of three-way PWM signals in the present invention;

[0027] Figure 5 This is a waveform diagram of a third embodiment of three-way PWM signal in the present invention;

[0028] Figure 6 This is a waveform diagram of a fourth embodiment of three-way PWM signal in the present invention;

[0029] Figure 7 is a flow chart of a third embodiment of a method for complementing three PWM signals of the present invention;

[0030] Figure 8 This is a waveform diagram of a fifth embodiment of three-way PWM signal in the present invention;

[0031] Figure 9 This is a waveform diagram of a sixth embodiment of three-way PWM signal in the present invention. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be described in further detail below with reference to the accompanying drawings.

[0033] See also Figure 1 , Figure 1A flow chart of a first embodiment of a method for complementing three PWM signals of the present invention is shown, which includes:

[0034] S101, setting the counting mode of the timer to center alignment mode;

[0035] like Figure 2 As shown in the figure, △ABC is the triangle wave corresponding to the center-aligned mode, point B is the midpoint of the triangle wave, and line segment AC is the triangle wave period (i.e., count period / PWM period). Among them, PWM1, PWM2, and PWM3 are the three channels that output PWM signals in the timer. After adopting the center-aligned mode, the timer count period is divided into the first half period and the second half period by line segment BB'.

[0036] S102, initializing a front comparison value of a first half cycle, a rear comparison value of a second half cycle, and an effective level of a first PWM channel, a second PWM channel, and a third PWM channel, so that a first PWM signal of the first PWM channel, a second PWM signal of the second PWM channel, and a third PWM signal of the third PWM channel are complementary;

[0037] It should be noted that the present invention configures a timer to specify the front comparison value of the first half cycle, the back comparison value of the second half cycle and the effective level of each PWM channel, so as to specifically construct the waveform of the PWM signal.

[0038] On the one hand, the step of initializing the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel includes:

[0039] (1) setting the effective level of the second PWM channel to the first level;

[0040] (2) setting the effective levels of the first PWM channel and the third PWM channel to the second level;

[0041] For example, when the first level is a high level, the second level is a low level;

[0042] For another example, when the first level is a low level, the second level is a high level.

[0043] That is to say, when setting the effective level, it is only necessary to ensure that the effective level of the second PWM channel is different from the effective levels of the first PWM channel and the third PWM channel.

[0044] On the other hand, the front comparison value of the first half cycle and the rear comparison value of the second half cycle of each PWM channel are configured according to the preset duty cycle setting value of each PWM signal; during configuration, the configuration of the front comparison value and the rear comparison value can be achieved by setting the first half comparison register and the second half comparison register of each PWM channel.

[0045] For example, Figure 2 As shown in the figure, when the effective level of the first PWM channel is set to a low level, and the front comparison value in the first half comparison register is 17, and the back comparison value in the second half comparison register is 25, it means that the low level accounts for 17% and the high level accounts for 33% in the first half cycle, and the low level accounts for 25% and the high level accounts for 25% in the second half cycle; generally, the waveform is constructed with point B' as the starting position, so in the first half cycle, a low level interval of 17% is first constructed from point B' to point A, and then a high level interval of 33% is constructed, and a low level interval of 25% is first constructed from point B' to point C, and then a high level interval of 25%.

[0046] S103, acquiring duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal in real time;

[0047] S104, adjusting the front comparison value, the rear comparison value, and the effective level of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal, so that the first PWM signal of the first PWM channel, the second PWM signal of the second PWM channel, and the third PWM signal of the third PWM channel complement each other.

[0048] In actual operation, if the duty cycle setting of any PWM signal exceeds 50%, anomalies may occur. Therefore, the pre-comparison value, post-comparison value, and active level of the first, second, and third PWM channels must be adjusted in real time based on the duty cycle settings of the first, second, and third PWM signals to ensure that the first, second, and third PWM signals complement each other.

[0049] Accordingly, the step of adjusting the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal includes:

[0050] (1) When the duty cycle setting value of any PWM signal among the first PWM signal, the second PWM signal, and the third PWM signal is greater than 50%, the PWM channel corresponding to the PWM signal with the duty cycle setting value greater than 50% is used as the first target PWM channel, the PWM channel corresponding to the PWM signal with the duty cycle setting value less than 50% is used as the second target PWM channel, and the PWM channel corresponding to the other PWM signal with the duty cycle setting value less than 50% is used as the third target PWM channel; the effective level of the first target PWM channel is adjusted to the first level; and the effective levels of the second target PWM channel and the third target PWM channel are adjusted to the second level.

[0051] (2) When the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal are all less than or equal to 50%, the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel are kept unchanged.

[0052] At the same time, it is also necessary to adjust the front comparison value and the rear comparison value of the first PWM channel, the second PWM channel and the third PWM channel in real time according to the two PWM signals configured as the second level to ensure that the first PWM signal, the second PWM signal and the third PWM signal are complementary.

[0053] See also Figure 3 , Figure 3 A flow chart of a second embodiment of the method for complementing three PWM signals of the present invention is shown, which includes:

[0054] S201, setting the counting mode of the timer to center alignment mode;

[0055] S202, initializing duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal so that the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal are all less than 50%, and the sum of the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal is 100%;

[0056] S203, setting the effective level of the second PWM channel to a high level, and setting the effective levels of the first PWM channel and the third PWM channel to a low level;

[0057] S204 calculates the front comparison value of the first half cycle and the rear comparison value of the second half cycle of the first PWM channel, the second PWM channel, and the third PWM channel respectively according to a preset formula;

[0058] The specific calculation formula is as follows:

[0059] (1) According to the formula CCR1 = (T / 2-D PWM1 )×E, calculate the first front comparison value CCR1 of the first half cycle of the first PWM channel (that is, the value of the first half comparison register of the first PWM channel); where T is 100%, D PWM1 is the duty cycle setting value of the first PWM signal, and E is the PWM resolution. Generally, E is 100 or 1000, but it is not limited to this and can be set according to actual conditions.

[0060] (2) According to the formula CCR2 = (T / 2-D PWM1 )×E, calculating the second previous comparison value CCR2 of the first half cycle of the second PWM channel (i.e., the value of the first half comparison register of the second PWM channel);

[0061] (3) Calculating a third front comparison value CCR3 of the first half cycle of the third PWM channel (i.e., the value of the first half comparison register of the third PWM channel) according to the formula CCR3=(T / 2)×E;

[0062] (4) Calculate the first post-comparison value CCR1FALL (i.e., the value of the second-half comparison register of the first PWM channel) of the second half cycle of the first PWM channel according to the formula CCR1FALL=(T / 2)×E;

[0063] (5) According to the formula CCR2FALL=(T / 2-D PWM3 )×E, calculate the second comparison value CCR2FALL of the second half cycle of the second PWM channel (that is, the value of the second half comparison register of the second PWM channel); where D PWM3 Setting a duty cycle value for the third PWM signal;

[0064] (6) According to the formula CCR3FALL=(T / 2-D PWM3 )×E, and calculating a third rear comparison value CCR3FALL of the rear half cycle of the third PWM channel (ie, the value of the rear half comparison register of the third PWM channel).

[0065] like Figure 2 As shown, when the duty cycle setting value D of the first PWM signal PWM1 The duty cycle setting value D of the third PWM signal is 33%. PWM3 When it is 25%, the calculated pre-comparison value and post-comparison value are as follows:

[0066] The first pre-comparison value of the first half cycle of the first PWM channel is: CCR1=B'D'=(100% / 2-33%)×100=17; the first post-comparison value of the second half cycle of the first PWM channel is: CCR1FALL=B'C=(100% / 2)×100=50. Since the first PWM channel is configured as active low, the first PWM signal is low in the B'D' segment, high in the D'A segment, and low in the B'C segment.

[0067] The second front comparison value of the first half cycle of the second PWM channel is: CCR2 = B'D' = (100% / 2-33%) × 100 = 17; the second back comparison value of the second half cycle of the second PWM channel is: CCR2FALL = B'E' = (100% / 2-25%) × 100 = 25. Since the second PWM channel is configured as high-level active, the second PWM signal is high in the B'D' segment and low in the D'A segment, high in the B'E' segment, and low in the E'C segment.

[0068] The third pre-comparison value of the first half cycle of the third PWM channel is: CCR3=B'A=(100% / 2)×100=50; the third post-comparison value of the second half cycle of the third PWM channel is: CCR3FALL=B'E'=(100% / 2-25%)×100=25. Since the third PWM channel is configured as low-level active, the third PWM signal is low in the B'A segment, low in the B'E' segment, and high in the E'C segment.

[0069] Therefore, after configuring the values ​​of the first half comparison register and the second half comparison register of each channel by the above method, the three PWM signals can be made complementary.

[0070] S205, acquiring duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal in real time;

[0071] S206, adjusting the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal;

[0072] (1) When the duty cycle setting value of any PWM signal among the first PWM signal, the second PWM signal, and the third PWM signal is greater than 50%, the PWM channel corresponding to the PWM signal with a duty cycle setting value greater than 50% is used as the first target PWM channel, the PWM channel corresponding to the PWM signal with a duty cycle setting value less than 50% is used as the second target PWM channel, and the PWM channel corresponding to the other PWM signal with a duty cycle setting value less than 50% is used as the third target PWM channel; the effective level of the first target PWM channel is adjusted to a high level; and the effective levels of the second target PWM channel and the third target PWM channel are adjusted to a low level.

[0073] For example, if the duty cycle setting value of the first PWM signal is greater than 50%, the effective level of the first PWM channel is adjusted to a high level, and the effective levels of the second PWM channel and the third PWM channel are adjusted to a low level.

[0074] For another example, if the duty cycle setting value of the third PWM signal is greater than 50%, the effective level of the third PWM channel is adjusted to a high level, and the effective levels of the first PWM channel and the second PWM channel are adjusted to a low level.

[0075] (2) When the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal are all less than or equal to 50%, the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel are kept unchanged.

[0076] S207, calculating the pre-comparison value and the post-comparison value of the first PWM channel, the second PWM channel, and the third PWM channel respectively according to a preset formula;

[0077] The specific calculation formula is as follows:

[0078] (1) According to the formula CCRa=(T / 2-D PWM’ )×E, calculate the first pre-target comparison value CCRa of the first half cycle of the first target PWM channel; wherein T is 100%, D PWM’ The duty cycle setting value of a PWM signal with a duty cycle setting value less than 50% is E, which is the resolution of PWM. Generally, the value of E is 100 or 1000, but it is not limited to this and can be set according to actual conditions.

[0079] (2) According to the formula CCRb = (T / 2-D PWM’ )×E, calculating the second front target comparison value CCRb of the first half cycle of the second target PWM channel;

[0080] (3) Calculating a third pre-target comparison value CCRc of the first half cycle of the third target PWM channel according to the formula CCRc=(T / 2)×E;

[0081] (4) According to the formula CCRaFALL=(T / 2-D PWM” )×E, calculate the first target comparison value CCRaFALL of the second half cycle of the first target PWM channel; wherein, D PWM” a duty cycle setting value for another PWM signal whose duty cycle setting value is less than 50%;

[0082] (5) According to the formula CCRbFALL=(T / 2)×E, the second target comparison value CCRbFALL of the second half cycle of the second target PWM channel is calculated.

[0083] (6) According to the formula CCRcFALL=(T / 2-D PWM” )×E, calculating a third subsequent target comparison value CCRcFALL of the second half cycle of the third target PWM channel;

[0084] like Figure 4 As shown, when the duty cycle setting value of the first PWM signal is greater than 50% (the duty cycle setting value of the second PWM signal is D PWM’ The duty cycle setting value D of the third PWM signal is 15%. PWM” 25%), configure the first PWM channel to be active high, and the second and third PWM channels to be active low. The calculated pre-comparison value and post-comparison value are as follows:

[0085] CCR1=CCRa=B'D'=35

[0086] CCR2=CCRb=B'D'=35

[0087] CCR3=CCRc=B'A=50

[0088] CCR1FALL=CCRaFALL=B'E'=25

[0089] CCR2FALL=CCRbFALL=B'C=50

[0090] CCR3FALL=CCRcFALL=B'E'=25

[0091] like Figure 5 As shown, when the duty cycle setting value of the second PWM signal is greater than 50% (the duty cycle setting value of the first PWM signal is D PWM’ The duty cycle setting value D of the third PWM signal is 15%. PWM” 25%), configure the second PWM channel to be active high, and configure the first and third PWM channels to be active low. The calculated pre-comparison value and post-comparison value are as follows:

[0092] CCR1=CCRb=B'D'=35

[0093] CCR2=CCRa=B'D'=35

[0094] CCR3=CCRc=B'A=50

[0095] CCR1FALL=CCRbFALL=B'C=50

[0096] CCR2FALL=CCRaFALL=B'E'=25

[0097] CCR3FALL=CCRcFALL=B'E'=25

[0098] like Figure 6 As shown, when the duty cycle setting value of the third PWM signal is greater than 50% (the duty cycle setting value of the first PWM signal is D PWM’ The duty cycle setting value D of the second PWM signal is 15%. PWM” 25%), configure the third PWM channel to be active high, and configure the first and second PWM channels to be active low. The calculated pre-comparison value and post-comparison value are as follows:

[0099] CCR1=CCRb=B'D'=35

[0100] CCR2=CCRc=B'A=50

[0101] CCR3=CCRa=B'D'=35

[0102] CCR1 FALL=CCRbFALL=B'C=50

[0103] CCR2FALL=CCRcFALL=B'E'=25

[0104] CCR3FALL=CCRaFALL=B'E'=25

[0105] That is, the present invention can calculate the pre-comparison value and post-comparison value of the first PWM channel, the second PWM channel and the third PWM channel according to the duty cycle setting value of each PWM signal, thereby adjusting the waveforms of the first PWM signal, the second PWM signal and the third PWM signal.

[0106] Therefore, the present invention uses an innovative timer configuration and duty cycle coupling mechanism to achieve strict alternating output of three signals and dynamically constant total duty cycle, fundamentally eliminating the risk of high-level overlap, while simplifying system design and improving color accuracy and energy efficiency.

[0107] See also Figure 7 , Figure 7 A flowchart of a third embodiment of the method for complementing three PWM signals of the present invention is shown, which includes:

[0108] S301, setting the counting mode of the timer to center alignment mode;

[0109] S302, initializing duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal so that the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal are all less than 50%, and the sum of the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal is 100%;

[0110] S303, setting the effective level of the second PWM channel to a low level, and setting the effective levels of the first PWM channel and the third PWM channel to a high level;

[0111] S304 calculates the front comparison value of the first half cycle and the rear comparison value of the second half cycle of the first PWM channel, the second PWM channel, and the third PWM channel respectively according to a preset formula;

[0112] The specific calculation formula is as follows:

[0113] (1) According to the formula CCR1 = D PWM1 ×E, calculate the first previous comparison value CCR1 of the first half cycle of the first PWM channel; where DPWM1 is the duty cycle setting value of the first PWM signal, and E is the PWM resolution. Generally, E is 100 or 1000, but it is not limited to this and can be set according to actual conditions.

[0114] (2) According to the formula CCR2 = D PWM1 × E, calculate the second previous comparison value CCR2 of the first half cycle of the second PWM channel;

[0115] (3) Calculating a third previous comparison value CCR3 of the first half cycle of the third PWM channel according to the formula CCR3=0;

[0116] (4) According to the formula CCR1 FALL=0, calculate the first rear comparison value CCR1 FALL of the second half cycle of the first PWM channel;

[0117] (5) According to the formula CCR2FALL=D PWM3 ×E, calculate the second comparison value CCR2FALL of the second half cycle of the second PWM channel; where D PWM3 Setting a duty cycle value for the third PWM signal;

[0118] (6) According to the formula CCR3FALL=D PWM3 ×E, calculate the third rear comparison value CCR3FALL of the second half cycle of the third PWM channel;

[0119] like Figure 8 As shown, when the duty cycle setting value D of the first PWM signal PWM1 The duty cycle setting value D of the third PWM signal is 33%. PWM3 When it is 20%, the calculated pre-comparison value and post-comparison value are as follows:

[0120] The first pre-comparison value of the first half cycle of the first PWM channel is: CCR1 = B'D' = 33% × 100 = 33; the first post-comparison value of the second half cycle of the first PWM channel is: CCR1 FALL = 0. Since the first PWM channel is configured as active high, the first PWM signal is high in the B'D' segment, low in the D'A segment, and low in the B'C segment.

[0121] The second front comparison value of the first half cycle of the second PWM channel is: CCR2 = B'D' = 33% × 100 = 33; the second back comparison value of the second half cycle of the second PWM channel is: CCR2FALL = B'E' = 20% × 100 = 20. Since the second PWM channel is configured as low-level active, the second PWM signal is low in the B'D' segment and high in the D'A segment, low in the B'E' segment, and high in the E'C segment.

[0122] The third pre-comparison value of the first half cycle of the third PWM channel is: CCR3 = 0; the third post-comparison value of the second half cycle of the third PWM channel is: CCR3FALL = B'E' = 20% × 100 = 20. Since the third PWM channel is configured as high-level active, the third PWM signal is low in the B'A segment, high in the B'E' segment, and low in the E'C segment.

[0123] Therefore, after configuring the values ​​of the first half comparison register and the second half comparison register of each channel by the above method, the three PWM signals can be made complementary.

[0124] S305, acquiring duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal in real time;

[0125] S306, adjusting the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal;

[0126] (1) When the duty cycle setting value of any PWM signal among the first PWM signal, the second PWM signal, and the third PWM signal is greater than 50%, the PWM channel corresponding to the PWM signal with a duty cycle setting value greater than 50% is used as the first target PWM channel, the PWM channel corresponding to the PWM signal with a duty cycle setting value less than 50% is used as the second target PWM channel, and the PWM channel corresponding to the other PWM signal with a duty cycle setting value less than 50% is used as the third target PWM channel; the effective level of the first target PWM channel is adjusted to a low level; and the effective levels of the second target PWM channel and the third target PWM channel are adjusted to a high level.

[0127] (2) When the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal are all less than or equal to 50%, the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel are kept unchanged.

[0128] S307, calculating the pre-comparison value and post-comparison value of the first PWM channel, the second PWM channel, and the third PWM channel respectively according to a preset formula;

[0129] The specific calculation formula is as follows:

[0130] (1) According to the formula CCRa=D PWM’ ×E, calculate the first pre-target comparison value CCRa of the first half cycle of the first target PWM channel; where D PWM’The duty cycle setting value of a PWM signal with a duty cycle setting value less than 50% is E, which is the resolution of PWM. Generally, the value of E is 100 or 1000, but it is not limited to this and can be set according to actual conditions.

[0131] (2) According to the formula CCRb=D PWM’ × E, calculate the second previous target comparison value CCRb of the first half cycle of the second target PWM channel;

[0132] (3) Calculating a third pre-target comparison value CCRc of the first half cycle of the third target PWM channel according to the formula CCRc=0;

[0133] (4) According to the formula CCRaFALL=D PWM” ×E, calculate the first target comparison value CCRaFALL of the second half cycle of the first target PWM channel; where D PWM” a duty cycle setting value for another PWM signal whose duty cycle setting value is less than 50%;

[0134] (5) According to the formula CCRbFALL=0, calculate the second target comparison value CCRbFALL of the second target PWM channel in the second half cycle;

[0135] (6) According to the formula CCRcFALL=D PWM” ×E, calculate the third target comparison value CCRcFALL of the second half cycle of the third target PWM channel;

[0136] like Figure 9 As shown, when the duty cycle setting value of the first PWM signal is greater than 50% (the duty cycle setting value of the second PWM signal is D PWM’ The duty cycle setting value D of the third PWM signal is 15%. PWM” 25%), configure the first PWM channel to be active low, and the second and third PWM channels to be active high. The calculated pre-comparison value and post-comparison value are as follows:

[0137] CCR1=CCRa=B'D'=15

[0138] CCR2=CCRb=B'D'=15

[0139] CCR3=CCRc=0

[0140] CCR1 FALL=CCRaFALL=B'E'=25

[0141] CCR2FALL=CCRbFALL=0

[0142] CCR3FALL=CCRcFALL=B'E'=25

[0143] As can be seen from the above, the present invention can be implemented by a common M0 single-chip microcomputer. The present invention can realize strict alternation and dynamic coordinated control of three PWM signals through a hardware timer, and has the following core advantages:

[0144] (1) Zero overlap risk, ensuring circuit safety and color mixing accuracy;

[0145] (2) Simplify system design, reduce MCU resource usage and external circuits, and reduce costs;

[0146] (3) Hardware implementation avoids software jitter risks, and the PWM output frequency is high to ensure stable RGB lighting brightness.

[0147] Correspondingly, the present invention further discloses a computer device, comprising a memory and a processor, wherein the memory stores a computer program, wherein the processor implements the steps of the above-mentioned three-way PWM signal complementation method when executing the computer program.

[0148] At the same time, the present invention also discloses a computer-readable storage medium on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of the above-mentioned method for complementing three PWM signals.

[0149] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for complementing three PWM signals, characterized in that: include: The counting mode of the timer is set to the center alignment mode, and the counting period of the timer is divided into a first half period and a second half period; Initializing a front comparison value of a first half cycle, a rear comparison value of a second half cycle, and an effective level of a first PWM channel, a second PWM channel, and a third PWM channel so that a first PWM signal of the first PWM channel, a second PWM signal of the second PWM channel, and a third PWM signal of the third PWM channel are complementary; Acquire duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal in real time; The front comparison value, the rear comparison value and the effective level of the first PWM channel, the second PWM channel and the third PWM channel are adjusted in real time according to the duty cycle setting values ​​of the first PWM signal, the second PWM signal and the third PWM signal, so that the first PWM signal, the second PWM signal and the third PWM signal are complementary.

2. The method for complementing three PWM signals according to claim 1, wherein: The step of initializing the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel includes: Setting the effective level of the second PWM channel to the first level; Setting the effective levels of the first PWM channel and the third PWM channel to a second level; When the first level is a high level, the second level is a low level; and when the first level is a low level, the second level is a high level.

3. The complementary method of three PWM signals according to claim 2, wherein: When the first level is a high level and the second level is a low level, the step of initializing the front comparison value of the first half cycle and the rear comparison value of the second half cycle of the first PWM channel, the second PWM channel, and the third PWM channel includes: Initializing duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal so that the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal are all less than 50%, and the sum of the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal is 100%; According to the formula CCR1=(T / 2-D PWM1 )×E, calculating the first previous comparison value CCR1 of the first half cycle of the first PWM channel; According to the formula CCR2=(T / 2-D PWM1 )×E, calculating the second previous comparison value CCR2 of the first half cycle of the second PWM channel; Calculate the third previous comparison value CCR3 of the first half cycle of the third PWM channel according to the formula CCR3=(T / 2)×E; According to the formula CCR1FALL=(T / 2)×E, a first post-comparison value CCR1FALL of the second half cycle of the first PWM channel is calculated; According to the formula CCR2FALL=(T / 2-D PWM3 )×E, calculating the second rear comparison value CCR2FALL of the second half cycle of the second PWM channel; According to the formula CCR3FALL=(T / 2-D PWM3 )×E, calculating a third rear comparison value CCR3FALL of the second half cycle of the third PWM channel; Among them, T is 100%, D PWM1 The duty cycle setting value of the first PWM signal, D PWM3 is the duty cycle setting value of the third PWM signal, and E is the resolution of PWM.

4. The method for complementing three PWM signals as claimed in claim 2, wherein: When the first level is a low level and the second level is a high level, the steps of initializing the front comparison value of the first half cycle and the rear comparison value of the second half cycle of the first PWM channel, the second PWM channel, and the third PWM channel include: Initializing duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal so that the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal are all less than 50%, and the sum of the duty cycle settings of the first PWM signal, the second PWM signal, and the third PWM signal is 100%; According to the formula CCR1=D PWM1 ×E, calculate the first previous comparison value CCR1 of the first half cycle of the first PWM channel; According to the formula CCR2=D PWM1 × E, calculate the second previous comparison value CCR2 of the first half cycle of the second PWM channel; According to the formula CCR3=0, a third previous comparison value CCR3 of the first half cycle of the third PWM channel is calculated; According to the formula CCR1FALL=0, calculate the first rear comparison value CCR1FALL of the second half cycle of the first PWM channel; According to the formula CCR2FALL=D PWM3 × E, calculate the second rear comparison value CCR2FALL of the second half cycle of the second PWM channel; According to the formula CCR3FALL=D PWM3 ×E, calculate the third rear comparison value CCR3FALL of the second half cycle of the third PWM channel; Among them, D PWM1 The duty cycle setting value of the first PWM signal, D PWM3 is the duty cycle setting value of the third PWM signal, and E is the resolution of PWM.

5. The method for complementing three PWM signals as claimed in claim 2, wherein: The step of adjusting the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal comprises: When the duty cycle setting value of any PWM signal among the first PWM signal, the second PWM signal, and the third PWM signal is greater than 50%, the PWM channel corresponding to the PWM signal with the duty cycle setting value greater than 50% is used as the first target PWM channel, the PWM channel corresponding to the PWM signal with the duty cycle setting value less than 50% is used as the second target PWM channel, and the PWM channel corresponding to the other PWM signal with the duty cycle setting value less than 50% is used as the third target PWM channel; adjusting the effective level of the first target PWM channel to a first level; The effective levels of the second target PWM channel and the third target PWM channel are adjusted to a second level.

6. The method for complementing three PWM signals as claimed in claim 2, wherein: The step of adjusting the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal comprises: When the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal are all less than or equal to 50%, the effective levels of the first PWM channel, the second PWM channel, and the third PWM channel are kept unchanged.

7. The method for complementing three PWM signals as claimed in claim 2, wherein: When the first level is high and the second level is low, the step of adjusting the front comparison value and the rear comparison value of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal comprises: According to the formula CCRa=(T / 2-D PWM’ )×E, calculating a first pre-target comparison value CCRa of the first half cycle of the first target PWM channel; According to the formula CCRb=(T / 2-D PWM’ )×E, calculating the second front target comparison value CCRb of the first half cycle of the second target PWM channel; Calculate the third previous target comparison value CCRc of the first half cycle of the third target PWM channel according to the formula CCRc=(T / 2)×E; According to the formula CCRaFALL=(T / 2-D PWM” )×E, calculating a first subsequent target comparison value CCRaFALL of the second half cycle of the first target PWM channel; According to the formula CCRbFALL=(T / 2)×E, the second target comparison value CCRbFALL of the second half cycle of the second target PWM channel is calculated; According to the formula CCRcFALL=(T / 2-D PWM” )×E, calculating a third subsequent target comparison value CCRcFALL of the second half cycle of the third target PWM channel; Among them, T is 100%, D PWM’ The duty cycle setting value of a PWM signal with a duty cycle setting value less than 50%, D PWM” is the duty cycle setting value of another PWM signal whose duty cycle setting value is less than 50%, and E is the resolution of PWM.

8. The method for complementing three PWM signals as claimed in claim 2, wherein: When the first level is a low level and the second level is a high level, the step of adjusting the front comparison value and the rear comparison value of the first PWM channel, the second PWM channel, and the third PWM channel in real time according to the duty cycle setting values ​​of the first PWM signal, the second PWM signal, and the third PWM signal includes: According to the formula CCRa=D PWM’ × E, calculate the first previous target comparison value CCRa of the first half cycle of the first target PWM channel; According to the formula CCRb=D PWM’ × E, calculate the second previous target comparison value CCRb of the first half cycle of the second target PWM channel; According to the formula CCRc=0, a third previous target comparison value CCRc of the first half cycle of the third target PWM channel is calculated; According to the formula CCRaFALL=D PWM” ×E, calculate the first target comparison value CCRaFALL of the second half cycle of the first target PWM channel; According to the formula CCRbFALL=0, calculate the second target comparison value CCRbFALL of the second half cycle of the second target PWM channel; According to the formula CC RcFALL = D PWM” ×E, calculate the third target comparison value CCRcFALL of the second half cycle of the third target PWM channel; Among them, D PWM’ The duty cycle setting value of a PWM signal with a duty cycle setting value less than 50%, D PWM” is the duty cycle setting value of another PWM signal whose duty cycle setting value is less than 50%, and E is the resolution of PWM.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the three-way PWM signal complementation method according to any one of claims 1 to 8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the three-way PWM signal complementation method according to any one of claims 1 to 8 are implemented.

Images