Groove type insulated gate bipolar transistor and manufacturing method thereof

Abstract

The invention discloses a groove type insulated gate bipolar transistor and a manufacturing method. The groove type insulated gate bipolar transistor comprises a first electrode layer; the drift layer is arranged on one side of the first electrode layer in the first direction; the plurality of gate trench regions are arranged in the drift layer at intervals along the second direction, and each gate trench region extends from the first surface of the drift layer to the first electrode layer; a plurality of base regions, each base region is arranged between two adjacent gate trench regions, each base region is internally provided with a plurality of highly-doped layers which are stacked along a first direction, and the highly-doped layers and the gate trench regions at two sides are arranged at intervals; the second electrode layer is arranged on the first surface of the drift layer and is connected with the highly doped layer; the drift layer and the second electrode layer have a first conduction type, the first electrode layer, the base region and the highly doped layer have a second conduction type, and the doping concentration of the highly doped layer is greater than that of the base region. The groove type insulated gate bipolar transistor and the manufacturing method aim at improving the device performance of the groove type insulated gate bipolar transistor.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a trench-type insulated gate bipolar transistor and a manufacturing method thereof. Background Art

[0002] Among semiconductor devices, IGBTs (Insulated-Gate Bipolar Transistors) are one type of high-power switching device. IGBTs are further categorized into planar IGBTs and trench IGBTs. Trench IGBTs have a smaller gate mesa area than planar IGBTs, resulting in lower conduction losses.

[0003] However, in current narrow-mesa trench IGBTs, the collector-induced barrier lowering effect is prevalent, causing latch-up during device short-circuit, resulting in lower short-circuit robustness of the trench IGBT and affecting the overall performance of the device. Summary of the Invention

[0004] The embodiments of the present application provide a trench-type insulated gate bipolar transistor and a manufacturing method thereof, aiming to improve the device performance of the trench-type insulated gate bipolar transistor.

[0005] An embodiment of the present application provides a trench-type insulated gate bipolar transistor, which includes a first electrode layer; a drift layer, which is arranged on one side of the first electrode layer in a first direction; a plurality of gate trench regions, which are arranged in the drift layer at intervals along a second direction, and each gate trench region extends from the first surface of the drift layer toward the first electrode layer; a plurality of base regions, a base region is provided between two adjacent gate trench regions, and each base region has a plurality of high-doped layers stacked along the first direction, and the plurality of high-doped layers are spaced apart from the gate trench regions on both sides; a second electrode layer, which is arranged on the first surface of the drift layer and connected to the high-doped layer; wherein the drift layer and the second electrode layer have a first conductivity type, the first electrode layer, the base region and the high-doped layer have a second conductivity type, and the doping concentration of the high-doped layer is greater than the doping concentration of the base region.

[0006] A trench-type insulated gate bipolar transistor as described above, wherein the second electrode layer includes a second metal layer and a second semiconductor layer connected to each other, the second semiconductor layer is arranged on the first surface of the drift layer and is connected to the base region and a portion of the highly doped layer, and at least a portion of the second metal layer passes through the second semiconductor layer along the first direction and is connected to the highly doped layer.

[0007] A trench-type insulated gate bipolar transistor as described above, wherein the second electrode layer further includes a dielectric layer, a first connecting portion and a second connecting portion vertically connected to the second metal layer, the first connecting portion, the dielectric layer and the second semiconductor layer are stacked in sequence along the first direction, the second connecting portion passes through the dielectric layer and the second semiconductor layer in sequence along the first direction, and is connected to the highly doped layer.

[0008] A trench-type insulated gate bipolar transistor as described above, which further includes multiple carrier storage regions, wherein a carrier storage region is provided between two adjacent gate trench regions, and the carrier storage regions are arranged in a one-to-one correspondence with the base regions, and each carrier storage region is connected to a side of the corresponding base region close to the first electrode layer; wherein the carrier storage region has a first conductivity type, and the doping concentration of the carrier storage region is higher than the doping concentration of the drift layer.

[0009] As described above, a trench-type insulated gate bipolar transistor, wherein the multiple highly doped layers have a first depth H1 in the first direction, and the base region has a second depth H2 in the first direction, wherein 10% H2 ≤ H1 ≤ 130% H2.

[0010] In the trench-type insulated gate bipolar transistor as described above, the width of each highly doped layer in the second direction increases along the first direction.

[0011] As described above, a trench-type insulated gate bipolar transistor, wherein each highly doped layer has a spacing distance D from the gate trench region on either side in the second direction, wherein D>0.1 μm.

[0012] The trench-type insulated gate bipolar transistor as described above further includes an electric field stop layer, which is arranged between the first electrode layer and the drift layer. The electric field stop layer has the first conductivity type, and the doping concentration of the electric field stop layer is higher than the doping concentration of the drift layer.

[0013] In the trench-type insulated gate bipolar transistor as described above, the first electrode layer includes a first metal layer and a first semiconductor layer stacked along a first direction, and the first semiconductor layer is provided on a side of the first metal layer close to the drift layer.

[0014] On the other hand, the present application also provides a method for manufacturing a trench-type insulated gate bipolar transistor, wherein the method for manufacturing the above-mentioned trench-type insulated gate bipolar transistor comprises:

[0015] providing a drift layer having a first conductivity type;

[0016] Etching a first surface of the drift layer to form a trench and forming polysilicon in the trench to form a plurality of gate trench regions;

[0017] Performing low-energy ion implantation of the second conductivity type between adjacent gate trench regions from the first surface of the drift layer, and pushing wells to form a plurality of base regions;

[0018] A second semiconductor layer and a dielectric layer having a first conductivity type are provided on the first surface of the drift layer, and a receiving groove extending along a first direction is formed by etching;

[0019] Performing multiple high-energy ion implantations of the second conductivity type into each base region from the receiving groove, and activating and forming multiple highly doped layers stacked along the first direction and spaced apart from the gate trench regions on both sides;

[0020] A second metal layer is disposed on the surface of the second semiconductor layer and the dielectric layer on one side of the drift layer to form a second electrode layer with a first conductivity type, and a first electrode layer with a second conductivity type is disposed on the other side of the drift layer.

[0021] The trench-type insulated gate bipolar transistor of the present application includes a first electrode layer, a drift layer, multiple gate trench regions, multiple base regions, multiple highly doped layers and a second electrode layer. The second electrode layer is provided on the first surface of the drift layer, and the first electrode layer is provided on the other side in the first direction. The multiple gate trench regions are arranged in the drift layer at intervals along the second direction and extend from the first surface toward the first electrode layer to form a trench gate structure of the insulated gate bipolar transistor. The structural arrangement of the gate trench regions makes the width of the base region between adjacent gate trench regions shorter in the second direction, so that the overall device has lower conduction loss.

[0022] Each base region has multiple highly doped layers stacked along a first direction, thereby forming a highly doped region extending along the first direction. Because the doping concentration of the highly doped region formed by the multiple highly doped layers is greater than the doping concentration of the base region, when the device is turned on, holes in the base region can be concentrated toward the region of the multiple highly doped layers, thereby forming a current path within the multiple highly doped layers, thereby avoiding excessive holes in the base region during the device short-circuit process, which could cause latch-up in the entire device. Therefore, the trench-type insulated gate bipolar transistor of the present application has high short-circuit robustness, improving the overall performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 A schematic diagram of the overall structure of a trench-type insulated gate bipolar transistor according to an embodiment of the present application;

[0025] Figure 2A schematic diagram of the internal hole path of a trench insulated gate bipolar transistor according to an embodiment of the present application;

[0026] Figure 3 A comparison diagram of short-circuit waveforms of a trench insulated gate bipolar transistor according to an embodiment of the present application and a structure according to the prior art;

[0027] Figure 4 This is a schematic diagram of the overall structure of another trench-type insulated gate bipolar transistor according to an embodiment of the present application;

[0028] Figure 5 This is a flow chart of a method for manufacturing a trench insulated gate bipolar transistor according to an embodiment of the present application.

[0029] Description of Figure Numbers:

[0030] 1. First electrode layer; 11. First metal layer; 12. First semiconductor layer; 2. Drift layer; 21. First surface; 3. Gate trench region; 4. Base region; 5. Highly doped layer; 6. Second electrode layer; 61. Second metal layer; 611. First connecting portion; 612. Second connecting portion; 62. Second semiconductor layer; 63. Dielectric layer; 64. Receiving groove; 7. Carrier storage region; 8. Electric field stop layer;

[0031] X, first direction; Y, second direction. DETAILED DESCRIPTION

[0032] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0033] like Figures 1 to 4As shown, an embodiment of the present application provides a trench-type insulated gate bipolar transistor, which includes a first electrode layer 1; a drift layer 2, which is arranged on one side of the first electrode layer 1 in a first direction X; a plurality of gate trench regions 3, which are arranged in the drift layer 2 at intervals along a second direction Y, and each gate trench region 3 extends from the first surface 21 of the drift layer 2 toward the first electrode layer 1; a plurality of base regions 4, wherein a base region 4 is provided between two adjacent gate trench regions 3, and each base region 4 has a plurality of highly doped layers 5 stacked along the first direction X, and the plurality of highly doped layers 5 are spaced apart from the gate trench regions 3 on both sides; a second electrode layer 6, which is provided on the first surface 21 of the drift layer 2 and connected to the highly doped layer 5; wherein the drift layer 2 and the second electrode layer 6 have a first conductivity type, the first electrode layer 1, the base region 4 and the highly doped layer 5 have a second conductivity type, and the doping concentration of the highly doped layer 5 is greater than the doping concentration of the base region 4.

[0034] It should be noted that the first direction X is Figure 1 The vertical direction in the second direction Y is Figure 1 Horizontal direction in .

[0035] The first conductivity type is a conductivity type having N-type doping, and the second conductivity type is a conductivity type having P-type doping.

[0036] In specific implementation, the trench-type insulated gate bipolar transistor of the present application includes a first electrode layer 1, a drift layer 2, multiple gate trench regions 3, multiple base regions 4, multiple layers of highly doped layers 5 and a second electrode layer 6. The second electrode layer 6 is provided on the first surface 21 of the drift layer 2, and the first electrode layer 1 is provided on the other side of the first direction X. The multiple gate trench regions 3 are arranged at intervals in the drift layer 2 along the second direction Y, and extend from the first surface 21 toward the first electrode layer 1 to form a trench gate structure of the insulated gate bipolar transistor. The structural setting of the gate trench region 3 makes the width of the base region 4 between adjacent gate trench regions 3 in the second direction Y shorter, so that the overall device has lower conduction loss.

[0037] In each base region 4, there are multiple layers of highly doped layers 5 stacked along the first direction X, thereby forming a highly doped region extending along the first direction X. Since the doping concentration of the highly doped region formed by the multiple layers of highly doped layers 5 is greater than the doping concentration of the base region 4, as shown in FIG. Figure 2 As shown, Figure 2The dotted path in the figure is the flow path of holes inside the device. When the device is turned on, the holes in the base region 4 can be concentrated toward the area of ​​the multi-layer highly doped layer 5, thereby forming a current path within the multi-layer highly doped layer 5, avoiding too many holes in the base region 4 during the short circuit of the device; if the current path formed by the movement of holes is distributed in the base region 4, due to the low doping concentration of the base region 4, the NPN transistor formed by the drift layer 2, the base region 4 and the second electrode layer 6 will form a latch-up phenomenon during the short circuit of the device, thereby affecting the overall performance of the device. However, the high doping concentration of the highly doped layer 5 is high, which will not cause the transistor to be turned on, thereby avoiding the occurrence of the latch-up phenomenon. Therefore, the trench-type insulated gate bipolar transistor of the present application has high short-circuit robustness and improves the overall performance of the device.

[0038] like Figure 3 As shown, Figure 3 A comparison diagram of the short-circuit waveform of the trench insulated gate bipolar transistor of the embodiment of the present application and the short-circuit waveform of the trench insulated gate bipolar transistor in the prior art is shown, wherein the dotted line portion is the short-circuit waveform of the prior art structure. After the short-circuit process of the device continues for a period of time, the current will change from a constant state to a sharply rising state, which indicates that the device has a latch-up phenomenon during the short-circuit process. Therefore, the short-circuit robustness of the device in the prior art is low and the occurrence of the latch-up phenomenon cannot be avoided; the solid line portion is the short-circuit waveform of the trench insulated gate bipolar transistor of the embodiment of the present application. It can be clearly seen that the current will not rise sharply during the short-circuit process, so the device does not have a latch-up phenomenon, thereby improving the overall anti-latch capability of the device and further improving the short-circuit robustness of the device.

[0039] A trench-type insulated gate bipolar transistor according to an embodiment of the present application further includes a plurality of carrier storage regions 7, wherein a carrier storage region 7 is provided between each adjacent gate trench region 3, and the carrier storage regions 7 are arranged in a one-to-one correspondence with the base regions 4, and each carrier storage region 7 is connected to a side of the corresponding base region 4 close to the first electrode layer 1; wherein the carrier storage region 7 has a first conductivity type, and the doping concentration of the carrier storage region 7 is higher than the doping concentration of the drift layer 2.

[0040] In specific implementation, when the device is turned on, the carrier storage area 7 can block the movement of holes and accumulate in the drift layer 2 close to the carrier storage area 7, thereby increasing the carrier concentration of the drift layer 2 and reducing the overall saturation voltage Vcesat of the device.

[0041] In a trench insulated gate bipolar transistor according to an embodiment of the present application, the multi-layer highly doped layer 5 has a first depth H1 in the first direction X, and the base region 4 has a second depth H2 in the first direction X, wherein 10% H2≤H1≤130% H2.

[0042] In a specific implementation, the first depth H1 of the multi-layer highly doped layer 5 is ≥ 10% H2, so that during the hole transfer process, there is a sufficient distance in the first direction X to complete the flow convergence into the highly doped layer 5, so that most holes are concentrated in the highly doped layer 5 and ultimately flow to the second metal layer 61. Therefore, the setting of the minimum depth of the first depth H1 ensures that the device suppresses the latch-up phenomenon, allowing the entire device to maintain high short-circuit robustness, and thus providing high overall device performance.

[0043] Furthermore, the first depth H1 of the multi-layer highly doped layer 5 is ≤ 130% H2, thereby preventing the multi-layer highly doped layer 5 from extending too deeply into the carrier storage region 7 or the drift layer 2, thereby affecting the characteristics of the carrier storage region 7 or the drift layer 2 itself.

[0044] like Figure 4 As shown, a trench-type insulated gate bipolar transistor according to an embodiment of the present application is provided, wherein along the first direction X, the width of each highly doped layer 5 in the second direction Y increases progressively.

[0045] In specific implementations, the width of each highly doped layer 5 in the second direction Y increases. When holes enter the base region 4, they first enter the lowest, widest highly doped layer 5. The width of the lowest highly doped layer 5 ensures its attraction to holes within the base region 4. As the width of the highly doped layer 5 decreases from bottom to top, holes flow toward the center in the second direction Y and ultimately converge at the second metal layer 61. Therefore, the increasing width of the highly doped layer 5 further enhances the hole confluence effect, thereby further improving the device's latch-up suppression effect, enhancing the overall short-circuit robustness of the device, and improving overall device performance.

[0046] In a trench-type insulated gate bipolar transistor according to an embodiment of the present application, each highly doped layer 5 has a spacing distance D from the gate trench region 3 on either side in the second direction Y, where D>0.1 μm.

[0047] In specific implementation, each layer of the highly doped layer 5 is spaced apart from the gate trench regions 3 on both sides, and the spacing distance D is greater than 0.1 μm, thereby avoiding the highly doped layer 5 from having an excessive impact on the area of ​​the base region 4, and further avoiding the highly doped layer 5 from affecting the overall characteristics of the device, thereby ensuring the overall performance of the device.

[0048] A trench-type insulated gate bipolar transistor according to an embodiment of the present application further includes an electric field stop layer 8, which is arranged between the first electrode layer 1 and the drift layer 2. The electric field stop layer 8 has a first conductivity type, and the doping concentration of the electric field stop layer 8 is higher than the doping concentration of the drift layer 2.

[0049] In practice, by providing an electric field stop layer 8 with a higher doping concentration, the thickness of the device's drift layer 2 can be reduced, thereby lowering the device's Vcesat while maintaining the device's withstand voltage. Furthermore, when the device is turned off, the hole tail time is shortened, thereby improving the device's overall turn-off efficiency and reducing the turn-off loss Eoff.

[0050] An embodiment of the present application provides a trench-type insulated gate bipolar transistor, wherein the first electrode layer 1 includes a first metal layer 11 and a first semiconductor layer 12 stacked along a first direction X, and the first semiconductor layer 12 is provided on a side of the first metal layer 11 close to the drift layer 2.

[0051] An embodiment of the present application provides a trench-type insulated gate bipolar transistor, wherein the second electrode layer 6 includes a second metal layer 61 and a second semiconductor layer 62 connected to each other, the second semiconductor layer 62 is provided on the first surface 21 of the drift layer 2 and is connected to the base region 4 and a portion of the highly doped layer 5, and at least a portion of the second metal layer 61 passes through the second semiconductor layer 62 along the first direction X and is connected to the highly doped layer 5.

[0052] In specific implementation, the first electrode layer 1 and the second electrode layer 6 can respectively serve as the collector and emitter of the trench insulated gate bipolar transistor, wherein the first semiconductor layer 12 has a second conductivity type and is a P+ collector connected to the electric field stop layer 8, the first metal layer 11 is connected to the first semiconductor layer 12 to form a collector metal that can be connected to an external drive circuit, and the second semiconductor layer 62 is an N+ emitter connected to the base region 4 and part of the highly doped layer 5, and has a first conductivity type. The second metal layer 61 is connected to the second semiconductor layer 62 to form an emitter metal that can be connected to an external drive circuit.

[0053] A trench-type insulated gate bipolar transistor in an embodiment of the present application, wherein the second electrode layer 6 further includes a dielectric layer 63, a first connecting portion 611 and a second connecting portion 612 vertically connected to the second metal layer 61, the first connecting portion 611, the dielectric layer 63 and the second semiconductor layer 62 are stacked in sequence along the first direction X, and the second connecting portion 612 passes through the dielectric layer 63 and the second semiconductor layer 62 in sequence along the first direction X and is connected to the highly doped layer 5.

[0054] In a specific implementation, by providing a dielectric layer 63, the first connection portion 611 of the second metal layer 61 can be separated from the second semiconductor layer 62 and the gate trench region 3. Furthermore, by providing a second connection portion 612 that sequentially penetrates the dielectric layer 63 and the second semiconductor layer 62 along the first direction X, a connection can be formed between the second connection portion 612 and the multi-layer highly doped layer 5. Therefore, the overall structural arrangement of the second electrode layer 6 not only ensures the overall conductive performance of the device, but also provides the device with high short-circuit robustness, thereby further improving the overall performance of the device.

[0055] In an embodiment of the present application, the electric field stop layer 8, the drift layer 2, the carrier storage region 7 and the second electrode layer 6 have a first conductivity type, that is, N-type doping; the first electrode layer 1, the base region 4 and the highly doped layer 5 have a second conductivity type, that is, P-type doping.

[0056] Please combine Figures 1 to 5 The present invention also provides a method for manufacturing a trench-type insulated gate bipolar transistor, wherein the method is used to manufacture the trench-type insulated gate bipolar transistor, such as Figure 5 Shown, including:

[0057] S110 , providing a drift layer 2 having a first conductivity type;

[0058] S120, etching to form trenches on the first surface 21 of the drift layer 2 and forming polysilicon in the trenches to form a plurality of gate trench regions 3;

[0059] S130 , performing low-energy ion implantation of the second conductivity type between adjacent gate trench regions 3 from the first surface 21 of the drift layer 2 , and forming a plurality of base regions 4 by pushing wells;

[0060] Before forming each base region 4, it is necessary to perform ion implantation of the first conductivity type and push wells between adjacent gate trench regions 3 to form multiple carrier storage regions 7. After the carrier storage regions 7 are formed, the base region 4 is formed.

[0061] S140 , disposing a second semiconductor layer 62 and a dielectric layer 63 of the first conductivity type on the first surface 21 of the drift layer 2 , and etching to form an accommodating groove 64 extending along the first direction X;

[0062] S150 , multiple high-energy ion implantations of the second conductivity type are performed into each base region 4 through the receiving groove 64 , and activated to form a plurality of highly doped layers 5 stacked along the first direction X and spaced evenly from the gate trench regions 3 on both sides;

[0063] S160, disposing a second metal layer 61 on the surface of the second semiconductor layer 62 and the dielectric layer 63 on one side of the drift layer 2 to form a second electrode layer 6 having a first conductivity type, and disposing a first electrode layer 1 having a second conductivity type on the other side of the drift layer 2;

[0064] Before providing the first electrode layer 1 , it is necessary to perform first conductivity type ion implantation and activation on the surface of the drift layer 2 away from the second electrode layer 6 to form an electric field cutoff layer 8 ;

[0065] The second connection portion 612 of the second metal layer 61 is formed in the receiving groove 64 , and the first connection portion 611 covers the second connection portion 612 and the surface of the dielectric layer 63 away from the second semiconductor layer 62 .

[0066] The first electrode layer 1 is formed on a surface of the electric field stop layer 8 away from the drift layer 2 .

[0067] In specific implementation, the manufacturing method of the trench-type insulated gate bipolar transistor of the embodiment of the present application is adopted to form a trench-type insulated gate bipolar transistor having a first electrode layer 1, a drift layer 2, multiple gate trench regions 3, multiple base regions 4, multiple highly doped layers 5 and a second electrode layer 6. The second electrode layer 6 is provided on the first surface 21 of the drift layer 2, and the first electrode layer 1 is provided on the other side of the first direction X. The multiple gate trench regions 3 are arranged at intervals in the drift layer 2 along the second direction Y and extend from the first surface 21 toward the first electrode layer 1 to form a trench gate structure of the insulated gate bipolar transistor. The structural setting of the gate trench regions 3 makes the width of the base region 4 between adjacent gate trench regions 3 in the second direction Y shorter, so that the overall device has lower conduction loss.

[0068] Each base region 4 has multiple layers of highly doped layers 5 stacked along a first direction X, thereby forming a highly doped region extending along the first direction X. Since the doping concentration of the highly doped region formed by the multiple layers of highly doped layers 5 is greater than the doping concentration of the base region 4, when the device is turned on, the holes in the base region 4 can be concentrated toward the region of the multiple layers of highly doped layers 5, thereby forming a current path within the multiple layers of highly doped layers 5, thereby avoiding excessive holes in the base region 4 during the device short-circuit process, which would cause latch-up of the entire device. Therefore, the trench-type insulated gate bipolar transistor of the present application has high short-circuit robustness, improving the overall performance of the device.

[0069] Specifically, if Figure 1 As shown, each base region 4 of the trench insulated gate bipolar transistor has four highly doped layers 5. In the process of forming the four highly doped layers 5, a first high energy, a second high energy, a third high energy and a fourth high energy implantation are performed on the first surface 21 respectively to form four highly doped layers 5 stacked along the first direction X. The implanted energy and dose can be adjusted according to the concentration depth of the base region 4 to obtain the best short-circuit characteristics.

[0070] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0071] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the scope of protection of the present application.

Claims

1. A trench insulated gate bipolar transistor, characterized in that: include: a first electrode layer (1); A drift layer (2) is provided on one side of the first electrode layer (1) in a first direction (X); A plurality of gate trench regions (3) are arranged in the drift layer (2) at intervals along a second direction (Y), and each gate trench region (3) extends from the first surface (21) of the drift layer (2) toward the first electrode layer (1); A plurality of base regions (4), each of the base regions (4) being provided between two adjacent gate trench regions (3), each of the base regions (4) having a plurality of highly doped layers (5) stacked along the first direction (X), the plurality of highly doped layers (5) being spaced apart from the gate trench regions (3) on both sides; a second electrode layer (6) provided on the first surface (21) of the drift layer (2) and connected to the highly doped layer (5); The drift layer (2) and the second electrode layer (6) have a first conductivity type, the first electrode layer (1), the base region (4) and the highly doped layer (5) have a second conductivity type, and the doping concentration of the highly doped layer (5) is greater than the doping concentration of the base region (4).

2. The trench insulated gate bipolar transistor according to claim 1, wherein: The second electrode layer (6) comprises a second metal layer (61) and a second semiconductor layer (62) connected to each other, the second semiconductor layer (62) being provided on the first surface (21) of the drift layer (2) and connected to the base region (4) and part of the highly doped layer (5), and at least part of the second metal layer (61) passing through the second semiconductor layer (62) along the first direction (X) and connected to the highly doped layer (5).

3. The trench insulated gate bipolar transistor according to claim 2, wherein: The second electrode layer (6) further comprises a dielectric layer (63), a first connecting portion (611) and a second connecting portion (612) vertically connected to the second metal layer (61), the first connecting portion (611), the dielectric layer (63) and the second semiconductor layer (62) being sequentially stacked along the first direction (X), and the second connecting portion (612) sequentially passes through the dielectric layer (63) and the second semiconductor layer (62) along the first direction (X) and is connected to the highly doped layer (5).

4. The trench insulated gate bipolar transistor according to claim 1, wherein: Also includes: a plurality of carrier storage regions (7), each of the carrier storage regions (7) being provided between two adjacent gate trench regions (3), the carrier storage regions (7) being provided in one-to-one correspondence with the base regions (4), and each of the carrier storage regions (7) being connected to a side of the corresponding base region (4) close to the first electrode layer (1); The carrier storage region (7) has a first conductivity type, and the doping concentration of the carrier storage region (7) is higher than the doping concentration of the drift layer (2).

5. The trench insulated gate bipolar transistor according to claim 1 or 4, wherein: The multi-layer highly doped layer (5) has a first depth H1 in the first direction (X), and the base region (4) has a second depth H2 in the first direction (X). Among them, 10%H2≤H1≤130%H2.

6. The trench insulated gate bipolar transistor according to claim 1, wherein: Along the first direction (X), the width of each highly doped layer (5) in the second direction (Y) shows an increasing trend.

7. The trench insulated gate bipolar transistor according to claim 1 or 6, wherein: Each of the highly doped layers (5) has a spacing distance D from the gate trench region (3) on either side in the second direction (Y). Among them, D>0.1μm.

8. The trench insulated gate bipolar transistor according to claim 1, wherein: Also includes: An electric field stop layer (8), the electric field stop layer (8) being arranged between the first electrode layer (1) and the drift layer (2), the electric field stop layer (8) having a first conductivity type, and a doping concentration of the electric field stop layer (8) being higher than a doping concentration of the drift layer (2).

9. The trench insulated gate bipolar transistor according to claim 1, wherein: The first electrode layer (1) comprises a first metal layer (11) and a first semiconductor layer (12) stacked along the first direction (X), and the first semiconductor layer (12) is arranged on a side of the first metal layer (11) close to the drift layer (2).

10. A method for manufacturing a trench insulated gate bipolar transistor, characterized in that: For manufacturing a trench-type insulated gate bipolar transistor according to any one of claims 1 to 9, comprising: Providing a drift layer (2) having a first conductivity type; Etching a first surface (21) of the drift layer (2) to form a trench and forming polysilicon in the trench to form a plurality of gate trench regions (3); Performing low-energy ion implantation of a second conductive type between adjacent gate trench regions (3) from the first surface (21) of the drift layer (2), and pushing wells to form a plurality of base regions (4); A second semiconductor layer (62) and a dielectric layer (63) having a first conductivity type are provided on the first surface (21) of the drift layer (2), and a receiving groove (64) extending along a first direction (X) is formed by etching; Performing multiple high-energy ion implantations of the second conductive type into each base region (4) through the receiving groove (64), and activating and forming a plurality of highly doped layers (5) stacked along the first direction (X) and spaced apart from the gate trench regions (3) on both sides; A second metal layer (61) is provided on the surface of the second semiconductor layer (62) and the dielectric layer (63) on one side of the drift layer (2) to form a second electrode layer (6) having a first conductivity type, and a first electrode layer (1) having a second conductivity type is provided on the other side of the drift layer (2).

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