PMOS device based on FDSOI substrate and preparation method thereof
By opening grooves in the buried oxide layer of the FDSOI substrate and using source and drain regions made of silicon germanium material, the problem of difficulty in introducing stress into the channel region of nanoscale PMOS devices was solved, thereby improving carrier mobility and device performance.
Patent Information
- Application Number
- CN202510620753.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-14
- Publication Date
- 2025-09-05
AI Technical Summary
In nanoscale FDSOI PMOS devices, stress is difficult to effectively introduce into the channel region, affecting device performance. This is especially true in the ultra-thin top silicon channel, where stress is difficult to introduce through channel engineering.
Grooves are opened in the buried oxide layer of the FDSOI substrate corresponding to the source and drain regions. The source and drain regions are placed in the grooves and are made of silicon germanium material. Through the epitaxial process, the bottom interface of the source and drain regions is made lower than the bottom interface of the channel region, and the top interface is higher than the top interface of the channel region. The thickness of the source and drain regions is limited to ensure that stress effectively acts on the channel region.
Effectively reduce stress relaxation, improve carrier mobility and performance of PMOS devices, and increase driving current and speed.
Smart Images
Figure CN120603282A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a PMOS device based on an FDSOI substrate, a preparation method thereof, and an electronic device. Background Art
[0002] The performance of silicon-based MOS devices is closely linked to the carrier mobility of the channel. Strain engineering is currently widely used to improve device performance. On the one hand, stress induces lattice distortion in the material, changing the lattice constant and bond length, thereby affecting the carrier relaxation time. On the other hand, stress modifies the material's band structure, thereby altering the effective carrier mass. Compressive stress is typically applied to the channel of a PMOS device to increase hole mobility. However, in nanoscale devices, stress easily relaxes, compromising the effectiveness of stress engineering. This is particularly true for FDSOI (Fully Depleted Silicon-On-Insulator) devices, where the ultra-thin top silicon channel makes it difficult to introduce stress through channel engineering. Summary of the Invention
[0003] The purpose of the embodiments of the present disclosure is to provide a PMOS device based on an FDSOI substrate, a method for manufacturing the same, and an electronic device, so as to solve the problems existing in the prior art.
[0004] The embodiments of the present disclosure adopt the following technical solution: a PMOS device based on an FDSOI substrate, characterized in that a groove is opened in the buried oxide layer of the FDSOI substrate corresponding to the source and drain regions, the source and drain regions are placed in the groove, the thickness of the source and drain regions is greater than the thickness of the channel region, and the bottom interface of the source and drain regions is lower than the bottom interface of the channel region, and the top interface of the source and drain regions is higher than the top interface of the channel region.
[0005] In some embodiments, the source and drain regions are made of silicon germanium.
[0006] In some embodiments, the germanium content in the silicon germanium material is less than or equal to 50%.
[0007] In some embodiments, the content of germanium in the source and drain regions increases horizontally from a side close to the channel region toward the outside.
[0008] In some embodiments, an end surface of the source / drain region close to the channel region is only bonded to a side surface of the channel region.
[0009] An embodiment of the present disclosure also provides a method for preparing a PMOS device based on an FDSOI substrate as described above, which at least includes: providing an FDSOI substrate, wherein the FDSOI substrate at least includes a base layer, a buried oxide layer, and a top silicon layer arranged in sequence from bottom to top; preparing an insulating layer and a dummy gate structure in sequence on the surface of the channel region of the FDSOI substrate; preparing a sidewall layer on the exposed surface of the current hierarchical structure; etching the sidewall layer, the top silicon layer, and part of the buried oxide layer corresponding to the source and drain regions in the current hierarchical structure to form a groove in the region of the buried oxide layer corresponding to the source and drain regions; and horizontally epitaxially growing the source and drain regions outward with the side surface of the channel region as a reference plane so that the bottom interface of the source and drain regions contacts the bottom surface of the groove.
[0010] In some embodiments, before epitaxially growing the source and drain regions horizontally outward with the side surface of the channel region as a reference plane so that the bottom interface of the source and drain regions contacts the bottom surface of the groove, the method further includes: performing interface processing on the side surface of the channel region.
[0011] In some embodiments, the method further includes: removing the insulating layer and the dummy gate structure; and sequentially preparing a gate dielectric layer, a gate layer, a gate interconnection metal, and a source-drain interconnection metal.
[0012] An embodiment of the present disclosure further provides an electronic device, comprising at least the PMOS device based on the FDSOI substrate as described above.
[0013] In some embodiments, the electronic device includes at least a computer, a mobile phone, a tablet, a vehicle-mounted device, a smart wearable device, a digital camera, a personal digital assistant, and a media player.
[0014] The beneficial effects of the embodiments disclosed herein are: by removing part of the buried oxide layer corresponding to the source and drain regions in the FDSOI substrate, the source and drain region structure is moved down into the buried oxide layer, and at the same time, the thickness of the source and drain regions is limited so that the stress of the source and drain regions can better act on the channel region, effectively reducing the occurrence of stress relaxation, and achieving the purpose of improving the performance of the PMOS device. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0016] Figure 1 It is a partial hierarchical cross-sectional diagram of a PMOS device based on an FDSOI substrate in the first embodiment of the present disclosure;
[0017] Figure 2Another schematic diagram of a partial hierarchical cross section of a PMOS device based on an FDSOI substrate in the first embodiment of the present disclosure;
[0018] Figure 3 Flowchart of a method for manufacturing a PMOS device based on an FDSOI substrate in the second embodiment of the present disclosure;
[0019] Figures 4 to 7 Schematic diagram of the implementation process of a PMOS device based on an FDSOI substrate in the second embodiment of the present disclosure. DETAILED DESCRIPTION
[0020] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below in conjunction with the drawings in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this document.
[0021] The performance of silicon-based MOS devices is related to the carrier mobility of the channel. For silicon-based PMOS devices, the hole mobility of silicon is low, which limits the driving current and speed of PMOS devices. Strain technology has been widely adopted to improve device performance. The carrier mobility can be expressed by the following formula:
[0022]
[0023] Among them, m * is the effective carrier mass, τ is the carrier relaxation time, and q is the elementary charge. As can be seen from the above formula, increasing the carrier relaxation time or reducing the effective carrier mass will increase the carrier mobility of the device. The introduction of stress, on the one hand, affects the carrier relaxation time by causing lattice distortion in the material, changing the lattice constant and bond length; on the other hand, it changes the effective carrier mass by altering the material band structure. Compressive stress is typically applied to the channel of a PMOS device to increase hole mobility. However, in nanoscale devices, stress easily relaxes, affecting the effectiveness of stress engineering. This is especially true for FDSOI (Fully Depleted Silicon-On-Insulator) devices, where the ultra-thin top silicon channel makes it difficult to introduce stress through channel engineering.
[0024] In order to solve the above problems, the first embodiment of the present disclosure provides a PMOS device based on an FDSOI substrate, which may have a conventional transistor structure, for example, including an FDSOI substrate, a channel region, a source and drain region, a gate dielectric, a gate interconnect metal, a source and drain interconnect metal, etc. Figure 1 and Figure 2 The PMOS device of this embodiment is described in detail.
[0025] Figure 1 FIG. 4 shows a partial cross-sectional view of a PMOS device according to the present embodiment. Figure 1 As shown, the FDSOI substrate of this embodiment includes at least a base layer Sub (Substrate), a buried oxide layer BOX, and a top silicon layer UTB (Ultra-Thin Body) arranged in sequence from bottom to top, wherein the base layer Sub is used to support the device structure, the buried oxide layer BOX is used to isolate the active layer from the base, and the top silicon layer UTB is etched to form the channel region 11 of the device. At the same time, the buried oxide layer BOX in this embodiment has a groove 20 in the area corresponding to the source and drain regions. The groove 20 is formed by etching away part of the thickness of the buried oxide layer BOX, as shown in FIG. Figure 1 As shown, the source and drain regions 12 are placed in the grooves 20, and the thickness of the source and drain regions 12 is greater than the thickness of the channel region 11. At the same time, the bottom interface of the source and drain regions 12 of this embodiment is lower than the bottom interface of the channel region 11, and the top interface of the source and drain regions 12 is higher than the top interface of the channel region 11. In this case, the source and drain regions 12 are more likely to introduce stress into the channel region 11 and maintain the stress application state of the channel region 11, thereby improving the carrier mobility of the channel region and ensuring that the performance of the PMOS device is improved.
[0026] It should be noted that the depth of the groove 20 and the thickness of the source and drain regions 12 in this embodiment can be set according to the level of the lithography process, the actual stress to be applied, and the size of the channel region 11. However, it should at least be ensured that after the groove 20 is opened, the thickness of the buried oxide layer BOX remaining in the corresponding area still meets the isolation requirements of the device, and the height of the top interface of the source and drain regions 12 should be lower than the height of the top interface after the gate dielectric layer and the gate layer 30 are prepared in the PMOS device. Figure 1 The gate dielectric layer and gate layer 30 are represented by an integrated pink area, and the gate dielectric layer and the gate layer are not distinguished separately. In the actual preparation process, the gate dielectric layer and the gate layer can be realized in combination with the conventional PMOS device structure. In addition, the setting of the insulating layer needs to be ensured to achieve insulation between the source and drain regions and the gate.
[0027] In some embodiments, the source and drain regions 12 are mainly based on silicon germanium Si 1-x Ge xIt is made of a material. By utilizing the lattice constant difference between silicon and germanium, a strain effect is introduced to improve the hole mobility and simultaneously reduce the channel resistance. In this embodiment, the content of germanium element in the silicon-germanium is limited to be less than or equal to 50%, that is, 0 < x ≤ 0.5. In actual implementation, x = 0.2 or x = 0.3 can be selected to ensure that the lattice mismatch between germanium and the silicon substrate does not exceed the threshold for inducing dislocation defects.
[0028] In the actual process of fabricating the source / drain regions 12, the silicon-germanium material is prepared by epitaxial process with the side surface of the channel region 11 as the reference plane. During the epitaxial process, by reasonably controlling the input concentration of each part in the epitaxial precursor, the content of germanium element in the source / drain regions 12 gradually increases horizontally outward from the side close to the channel region 11, making it easier to introduce stress into the channel region 11. At the same time, during the process of increasing the germanium component, the high-germanium component is kept away from the channel region 11 to reduce the influence of strain defects on the channel.
[0029] In some embodiments, the end face of the source / drain region 12 close to the channel region 11 is only joined to the side surface of the channel region 11, as Figure 2 shown. At this time, a gap is formed between the end of the source / drain region 12 close to the channel region 11 and the side wall and bottom surface of the groove 20, so that the stress of the source / drain region 12 only acts on the channel region 11 to ensure the stress application effect. However, it should be noted that the gap area should not be too large, and the contact area between the bottom interface of the source / drain region 12 and the bottom surface of the groove 20 should at least ensure the structural stability of the transistor.
[0030] In this embodiment, by removing the corresponding part of the buried oxide layer in the FDSOI substrate for the source / drain regions, the source / drain region structure is moved down to the buried oxide layer. At the same time, the thickness of the source / drain regions is limited so that the stress of the source / drain regions can better act on the channel region, effectively reducing the occurrence of stress relaxation and achieving the purpose of improving the performance of the PMOS device.
[0031] Based on the same inventive concept, the second embodiment of the present disclosure provides a method for fabricating a PMOS device based on an FDSOI substrate in the first embodiment, and its flowchart is as Figure 3 shown, and at least includes the following steps:
[0032] S1, provide an FDSOI substrate;
[0033] S2, sequentially fabricate an insulating layer and a dummy gate structure on the surface of the channel region of the FDSOI substrate;
[0034] S3, fabricate a sidewall layer on the exposed surface of the current hierarchical structure;
[0035] S4, etch the sidewall layer, the top silicon layer and a part of the buried oxide layer corresponding to the source / drain regions in the current hierarchical structure to form a groove in the region of the buried oxide layer corresponding to the source / drain regions;
[0036] S5, epitaxially growing the source and drain regions horizontally outward with the side surface of the channel region as a reference plane, so that the bottom interface of the source and drain regions contacts the bottom surface of the groove.
[0037] In this embodiment, the substrate provided in step S1 can be an FDSOI wafer, or a buried oxide layer and a second semiconductor layer can be sequentially formed on one side of the first semiconductor layer to form a substrate, and the thickness of the second semiconductor layer is less than that of the first semiconductor layer, and both can be prepared based on the same semiconductor material. The semiconductor material in this embodiment is mainly silicon, forming a base layer, a buried oxide layer, and a top silicon layer arranged in sequence from bottom to top.
[0038] When the step S2 is actually performed, it can be realized by a conventional transistor manufacturing process to form a transistor as shown in FIG. Figure 4 The device hierarchical structure shown in FIG. Specifically, the insulating layer 41 can be made of the same material as the buried oxide layer BOX, or any metal oxide with insulating properties. The dummy gate structure 42 can be made of amorphous silicon or other materials. Furthermore, a hard mask 43 can be further formed on top of the dummy gate structure 42 using silicon oxide, silicon nitride, or a stacked structure thereof to protect the dummy gate structure 42. Furthermore, a shallow trench dielectric isolation region 50 is included between adjacent PMOS devices to provide isolation between the different PMOS devices.
[0039] After the dummy gate structure is prepared, a spacer layer 60 is prepared on the exposed surface of the current hierarchical structure, such as Figure 5 As shown, the spacer layer 60 can be realized by a deposition process, and its main material is silicon oxide, silicon nitride or a stack thereof, so as to protect the side surface of the dummy gate structure 42 .
[0040] Step S4 etches the sidewall layer, top silicon layer and part of the buried oxide layer corresponding to the source and drain regions in the current hierarchical structure, so that the sidewall layer and top silicon layer corresponding to the source and drain regions are completely etched away, and the buried oxide layer is partially etched to form a groove, such as Figure 6 As shown. The specific etching process can be selected based on the materials of each layer, including but not limited to dry etching, wet etching, electron beam lithography, etc. It should be noted that the depth of the groove can be set according to the level of lithography technology, the actual stress required, and the size of the channel region 11. However, it should at least ensure that after the groove is opened, the thickness of the buried oxide layer BOX remaining in the corresponding area still meets the isolation requirements of the device.
[0041] Finally, in step S5, the source and drain regions are prepared by epitaxial process with the sidewall of the channel region remaining after etching the top silicon layer as the reference, forming the following: Figure 7 The hierarchical structure shown in FIG. In this embodiment, the source and drain regions are based on silicon germanium Si 1-x Ge xIt is made of materials. By utilizing the lattice constant difference between silicon and germanium, a strain effect is introduced to improve the hole mobility and simultaneously reduce the channel resistance. In this embodiment, the content of germanium element in the silicon-germanium is restricted to be less than or equal to 50%, that is, 0 < x ≤ 0.5. In actual implementation, x = 0.2 or x = 0.3 can be selected to ensure that the lattice mismatch between germanium and the silicon substrate does not exceed the threshold for inducing dislocation defects. During the actual process of fabricating the source-drain regions, the silicon-germanium material is prepared by an epitaxial process with the side surface of the channel region as the reference plane. During the epitaxial process, by reasonably controlling the input concentration of each part in the epitaxial precursor, the content of germanium element in the source-drain regions gradually increases horizontally outward from the side close to the channel region, which is more likely to introduce stress into the channel region. At the same time, during the process of increasing the germanium component, the high-germanium component is kept away from the channel region to reduce the influence of strain defects on the channel.
[0042] In some embodiments, the end surface of the source-drain region close to the channel region is only joined to the side surface of the channel region. At this time, a gap is formed between one end of the source-drain region close to the channel region and the side wall and bottom surface of the groove, so that the stress of the source-drain region only acts on the channel region to ensure the stress application effect. In some embodiments, before performing step S5, it further includes a step of performing interface treatment on the side surface of the channel region to improve the effect of the epitaxial process.
[0043] Finally, after the source-drain regions are fabricated, the insulating layer and the dummy gate structure can be removed, and in combination with the traditional crystal hanging preparation process, the gate dielectric layer and the gate electrode layer 30, the gate interconnect metal 71 and the source-drain electrode interconnect metal 72 are prepared in sequence, and finally a PMOS transistor structure as shown in Figure 1 is formed.
[0044] In this embodiment, by removing the corresponding part of the buried oxide layer in the source-drain regions of the FDSOI substrate, the source-drain region structure is moved down into the buried oxide layer. At the same time, the thickness of the source-drain regions is restricted so that the stress of the source-drain regions can act better on the channel region, effectively reducing the occurrence of stress relaxation and achieving the purpose of improving the performance of the PMOS device. At the same time, the traditional epitaxy method from bottom (top silicon) to top is changed to an epitaxy method from the side of the channel horizontally outward, which is more likely to introduce stress into the channel. At the same time, when increasing the germanium component, the high-germanium component can be kept away from the channel to reduce the influence of strain defects on the channel.
[0045] Based on the same inventive concept, the third embodiment of the present disclosure provides an electronic device, which at least includes the PMOS device of the first embodiment of the present disclosure. Specifically, the electronic device in this embodiment can be any one of a computer, a mobile phone, a tablet, a vehicle-mounted device, a smart wearable device, a digital camera, a personal digital assistant, and a media player.
[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A PMOS device based on an FDSOI substrate, characterized in that: The buried oxide layer of the FDSOI substrate is provided with a groove corresponding to the source and drain region, the source and drain region is placed in the groove, the thickness of the source and drain region is greater than the thickness of the channel region, and the bottom interface of the source and drain region is lower than the bottom interface of the channel region, and the top interface of the source and drain region is higher than the top interface of the channel region.
2. The PMOS device according to claim 1, wherein: The source and drain regions are made of silicon germanium material.
3. The PMOS device according to claim 2, wherein: The content of germanium in the silicon germanium material is less than or equal to 50%.
4. The PMOS device according to claim 3, wherein: The content of the germanium element in the source and drain regions increases horizontally outward from the side close to the channel region.
5. The PMOS device according to any one of claims 1 to 4, characterized in that: An end surface of the source / drain region close to the channel region is only joined to a side surface of the channel region.
6. A method for preparing a PMOS device based on an FDSOI substrate according to any one of claims 1 to 5, characterized in that: At least: Providing an FDSOI substrate, wherein the FDSOI substrate comprises at least a base layer, a buried oxide layer, and a top silicon layer arranged in sequence from bottom to top; sequentially preparing an insulating layer and a dummy gate structure on the surface of the channel region of the FDSOI substrate; Prepare a sidewall layer on the exposed surface of the current layer structure; Etching the sidewall layer, the top silicon layer and a portion of the buried oxide layer corresponding to the source and drain regions in the current hierarchical structure to form grooves in regions of the buried oxide layer corresponding to the source and drain regions; The source and drain regions are horizontally epitaxially grown outward with the side surface of the channel region as a reference plane, so that the bottom interface of the source and drain regions contacts the bottom surface of the groove.
7. The preparation method according to claim 6, characterized in that Before epitaxially growing the source and drain regions horizontally outward with the side surface of the channel region as a reference plane so that the bottom interface of the source and drain regions contacts the bottom surface of the groove, the method further includes: Interface processing is performed on the side surfaces of the channel region.
8. The preparation method according to claim 6 or 7, characterized in that Also includes: removing the insulating layer and the dummy gate structure; The gate dielectric layer, gate layer, gate interconnection metal and source-drain interconnection metal are prepared in sequence.
9. An electronic device, characterized in that: The device at least comprises the PMOS device based on the FDSOI substrate according to any one of claims 1 to 5.
10. The electronic device according to claim 9, characterized in that At least include computers, mobile phones, tablets, car devices, smart wearable devices, digital cameras, personal digital assistants, and media players.