Chip structure with base

Abstract

The invention provides a chip structure with a pedestal, which can suppress strain possibly generated in a chip of a semiconductor laser. A chip structure with a base (1) is provided with: a chip (10) including a current injection strip (161) for injecting a current into an active layer (13); a strain suppression layer (20) that is made of metal and covers the current injection strip (161); a susceptor (40) including an electrode layer (electrode pattern 42); and a solder layer (30) interposed between the strain suppression layer (20) and the electrode layer (electrode pattern 42), the thickness of an unreacted layer (201) in the strain suppression layer (20), in which components of the solder layer (30) are not diffused, being 1.4 [mu] m or more.

Description

Technical Field

[0001] The present invention relates to a chip-on-submount (Chip-on-Submount) structure in which a semiconductor laser chip is mounted on a submount. Background Art

[0002] Semiconductor laser chips with high output exceeding 10W are known (for example, see Figure 9 of Patent Document 1). Such semiconductor lasers achieve high output by increasing the width of current injection bars, electrodes used to inject current into the active layer. Such chips achieve high output by increasing the width of current injection bars used to inject current into the active layer.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: (Japanese) Patent Publication No. 9-36493 Summary of the Invention

[0006] (1) Technical issues to be resolved

[0007] In addition, when manufacturing semiconductor laser chips, it is important to reduce manufacturing costs. One method of reducing chip manufacturing costs is to miniaturize the chip. However, it is desirable to avoid a decrease in output as the chip is miniaturized. Therefore, in order to miniaturize the chip, the practical option is not to shorten the chip length, which is determined by the length of the current injection bar, but to reduce the chip width. However, the smaller the chip width, the more difficult it is to manufacture a chip structure with a base.

[0008] In a chip-on-substrate structure, an electrode layer is formed on one main surface of the substrate. The chip is configured so that a current injection bar is close to the electrode layer. The current injection bar and the electrode layer are then electrically bonded using solder.

[0009] During the process of bonding the chip to the base, strain may occur in the chip. Furthermore, even when the semiconductor laser is driven after manufacturing, the chip may still be strained. The smaller the chip width, the more likely these strains are to occur. The strain generated in the chip is the cause of the unstable radiation shape of the laser light emitted from the semiconductor laser. In other words, the smaller the chip width, the more likely the radiation shape of the laser light emitted from the semiconductor laser becomes unstable.

[0010] A chip-on-pedestal structure according to one embodiment of the present invention has been developed in view of the above-mentioned technical problems, and an object thereof is to provide a chip-on-pedestal structure capable of suppressing strain that may be generated in a chip.

[0011] (2) Technical solution

[0012] To address the aforementioned technical issues, one embodiment of the present invention provides a chip-on-substrate structure comprising: a wide-area chip including an active layer and current injection bars for injecting current into the active layer; a metal strain suppression layer covering the current injection bars; a substrate comprising a substrate and an electrode layer disposed on one principal surface of the substrate; and a solder layer interposed between the strain suppression layer and the electrode layer, bonding the chip and substrate. In this chip-on-substrate structure, the strain suppression layer comprises a reaction layer into which components of the solder layer diffuse, and an unreacted layer into which components of the solder layer do not diffuse, with the unreacted layer having a thickness of at least 1.4 μm.

[0013] (3) Beneficial effects

[0014] According to one aspect of the present invention, a chip-on-susceptor structure capable of suppressing strain that may be generated in a semiconductor laser chip is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a perspective view of a chip-on-substrate structure according to one embodiment of the present invention.

[0016] Figure 2 yes Figure 1 A cross-sectional view of a chip structure with a base is shown.

[0017] Figure 3 (a) is observed from the current injection side Figure 1 (b) is a top view of a chip having a chip-on-pedestal structure as shown in FIG. (b) is a top view of a modification of the chip shown in (a) as viewed from the current injection bar side.

[0018] Figure 4 (a)~(f) represent Figure 2 A cross-sectional view of a method for manufacturing a first specific example of a chip is shown.

[0019] Figure 5 Yes means through Figure 4 A top view of multiple chips manufactured by the manufacturing method shown.

[0020] Figure 6 (a) to (c) represent Figure 2 A cross-sectional view of a method for manufacturing a second specific example of a chip is shown.

[0021] Figure 7 (a) is observed from the current injection side using Figure 6 (b) is a top view of a chip manufactured by the manufacturing method shown in (a). (b) is a top view of a modification of the chip shown in (a) as viewed from the current injection bar side. DETAILED DESCRIPTION

[0022] [Structure with base chip structure]

[0023] Regarding the chip-on-substrate structure 1 according to one embodiment of the present invention, refer to Figures 1 to 3 Provide explanation. Figure 1 It is a three-dimensional diagram of the chip structure 1 with a base. Figure 2 1 is a cross-sectional view of the chip structure 1 with a base. Figure 2 The cross-sectional view is through Figure 1 The diagram is a cross-sectional view taken along line AA′ and perpendicular to the main surface of the substrate 11 . Figure 3 (a) is a plan view of the chip 10 included in the chip-on-pedestal structure 1 as viewed from the current injection bar 161 side. Figure 3 (b) is a plan view of a chip 10A, which is a modified example of the chip 10 , as viewed from the current injection bar 161A side. Note that both the chip 10 and the chip 10A are examples of semiconductor laser chips.

[0024] In addition, Figures 1 to 3 In the chip structure 1 with a base shown in FIG, a chip 10 having a simplified structure is used to describe the chip structure 1 with a base according to one embodiment of the present invention. Figure 4 and Figure 6 This will be described later.

[0025] like Figure 1 and Figure 2 As shown, the chip-on-substrate structure 1 includes a chip 10 , a strain suppression layer 20 , a solder layer 30 , and a substrate 40 .

[0026] <Base>

[0027] The base 40 is a substrate for mounting the chip 10 on one main surface. Figure 1 and Figure 2 As shown, the base 40 includes a substrate 41 and electrode patterns 42 and 43. The electrode pattern 42 is an example of an electrode layer of the base 40.

[0028] The substrate 41 is a plate-shaped member with a pair of flat main surfaces. The substrate 41 is made of a high thermal conductivity material. In this embodiment, as the high thermal conductivity material constituting the substrate 41, a ceramic with low electrical conductivity (preferably an insulator) and high thermal conductivity is used. However, the high thermal conductivity material constituting the substrate 41 is not limited to a material with high electrical conductivity, and can be appropriately selected based on the structure of the chip 10, the preferred thermal conductivity of the substrate 41, etc. In the case where the substrate 41 is composed of a conductor, a structure that insulates the electrode pattern 42 and the electrode pattern 43 described later can be adopted. In order to insulate the electrode pattern 42 and the electrode pattern 43, an insulating layer can be provided between the substrate 41 and the electrode pattern 42, and between the substrate 41 and the electrode pattern 43, respectively, or a structure that allows current to flow in a direction perpendicular to the substrate can be used.

[0029] An electrode pattern 42 and an electrode pattern 43 are formed on one main surface of the substrate 41. The electrode patterns 42 and 43 are respectively composed of a thin film, and the thin film is composed of a conductive material. In the present embodiment, gold, which is a type of metal, is used as the material that constitutes the electrode patterns 42 and 43. However, the material that constitutes the electrode patterns 42 and 43 can be appropriately selected from conductive materials. The material that constitutes the electrode patterns 42 and 43 preferably has good conductivity. Examples of materials with good conductivity include gold, copper, silver and aluminum. In addition, the electrode patterns 42 and 43 can be a single-layer film composed of these materials, or a multilayer film in which each layer is composed of these materials. The electrode patterns 42 and 43 are respectively separated from each other and are therefore insulated from each other.

[0030] Chip

[0031] In the chip 10 as an example of a semiconductor laser chip, the total length of the current injection bar 161 described later, that is, the length L (see Figure 3 (a)), 4 mm is used. That is, the resonator length in the chip 10 is 4 mm. In addition, the chip 10 is the width W of the current injection strip 161 (refer to Figure 3(a)) A wide-area chip with a length L of 75 μm or more across the entire area. A wide-area chip 10 with a length L of 4 mm can emit a laser with an output of 10 W or more. In addition, the minimum value of the width of the current injection bar 161 is not limited to 75 μm, and similarly, the output of the chip 10 is not limited to 10 W. In addition, when the output of the laser in the chip 10 is mentioned in this embodiment, it refers to the maximum output of the chip 10. In this embodiment, 4 mm and 220 μm are used as the length L and width W, respectively, and the output exceeds 20 W. In the chip structure 1 with a base, if the heat generated in the chip 10 during driving is sufficiently dissipated, a 13 W laser can be stably emitted for a width W of 100 μm. That is, when 220 μm is used as the width W, the length L is selected within the range of approximately 4 mm to 6 mm, thereby stably emitting a laser with an output of approximately 25 W to 28 W.

[0032] like Figure 1 and Figure 2 As shown, the chip 10 includes a substrate 11 , an n-type layer 12 , an active layer 13 , a p-type layer 14 , a barrier layer 15 , an electrode layer 16 , and an electrode layer 17 .

[0033] (Substrate)

[0034] The substrate 11 is a semiconductor plate-shaped member having a pair of flat principal surfaces 111 and 112. In this embodiment, the substrate 11 is made of GaAs. However, the material constituting the substrate 11 can be selected as appropriate.

[0035] On one main surface of the substrate 11, Figure 2 An electrode layer 17 is formed on the upper main surface 111. The electrode layer 17 is a metal thin film formed to cover the main surface 111. In this embodiment, a three-layer film of Ni / Ge / Au is used as the electrode layer 17. However, the electrode layer 17 is not limited to this.

[0036] On the other main surface of the substrate 11, Figure 2 An n-type layer 12, an active layer 13, a p-type layer 14, and an electrode layer 16 are sequentially stacked on the lower main surface 112. A barrier layer 15 is embedded in the p-type layer 14.

[0037] (n-type layer)

[0038] The n-type layer 12 is composed of an n-type semiconductor. Examples of n-type semiconductors constituting the n-type layer 12 include GaAs-based semiconductors (e.g., AlGaAs). The n-type layer 12 may also have a multilayer structure, with each layer composed of a different type of n-type semiconductor. In this case, each layer of the n-type layer 12 may have different functions, such as a layer functioning as a buffer layer, a layer functioning as a cladding layer, and a layer functioning as a guide layer.

[0039] (Active layer)

[0040] Examples of semiconductors constituting the active layer 13 include GaAs-based semiconductors (eg, InGaAs), but the material can be appropriately selected according to the desired oscillation wavelength.

[0041] (p-type layer)

[0042] The p-type layer 14 is composed of a p-type semiconductor. Examples of p-type semiconductors constituting the p-type layer 14 include GaAs-based semiconductors (e.g., AlGaAs). The p-type layer 14 may also have a multilayer structure, with each layer composed of a different type of p-type semiconductor. In this case, the layers of the active layer 13 may each have different functions, such as a layer functioning as a guide layer, a layer functioning as a cladding layer, and a layer functioning as a contact layer.

[0043] Of the pair of main surfaces of the p-type layer 14, the main surface on the opposite side to the active layer 13 ( Figure 2 An electrode layer 16 is formed on the lower principal surface of the p-type layer 14. Electrode layer 16 is a thin metal film formed to cover the principal surface opposite to active layer 13 of the pair of principal surfaces of p-type layer 14. In this embodiment, a two-layer film of Ti / Au is used as electrode layer 16. However, electrode layer 16 is not limited to this.

[0044] (Electrode layer)

[0045] Electrode layer 16 and electrode layer 17 function as an electrode pair for flowing current into active layer 13. Hereinafter, a region for injecting current into active layer 13 is referred to as current injection stripe 161 when the main surface of electrode layer 16 is viewed in plan.

[0046] (Barrier layer)

[0047] like Figure 2As shown, the barrier layer 15 is provided to limit the area where current can be injected from the electrode layer 16 to the active layer 13. The barrier layer 15 is embedded in the inner layer of the p-type layer 14 in a manner that separates the electrode layer 16 from the active layer 13. The barrier layer 15 is composed of an n-type semiconductor having lower conductivity than the p-type semiconductor constituting the p-type layer 14. An example of a material constituting the barrier layer 15 is n-type GaAs. In order to limit the area where current injected from the electrode layer 16 flows, an opening 151 is formed in the barrier layer 15 (see Figure 2 In this embodiment, when the main surface of the barrier layer 15 is viewed from above, the shape of the opening 151 is a rectangle (see Figure 3 (a)). However, the shape of the opening 151 is not limited to a rectangle, and may be, for example, Figure 3 The shape of the opening 151A shown in (b) of FIG. Opening 151A will be described later. Furthermore, when viewing the main surface of electrode layer 16 from above, the region overlapping with opening 151 and injecting current into active layer 13 is current injection strip 161. That is, current injection strip 161 also includes the region of p-type layer 14 between electrode layer 16 and active layer 13 that overlaps with opening 151.

[0048] Thus, in the chip 10, the opening 151 is formed in the barrier layer 15. Therefore, the main surface of the pair of main surfaces of the barrier layer 15 opposite to the active layer 13 (in the Figure 2 The region corresponding to the opening 151 in the main surface located on the lower side is recessed compared to the region where the opening is not formed in the barrier layer 15 (refer to Figure 2 Therefore, the surface of the current injection strip 161 in the region overlapping with the opening 151 in a plan view is recessed compared to the surface of the region of the electrode layer 16 that does not overlap with the opening 151 in a plan view (see Figure 2 The surface of the region of the electrode layer 16 that does not overlap with the opening 151 in a plan view is the outermost surface of the chip 10 and is the outermost surface on the side where the strain suppression layer 20 is provided.

[0049] (Reflective film)

[0050] In the chip 10, a pair of reflective films are formed on a pair of end faces constituting the resonator. Figure 1 One of the pair of end faces of the resonator chip 10 shown in FIG. Figure 1 A low reflection film 18 is formed on the left end face of the image, and a low reflection film 18 is formed on the other end face (on the left end face of the image). Figure 1 A high-reflection film 19 is formed on the end surface (located on the right side in the middle). That is, the distance between the low-reflection film 18 and the high-reflection film 19 is equal to the resonator length of the chip 10. In addition, the reflectivity of the low-reflection film 18 with respect to light of the oscillation wavelength is lower than the reflectivity of the high-reflection film with respect to the same light.

[0051] The reflectivity of each high-reflection film and low-reflection film can be appropriately set according to the design of chip 10. The structures of each high-reflection film and low-reflection film can be appropriately selected from existing structures. For example, as a low-light reflective film with relatively low reflectivity, a single layer of Al2O3, AlN, Si, SiO2, TiO2, or a multilayer film composed of these materials can be used. Alternatively, as a high-light reflective film with relatively high reflectivity, a multilayer film composed of two layers of these materials can be used.

[0052] <Strain suppression layer and solder layer>

[0053] like Figure 2 As shown, the strain suppression layer 20 is formed on the main surface opposite to the active layer 13 among the pair of main surfaces of the electrode layer 16 ( Figure 2 The strain suppression layer 20 covers the current injection strip 161 in the electrode layer 16 and the region surrounding the current injection strip 161.

[0054] The solder layer 30 is a metal layer interposed between the strain suppression layer 20 and the electrode pattern 42 .

[0055] In this embodiment, gold is used as the material constituting the strain suppression layer 20. However, the material constituting the strain suppression layer 20 can be appropriately selected from metals that have good electrical conductivity and are relatively soft. Examples of materials that have good electrical conductivity and are relatively soft include gold, copper, silver, and aluminum. Alternatively, the material constituting the strain suppression layer 20 may be an alloy containing one of gold, copper, silver, and aluminum as a primary component. In this embodiment, the primary component refers to the component with the highest composition ratio in the alloy constituting the strain suppression layer 20.

[0056] In this embodiment, the strain suppression layer 20 is formed using a plating method. However, the method for forming the strain suppression layer 20 is not limited to plating. The method for forming the strain suppression layer 20 can be appropriately selected from methods that can form a film of a desired thickness (e.g., 2 μm, 3 μm, etc.). Another example of a method for forming the strain suppression layer 20 is sputtering.

[0057] There is no particular limitation on the material constituting the solder before forming the solder layer 30. The material constituting the solder can be appropriately selected according to desired properties.

[0058] The strain suppression layer 20 and the electrode pattern 42 are bonded via the solder layer 30 , whereby the chip 10 is bonded to the base 40 .

[0059] During the process of bonding the chip 10 to the base 40 using this solder, the solder melts and then solidifies again to form the solder layer 30, thereby bonding the strain suppression layer 20 to the electrode pattern 42. As the solder transitions to the solder layer 30, the components of the solder layer 30 diffuse into the interior of the strain suppression layer 20. Consequently, an alloy of the material constituting the strain suppression layer 20 (gold in this embodiment) and the components of the solder layer 30 is formed near the interface between the strain suppression layer 20 and the solder layer 30.

[0060] Hereinafter, within the strain suppression layer 20, the layer into which the components of the solder layer 30 are diffused is referred to as the reaction layer 202, and the layer into which the components of the solder layer 30 are not diffused is referred to as the unreacted layer 201. Furthermore, the thicknesses of the unreacted layer 201 and the reaction layer 202 in the region overlapping the current injection bar 161 in a plan view are referred to as thickness t1 and thickness t2, respectively. In the chip 10, when the strain suppression layer 20 and the electrode pattern 42 are bonded via the solder layer 30, the thickness of the strain suppression layer 20 (the sum of thickness t1 and thickness t2) is determined so that thickness t1 is 1.4 μm or greater. Furthermore, thickness t1 is preferably 2.0 μm or greater.

[0061] Gold, copper, silver, and aluminum, which constitute the strain suppression layer 20, are known to be relatively soft metals. Strain suppression layer 20 is composed of a soft material, thereby alleviating the strain that may occur when chip 10 is bonded to base 40 using solder layer 30. As a result, the effects of strain caused by bonding are less likely to affect chip 10. Furthermore, materials such as gold, copper, silver, and aluminum can sometimes become hardened by reacting with solder. In such cases, an unreacted layer 201, which has not reacted with the solder, is interposed between electrode layer 16 and reaction layer 202 with sufficient thickness, which is important for suppressing strain. The inventors of the present invention investigated the thickness of unreacted layer 201 in chips 10 selected from a group of chips 10 that were statistically considered to be free of failures due to strain generated during bonding. The results showed that the average thickness of unreacted layer 201 in chips 10 considered to be free of failures due to strain was 2030 nm, with a standard deviation σ of 207 nm. Taking into account various process variations, this group is estimated to have an unreacted layer 201 thicker than 3σ, that is, an unreacted layer 201 with a thickness of 1.4 μm or greater. Therefore, the presence of an unreacted layer 201 of at least 1.4 μm can dissipate the stress generated by the reaction between the plating layer and the solder in the strain suppression layer 20.

[0062] Symmetry of the current injection strip

[0063] like Figure 1As shown, in the chip-on-substrate structure 1, a columnar chip 10 and a substrate 40 are bonded via a strain suppression layer 20 and a solder layer 30. A low-reflection film 18 and a high-reflection film 19 are formed on a pair of end faces of the columnar chip 10. On this basis, an electrode layer 16 and an electrode layer 17 are formed on a pair of side faces of the columnar chip 10 (see FIG. 1 ). Figure 2 The electrode layer 16 is connected to the electrode pattern 42 via the strain suppression layer 20 and the solder layer 30 .

[0064] From the normal direction of the main surface of the active layer 13 (at Figure 1 In the case of looking down at the chip-on-base structure 1 thus constructed, the chip 10 has a strip-like shape (refer to Figure 3 In this embodiment, the axis parallel to the longitudinal direction of the chip 10 and bisecting the active layer 13 in the plan view is referred to as the central axis AC of the chip 10 (see Figure 2 and Figure 3 (a) In the chip 10 , in the plan view, the current injection bar 161 is arranged to overlap with the central axis AC.

[0065] In addition, Figure 2 In the AA' cross section shown, the current injection bar 161 is linearly symmetric about an axis (line BB') passing through the central axis AC and perpendicular to the main surface of the active layer 13. Thus, in one embodiment of the present invention, the chip 10 including the current injection bar 161 is preferably linearly symmetric about this axis of symmetry. Similarly, the strain suppression layer 20 and the solder layer 30 are preferably also linearly symmetric about this axis of symmetry. However, the base 40 does not necessarily need to be linearly symmetric about this axis of symmetry.

[0066] <Chip Variation Example>

[0067] Reference Figure 3 (b) of the present invention will now be described a chip 10A as a modified example of the chip 10. The chip 10A is formed by changing the shape of the opening 151 of the barrier layer 15 provided in the chip 10 (see FIG. Figure 3 (a)) is transformed into the opening 151A (refer to Figure 3 (b)). Chip 10A is identical to chip 10 in structure except for the shape of opening 151A. Furthermore, in this modified example, electrode layer 16 and current injection bar 161 in chip 10 are referred to as electrode layer 16A and current injection bar 161A, respectively. Specifically, current injection bar 161A is a region that overlaps with opening 151A when viewed from above the main surface of electrode layer 16A and is a region that injects current into active layer 13. Current injection bar 161A also includes a region of p-type layer 14 between electrode layer 16A and active layer 13 that overlaps with opening 151A.

[0068] In addition, for the sake of convenience, components having the same functions as those of the components described in connection with the chip 10 are denoted by the same reference numerals, and their description will not be repeated.

[0069] The chip 10A has a pair of end faces each having a low-reflection film 18 and a high-reflection film 19 formed thereon, similarly to the chip 10. The low-reflection film 18 and the high-reflection film 19 constitute a resonator.

[0070] In the chip 10A, the current injection strip 161A is composed of a first section 161A1 and a second section 161A2. Hereinafter, the widths of the first section 161A1 and the second section 161A2 are referred to as width W1 and width W2, respectively. The first section 161A1 is a section with a constant width W1 and is located on the side of the high-reflection film 19. The second section 161A2 is a section with a width W2 that tapers away from the first section 161A1 and is located on the side of the low-reflection film 18. Figure 3 As can be seen from (b), the width W2 is the largest at the boundary between the first section 161A1 and the second section 161A2, and is consistent with the width W1. In this modification, 220 μm is used as the width W1, 220 μm is used as the maximum value of the width W2, and 180 μm is used as the minimum value of the width W2. In addition, as another example of the minimum value of the width W2, 150 μm can be cited. In this modification, Figure 3 As shown in (b), a trapezoid (specifically, an isosceles trapezoid) is adopted as the shape of the second section 161A2.

[0071] Hereinafter, the entire length of the current injection bar 161A is referred to as length L, the length of the first section 161A1 is referred to as length L1, and the length of the second section 161A2 is referred to as length L2. In the chip 10A, the length L is substantially equal to the length of the resonator.

[0072] In the chip 10A, the length L is 4 mm, the length L1 is 3200 μm, and the length L2 is 800 μm. In this modified example, in the second section 161A2 with a length L2 of 800 μm, the width W2 is narrowed by 40 μm from 220 μm to 180 μm. Therefore, the ratio of the area of ​​the second section 161A2 to the area of ​​the current injection bar 161A is 18.5%, and the contraction angle θ of the second section 161A2 when looking down at the current injection bar 161 is 1.43°. In addition, another parameter related to the shape of the second section 161A2 can also be expressed as the area of ​​the second section 161A2 relative to the chip 10 (refer to FIG. 10A ) without the second section 161A2. Figure 3The ratio of the area of ​​the current injection bar 161 in (a) above is 18.2%. In the aforementioned chip 10A, this ratio is 18.2%. Another parameter related to the shape of the second segment 161A2 can be calculated by calculating the difference between the area of ​​the current injection bar 161 and the area of ​​the current injection bar 161A in chip 10, and then calculating the ratio of this difference to the area of ​​the current injection bar 161. This difference corresponds to the area of ​​the portion where the width W2 of the second segment 161A2 tapers as it moves away from the first segment 161A1, assuming deformation from the current injection bar 161 toward the current injection bar 161A. In chip 10A, the ratio of this difference to the area of ​​the current injection bar 161 is 1.82%. Below, the ratios and the values ​​of the contraction angle θ are expressed to three significant figures. The contraction angle θ is the angle formed between the legs of the second segment 161A2, which is a trapezoid (an isosceles trapezoid in this embodiment), and the central axis AC. In addition, the length L, the length L1, the length L2, the minimum value of the width W1, the width W2, and the contraction angle θ are not limited thereto.

[0073] Furthermore, when 800 μm is used as the length L2 and 150 μm is used as the minimum value of the width W2, the ratio of the area of ​​the second section 161A2 to the area of ​​the current injection bar 161A is 17.4%, the contraction angle θ of the second section 161A2 when the current injection bar 161 is viewed from above is 2.51°, and the area of ​​the second section 161A2 is 17.4% of the area of ​​the chip 10 without the second section 161A2 (see FIG. 1 ). Figure 3 The ratio of the area of ​​the current injection bar 161 in (a) is 16.8%. In addition, the ratio of the difference between the area of ​​the current injection bar 161 and the area of ​​the current injection bar 161A in the chip 10 to the area of ​​the current injection bar 161 is 3.18%.

[0074] Furthermore, the inventors of the present invention conducted simulations on the minimum values ​​of the length L, the length L1, the length L2, the width W1, the width W2, and the contraction angle θ, and found the following.

[0075] First, increasing the contraction angle θ can improve the coupling efficiency when optically coupling the laser light emitted from the chip-on-substrate structure 1 with the core of the optical fiber. In other words, it can improve the laser output efficiency. However, it is known that if the contraction angle θ is increased too much, the laser radiation pattern will become distorted. The inventors have discovered that if the contraction angle θ is less than 2.51°, this potential turbulence in the laser radiation pattern can be tolerated. Therefore, the contraction angle θ is preferably less than 2.51° (the first condition).

[0076] Furthermore, when the contraction angle θ is kept constant, the longer the length L2 is, the smaller the minimum value of the width W2 can be. This means that the aforementioned coupling efficiency can be improved. However, as the length L2 is increased, the area of ​​the current injection bar 161 decreases, thereby increasing the operating voltage during chip 10 operation and, in turn, the power consumption of the chip 10. The inventors have discovered that to achieve both high coupling efficiency and low power consumption, when width W1 is 220 μm, width W2 is preferably 150 μm or greater. In other words, the minimum value of width W2 is preferably 68.2% or greater of the maximum value of width W2 (the second condition). Furthermore, the inventors discovered that if the ratio of the area of ​​the second section 161A2 to the area of ​​the current injection bar 161A is 17.4% or greater, an increase in the operating voltage during operation can be tolerated. In other words, if the ratio of the area of ​​the second section 161A2 to the area of ​​the current injection bar 161 in a chip 10 without the second section 161A2 is 16.8% or greater, an increase in the operating voltage during operation can be tolerated. In other words, if the ratio of the difference between the area of ​​the current injection bar 161 in the chip 10 and the area of ​​the current injection bar 161A relative to the area of ​​the current injection bar 161 is 3.18% or less, an increase in the operating voltage during driving can be permitted. Therefore, it is preferable that at least one of the following conditions is satisfied when looking down at the current injection bar 161A: (1) the ratio of the area of ​​the second section 161A2 relative to the area of ​​the current injection bar 161A is 17.4% or more; (2) the ratio of the area of ​​the second section 161A2 relative to the area of ​​the current injection bar 161 in the chip 10 without the second section 161A2 is 16.8% or more; and (3) the ratio of the difference between the area of ​​the current injection bar 161 in the chip 10 and the area of ​​the current injection bar 161A relative to the area of ​​the current injection bar 161 is 3.18% or less (third condition).

[0077] In one embodiment of the present invention, by satisfying the above-mentioned three conditions (the first condition to the third condition), it is possible to improve the beam quality of the laser beam and suppress power loss.

[0078] In addition, if Figure 4 As shown in (f), a modified example of the chip 10 may further include a reaction control layer 21 covering the principal surface of the strain suppression layer 20 opposite the active layer 13. The reaction control layer 21 is used to suppress the diffusion of components of the solder layer 30 into the strain suppression layer 20 when the chip 10 is bonded to the base 40 using the solder layer 30. Examples of the reaction control layer 21 include a two-layer film such as Pt / Au or Ti / Au, and a three-layer film of Ti / Pt / Au.

[0079] When forming the strain suppression layer 20 by plating and then forming the reaction control layer 21 by plating, platinum, palladium, copper, nickel, a two-layer film of Pt / Au, etc. can be selected. However, the film formation method and structure of the reaction control layer 21 are not limited and can be selected as appropriate.

[0080] In addition, with Figure 3 Compared with the chip 10 shown in (a), the chip 10A including the second section 161A2 (see Figure 3 (b)) The width W2 gradually narrows toward the tip of the current injection strip 161, and therefore strain is easily generated when bonded to the base 40. Therefore, the effect of providing the strain suppression layer 20 is greater in the case of chip 10A than in the case of chip 10.

[0081] Chip Manufacturing Method

[0082] Regarding the method for manufacturing the chip 10A, refer to Figure 4 and Figure 5 In the description of this manufacturing method, Figures 1 to 3 A first specific example of the chip 10 is shown. Figure 4 (a)~(f) represent Figure 2 A cross-sectional view of a method for manufacturing a first specific example of a chip 10 is shown. This method includes a stacking step, an opening forming step, a contact layer stacking step, a first electrode layer stacking step, a mask forming step, a strain suppression layer stacking step, a window forming step, a second electrode layer stacking step, and a cleaving step. Figure 5 1 is a plan view showing a plurality of chips 10 manufactured by this manufacturing method.

[0083] Figure 4 (a) shows substrate 11 after the lamination step. The lamination step involves laminating buffer layer 121, n-type cladding layer 122, n-type guide layer 123, active layer 13, p-type guide layer 141, p-type cladding layer 142, and barrier layer 150 on primary surface 112 of substrate 11. In this manufacturing method, these layers are laminated using MOCVD.

[0084] The buffer layer 121, the n-type cladding layer 122 and the n-type guide layer 123 correspond to Figure 1 and Figure 2 The n-type layer 12 shown. In addition, the p-type guide layer 141 and the p-type cladding layer 142 correspond to the p-type contact layer 143 described later. Figure 1 and Figure 2 The p-type layer 14 is shown.

[0085] In this manufacturing method, a GaAs wafer is used as the substrate 11. In addition, GaAs is used as the material for forming the buffer layer 121, and Al

[0088] , ,

[0089] , Ga 1-x1 As is used as the material for forming the n-type guiding layer 123, and Al x2 Ga 1-x2 As is used as the material for forming the active layer 13, undoped InGaAs is used as the material for forming the p-type guiding layer 141, and Al x3 Ga 1-x3 As is used as the material for forming the p-type cladding layer 142, and Al x4 Ga 1-x4 As is used as the material for forming the blocking layer 150, and n-type GaAs is used. Here, x1 > x2 and x4 > x3. In addition, since the blocking layer 150 is a solid film (Japanese: ベタ膜) without an opening, the reference numeral 150 is used to distinguish it from the blocking layer 15 described later. The composition and film thickness of the active layer 13 can be appropriately adjusted to obtain the desired oscillation wavelength.

[0086] Figure 4 Figure (b) shows the substrate 11 after the opening forming process. The opening forming process is a process of forming an opening 151 in the blocking layer 150 as a solid film. In this manufacturing method, the opening 151 is formed by photolithography and etching. In addition, if surface treatment is required in the opening forming process, shallow etching (Japanese: シャロ―エッチ) based on HF or inorganic acid can also be performed.

[0087] Figure 4 Figure (c) shows the substrate 11 after the contact layer stacking process. The contact layer stacking process is a process of stacking a p-type contact layer 143 on the p-type cladding layer 142 and the blocking layer 15. In this manufacturing method, p-type GaAs is used as the material for forming the p-type contact layer 143. By performing the above processes, a chip with a Self-aligned Structure (SAS) is obtained.

[0088] In addition, regarding the changes in the composition, layer thickness, doping, etc. of the above-mentioned layers, there are many combinations suitable for laser oscillation. Therefore, it is only necessary to select a combination that can obtain the desired laser oscillation characteristics. Regarding the above-mentioned layers, as long as they have the same function structure, they can be appropriately selected. The above-mentioned layers can be single-layer films or multi-layer films.

[0089] In this manufacturing method, GaAs-based materials are used as the materials constituting n-type layer 12, active layer 13, and p-type layer 14. However, AlInGaP-based materials that are lattice-matched to GaAs substrate 11 can also be used as the materials constituting n-type layer 12, active layer 13, and p-type layer 14.

[0090] Figure 4 (d) shows the substrate 11 after the first electrode layer lamination step. The first electrode layer lamination step involves laminating the electrode layer 16 on the p-type contact layer 143. In this manufacturing method, a two-layer film of Ti / Au is used as the electrode layer 16. Furthermore, the region of the electrode layer 16 that overlaps the opening 151 functions as a current injection bar 161. The above steps complete the chip 10.

[0091] Figure 4 (e) shows the substrate 11 after the mask forming step. The mask forming step is a step of forming a photomask M on the electrode layer 16. The photomask M has openings corresponding to regions where the strain suppression layer 20 is to be formed.

[0092] Figure 4 (f) shows the substrate 11 after the strain suppression layer lamination step. The strain suppression layer lamination step involves laminating the strain suppression layer 20 and the reaction control layer 21 on the electrode layer 16 and the photomask M. In this manufacturing method, the strain suppression layer 20 and the reaction control layer 21 are laminated using a plating method. In this manufacturing method, Au is used as the material constituting the strain suppression layer 20, and a two-layer film of Pt / Au is used as the reaction control layer 21. After this, the photomask M is peeled off, resulting in the chip 10 having the strain suppression layer 20 and the reaction control layer 21.

[0093] The growth method of each of the above-mentioned layers is not limited to the MOCVD method, and liquid phase epitaxy, molecular beam epitaxy, etc. may also be used.

[0094] Figure 5 A plurality of chips 10A are shown that are manufactured on the main surface of a substrate S made of GaAs. Figure 5 There are three laser rods in the Figure 5 For illustrative purposes, a portion of substrate S (the region containing three laser bars) is enlarged. More laser bars are provided on the main surface of substrate S. Each laser bar is comprised of multiple chips 10A. Since chip 10A differs only in the shape of opening 151A from that of opening 151 in chip 10, it can be manufactured using the aforementioned manufacturing method.

[0095] The second electrode layer lamination step is a step of laminating the electrode layer 17 on the principal surface 111 of the substrate 11. In the second electrode layer lamination step, after the thickness of the substrate 11 is adjusted by grinding and polishing the principal surface 111, the electrode layer 17 composed of Ni / Ge / Au is laminated. The method for laminating the electrode layer 17 is not limited; examples thereof include electron beam evaporation and sputtering.

[0096] In the second electrode layer lamination step, heat treatment may be performed after lamination of the electrode layer 17. The temperature of the heat treatment can be appropriately determined and is, for example, 400°C.

[0097] Alternatively, a metallization layer (eg, Ti / Pt / Au) having an Au surface may be provided on the electrode layer 17. This can improve wire bonding properties with the electrode pattern 43 of the base 40 or external electrodes.

[0098] The splitting process is done by Figure 5 The illustrated process involves cleaving the substrate S, for example, along lines C-C' and D-D' to obtain individual laser bars. Alternatively, when obtaining individual chips 10A from a single laser bar, adjacent chips 10A can be separated. This separation can be performed by cleaving the substrate S that constitutes the laser bars or by dicing.

[0099] [Second specific example of chip]

[0100] Regarding the second specific example of the chip 10, refer to Figure 6 and Figure 7 Provide explanation. Figure 6 (a) to (c) are cross-sectional views showing a second specific example of a method for manufacturing the chip 10. The stacking steps of the second specific example of the manufacturing method are as follows: Figure 4 In addition, the method of forming the barrier layer 15 after the lamination process is also different. Figure 7 (a) is a plan view of the second specific example of the chip 10 as viewed from the current injection bar 161B side. Figure 7 (b) is viewed from the current injection bar 161C side Figure 7 (a) is a top view of a modified example of the second specific example.

[0101] In addition, for the sake of convenience, components having the same functions as those of the components described in connection with the chip 10 are denoted by the same reference numerals, and their description will not be repeated.

[0102] Figure 6(a) shows the substrate 11 after the lamination and mask formation steps. The lamination step involves laminating the buffer layer 121, n-type cladding layer 122, n-type guide layer 123, active layer 13, p-type guide layer 141, p-type cladding layer 142, etch stop layer 14s, and p-type contact layer 143 on the main surface 112 of the substrate 11. The mask formation step involves forming a photomask M on the p-type contact layer 143. The etch stop layer 14s is made of a material with a slower etching rate than the p-type contact layer 143. Many suitable combinations exist for the material of the etch stop layer 14s and the method for etching the p-type contact layer 143. Therefore, a suitable combination of the material of the etch stop layer 14s and the method for etching the p-type contact layer 143 can be appropriately selected from existing suitable combinations. For example, AlGaAs can be used as the material for the etch stop layer 14s, and a citric acid-based etchant can be used as the method for etching the p-type contact layer 143.

[0103] Figure 6 (b) shows the substrate 11 after the etching process. The etching process is a process of etching the p-type contact layer 143 to a depth that reaches the etching stop layer 14s to form two grooves 14t. As a result, the area sandwiched between the two grooves 14t in the p-type contact layer 143 is patterned into a ridge shape. Figure 6 (b) shows the substrate 11 in a state where the photomask M has been removed after the etching step.

[0104] Figure 6 (c) shows substrate 11 after the dielectric layer forming step. The dielectric layer forming step forms dielectric layer 15A on p-type contact layer 143 and etching stop layer 14s. Dielectric layer 15A is composed of a dielectric having lower conductivity than the p-type semiconductor constituting p-type contact layer 143.

[0105] In addition, although the description is omitted here, after the barrier layer forming process, a second specific example of the chip 10 can be obtained by implementing the above-mentioned first electrode layer stacking process, mask forming process, strain suppression layer stacking process, window forming process, second electrode layer stacking process, and splitting process.

[0106] Hereinafter, the second specific example of the chip 10 is referred to as chip 10B (see Figure 7 (a)). In addition, a modified example of chip 10B is referred to as chip 10C (see Figure 7 (b)). The chip with a base chip structure 1 may be a chip 10 (see Figure 3 (a) and Figure 4 ) and chip 10A (refer to Figure 3Alternatively, a chip having two grooves 14t formed in the p-type contact layer 143, as in chip 10B and chip 10C, may be formed. Furthermore, among the chips having the chip-on-base structure 1, a chip having a ridged p-type contact layer 143 may also employ a current injection strip 161 having a constant width W, as in chip 10.

[0107] 〔Summarize〕

[0108] To address the aforementioned technical issues, the first embodiment of the present invention employs a chip-on-substrate structure comprising: a wide-area chip including an active layer and current injection bars for injecting current into the active layer; a metal strain suppression layer covering the current injection bars; a substrate comprising a substrate and an electrode layer disposed on one principal surface of the substrate; and a solder layer interposed between the strain suppression layer and the electrode layer, bonding the chip and substrate. In this chip-on-substrate structure, the strain suppression layer comprises a reaction layer into which components of the solder layer diffuse, and an unreacted layer into which components of the solder layer do not diffuse, with the unreacted layer having a thickness of at least 1.4 μm.

[0109] The chip-on-substrate structure of the first embodiment has an unreacted layer of the strain suppression layer having a thickness of 1.4 μm or greater, thereby suppressing strain that may occur during the process of bonding the chip to the substrate using solder. Therefore, the chip-on-substrate structure can stabilize the laser radiation shape.

[0110] Furthermore, in a chip-on-substrate structure according to a second aspect of the present invention, in addition to the structure of the chip-on-substrate structure according to the first aspect, a main component of the strain suppression layer is gold.

[0111] Gold is a relatively soft metal. The aforementioned strain can be reliably suppressed by placing a relatively soft metal between the chip and the base in this structure. Furthermore, gold has high electrical and thermal conductivity. Therefore, this chip-on-base structure can reduce power loss that can occur when driving current is supplied to the chip and efficiently dissipate heat that may be generated in the chip to the base.

[0112] In addition, in the third form of the chip-with-base structure of the present invention, the following structure is adopted: on the basis of the structure of the chip-with-base structure of the above-mentioned first form or second form, when the main surface of the active layer is viewed from the normal direction of the main surface, the chip has a strip shape, and the current injection strip is arranged to overlap with the central axis of the chip in the strip shape.

[0113] Heat generated when driving the chip tends to be generated near the active layer, where it overlaps with the current injection strips when viewed from above. This structure improves the symmetry of the current injection strips within the chip. Therefore, this chip-on-base structure can suppress thermal strain that can occur when driving the chip.

[0114] In addition, in the fourth embodiment of the chip-with-base structure of the present invention, the following structure is adopted: on the basis of the structure of the third embodiment of the chip-with-base structure, in the cross-section of the chip, that is, in the cross-section parallel to each of a pair of end faces of the resonator constituting the chip, the current injection strip is linearly symmetrical with the axis passing through the center axis and orthogonal to the main surface of the active layer as the symmetry axis.

[0115] According to the above structure, the symmetry of the current injection strips inside the chip can be further improved. Therefore, the chip with base structure can further suppress the thermal strain that may be generated in the chip when the chip is driven.

[0116] Furthermore, in a fifth aspect of the present invention, in addition to the structure of the third aspect, the current injection strip is recessed relative to the outermost surface of the chip, that is, the outermost surface on the side where the strain suppression layer is provided.

[0117] This structure can suppress strain that may be generated during the soldering process of joining the chip to the base, compared to a case where the current injection bar protrudes from the outermost surface of the chip, i.e., the outermost surface on the side where the strain suppression layer is provided. Therefore, this chip-on-base structure can stabilize the laser radiation pattern.

[0118] Furthermore, a sixth aspect of the present invention employs a chip-on-base structure, in addition to the structure of any of the first to third aspects, wherein the chip further comprises a high-reflection film and a low-reflection film constituting the chip's resonator, wherein the low-reflection film has a lower reflectivity than the high-reflection film. In this chip-on-base structure, the current injection strip is composed of a first section and a second section, wherein the first section has a constant width and is located on the high-reflection film side, and the second section has a width that decreases as it moves away from the first section and is located on the low-reflection film side.

[0119] The above structure can improve the beam quality of the laser light emitted from the chip. Therefore, the chip-on-susceptor structure can improve the coupling efficiency when optically coupling the laser light to the core of the optical fiber, in other words, it can improve the output efficiency of the laser light.

[0120] In addition, in the seventh embodiment of the present invention, the following structure is adopted: on the basis of the structure of the sixth embodiment of the chip structure with a base, when the main surface of the current injection strip is viewed from the normal direction of the main surface, the chip has a strip shape, and the second interval has a trapezoidal shape whose width becomes narrower as it moves away from the first interval. In the second interval, the ratio of the minimum value of the width to the maximum value is greater than 68.2%, the ratio of the area of ​​the second interval to the area of ​​the current injection strip is greater than 17.4%, and the angle formed by the waist of the trapezoid constituting the second interval and the central axis of the chip in the strip shape, that is, the contraction angle θ, is greater than 0° and less than 2.51°.

[0121] By satisfying the above two conditions, the laser beam quality can be improved and the power loss that may occur when the chip is driven can be suppressed.

[0122] In addition, in the eighth embodiment of the chip structure with a base of the present invention, the following structure is adopted: on the basis of the structure of the chip structure with a base of any one of the first to seventh embodiments mentioned above, there is also a reaction control layer, and the reaction control layer is arranged between the strain suppression layer and the solder layer, and is composed of a multilayer film made of metal.

[0123] With this structure, the reaction control layer interposed between the strain suppression layer and the solder layer prevents diffusion of solder layer components into the strain suppression layer. Therefore, compared to direct bonding of the strain suppression layer and the solder layer, this chip-on-substrate structure can easily maintain an unreacted layer with a thickness of 1.4 μm or greater.

[0124] In addition, in the chip-on-base structure of the ninth aspect of the present invention, the following structure is adopted: based on the structure of the chip-on-base structure of any one of the first to eighth aspects, the width of the current injection strip is greater than 75 μm across the entire interval.

[0125] A structure in which the unreacted layer in the strain suppression layer has a thickness of 1.4 μm or greater is suitable for a chip-on-base structure having a wide-area chip, where the width of the current injection stripe is 75 μm or greater across the entire area. Such a wide-area chip can emit laser light with an output of 10 W or greater.

[0126] 〔Remarks〕

[0127] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining technical means disclosed in different embodiments are also included in the technical scope of the present invention.

[0128] Description of reference numerals:

[0129] 1: Chip structure with base; 10, 10A: Chip; 11: Substrate; 12: n-type layer; 121: Buffer layer; 122: n-type cladding layer; 123: n-type guide layer; 13: Active layer; 14: P-type layer; 14t: Groove; 141: P-type guide layer; 142: P-type cladding layer; 143: P-type contact layer; 15: Barrier layer; 15A: Dielectric layer; 16, 17: Electrode layer; 161: Current injection bar; 18: Low-reflection film; 19: High-reflection film; 20: Strain suppression layer; 21: Reaction control layer; 30: Solder layer; 40: Base; 41: Substrate; 42, 43: Electrode pattern.

Claims

1. A chip structure with a base, characterized in that: have: A wide-area chip comprising an active layer and current injection strips for injecting current into the active layer; a strain suppression layer made of metal and covering the current injection strip; A base comprising a substrate and an electrode layer provided on a main surface of the substrate; as well as a solder layer interposed between the strain suppression layer and the electrode layer, bonding the chip and the base; The strain suppression layer is composed of a reaction layer in which the components of the solder layer are diffused and an unreacted layer in which the components of the solder layer are not diffused. The thickness of the unreacted layer is greater than 1.4 μm.

2. The chip structure with base according to claim 1, characterized in that: The main component of the strain suppression layer is gold.

3. The chip structure with base according to claim 1 or 2, characterized in that: When the main surface of the active layer is viewed from above in the normal direction of the main surface, The chip has a strip shape, The current injection strip is arranged to overlap with the central axis of the strip-shaped chip.

4. The chip structure with base according to claim 3, characterized in that: In a cross section of the chip, that is, a cross section parallel to each of a pair of end faces of a resonator constituting the chip, The current injection bar is line-symmetrical about an axis passing through the central axis and perpendicular to the main surface of the active layer.

5. The chip structure with base according to claim 3, characterized in that: The current injection strip is recessed relative to the outermost surface of the chip, that is, the outermost surface on the side where the strain suppression layer is provided.

6. The chip-on-substrate structure according to any one of claims 1 to 3, wherein: The chip further includes a high-reflection film and a low-reflection film constituting a resonator of the chip, wherein the reflectivity of the low-reflection film is lower than that of the high-reflection film. The current injection stripe is composed of a first section having a constant width and located on the high reflection film side, and a second section having a width that becomes narrower as it moves away from the first section and located on the low reflection film side.

7. The chip structure with base according to claim 6, characterized in that: When the main surface of the current injection strip is viewed from above in the normal direction of the main surface, The chip has a strip shape, The second section has a trapezoidal shape whose width becomes narrower as it moves away from the first section. In the second interval, the ratio of the minimum value of the width to the maximum value is greater than 68.2%. The ratio of the area of ​​the second section to the area of ​​the current injection bar is greater than 17.4%, The contraction angle θ, which is an angle formed between the waist of the trapezoid constituting the second section and the central axis of the strip-shaped chip, is equal to or greater than 0° and less than 2.51°.

8. The chip-on-substrate structure according to any one of claims 1 to 7, wherein: The device further includes a reaction control layer provided between the strain suppression layer and the solder layer and composed of a metal multilayer film.

9. The chip-on-substrate structure according to any one of claims 1 to 8, wherein: The width of the current injection strip is greater than 75 μm across the entire section.

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