Embedded high-voltage semiconductor element and manufacturing method thereof

Abstract

The invention discloses an embedded high-voltage semiconductor device and a manufacturing method thereof, and the embedded high-voltage semiconductor device comprises a substrate which is provided with a low-voltage device region and a high-voltage device region; an ILD layer disposed on the substrate; the first interconnection metal layer is positioned on the ILD layer in the low-voltage component region; a first IMD layer between the ILD layer and the first interconnect metal layer; the second interconnection metal layer is positioned on the ILD layer in the high-voltage element region; and a second IMD layer between the ILD layer and the second interconnect metal layer, where the second IMD layer is denser than the first IMD layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an embedded high voltage (eHV) semiconductor element and a manufacturing method thereof. Background Art

[0002] To reduce RC delay, metal interconnects in semiconductor substrate circuits often utilize materials with relatively low dielectric constants. These materials are referred to as low-k and ultra-low-k dielectric materials. Low-k dielectric materials generally refer to materials with a dielectric constant lower than that of SiO2, which has a dielectric constant of approximately 4.0. Ultra-low-k dielectric materials generally refer to materials with a dielectric constant of approximately 2.1 or lower.

[0003] Due to the reduced thickness of the intermetallic dielectric layer (ILD) made of low-k or ultra-low-k dielectric material between the M1 and M0 metal layers, the medium-voltage and high-voltage regions of embedded high-voltage (eHV) devices (eHV) cannot pass the 8V TDDB (Time-Dependent Dielectric Breakdown) reliability test. Therefore, there is a need for an improved embedded high-voltage semiconductor device and its manufacturing method to address the IMD breakdown issue. Summary of the Invention

[0004] The main purpose of the present invention is to provide an improved embedded high-voltage semiconductor component and a manufacturing method thereof to address the deficiencies or shortcomings of the prior art.

[0005] In one aspect, the present invention provides an embedded high-voltage (eHV) semiconductor device, comprising: a substrate having a low-voltage device region and a high-voltage device region thereon; an interlayer dielectric (ILD) layer disposed on the substrate; a first trench isolation region located in the substrate within the low-voltage device region; a first gate located in the ILD layer and located on the first trench isolation region; a first gate contact located in the ILD layer and located on the first gate; a first interconnect metal layer covering the first gate contact; and a first intermetallic dielectric (IMD) layer located on the ILD layer. and is located between the first interconnect metal layer and the first gate contact; a second trench isolation region is located in the substrate within the high-voltage device region; a second gate is located in the ILD layer and is located on the second trench isolation region; a second gate contact is located in the ILD layer and is located on the second gate; a second interconnect metal layer covers the second gate contact; and a second intermetal dielectric (IMD) layer is located on the ILD layer and is located between the second interconnect metal layer and the second gate contact, wherein the second IMD layer is denser than the first IMD layer.

[0006] According to an embodiment of the present invention, the second interconnect metal layer overlaps with the second gate contact.

[0007] According to an embodiment of the present invention, the first IMD layer includes an ultra-low dielectric constant material layer.

[0008] According to an embodiment of the present invention, the second IMD layer includes a TEOS oxide layer or a high-density plasma oxide layer.

[0009] According to an embodiment of the present invention, the second interconnect metal layer is disposed in the second IMD layer.

[0010] According to an embodiment of the present invention, the first IMD layer extends onto a top surface of the second IMD layer.

[0011] According to an embodiment of the present invention, the second interconnect metal layer is disposed in the first IMD layer extending onto the top surface of the second IMD layer.

[0012] According to an embodiment of the present invention, the first gate contact and the second gate contact include tungsten.

[0013] According to an embodiment of the present invention, the first gate and the second gate are metal gates.

[0014] According to an embodiment of the present invention, the first IMD layer and the second IMD layer are ultra-low dielectric constant material layers.

[0015] Another aspect of the present invention provides a method for forming an embedded high-voltage (eHV) semiconductor component. First, a substrate having a low-voltage component region and a high-voltage component region is provided. An interlayer dielectric (ILD) layer is formed on the substrate. A first trench isolation region is formed in the substrate within the low-voltage component region. A first gate is formed in the ILD layer and on the first trench isolation region. A first gate contact is formed in the ILD layer and on the first gate. A first interconnect metal layer is formed covering the first gate contact. A first intermetallic dielectric (IMD) layer is formed on the ILD layer and between the first interconnect metal layer and the first gate contact. A second trench isolation region is formed in the substrate within the high-voltage component region. A second gate is formed in the ILD layer and on the second trench isolation region. A second gate contact is formed in the ILD layer and on the second gate. A second interconnect metal layer is formed covering the second gate contact. A second intermetallic dielectric (IMD) layer is formed on the ILD layer and between the second interconnect metal layer and the second gate contact. The second IMD layer is denser than the first IMD layer.

[0016] According to an embodiment of the present invention, the second interconnect metal layer overlaps with the second gate contact.

[0017] According to an embodiment of the present invention, the first IMD layer includes an ultra-low dielectric constant material layer.

[0018] According to an embodiment of the present invention, the second IMD layer includes a TEOS oxide layer or a high-density plasma oxide layer.

[0019] According to an embodiment of the present invention, the second interconnect metal layer is disposed in the second IMD layer.

[0020] According to an embodiment of the present invention, the first IMD layer extends onto a top surface of the second IMD layer.

[0021] According to an embodiment of the present invention, the second interconnect metal layer is disposed in the first IMD layer extending onto the top surface of the second IMD layer.

[0022] According to an embodiment of the present invention, the first gate contact and the second gate contact include tungsten.

[0023] According to an embodiment of the present invention, the first gate and the second gate are metal gates.

[0024] According to an embodiment of the present invention, the first IMD layer and the second IMD layer are ultra-low dielectric constant material layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 7 is a schematic diagram illustrating a method for forming an embedded high-voltage (eHV) semiconductor device according to an embodiment of the present invention;

[0026] Figures 8 to 14 is a schematic diagram illustrating a method for forming an eHV semiconductor device according to another embodiment of the present invention;

[0027] Figures 15 to 18 FIG. 4 is a schematic diagram illustrating a method for forming an eHV semiconductor device according to yet another embodiment of the present invention.

[0028] Explanation of symbols

[0029] 1, 2, 3 Embedded High Voltage (eHV) semiconductor components

[0030] 20, 30 circuit components

[0031] 100 base

[0032] 201 fin structure

[0033] 202 Metal Gate

[0034] 204 gate

[0035] 301 drain or source doping region

[0036] 302 gate

[0037] 304 gate

[0038] 410 interlayer dielectric (ILD) layer

[0039] 420, 440, 440d intermetal dielectric (IMD) layers

[0040] 431, 451 interconnect metal layers

[0041] 432, 452 vias

[0042] 510 shielding layer

[0043] MD1, MD2 doped region contacts

[0044] MP1, MP2 gate contacts

[0045] PR photoresist pattern

[0046] RL low voltage component area

[0047] RH high voltage component area

[0048] ST1, ST2 trench isolation area DETAILED DESCRIPTION

[0049] Hereinafter, the details will be described with reference to the accompanying drawings, which also constitute a part of the detailed description of the specification and are illustrated in a manner that describes specific examples of the embodiments that can be implemented. The following embodiments are described in sufficient detail to enable a person skilled in the art to implement them.

[0050] Of course, other embodiments may be employed, and any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered limiting, and the embodiments contained therein are to be defined by the appended claims.

[0051] See also Figures 1 to 7 , which illustrates a method for forming an embedded high-voltage (eHV) semiconductor device 1 according to one embodiment of the present invention. For example, the eHV semiconductor device 1 of the present invention can be used in a display driver chip (DDIC) fabricated using a 17nm or lower fin field-effect transistor (FinFET) process.

[0052] like Figure 1As shown, a substrate 100 is first provided, such as, but not limited to, a silicon substrate. According to an embodiment of the present invention, a low-voltage component region RL and a high-voltage component region RH are formed on the substrate 100. Trench isolation regions SI1 and SI2 are formed in the low-voltage component region RL and the high-voltage component region RH, respectively. Trench isolation regions SI1 and SI2 can be formed using a shallow trench isolation (STI) process.

[0053] According to an embodiment of the present invention, a circuit element 20 is formed on the substrate 100 next to the trench isolation region SI1 in the low-voltage component region RL. A circuit element 30 is formed on the substrate 100 next to the trench isolation region SI2 in the high-voltage component region RH. According to an embodiment of the present invention, for example, the circuit element 20 may be a fin field-effect transistor (FinFET) element, but is not limited thereto. According to an embodiment of the present invention, the operating voltage of the circuit element 20 may be less than 5V, for example, 1.8V. The circuit element 20 may include a fin-shaped structure 201 and a metal gate 202 spanning the fin-shaped structure 201. According to an embodiment of the present invention, for example, the circuit element 30 may be a high-voltage transistor element having an operating voltage greater than 5V. For example, the circuit element 20 may be a planar field-effect transistor including a drain or source doping region 301 and a gate 302.

[0054] According to an embodiment of the present invention, a gate 204 and a gate 304 are formed on the trench isolation region SI1 and the trench isolation region SI2, respectively. According to an embodiment of the present invention, the gate 204 and the gate 304 can be metal gates, for example, but are not limited thereto.

[0055] Next, a chemical vapor deposition (CVD) process can be performed to deposit an interlayer dielectric (ILD) layer 410 on the substrate 100. A metallization process is then performed to form a doped region contact MD1 and a gate contact MP1 in the ILD layer 410 within the low-voltage device region RL, and a doped region contact MD2 and a gate contact MP2 in the ILD layer within the high-voltage device region RH. According to an embodiment of the present invention, the doped region contact MD1 directly contacts the doped region on the fin structure 201, the gate contact MP1 directly contacts the gate 204, the doped region contact MD2 directly contacts the drain or source doped region 301, and the gate contact MP2 directly contacts the gate 304. According to an embodiment of the present invention, the gate 204 and the gate contact MP1 are located directly above the trench isolation region SI1, and the gate 304 and the gate contact MP2 are located directly above the trench isolation region SI2. According to an embodiment of the present invention, the gate contact MP1 and the gate contact MP2 may include tungsten, but are not limited thereto.

[0056] Next, a chemical vapor deposition process may be performed to deposit an intermetallic dielectric (IMD) layer 420 on the substrate 100. According to an embodiment of the present invention, the IMD layer 420 may include a structurally dense dielectric layer such as a TEOS oxide layer or a high-density plasma oxide layer.

[0057] like Figure 2 As shown, a metallization process, such as a damascene copper process, is then performed to form an interconnect metal layer 431 and vias 432 in the IMD layer 420 within the high-voltage component region RH. Vias 432 electrically connect the interconnect metal layer 431 to the underlying doped region contact MD2. According to an embodiment of the present invention, the interconnect metal layer 431 extends laterally to directly above the gate 304 and the gate contact MP2. Therefore, when viewed from above, the interconnect metal layer 431 overlaps the gate contact MP2. The IMD layer 420 is located between the interconnect metal layer 431 and the gate contact MP2.

[0058] like Figure 3 As shown, a photolithography process is then performed to form a photoresist pattern PR on the high voltage device region RH, wherein the photoresist pattern PR covers the high voltage device region RH but exposes the IMD layer 420 of the low voltage device region RL.

[0059] like Figure 4 As shown, then, an etching process is performed, for example, an anisotropic dry etching process, using the photoresist pattern PR as an etching resistance mask to remove the IMD layer 420 in the low-voltage device area RL not covered by the photoresist pattern PR, thereby exposing the ILD layer 410, the doped region contact MD1 and the gate contact MP1 in the low-voltage device area RL.

[0060] like Figure 5 As shown, a chemical vapor deposition process is then performed to deposit an intermetallic dielectric (IMD) layer 440 on the entire surface of substrate 100. According to embodiments of the present invention, for example, IMD layer 440 may comprise a low-k dielectric material or an ultra-low-k dielectric material. For example, IMD layer 440 may comprise porous silicon dioxide, porous carbon-doped silicon dioxide, porous SiLK, or a porous SiCOH layer. According to embodiments of the present invention, IMD layer 420 is denser than IMD layer 440.

[0061] like Figure 6 As shown, a chemical mechanical polishing (CMP) process is then performed to polish the surface of the IMD layer 440 so that the surface of the IMD layer 440 in the low voltage device region RL and the high voltage device region RH is close to the same level.

[0062] like Figure 7As shown, a metallization process, such as a damascene copper process, is then performed to form an interconnect metal layer 451 and a via 452 in the IMD layer 440 within the low-voltage device region RL. The via 452 electrically connects the interconnect metal layer 451 to the underlying doped region contact MD1. According to an embodiment of the present invention, the interconnect metal layer 451 extends laterally to directly above the gate 204 and the gate contact MP1. Therefore, when viewed from above, the interconnect metal layer 451 overlaps the gate contact MP1. The IMD layer 440 is located between the interconnect metal layer 451 and the gate contact MP1. Chemical mechanical polishing (CMP) can then be performed to expose the interconnect metal layer 431 and the interconnect metal layer 451, allowing subsequent metal interconnect fabrication processes to proceed.

[0063] See also Figures 8 to 14 , which illustrates a method for forming an eHV semiconductor device 2 according to another embodiment of the present invention. Identical regions, layers, or components are represented by the same symbols. For example, the eHV semiconductor device 2 of the present invention can be used in display driver ICs (DDICs) fabricated using a 17nm or lower fin field-effect transistor (FinFET) process.

[0064] like Figure 8 As shown, a substrate 100 is first provided, such as, but not limited to, a silicon substrate. According to an embodiment of the present invention, a low-voltage component region RL and a high-voltage component region RH are formed on the substrate 100. Trench isolation regions SI1 and SI2 are formed in the low-voltage component region RL and the high-voltage component region RH, respectively. Trench isolation regions SI1 and SI2 can be formed using a shallow trench isolation (STI) process.

[0065] According to an embodiment of the present invention, a circuit element 20 is formed on the substrate 100 next to the trench isolation region SI1 in the low-voltage component region RL. A circuit element 30 is formed on the substrate 100 next to the trench isolation region SI2 in the high-voltage component region RH. According to an embodiment of the present invention, for example, the circuit element 20 may be a FinFET element, but is not limited thereto. According to an embodiment of the present invention, the operating voltage of the circuit element 20 may be less than 5V, for example, 1.8V. The circuit element 20 may include a fin-shaped structure 201 and a metal gate 202 spanning the fin-shaped structure 201. According to an embodiment of the present invention, for example, the circuit element 30 may be a high-voltage transistor element having an operating voltage greater than 5V. For example, the circuit element 20 may be a planar field-effect transistor including a drain or source doping region 301 and a gate 302.

[0066] According to an embodiment of the present invention, a gate 204 and a gate 304 are formed on the trench isolation region SI1 and the trench isolation region SI2, respectively. According to an embodiment of the present invention, the gate 204 and the gate 304 can be metal gates, for example, but are not limited thereto.

[0067] Next, a chemical vapor deposition process can be performed to deposit an interlayer dielectric (ILD) layer 410 on the entire substrate 100. A metallization process is then performed to form a doped region contact MD1 and a gate contact MP1 in the ILD layer 410 within the low-voltage component region RL, and to form a doped region contact MD2 and a gate contact MP2 in the ILD layer within the high-voltage component region RH. According to an embodiment of the present invention, the doped region contact MD1 directly contacts the doped region on the fin structure 201, the gate contact MP1 directly contacts the gate 204, the doped region contact MD2 directly contacts the drain or source doped region 301, and the gate contact MP2 directly contacts the gate 304. According to an embodiment of the present invention, the gate 204 and the gate contact MP1 are located directly above the trench isolation region SI1, and the gate 304 and the gate contact MP2 are located directly above the trench isolation region SI2. According to an embodiment of the present invention, the gate contact MP1 and the gate contact MP2 may include tungsten, but are not limited thereto.

[0068] Next, a chemical vapor deposition process may be performed to deposit an intermetallic dielectric (IMD) layer 420 on the substrate 100. According to an embodiment of the present invention, the IMD layer 420 may include a structurally dense dielectric layer such as a TEOS oxide layer or a high-density plasma oxide layer.

[0069] like Figure 9 As shown, a metallization process, such as a damascene copper process, is then performed to form a via 432 in the IMD layer 420 within the high-voltage device region RH, wherein the via 432 is electrically connected to the underlying doped region contact MD2.

[0070] like Figure 10 As shown, a photolithography process is then performed to form a photoresist pattern PR on the high voltage device region RH, wherein the photoresist pattern PR covers the high voltage device region RH but exposes the IMD layer 420 of the low voltage device region RL.

[0071] like Figure 11 As shown, then, an etching process is performed, for example, an anisotropic dry etching process, using the photoresist pattern PR as an etching resistance mask to remove the IMD layer 420 in the low-voltage device area RL not covered by the photoresist pattern PR, thereby exposing the ILD layer 410, the doped region contact MD1 and the gate contact MP1 in the low-voltage device area RL.

[0072] like Figure 12As shown, a chemical vapor deposition process is then performed to deposit an intermetallic dielectric (IMD) layer 440 on the entire surface of substrate 100. According to embodiments of the present invention, IMD layer 440 may comprise, for example, a low-k or ultra-low-k dielectric material. For example, IMD layer 440 may comprise porous silicon dioxide, porous carbon-doped silicon dioxide, porous SiLK, or a porous SiCOH layer. According to embodiments of the present invention, IMD layer 420 is denser than IMD layer 440.

[0073] like Figure 13 As shown, a chemical mechanical polishing (CMP) process is then performed to polish the surface of the IMD layer 440 so that the surface of the IMD layer 440 is approximately at the same level in the low-voltage device region RL and the high-voltage device region RH. According to an embodiment of the present invention, in the high-voltage device region RH, the IMD layer 440 extends onto the top surface of the IMD layer 420.

[0074] like Figure 14 As shown, a metallization process, such as a damascene copper process, is then performed to form an interconnect metal layer 431 in the IMD layer 440 within the high-voltage device region RH, and an interconnect metal layer 451 and a via 452 are formed in the IMD layer 440 within the low-voltage device region RL. The interconnect metal layer 431 is electrically connected to the via 432, and the via 452 is electrically connected to the interconnect metal layer 451 and the underlying doped region contact MD1. According to an embodiment of the present invention, the interconnect metal layer 431 is disposed in the IMD layer 440 extending onto the top surface of the IMD layer 420.

[0075] According to an embodiment of the present invention, interconnect metal layer 431 extends laterally to directly above gate 304 and gate contact MP2. Therefore, when viewed from above, interconnect metal layer 431 overlaps with gate contact MP2. Between interconnect metal layer 431 and gate contact MP2 is IMD layer 420. According to an embodiment of the present invention, interconnect metal layer 451 extends laterally to directly above gate 204 and gate contact MP1. Therefore, when viewed from above, interconnect metal layer 451 overlaps with gate contact MP1. Between interconnect metal layer 451 and gate contact MP1 is IMD layer 440.

[0076] See also Figures 15 to 18 , which illustrates a method for forming an eHV semiconductor device 3 according to yet another embodiment of the present invention. Identical regions, layers, or components are represented by the same symbols. For example, the eHV semiconductor device 3 of the present invention can be used in display driver ICs (DDICs) fabricated using a 17nm or lower fin field-effect transistor (FinFET) process.

[0077] like Figure 15As shown, a substrate 100 is also provided, such as, but not limited to, a silicon substrate. According to an embodiment of the present invention, a low-voltage component region RL and a high-voltage component region RH are formed on the substrate 100. Trench isolation regions SI1 and SI2 are formed in the low-voltage component region RL and the high-voltage component region RH, respectively. Trench isolation regions SI1 and SI2 can be formed using a shallow trench isolation (STI) process.

[0078] According to an embodiment of the present invention, in the low-voltage component region RL, a circuit element 20 is also formed on the substrate 100 next to the trench isolation region SI1. In the high-voltage component region RH, a circuit element 30 is also formed on the substrate 100 next to the trench isolation region SI2. According to an embodiment of the present invention, for example, the circuit element 20 may be a FinFET element, but is not limited thereto. According to an embodiment of the present invention, the operating voltage of the circuit element 20 may be less than 5V, for example, 1.8V. The circuit element 20 may include a fin-shaped structure 201 and a metal gate 202 spanning the fin-shaped structure 201. According to an embodiment of the present invention, for example, the circuit element 30 may be a high-voltage transistor element, whose operating voltage is greater than 5V. For example, the circuit element 20 may be a planar field-effect transistor, including a drain or source doping region 301 and a gate 302.

[0079] According to an embodiment of the present invention, a gate 204 and a gate 304 are formed on the trench isolation region SI1 and the trench isolation region SI2, respectively. According to an embodiment of the present invention, the gate 204 and the gate 304 can be metal gates, for example, but are not limited thereto.

[0080] Next, a chemical vapor deposition process can be performed to deposit an interlayer dielectric (ILD) layer 410 on the entire substrate 100. A metallization process is then performed to form a doped region contact MD1 and a gate contact MP1 in the ILD layer 410 within the low-voltage component region RL, and to form a doped region contact MD2 and a gate contact MP2 in the ILD layer within the high-voltage component region RH. According to an embodiment of the present invention, the doped region contact MD1 directly contacts the doped region on the fin structure 201, the gate contact MP1 directly contacts the gate 204, the doped region contact MD2 directly contacts the drain or source doped region 301, and the gate contact MP2 directly contacts the gate 304. According to an embodiment of the present invention, the gate 204 and the gate contact MP1 are located directly above the trench isolation region SI1, and the gate 304 and the gate contact MP2 are located directly above the trench isolation region SI2. According to an embodiment of the present invention, the gate contact MP1 and the gate contact MP2 may include tungsten, but are not limited thereto.

[0081] Next, a chemical vapor deposition process may be performed to deposit an intermetallic dielectric (IMD) layer 440 on the entire surface of the substrate 100. According to an embodiment of the present invention, for example, the IMD layer 440 may comprise a low-k or ultra-low-k dielectric material that can be cured by ultraviolet light. For example, the IMD layer 440 may comprise porous silicon dioxide, porous carbon-doped silicon dioxide, porous SiLK, a porous SiCOH layer, or the like. Next, a shielding layer 510 is formed on the IMD layer 440 in the low-voltage component region RL. For example, the shielding layer 510 may comprise silicon oxynitride, but is not limited thereto. At this point, the IMD layer 440 in the high-voltage component region RH is not covered by the shielding layer 510 but is exposed.

[0082] like Figure 16 As shown, a UV curing process is performed to directly irradiate the IMD layer 440 in the high-voltage component region RH with UV light to form a densified IMD layer 440d. According to an embodiment of the present invention, both the IMD layer 440 and the IMD layer 440d are ultra-low dielectric constant material layers. According to an embodiment of the present invention, for example, the IMD layer 440 in the high-voltage component region RH is irradiated with UV light for approximately 300 seconds, which can increase the hardness of the IMD layer 440 in the high-voltage component region RH from approximately 0.75 GPa to approximately 1-2 GPa, thereby forming a densified IMD layer 440d.

[0083] like Figure 17 As shown, after the UV curing process is completed, an etching process, such as a wet etching process, is performed to remove the shielding layer 510 to expose the IMD layer 440 in the low-voltage device region RL.

[0084] like Figure 18 As shown, a metallization process is then performed, for example, a copper inlay process, to form an interconnection metal layer 431 and a via 432 in the IMD layer 440d in the high-voltage device region RH, and to form an interconnection metal layer 451 and a via 452 in the IMD layer 440 in the low-voltage device region RL.

[0085] According to an embodiment of the present invention, interconnect metal layer 431 extends laterally to directly above gate 304 and gate contact MP2. Therefore, when viewed from above, interconnect metal layer 431 overlaps gate contact MP2. Between interconnect metal layer 431 and gate contact MP2 is IMD layer 440d. According to an embodiment of the present invention, interconnect metal layer 451 extends laterally to directly above gate 204 and gate contact MP1. Therefore, when viewed from above, interconnect metal layer 451 overlaps gate contact MP1. Between interconnect metal layer 451 and gate contact MP1 is IMD layer 440.

[0086] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. An embedded high-voltage semiconductor component, comprising: A substrate having a low-voltage component area and a high-voltage component area; an interlayer dielectric layer disposed on the substrate; A first trench isolation region is located in the substrate within the low voltage device region; a first gate located in the interlayer dielectric layer and on the first trench isolation region; a first gate contact located in the interlayer dielectric layer and on the first gate; a first interconnect metal layer covering the first gate contact; a first intermetallic dielectric layer on the interlayer dielectric layer and between the first interconnect metal layer and the first gate contact; a second trench isolation region located in the substrate within the high voltage device region; a second gate located in the interlayer dielectric layer and on the second trench isolation region; a second gate contact located in the interlayer dielectric layer and on the second gate; a second interconnect metal layer covering the second gate contact; as well as The second intermetallic dielectric layer is located on the interlayer dielectric layer and between the second interconnect metal layer and the second gate contact, wherein the second intermetallic dielectric layer is denser than the first intermetallic dielectric layer.

2. The embedded high-voltage semiconductor component according to claim 1, wherein: The second interconnect metal layer overlaps the second gate contact.

3. The embedded high-voltage semiconductor component according to claim 1, wherein: The first intermetal dielectric layer includes an ultra-low dielectric constant material layer.

4. The embedded high-voltage semiconductor component according to claim 3, wherein: The second intermetal dielectric layer includes a TEOS oxide layer or a high-density plasma oxide layer.

5. The embedded high-voltage semiconductor component according to claim 4, wherein: The second interconnect metal layer is disposed in the second intermetallic dielectric layer.

6. The embedded high-voltage semiconductor component according to claim 4, wherein: The first intermetal dielectric layer extends onto a top surface of the second intermetal dielectric layer.

7. The embedded high-voltage semiconductor component according to claim 6, wherein: The second interconnect metal layer is disposed in the first intermetal dielectric layer extending onto the top surface of the second intermetal dielectric layer.

8. The embedded high-voltage semiconductor component according to claim 1, wherein: The first gate contact and the second gate contact include tungsten.

9. The embedded high-voltage semiconductor component according to claim 1, wherein: The first gate and the second gate are metal gates.

10. The embedded high-voltage semiconductor component according to claim 1, wherein: The first intermetal dielectric layer and the second intermetal dielectric layer are ultra-low dielectric constant material layers.

11. A method for forming an embedded high-voltage semiconductor device, comprising: providing a substrate having a low voltage component region and a high voltage component region thereon; forming an interlayer dielectric layer on the substrate; forming a first trench isolation region in the substrate within the low voltage device region; forming a first gate disposed in the interlayer dielectric layer and on the first trench isolation region; forming a first gate contact in the interlayer dielectric layer and on the first gate; forming a first interconnect metal layer covering the first gate contact; forming a first intermetallic dielectric layer on the interlayer dielectric layer and between the first interconnect metal layer and the first gate contact; forming a second trench isolation region in the substrate within the high voltage device region; forming a second gate in the interlayer dielectric layer and on the second trench isolation region; forming a second gate contact in the interlayer dielectric layer and on the second gate; forming a second interconnect metal layer covering the second gate contact; as well as A second intermetallic dielectric layer is formed on the interlayer dielectric layer and between the second interconnect metal layer and the second gate contact, wherein the second intermetallic dielectric layer is denser than the first intermetallic dielectric layer.

12. The method of claim 11, wherein: The second interconnect metal layer overlaps the second gate contact.

13. The method of claim 11, wherein: The first intermetal dielectric layer includes an ultra-low dielectric constant material layer.

14. The method of claim 13, wherein: The second intermetal dielectric layer includes a TEOS oxide layer or a high-density plasma oxide layer.

15. The method of claim 14, wherein: The second interconnect metal layer is disposed in the second intermetallic dielectric layer.

16. The method of claim 14, wherein: The first intermetal dielectric layer extends onto a top surface of the second intermetal dielectric layer.

17. The method of claim 16, wherein: The second interconnect metal layer is disposed in the first intermetal dielectric layer extending onto a top surface of the second intermetal dielectric layer.

18. The method of claim 11, wherein: The first gate contact and the second gate contact include tungsten.

19. The method of claim 11, wherein: The first gate and the second gate are metal gates.

20. The method of claim 11, wherein: The first intermetallic dielectric layer and the second intermetallic dielectric layer are ultra-low dielectric constant material layers.

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