VDMOS device single event effect test method

Abstract

The invention discloses a VDMOS (vertical double-diffused metal oxide semiconductor) device single event effect test method, which puts forward requirements from the aspects of test process, test sample, test condition, test device, test development, test data analysis and test report, establishes a reasonable and unified VDMOS single event effect test method, and gives a radiation safety working area. The anti-radiation capability of the components is comprehensively displayed, and more detailed data support is provided for work such as product evaluation and user selection; the VDMOS single event effect test method fills the blank in the aspect of the VDMOS single event effect test method, lays the foundation for the domestic VDMOS radiation resistance evaluation, and supports the application of the VDMOS in the related fields.

Description

Technical Field

[0001] The present invention belongs to the field of space radiation effects, relates to VDMOS single particle radiation effects, and in particular to a VDMOS single particle effect test method. The method is suitable for VDMOS used in the space field and having radiation requirements, and for occasions where a ground radiation source is required to perform radiation tests. Background Art

[0002] VDMOS devices are increasingly used in extremely complex environments such as aviation, aerospace, and nuclear engineering. Especially in the aerospace field, VDMOS is widely used in DC / DC and is one of the products that urgently needs to be domestically produced. Radiation resistance is a core indicator.

[0003] To address product radiation resistance, scientific, rational, and accurate evaluation of radiation resistance is essential. Currently, there are some issues with VDMOS radiation testing methods. For example, detailed methods involving core elements are not publicly available abroad, and relevant domestic testing methods are insufficiently detailed and lack some key requirements.

[0004] Therefore, developing a VDMOS single-particle effect test method can lay the foundation for domestic VDMOS radiation resistance evaluation and support the application of VDMOS in related fields. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a single event effects test method for VDMOS devices, aiming to fill the gap in VDMOS single event effects test methods. The method can guide personnel to perform single event effects tests on VDMOS using a ground radiation source and carry out related work.

[0006] A single event effect test method for a VDMOS device, including test sample preparation, test condition determination, test implementation, test data analysis, and test report preparation;

[0007] The implementation of the trial specifically includes:

[0008] (1) Determine the initial gate-source voltage VGS and drain-source voltage VDS, apply the determined test conditions to the test sample, carry out the test, and use the test equipment to monitor the gate-source current IGS and drain-source current IDS.

[0009] (2) Based on the test results, determine the next VGS and VDS to be applied, apply the determined test conditions to the test sample, conduct the test, and monitor using the test equipment;

[0010] (3) Under each test condition, if no single event effect occurs, repeat the test on the three selected test samples. If a single event effect occurs, there is no need to repeat the test;

[0011] (4) For each sample that has completed the test, perform electrical parameter testing and record the test results.

[0012] Preferably, the test sample preparation includes:

[0013] (1) Test samples should be randomly selected from the same batch of products;

[0014] (2) If necessary, the test sample needs to be uncapped.

[0015] Preferably, the test conditions include:

[0016] (1) Determine the type of radiation source particles;

[0017] (2) Determine the energy of radiation source particles;

[0018] (3) Determine the range of radiation source particles;

[0019] (4) Determine the LET value of the radiation source particles;

[0020] (5) Determine the particle fluence rate of the radiation source;

[0021] (6) Determine the maximum injection volume required for each test point.

[0022] Preferably, the test data analysis includes:

[0023] (1) Give the device's ability to resist single-event gate punch-through;

[0024] (2) Provide the device's ability to withstand single-event burnout;

[0025] (3) Combining the single-particle gate penetration and single-particle burnout situations, the device's ability to resist single-particle effects is comprehensively given.

[0026] Preferably, the test data analysis includes providing the safe operating area of ​​the device, specifically:

[0027] Take VGS and VDS as the two axes of a two-dimensional rectangular coordinate system; carry out single-particle tests under multiple test conditions to obtain multiple test points where the device does not have a single-particle effect, among which: under the same VGS, take a higher VDS; under the same VDS, take a higher VGS. The area enclosed by the line connecting the test points and the two coordinate axes is the safe operating area of ​​the device; when there are multiple VDS voltages under the same VGS voltage, take the data point with the higher VDS voltage to draw the safe operating curve; when there are multiple VGS voltages under the same VDS voltage, take the data point with the higher VGS voltage to draw the safe operating curve.

[0028] The present invention has the following beneficial effects:

[0029] (1) Fill the gap in VDMOS single particle effect test methods, lay the foundation for domestic VDMOS radiation resistance evaluation, and support the application of VDMOS in related fields.

[0030] (2) The present invention puts forward requirements in terms of test process, test samples, test conditions, test equipment, test implementation, test data analysis and test report, and establishes a reasonable and unified VDMOS single-particle effect test method.

[0031] (3) Provide a radiation safety working area, comprehensively demonstrate the radiation resistance of components, and provide more detailed data support for product evaluation, user selection, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a flow chart of the test method of the present invention;

[0033] Figure 2 This is a curve diagram of the radiation safe working area determined by the present invention. DETAILED DESCRIPTION

[0034] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0035] A single event effect test method for a VDMOS device includes a test process, test samples, test conditions, test equipment, test development, test data analysis and test report.

[0036] The test process requirements for the above-mentioned VDMOS single event effect test method are as follows:

[0037] The test is carried out in the following order: test sample preparation, test condition determination, test equipment development, test implementation, test data analysis and test report preparation.

[0038] A VDMOS single event effect test method, the test sample requirements are as follows:

[0039] (1) Test samples should be randomly selected from the same batch of products.

[0040] (2) If necessary, the test sample needs to be uncapped.

[0041] A VDMOS single event effect test method, the test conditions are as follows:

[0042] (1) Determine the type of radiation source particles.

[0043] (2) Determine the energy of the radiation source particles.

[0044] (3) Determine the range of radiation source particles.

[0045] (4) Determine the LET value of the radiation source particles.

[0046] (5) Determine the particle fluence rate of the radiation source.

[0047] (6) Determine the maximum injection volume required for each test point.

[0048] A VDMOS single event effect test method, the test equipment requirements are as follows:

[0049] (1) An adjustable gate-source voltage VGS can be applied and the gate-source current IGS can be monitored in real time.

[0050] (2) An adjustable drain-source voltage VDS can be applied and the drain-source current IDS can be monitored in real time.

[0051] (3) It has the function of limiting the gate-source current IGS and the drain-source current IDS.

[0052] A VDMOS single event effects test method, the test requirements are as follows:

[0053] (1) Determine the initial gate-source voltage VGS and drain-source voltage VDS, apply the determined test conditions to the test sample, carry out the test, and use the test equipment to monitor the gate-source current IGS and drain-source current IDS.

[0054] (2) Based on the test results, determine the next VGS and VDS to be applied, apply the determined test conditions to the test sample, conduct the test, and monitor using the test equipment.

[0055] (3) Under each test condition, if no single-particle effect occurs, three samples need to be tested repeatedly. If a single-particle effect occurs, no repeated test is required.

[0056] (4) Each sample that has completed the test must undergo electrical parameter testing in accordance with relevant requirements and the test results must be recorded.

[0057] A VDMOS single event effects test method with the following test data analysis requirements:

[0058] (1) The device's ability to resist single-particle gate punchout should be given. That is, if the IGS of the device increases significantly under certain test conditions, it means that single-particle gate punchout has occurred, and the device's ability to resist single-particle gate punchout can be given.

[0059] (2) The device's ability to withstand single-event burnout should be given. That is, if the device's IDS increases significantly under certain test conditions, it means that a single-event burnout has occurred, and the device's ability to withstand single-event burnout can be given.

[0060] (3) Combining the single-particle gate penetration and single-particle burnout situations, the device's ability to resist single-particle effects is comprehensively given.

[0061] (4) If necessary, the safe operating area of ​​the device should be given, including:

[0062] By conducting single-event testing under multiple test conditions (i.e., different VGS and VDS combinations), we can obtain multiple test points where the device does not experience single-event effects. Under test conditions where VGS or VDS is below these test points, a single-event effect theoretically cannot occur (for example, if a device does not experience a single-event effect at VGS of 10V and VDS of 100V, then any combination of VGS below 10V and VDS below 100V will also not experience a single-event effect). Therefore, by combining all test conditions (VGS, VDS) where no single-event effect occurs, using a higher VDS for the same VGS and a higher VGS for the same VDS. Using VGS and VDS as the two axes of a two-dimensional rectangular coordinate system, the area enclosed by the line connecting the test points and the two coordinate axes is the safe operating area of ​​the device. Among them, if there are many test conditions and there are multiple VDS voltages under the same VGS voltage, the data point with the higher VDS voltage is taken to draw the safe working curve; similarly, if there are many test conditions and there are multiple VGS voltages under the same VDS voltage, the data point with the higher VGS voltage is taken to draw the safe working curve.

[0063] A VDMOS single event effects test method with the following test report requirements:

[0064] The report should include at least the following:

[0065] a) Overview of the test;

[0066] b) Test basis;

[0067] c) Basic information of the test sample;

[0068] d) Basic information on test conditions;

[0069] e) Basic information of the test device;

[0070] f) Test process and related data;

[0071] g) Test data analysis and process;

[0072] h) Test conclusions.

[0073] Example:

[0074] (1) Carry out single event effect test of a certain type of N-channel VDMOS, and formulate the test process as follows: test sample preparation, test condition determination, test equipment development, test implementation, test data analysis and test report preparation.

[0075] (2) The test samples were randomly selected from the same batch of products; considering that the selected radiation source could not penetrate the sample tube shell, the sample was uncapped.

[0076] (3) Test conditions: the radiation source is Bi particles, the energy is 9.5 MeV / u, the range is 70 μm in Si, and the LET value is 99 MeV / (mg / cm 2 ), injection rate 5000cm -2 ·s -1 , the maximum injection volume of each test point is 10 7 cm -2 .

[0077] (4) Using LabVIEW software, NI hardware, power supply and source meter, a test device was built to apply adjustable VGS and monitor IGS in real time, apply adjustable VDS and monitor IDS in real time, and have IGS and IDS current limiting functions.

[0078] (5) The test process is as follows:

[0079] (a) VGS = 0, VDS = 200 V, 3 samples were selected.

[0080] (b) If no single event effect occurs in any of the three samples, the test passes; if only one sample experiences a single event effect, the test fails and the remaining samples do not need to be tested further.

[0081] (c) Based on the test conditions of step (a), VGS is reduced by 5V. Three samples are selected and tested according to step (b). The test is stopped when VGS = -20V.

[0082] (d) Based on the test conditions of step (a), VDS is reduced by 50V. Three samples are selected and tested according to step (b). The test is stopped when VDS = 50V.

[0083] It should be noted that test conditions are generally determined based on the device's specific conditions (whether it is a radiation-hardened device, whether historical test data is available, etc.) and user requirements (whether a comprehensive assessment of the device's radiation resistance is required, or whether the device is only required to verify normal operation under specific conditions, etc.). It should be noted that the test plan for this test is generally determined based on the above principles before the irradiation test is carried out. Therefore, the examples only need to be carried out according to the determined test plan.

[0084] (e) Perform endpoint electrical testing on all test samples.

[0085] (6) Analyze the test data and determine:

[0086] (a) At an LET value of 99 MeV / (mg / cm 2) conditions, the device does not have the ability to resist single-particle gate punch-through.

[0087] (b) At an LET value of 99 MeV / (mg / cm 2 ) under the condition of VGS=0, VDS=150V, the device's ability to resist single-particle burnout can reach VGS=0, VDS=150V.

[0088] (c) In general, at an LET value of 99 MeV / (mg / cm 2 ) conditions, the device does not have the ability to resist single event effects.

[0089] (7) Complete the preparation of the test report from the aspects of test overview, test basis, basic information of test samples, basic information of test conditions, basic information of test equipment, test process and related data, test data analysis and process, and test conclusions.

[0090] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A single event effect test method for a VDMOS device, characterized in that: Including test sample preparation, test condition determination, test implementation, test data analysis and test report preparation; The implementation of the trial specifically includes: (1) Determine the initial gate-source voltage VGS and drain-source voltage VDS, apply the determined test conditions to the test sample, carry out the test, and use the test equipment to monitor the gate-source current IGS and drain-source current IDS. (2) Based on the test results, determine the next VGS and VDS to be applied, apply the determined test conditions to the test sample, conduct the test, and monitor using the test equipment; (3) Under each test condition, if no single event effect occurs, repeat the test on the three selected test samples. If a single event effect occurs, there is no need to repeat the test; (4) For each sample that has completed the test, perform electrical parameter testing and record the test results.

2. A single event effect test method for a VDMOS device according to claim 1, characterized in that: Test sample preparation includes: (1) Test samples should be randomly selected from the same batch of products; (2) If necessary, the test sample needs to be uncapped.

3. A single event effect test method for a VDMOS device as claimed in claim 1, characterized in that: The test conditions include: (1) Determine the type of radiation source particles; (2) Determine the energy of radiation source particles; (3) Determine the range of radiation source particles; (4) Determine the LET value of the radiation source particles; (5) Determine the particle fluence rate of the radiation source; (6) Determine the maximum injection volume required for each test point.

4. A single event effect test method for a VDMOS device as claimed in claim 1, characterized in that: The test data analysis includes: (1) Give the device's ability to resist single-event gate punch-through; (2) Provide the device's ability to withstand single-event burnout; (3) Combining the single-particle gate penetration and single-particle burnout situations, the device's ability to resist single-particle effects is comprehensively given.

5. A single event effect test method for a VDMOS device as claimed in claim 4, characterized in that: The test data analysis includes providing the safe operating area of ​​the device, specifically: Take VGS and VDS as the two axes of a two-dimensional rectangular coordinate system; carry out single-particle tests under multiple test conditions to obtain multiple test points where the device does not have a single-particle effect, among which: under the same VGS, take a higher VDS; under the same VDS, take a higher VGS. The area enclosed by the line connecting the test points and the two coordinate axes is the safe operating area of ​​the device; when there are multiple VDS voltages under the same VGS voltage, take the data point with the higher VDS voltage to draw the safe operating curve; when there are multiple VGS voltages under the same VDS voltage, take the data point with the higher VGS voltage to draw the safe operating curve.

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